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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[mirror_ubuntu-eoan-kernel.git] / arch / arm / plat-omap / dma.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/dma.c
3 *
97b7f715 4 * Copyright (C) 2003 - 2008 Nokia Corporation
96de0e25 5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
f8151e5c 9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
1a8bfa1e 10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
5e1c5ff4
TL		 11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
44169075
SS		 13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 *
5e1c5ff4
TL		 16 * Support functions for the OMAP internal DMA channels.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/sched.h>
27#include <linux/spinlock.h>
28#include <linux/errno.h>
29#include <linux/interrupt.h>
418ca1f0 30#include <linux/irq.h>
97b7f715 31#include <linux/io.h>
5a0e3ad6 32#include <linux/slab.h>
5e1c5ff4
TL		 33
34#include <asm/system.h>
a09e64fb 35#include <mach/hardware.h>
ce491cf8 36#include <plat/dma.h>
5e1c5ff4 37
ce491cf8 38#include <plat/tc.h>
5e1c5ff4 39
f8151e5c
AG		 40#undef DEBUG
41
42#ifndef CONFIG_ARCH_OMAP1
43enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
44 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
45};
46
47enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
1a8bfa1e 48#endif
5e1c5ff4 49
97b7f715 50#define OMAP_DMA_ACTIVE 0x01
7ff879db 51#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
5e1c5ff4 52
97b7f715 53#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
5e1c5ff4 54
97b7f715 55static int enable_1510_mode;
5e1c5ff4 56
f2d11858
TK		 57static struct omap_dma_global_context_registers {
58 u32 dma_irqenable_l0;
59 u32 dma_ocp_sysconfig;
60 u32 dma_gcr;
61} omap_dma_global_context;
62
5e1c5ff4
TL		 63struct omap_dma_lch {
64 int next_lch;
65 int dev_id;
66 u16 saved_csr;
67 u16 enabled_irqs;
68 const char *dev_name;
97b7f715 69 void (*callback)(int lch, u16 ch_status, void *data);
5e1c5ff4 70 void *data;
f8151e5c
AG		 71
72#ifndef CONFIG_ARCH_OMAP1
73 /* required for Dynamic chaining */
74 int prev_linked_ch;
75 int next_linked_ch;
76 int state;
77 int chain_id;
78
79 int status;
80#endif
5e1c5ff4
TL		 81 long flags;
82};
83
f8151e5c
AG		 84struct dma_link_info {
85 int *linked_dmach_q;
86 int no_of_lchs_linked;
87
88 int q_count;
89 int q_tail;
90 int q_head;
91
92 int chain_state;
93 int chain_mode;
94
95};
96
4d96372e
TL		 97static struct dma_link_info *dma_linked_lch;
98
99#ifndef CONFIG_ARCH_OMAP1
f8151e5c
AG		 100
101/* Chain handling macros */
102#define OMAP_DMA_CHAIN_QINIT(chain_id) \
103 do { \
104 dma_linked_lch[chain_id].q_head = \
105 dma_linked_lch[chain_id].q_tail = \
106 dma_linked_lch[chain_id].q_count = 0; \
107 } while (0)
108#define OMAP_DMA_CHAIN_QFULL(chain_id) \
109 (dma_linked_lch[chain_id].no_of_lchs_linked == \
110 dma_linked_lch[chain_id].q_count)
111#define OMAP_DMA_CHAIN_QLAST(chain_id) \
112 do { \
113 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
114 dma_linked_lch[chain_id].q_count) \
115 } while (0)
116#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
117 (0 == dma_linked_lch[chain_id].q_count)
118#define __OMAP_DMA_CHAIN_INCQ(end) \
119 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
120#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
121 do { \
122 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
123 dma_linked_lch[chain_id].q_count--; \
124 } while (0)
125
126#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
127 do { \
128 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
129 dma_linked_lch[chain_id].q_count++; \
130 } while (0)
131#endif
4d96372e
TL		 132
133static int dma_lch_count;
5e1c5ff4 134static int dma_chan_count;
2263f022 135static int omap_dma_reserve_channels;
5e1c5ff4
TL		 136
137static spinlock_t dma_chan_lock;
4d96372e 138static struct omap_dma_lch *dma_chan;
0499bdeb 139static void __iomem *omap_dma_base;
5e1c5ff4 140
4d96372e 141static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
5e1c5ff4
TL		 142 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
143 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
144 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
145 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
146 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
147};
148
f8151e5c
AG		 149static inline void disable_lnk(int lch);
150static void omap_disable_channel_irq(int lch);
151static inline void omap_enable_channel_irq(int lch);
152
1a8bfa1e 153#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
8e86f427 154 __func__);
1a8bfa1e 155
0499bdeb
TL		 156#define dma_read(reg) \
157({ \
158 u32 __val; \
159 if (cpu_class_is_omap1()) \
160 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
161 else \
162 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
163 __val; \
164})
165
166#define dma_write(val, reg) \
167({ \
168 if (cpu_class_is_omap1()) \
169 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
170 else \
171 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
172})
173
1a8bfa1e
TL		 174#ifdef CONFIG_ARCH_OMAP15XX
175/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
176int omap_dma_in_1510_mode(void)
177{
178 return enable_1510_mode;
179}
180#else
181#define omap_dma_in_1510_mode() 0
182#endif
183
184#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 185static inline int get_gdma_dev(int req)
186{
187 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
188 int shift = ((req - 1) % 5) * 6;
189
190 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
191}
192
193static inline void set_gdma_dev(int req, int dev)
194{
195 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
196 int shift = ((req - 1) % 5) * 6;
197 u32 l;
198
199 l = omap_readl(reg);
200 l &= ~(0x3f << shift);
201 l |= (dev - 1) << shift;
202 omap_writel(l, reg);
203}
1a8bfa1e
TL		 204#else
205#define set_gdma_dev(req, dev) do {} while (0)
206#endif
5e1c5ff4 207
0499bdeb 208/* Omap1 only */
5e1c5ff4
TL		 209static void clear_lch_regs(int lch)
210{
211 int i;
0499bdeb 212 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
5e1c5ff4
TL		 213
214 for (i = 0; i < 0x2c; i += 2)
0499bdeb 215 __raw_writew(0, lch_base + i);
5e1c5ff4
TL		 216}
217
709eb3e5 218void omap_set_dma_priority(int lch, int dst_port, int priority)
5e1c5ff4
TL		 219{
220 unsigned long reg;
221 u32 l;
222
709eb3e5
TL		 223 if (cpu_class_is_omap1()) {
224 switch (dst_port) {
225 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
226 reg = OMAP_TC_OCPT1_PRIOR;
227 break;
228 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
229 reg = OMAP_TC_OCPT2_PRIOR;
230 break;
231 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
232 reg = OMAP_TC_EMIFF_PRIOR;
233 break;
234 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
235 reg = OMAP_TC_EMIFS_PRIOR;
236 break;
237 default:
238 BUG();
239 return;
240 }
241 l = omap_readl(reg);
242 l &= ~(0xf << 8);
243 l |= (priority & 0xf) << 8;
244 omap_writel(l, reg);
245 }
246
f8151e5c 247 if (cpu_class_is_omap2()) {
0499bdeb
TL		 248 u32 ccr;
249
250 ccr = dma_read(CCR(lch));
709eb3e5 251 if (priority)
0499bdeb 252 ccr |= (1 << 6);
709eb3e5 253 else
0499bdeb
TL		 254 ccr &= ~(1 << 6);
255 dma_write(ccr, CCR(lch));
5e1c5ff4 256 }
5e1c5ff4 257}
97b7f715 258EXPORT_SYMBOL(omap_set_dma_priority);
5e1c5ff4
TL		 259
260void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
1a8bfa1e
TL		 261 int frame_count, int sync_mode,
262 int dma_trigger, int src_or_dst_synch)
5e1c5ff4 263{
0499bdeb
TL		 264 u32 l;
265
266 l = dma_read(CSDP(lch));
267 l &= ~0x03;
268 l |= data_type;
269 dma_write(l, CSDP(lch));
5e1c5ff4 270
1a8bfa1e 271 if (cpu_class_is_omap1()) {
0499bdeb
TL		 272 u16 ccr;
273
274 ccr = dma_read(CCR(lch));
275 ccr &= ~(1 << 5);
1a8bfa1e 276 if (sync_mode == OMAP_DMA_SYNC_FRAME)
0499bdeb
TL		 277 ccr |= 1 << 5;
278 dma_write(ccr, CCR(lch));
1a8bfa1e 279
0499bdeb
TL		 280 ccr = dma_read(CCR2(lch));
281 ccr &= ~(1 << 2);
1a8bfa1e 282 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
0499bdeb
TL		 283 ccr |= 1 << 2;
284 dma_write(ccr, CCR2(lch));
1a8bfa1e
TL		 285 }
286
f8151e5c 287 if (cpu_class_is_omap2() && dma_trigger) {
0499bdeb 288 u32 val;
1a8bfa1e 289
0499bdeb 290 val = dma_read(CCR(lch));
4b3cf448
AG		 291
292 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
293 val &= ~((3 << 19) | 0x1f);
294 val |= (dma_trigger & ~0x1f) << 14;
295 val |= dma_trigger & 0x1f;
5e1c5ff4 296
1a8bfa1e
TL		 297 if (sync_mode & OMAP_DMA_SYNC_FRAME)
298 val |= 1 << 5;
eca9e56e
PU		 299 else
300 val &= ~(1 << 5);
5e1c5ff4 301
1a8bfa1e
TL		 302 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
303 val |= 1 << 18;
eca9e56e
PU		 304 else
305 val &= ~(1 << 18);
5e1c5ff4 306
1a8bfa1e
TL		 307 if (src_or_dst_synch)
308 val |= 1 << 24; /* source synch */
309 else
310 val &= ~(1 << 24); /* dest synch */
311
0499bdeb 312 dma_write(val, CCR(lch));
1a8bfa1e
TL		 313 }
314
0499bdeb
TL		 315 dma_write(elem_count, CEN(lch));
316 dma_write(frame_count, CFN(lch));
5e1c5ff4 317}
97b7f715 318EXPORT_SYMBOL(omap_set_dma_transfer_params);
1a8bfa1e 319
5e1c5ff4
TL		 320void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
321{
5e1c5ff4
TL		 322 BUG_ON(omap_dma_in_1510_mode());
323
0815f8ea
TV		 324 if (cpu_class_is_omap1()) {
325 u16 w;
1a8bfa1e 326
0815f8ea
TV		 327 w = dma_read(CCR2(lch));
328 w &= ~0x03;
329
330 switch (mode) {
331 case OMAP_DMA_CONSTANT_FILL:
332 w |= 0x01;
333 break;
334 case OMAP_DMA_TRANSPARENT_COPY:
335 w |= 0x02;
336 break;
337 case OMAP_DMA_COLOR_DIS:
338 break;
339 default:
340 BUG();
341 }
342 dma_write(w, CCR2(lch));
343
344 w = dma_read(LCH_CTRL(lch));
345 w &= ~0x0f;
346 /* Default is channel type 2D */
347 if (mode) {
348 dma_write((u16)color, COLOR_L(lch));
349 dma_write((u16)(color >> 16), COLOR_U(lch));
350 w |= 1; /* Channel type G */
351 }
352 dma_write(w, LCH_CTRL(lch));
5e1c5ff4 353 }
0815f8ea
TV		 354
355 if (cpu_class_is_omap2()) {
356 u32 val;
357
358 val = dma_read(CCR(lch));
359 val &= ~((1 << 17) | (1 << 16));
360
361 switch (mode) {
362 case OMAP_DMA_CONSTANT_FILL:
363 val |= 1 << 16;
364 break;
365 case OMAP_DMA_TRANSPARENT_COPY:
366 val |= 1 << 17;
367 break;
368 case OMAP_DMA_COLOR_DIS:
369 break;
370 default:
371 BUG();
372 }
373 dma_write(val, CCR(lch));
374
375 color &= 0xffffff;
376 dma_write(color, COLOR(lch));
5e1c5ff4 377 }
5e1c5ff4 378}
97b7f715 379EXPORT_SYMBOL(omap_set_dma_color_mode);
5e1c5ff4 380
709eb3e5
TL		 381void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
382{
f8151e5c 383 if (cpu_class_is_omap2()) {
0499bdeb
TL		 384 u32 csdp;
385
386 csdp = dma_read(CSDP(lch));
387 csdp &= ~(0x3 << 16);
388 csdp |= (mode << 16);
389 dma_write(csdp, CSDP(lch));
709eb3e5
TL		 390 }
391}
97b7f715 392EXPORT_SYMBOL(omap_set_dma_write_mode);
709eb3e5 393
0499bdeb
TL		 394void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
395{
396 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
397 u32 l;
398
399 l = dma_read(LCH_CTRL(lch));
400 l &= ~0x7;
401 l |= mode;
402 dma_write(l, LCH_CTRL(lch));
403 }
404}
405EXPORT_SYMBOL(omap_set_dma_channel_mode);
406
1a8bfa1e 407/* Note that src_port is only for omap1 */
5e1c5ff4 408void omap_set_dma_src_params(int lch, int src_port, int src_amode,
1a8bfa1e
TL		 409 unsigned long src_start,
410 int src_ei, int src_fi)
5e1c5ff4 411{
97b7f715
TL		 412 u32 l;
413
1a8bfa1e 414 if (cpu_class_is_omap1()) {
0499bdeb 415 u16 w;
1a8bfa1e 416
0499bdeb
TL		 417 w = dma_read(CSDP(lch));
418 w &= ~(0x1f << 2);
419 w |= src_port << 2;
420 dma_write(w, CSDP(lch));
97b7f715 421 }
1a8bfa1e 422
97b7f715
TL		 423 l = dma_read(CCR(lch));
424 l &= ~(0x03 << 12);
425 l |= src_amode << 12;
426 dma_write(l, CCR(lch));
0499bdeb 427
97b7f715 428 if (cpu_class_is_omap1()) {
0499bdeb
TL		 429 dma_write(src_start >> 16, CSSA_U(lch));
430 dma_write((u16)src_start, CSSA_L(lch));
1a8bfa1e 431 }
5e1c5ff4 432
97b7f715 433 if (cpu_class_is_omap2())
0499bdeb 434 dma_write(src_start, CSSA(lch));
97b7f715
TL		 435
436 dma_write(src_ei, CSEI(lch));
437 dma_write(src_fi, CSFI(lch));
1a8bfa1e 438}
97b7f715 439EXPORT_SYMBOL(omap_set_dma_src_params);
5e1c5ff4 440
97b7f715 441void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
1a8bfa1e
TL		 442{
443 omap_set_dma_transfer_params(lch, params->data_type,
444 params->elem_count, params->frame_count,
445 params->sync_mode, params->trigger,
446 params->src_or_dst_synch);
447 omap_set_dma_src_params(lch, params->src_port,
448 params->src_amode, params->src_start,
449 params->src_ei, params->src_fi);
450
451 omap_set_dma_dest_params(lch, params->dst_port,
452 params->dst_amode, params->dst_start,
453 params->dst_ei, params->dst_fi);
f8151e5c
AG		 454 if (params->read_prio || params->write_prio)
455 omap_dma_set_prio_lch(lch, params->read_prio,
456 params->write_prio);
5e1c5ff4 457}
97b7f715 458EXPORT_SYMBOL(omap_set_dma_params);
5e1c5ff4
TL		 459
460void omap_set_dma_src_index(int lch, int eidx, int fidx)
461{
97b7f715 462 if (cpu_class_is_omap2())
1a8bfa1e 463 return;
97b7f715 464
0499bdeb
TL		 465 dma_write(eidx, CSEI(lch));
466 dma_write(fidx, CSFI(lch));
5e1c5ff4 467}
97b7f715 468EXPORT_SYMBOL(omap_set_dma_src_index);
5e1c5ff4
TL		 469
470void omap_set_dma_src_data_pack(int lch, int enable)
471{
0499bdeb
TL		 472 u32 l;
473
474 l = dma_read(CSDP(lch));
475 l &= ~(1 << 6);
1a8bfa1e 476 if (enable)
0499bdeb
TL		 477 l |= (1 << 6);
478 dma_write(l, CSDP(lch));
5e1c5ff4 479}
97b7f715 480EXPORT_SYMBOL(omap_set_dma_src_data_pack);
5e1c5ff4
TL		 481
482void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
483{
6dc3c8f2 484 unsigned int burst = 0;
0499bdeb
TL		 485 u32 l;
486
487 l = dma_read(CSDP(lch));
488 l &= ~(0x03 << 7);
5e1c5ff4 489
5e1c5ff4
TL		 490 switch (burst_mode) {
491 case OMAP_DMA_DATA_BURST_DIS:
492 break;
493 case OMAP_DMA_DATA_BURST_4:
f8151e5c 494 if (cpu_class_is_omap2())
6dc3c8f2
KP		 495 burst = 0x1;
496 else
497 burst = 0x2;
5e1c5ff4
TL		 498 break;
499 case OMAP_DMA_DATA_BURST_8:
f8151e5c 500 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 501 burst = 0x2;
502 break;
503 }
504 /* not supported by current hardware on OMAP1
5e1c5ff4
TL		 505 * w |= (0x03 << 7);
506 * fall through
507 */
6dc3c8f2 508 case OMAP_DMA_DATA_BURST_16:
f8151e5c 509 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 510 burst = 0x3;
511 break;
512 }
513 /* OMAP1 don't support burst 16
514 * fall through
515 */
5e1c5ff4
TL		 516 default:
517 BUG();
518 }
0499bdeb
TL		 519
520 l |= (burst << 7);
521 dma_write(l, CSDP(lch));
5e1c5ff4 522}
97b7f715 523EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
5e1c5ff4 524
1a8bfa1e 525/* Note that dest_port is only for OMAP1 */
5e1c5ff4 526void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
1a8bfa1e
TL		 527 unsigned long dest_start,
528 int dst_ei, int dst_fi)
5e1c5ff4 529{
0499bdeb
TL		 530 u32 l;
531
1a8bfa1e 532 if (cpu_class_is_omap1()) {
0499bdeb
TL		 533 l = dma_read(CSDP(lch));
534 l &= ~(0x1f << 9);
535 l |= dest_port << 9;
536 dma_write(l, CSDP(lch));
1a8bfa1e 537 }
5e1c5ff4 538
0499bdeb
TL		 539 l = dma_read(CCR(lch));
540 l &= ~(0x03 << 14);
541 l |= dest_amode << 14;
542 dma_write(l, CCR(lch));
1a8bfa1e
TL		 543
544 if (cpu_class_is_omap1()) {
0499bdeb
TL		 545 dma_write(dest_start >> 16, CDSA_U(lch));
546 dma_write(dest_start, CDSA_L(lch));
1a8bfa1e 547 }
5e1c5ff4 548
f8151e5c 549 if (cpu_class_is_omap2())
0499bdeb 550 dma_write(dest_start, CDSA(lch));
5e1c5ff4 551
0499bdeb
TL		 552 dma_write(dst_ei, CDEI(lch));
553 dma_write(dst_fi, CDFI(lch));
5e1c5ff4 554}
97b7f715 555EXPORT_SYMBOL(omap_set_dma_dest_params);
5e1c5ff4
TL		 556
557void omap_set_dma_dest_index(int lch, int eidx, int fidx)
558{
97b7f715 559 if (cpu_class_is_omap2())
1a8bfa1e 560 return;
97b7f715 561
0499bdeb
TL		 562 dma_write(eidx, CDEI(lch));
563 dma_write(fidx, CDFI(lch));
5e1c5ff4 564}
97b7f715 565EXPORT_SYMBOL(omap_set_dma_dest_index);
5e1c5ff4
TL		 566
567void omap_set_dma_dest_data_pack(int lch, int enable)
568{
0499bdeb
TL		 569 u32 l;
570
571 l = dma_read(CSDP(lch));
572 l &= ~(1 << 13);
1a8bfa1e 573 if (enable)
0499bdeb
TL		 574 l |= 1 << 13;
575 dma_write(l, CSDP(lch));
5e1c5ff4 576}
97b7f715 577EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
5e1c5ff4
TL		 578
579void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
580{
6dc3c8f2 581 unsigned int burst = 0;
0499bdeb
TL		 582 u32 l;
583
584 l = dma_read(CSDP(lch));
585 l &= ~(0x03 << 14);
5e1c5ff4 586
5e1c5ff4
TL		 587 switch (burst_mode) {
588 case OMAP_DMA_DATA_BURST_DIS:
589 break;
590 case OMAP_DMA_DATA_BURST_4:
f8151e5c 591 if (cpu_class_is_omap2())
6dc3c8f2
KP		 592 burst = 0x1;
593 else
594 burst = 0x2;
5e1c5ff4
TL		 595 break;
596 case OMAP_DMA_DATA_BURST_8:
f8151e5c 597 if (cpu_class_is_omap2())
6dc3c8f2
KP		 598 burst = 0x2;
599 else
600 burst = 0x3;
5e1c5ff4 601 break;
6dc3c8f2 602 case OMAP_DMA_DATA_BURST_16:
f8151e5c 603 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 604 burst = 0x3;
605 break;
606 }
607 /* OMAP1 don't support burst 16
608 * fall through
609 */
5e1c5ff4
TL		 610 default:
611 printk(KERN_ERR "Invalid DMA burst mode\n");
612 BUG();
613 return;
614 }
0499bdeb
TL		 615 l |= (burst << 14);
616 dma_write(l, CSDP(lch));
5e1c5ff4 617}
97b7f715 618EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
5e1c5ff4 619
1a8bfa1e 620static inline void omap_enable_channel_irq(int lch)
5e1c5ff4 621{
1a8bfa1e 622 u32 status;
5e1c5ff4 623
7ff879db
TL		 624 /* Clear CSR */
625 if (cpu_class_is_omap1())
0499bdeb 626 status = dma_read(CSR(lch));
f8151e5c 627 else if (cpu_class_is_omap2())
0499bdeb 628 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
1a8bfa1e 629
5e1c5ff4 630 /* Enable some nice interrupts. */
0499bdeb 631 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
5e1c5ff4
TL		 632}
633
1a8bfa1e 634static void omap_disable_channel_irq(int lch)
5e1c5ff4 635{
f8151e5c 636 if (cpu_class_is_omap2())
0499bdeb 637 dma_write(0, CICR(lch));
1a8bfa1e
TL		 638}
639
640void omap_enable_dma_irq(int lch, u16 bits)
641{
642 dma_chan[lch].enabled_irqs |= bits;
643}
97b7f715 644EXPORT_SYMBOL(omap_enable_dma_irq);
5e1c5ff4 645
1a8bfa1e
TL		 646void omap_disable_dma_irq(int lch, u16 bits)
647{
648 dma_chan[lch].enabled_irqs &= ~bits;
649}
97b7f715 650EXPORT_SYMBOL(omap_disable_dma_irq);
1a8bfa1e
TL		 651
652static inline void enable_lnk(int lch)
653{
0499bdeb
TL		 654 u32 l;
655
656 l = dma_read(CLNK_CTRL(lch));
657
1a8bfa1e 658 if (cpu_class_is_omap1())
0499bdeb 659 l &= ~(1 << 14);
5e1c5ff4 660
1a8bfa1e 661 /* Set the ENABLE_LNK bits */
5e1c5ff4 662 if (dma_chan[lch].next_lch != -1)
0499bdeb 663 l = dma_chan[lch].next_lch | (1 << 15);
f8151e5c
AG		 664
665#ifndef CONFIG_ARCH_OMAP1
97b7f715
TL		 666 if (cpu_class_is_omap2())
667 if (dma_chan[lch].next_linked_ch != -1)
668 l = dma_chan[lch].next_linked_ch | (1 << 15);
f8151e5c 669#endif
0499bdeb
TL		 670
671 dma_write(l, CLNK_CTRL(lch));
5e1c5ff4
TL		 672}
673
674static inline void disable_lnk(int lch)
675{
0499bdeb
TL		 676 u32 l;
677
678 l = dma_read(CLNK_CTRL(lch));
679
5e1c5ff4 680 /* Disable interrupts */
1a8bfa1e 681 if (cpu_class_is_omap1()) {
0499bdeb 682 dma_write(0, CICR(lch));
1a8bfa1e 683 /* Set the STOP_LNK bit */
0499bdeb 684 l |= 1 << 14;
1a8bfa1e 685 }
5e1c5ff4 686
f8151e5c 687 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 688 omap_disable_channel_irq(lch);
689 /* Clear the ENABLE_LNK bit */
0499bdeb 690 l &= ~(1 << 15);
1a8bfa1e 691 }
5e1c5ff4 692
0499bdeb 693 dma_write(l, CLNK_CTRL(lch));
5e1c5ff4
TL		 694 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
695}
696
1a8bfa1e 697static inline void omap2_enable_irq_lch(int lch)
5e1c5ff4 698{
1a8bfa1e 699 u32 val;
ee907324 700 unsigned long flags;
1a8bfa1e 701
f8151e5c 702 if (!cpu_class_is_omap2())
1a8bfa1e
TL		 703 return;
704
ee907324 705 spin_lock_irqsave(&dma_chan_lock, flags);
0499bdeb 706 val = dma_read(IRQENABLE_L0);
1a8bfa1e 707 val |= 1 << lch;
0499bdeb 708 dma_write(val, IRQENABLE_L0);
ee907324 709 spin_unlock_irqrestore(&dma_chan_lock, flags);
1a8bfa1e
TL		 710}
711
712int omap_request_dma(int dev_id, const char *dev_name,
97b7f715 713 void (*callback)(int lch, u16 ch_status, void *data),
1a8bfa1e
TL		 714 void *data, int *dma_ch_out)
715{
716 int ch, free_ch = -1;
717 unsigned long flags;
718 struct omap_dma_lch *chan;
719
720 spin_lock_irqsave(&dma_chan_lock, flags);
721 for (ch = 0; ch < dma_chan_count; ch++) {
722 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
723 free_ch = ch;
724 if (dev_id == 0)
725 break;
726 }
727 }
728 if (free_ch == -1) {
729 spin_unlock_irqrestore(&dma_chan_lock, flags);
730 return -EBUSY;
731 }
732 chan = dma_chan + free_ch;
733 chan->dev_id = dev_id;
734
735 if (cpu_class_is_omap1())
736 clear_lch_regs(free_ch);
5e1c5ff4 737
f8151e5c 738 if (cpu_class_is_omap2())
1a8bfa1e
TL		 739 omap_clear_dma(free_ch);
740
741 spin_unlock_irqrestore(&dma_chan_lock, flags);
742
743 chan->dev_name = dev_name;
744 chan->callback = callback;
745 chan->data = data;
a92fda19 746 chan->flags = 0;
97b7f715 747
f8151e5c 748#ifndef CONFIG_ARCH_OMAP1
97b7f715
TL		 749 if (cpu_class_is_omap2()) {
750 chan->chain_id = -1;
751 chan->next_linked_ch = -1;
752 }
f8151e5c 753#endif
97b7f715 754
7ff879db 755 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
1a8bfa1e 756
7ff879db
TL		 757 if (cpu_class_is_omap1())
758 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
f8151e5c 759 else if (cpu_class_is_omap2())
7ff879db
TL		 760 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
761 OMAP2_DMA_TRANS_ERR_IRQ;
1a8bfa1e
TL		 762
763 if (cpu_is_omap16xx()) {
764 /* If the sync device is set, configure it dynamically. */
765 if (dev_id != 0) {
766 set_gdma_dev(free_ch + 1, dev_id);
767 dev_id = free_ch + 1;
768 }
97b7f715
TL		 769 /*
770 * Disable the 1510 compatibility mode and set the sync device
771 * id.
772 */
0499bdeb 773 dma_write(dev_id | (1 << 10), CCR(free_ch));
557096fe 774 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
0499bdeb 775 dma_write(dev_id, CCR(free_ch));
1a8bfa1e
TL		 776 }
777
f8151e5c 778 if (cpu_class_is_omap2()) {
1a8bfa1e 779 omap2_enable_irq_lch(free_ch);
1a8bfa1e
TL		 780 omap_enable_channel_irq(free_ch);
781 /* Clear the CSR register and IRQ status register */
0499bdeb
TL		 782 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
783 dma_write(1 << free_ch, IRQSTATUS_L0);
1a8bfa1e
TL		 784 }
785
786 *dma_ch_out = free_ch;
787
788 return 0;
789}
97b7f715 790EXPORT_SYMBOL(omap_request_dma);
1a8bfa1e
TL		 791
792void omap_free_dma(int lch)
793{
794 unsigned long flags;
795
1a8bfa1e 796 if (dma_chan[lch].dev_id == -1) {
97b7f715 797 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
1a8bfa1e 798 lch);
1a8bfa1e
TL		 799 return;
800 }
97b7f715 801
1a8bfa1e
TL		 802 if (cpu_class_is_omap1()) {
803 /* Disable all DMA interrupts for the channel. */
0499bdeb 804 dma_write(0, CICR(lch));
1a8bfa1e 805 /* Make sure the DMA transfer is stopped. */
0499bdeb 806 dma_write(0, CCR(lch));
1a8bfa1e
TL		 807 }
808
f8151e5c 809 if (cpu_class_is_omap2()) {
1a8bfa1e 810 u32 val;
ee907324
TH		 811
812 spin_lock_irqsave(&dma_chan_lock, flags);
1a8bfa1e 813 /* Disable interrupts */
0499bdeb 814 val = dma_read(IRQENABLE_L0);
1a8bfa1e 815 val &= ~(1 << lch);
0499bdeb 816 dma_write(val, IRQENABLE_L0);
ee907324 817 spin_unlock_irqrestore(&dma_chan_lock, flags);
1a8bfa1e
TL		 818
819 /* Clear the CSR register and IRQ status register */
0499bdeb
TL		 820 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
821 dma_write(1 << lch, IRQSTATUS_L0);
1a8bfa1e
TL		 822
823 /* Disable all DMA interrupts for the channel. */
0499bdeb 824 dma_write(0, CICR(lch));
1a8bfa1e
TL		 825
826 /* Make sure the DMA transfer is stopped. */
0499bdeb 827 dma_write(0, CCR(lch));
1a8bfa1e
TL		 828 omap_clear_dma(lch);
829 }
da1b94e6
SS		 830
831 spin_lock_irqsave(&dma_chan_lock, flags);
832 dma_chan[lch].dev_id = -1;
833 dma_chan[lch].next_lch = -1;
834 dma_chan[lch].callback = NULL;
835 spin_unlock_irqrestore(&dma_chan_lock, flags);
1a8bfa1e 836}
97b7f715 837EXPORT_SYMBOL(omap_free_dma);
1a8bfa1e 838
f8151e5c
AG		 839/**
840 * @brief omap_dma_set_global_params : Set global priority settings for dma
841 *
842 * @param arb_rate
843 * @param max_fifo_depth
70cf644c
AA		 844 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
845 * DMA_THREAD_RESERVE_ONET
846 * DMA_THREAD_RESERVE_TWOT
847 * DMA_THREAD_RESERVE_THREET
f8151e5c
AG		 848 */
849void
850omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
851{
852 u32 reg;
853
854 if (!cpu_class_is_omap2()) {
8e86f427 855 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
f8151e5c
AG		 856 return;
857 }
858
70cf644c
AA		 859 if (max_fifo_depth == 0)
860 max_fifo_depth = 1;
f8151e5c
AG		 861 if (arb_rate == 0)
862 arb_rate = 1;
863
70cf644c
AA		 864 reg = 0xff & max_fifo_depth;
865 reg |= (0x3 & tparams) << 12;
866 reg |= (arb_rate & 0xff) << 16;
f8151e5c 867
0499bdeb 868 dma_write(reg, GCR);
f8151e5c
AG		 869}
870EXPORT_SYMBOL(omap_dma_set_global_params);
871
872/**
873 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
874 *
875 * @param lch
876 * @param read_prio - Read priority
877 * @param write_prio - Write priority
878 * Both of the above can be set with one of the following values :
879 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
880 */
881int
882omap_dma_set_prio_lch(int lch, unsigned char read_prio,
883 unsigned char write_prio)
884{
0499bdeb 885 u32 l;
f8151e5c 886
4d96372e 887 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
f8151e5c
AG		 888 printk(KERN_ERR "Invalid channel id\n");
889 return -EINVAL;
890 }
0499bdeb
TL		 891 l = dma_read(CCR(lch));
892 l &= ~((1 << 6) | (1 << 26));
44169075 893 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
0499bdeb 894 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
f8151e5c 895 else
0499bdeb
TL		 896 l |= ((read_prio & 0x1) << 6);
897
898 dma_write(l, CCR(lch));
f8151e5c 899
f8151e5c
AG		 900 return 0;
901}
902EXPORT_SYMBOL(omap_dma_set_prio_lch);
903
1a8bfa1e
TL		 904/*
905 * Clears any DMA state so the DMA engine is ready to restart with new buffers
906 * through omap_start_dma(). Any buffers in flight are discarded.
907 */
908void omap_clear_dma(int lch)
909{
910 unsigned long flags;
911
912 local_irq_save(flags);
913
914 if (cpu_class_is_omap1()) {
0499bdeb
TL		 915 u32 l;
916
917 l = dma_read(CCR(lch));
918 l &= ~OMAP_DMA_CCR_EN;
919 dma_write(l, CCR(lch));
1a8bfa1e
TL		 920
921 /* Clear pending interrupts */
0499bdeb 922 l = dma_read(CSR(lch));
1a8bfa1e
TL		 923 }
924
f8151e5c 925 if (cpu_class_is_omap2()) {
1a8bfa1e 926 int i;
0499bdeb 927 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
1a8bfa1e 928 for (i = 0; i < 0x44; i += 4)
0499bdeb 929 __raw_writel(0, lch_base + i);
1a8bfa1e
TL		 930 }
931
932 local_irq_restore(flags);
933}
97b7f715 934EXPORT_SYMBOL(omap_clear_dma);
1a8bfa1e
TL		 935
936void omap_start_dma(int lch)
937{
0499bdeb
TL		 938 u32 l;
939
5e1c5ff4
TL		 940 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
941 int next_lch, cur_lch;
4d96372e 942 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
5e1c5ff4
TL		 943
944 dma_chan_link_map[lch] = 1;
945 /* Set the link register of the first channel */
946 enable_lnk(lch);
947
948 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
949 cur_lch = dma_chan[lch].next_lch;
950 do {
951 next_lch = dma_chan[cur_lch].next_lch;
952
1a8bfa1e 953 /* The loop case: we've been here already */
5e1c5ff4
TL		 954 if (dma_chan_link_map[cur_lch])
955 break;
956 /* Mark the current channel */
957 dma_chan_link_map[cur_lch] = 1;
958
959 enable_lnk(cur_lch);
1a8bfa1e 960 omap_enable_channel_irq(cur_lch);
5e1c5ff4
TL		 961
962 cur_lch = next_lch;
963 } while (next_lch != -1);
284119c4
VP		 964 } else if (cpu_is_omap242x() ||
965 (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) {
966
1a8bfa1e 967 /* Errata: Need to write lch even if not using chaining */
0499bdeb 968 dma_write(lch, CLNK_CTRL(lch));
5e1c5ff4
TL		 969 }
970
1a8bfa1e
TL		 971 omap_enable_channel_irq(lch);
972
0499bdeb
TL		 973 l = dma_read(CCR(lch));
974
97b7f715
TL		 975 /*
976 * Errata: On ES2.0 BUFFERING disable must be set.
977 * This will always fail on ES1.0
978 */
0499bdeb
TL		 979 if (cpu_is_omap24xx())
980 l |= OMAP_DMA_CCR_EN;
1a8bfa1e 981
0499bdeb
TL		 982 l |= OMAP_DMA_CCR_EN;
983 dma_write(l, CCR(lch));
5e1c5ff4 984
5e1c5ff4
TL		 985 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
986}
97b7f715 987EXPORT_SYMBOL(omap_start_dma);
5e1c5ff4
TL		 988
989void omap_stop_dma(int lch)
990{
0499bdeb
TL		 991 u32 l;
992
9da65a99
SS		 993 /* Disable all interrupts on the channel */
994 if (cpu_class_is_omap1())
995 dma_write(0, CICR(lch));
996
997 l = dma_read(CCR(lch));
998 l &= ~OMAP_DMA_CCR_EN;
999 dma_write(l, CCR(lch));
1000
5e1c5ff4
TL		 1001 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
1002 int next_lch, cur_lch = lch;
4d96372e 1003 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
5e1c5ff4
TL		 1004
1005 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
1006 do {
1007 /* The loop case: we've been here already */
1008 if (dma_chan_link_map[cur_lch])
1009 break;
1010 /* Mark the current channel */
1011 dma_chan_link_map[cur_lch] = 1;
1012
1013 disable_lnk(cur_lch);
1014
1015 next_lch = dma_chan[cur_lch].next_lch;
1016 cur_lch = next_lch;
1017 } while (next_lch != -1);
5e1c5ff4 1018 }
1a8bfa1e 1019
5e1c5ff4
TL		 1020 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1021}
97b7f715 1022EXPORT_SYMBOL(omap_stop_dma);
5e1c5ff4 1023
709eb3e5
TL		 1024/*
1025 * Allows changing the DMA callback function or data. This may be needed if
1026 * the driver shares a single DMA channel for multiple dma triggers.
1027 */
1028int omap_set_dma_callback(int lch,
97b7f715 1029 void (*callback)(int lch, u16 ch_status, void *data),
709eb3e5
TL		 1030 void *data)
1031{
1032 unsigned long flags;
1033
1034 if (lch < 0)
1035 return -ENODEV;
1036
1037 spin_lock_irqsave(&dma_chan_lock, flags);
1038 if (dma_chan[lch].dev_id == -1) {
1039 printk(KERN_ERR "DMA callback for not set for free channel\n");
1040 spin_unlock_irqrestore(&dma_chan_lock, flags);
1041 return -EINVAL;
1042 }
1043 dma_chan[lch].callback = callback;
1044 dma_chan[lch].data = data;
1045 spin_unlock_irqrestore(&dma_chan_lock, flags);
1046
1047 return 0;
1048}
97b7f715 1049EXPORT_SYMBOL(omap_set_dma_callback);
709eb3e5 1050
1a8bfa1e
TL		 1051/*
1052 * Returns current physical source address for the given DMA channel.
1053 * If the channel is running the caller must disable interrupts prior calling
1054 * this function and process the returned value before re-enabling interrupt to
1055 * prevent races with the interrupt handler. Note that in continuous mode there
1056 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1057 * in incorrect return value.
1058 */
1059dma_addr_t omap_get_dma_src_pos(int lch)
5e1c5ff4 1060{
0695de32 1061 dma_addr_t offset = 0;
5e1c5ff4 1062
0499bdeb
TL		 1063 if (cpu_is_omap15xx())
1064 offset = dma_read(CPC(lch));
1065 else
1066 offset = dma_read(CSAC(lch));
5e1c5ff4 1067
0499bdeb
TL		 1068 /*
1069 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1070 * read before the DMA controller finished disabling the channel.
1071 */
1072 if (!cpu_is_omap15xx() && offset == 0)
1073 offset = dma_read(CSAC(lch));
1074
1075 if (cpu_class_is_omap1())
1076 offset |= (dma_read(CSSA_U(lch)) << 16);
5e1c5ff4 1077
1a8bfa1e 1078 return offset;
5e1c5ff4 1079}
97b7f715 1080EXPORT_SYMBOL(omap_get_dma_src_pos);
5e1c5ff4 1081
1a8bfa1e
TL		 1082/*
1083 * Returns current physical destination address for the given DMA channel.
1084 * If the channel is running the caller must disable interrupts prior calling
1085 * this function and process the returned value before re-enabling interrupt to
1086 * prevent races with the interrupt handler. Note that in continuous mode there
1087 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1088 * in incorrect return value.
1089 */
1090dma_addr_t omap_get_dma_dst_pos(int lch)
5e1c5ff4 1091{
0695de32 1092 dma_addr_t offset = 0;
5e1c5ff4 1093
0499bdeb
TL		 1094 if (cpu_is_omap15xx())
1095 offset = dma_read(CPC(lch));
1096 else
1097 offset = dma_read(CDAC(lch));
5e1c5ff4 1098
0499bdeb
TL		 1099 /*
1100 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1101 * read before the DMA controller finished disabling the channel.
1102 */
1103 if (!cpu_is_omap15xx() && offset == 0)
1104 offset = dma_read(CDAC(lch));
1105
1106 if (cpu_class_is_omap1())
1107 offset |= (dma_read(CDSA_U(lch)) << 16);
5e1c5ff4 1108
1a8bfa1e 1109 return offset;
5e1c5ff4 1110}
97b7f715 1111EXPORT_SYMBOL(omap_get_dma_dst_pos);
0499bdeb
TL		 1112
1113int omap_get_dma_active_status(int lch)
1114{
1115 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
5e1c5ff4 1116}
0499bdeb 1117EXPORT_SYMBOL(omap_get_dma_active_status);
5e1c5ff4 1118
1a8bfa1e 1119int omap_dma_running(void)
5e1c5ff4 1120{
1a8bfa1e 1121 int lch;
5e1c5ff4 1122
f8e9e984
JK		 1123 if (cpu_class_is_omap1())
1124 if (omap_lcd_dma_running())
1a8bfa1e 1125 return 1;
5e1c5ff4 1126
1a8bfa1e 1127 for (lch = 0; lch < dma_chan_count; lch++)
0499bdeb 1128 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1a8bfa1e 1129 return 1;
5e1c5ff4 1130
1a8bfa1e 1131 return 0;
5e1c5ff4
TL		 1132}
1133
1134/*
1135 * lch_queue DMA will start right after lch_head one is finished.
1136 * For this DMA link to start, you still need to start (see omap_start_dma)
1137 * the first one. That will fire up the entire queue.
1138 */
97b7f715 1139void omap_dma_link_lch(int lch_head, int lch_queue)
5e1c5ff4
TL		 1140{
1141 if (omap_dma_in_1510_mode()) {
9f0f4ae5
JK		 1142 if (lch_head == lch_queue) {
1143 dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1144 CCR(lch_head));
1145 return;
1146 }
5e1c5ff4
TL		 1147 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1148 BUG();
1149 return;
1150 }
1151
1152 if ((dma_chan[lch_head].dev_id == -1) ||
1153 (dma_chan[lch_queue].dev_id == -1)) {
1a8bfa1e
TL		 1154 printk(KERN_ERR "omap_dma: trying to link "
1155 "non requested channels\n");
5e1c5ff4
TL		 1156 dump_stack();
1157 }
1158
1159 dma_chan[lch_head].next_lch = lch_queue;
1160}
97b7f715 1161EXPORT_SYMBOL(omap_dma_link_lch);
5e1c5ff4
TL		 1162
1163/*
1164 * Once the DMA queue is stopped, we can destroy it.
1165 */
97b7f715 1166void omap_dma_unlink_lch(int lch_head, int lch_queue)
5e1c5ff4
TL		 1167{
1168 if (omap_dma_in_1510_mode()) {
9f0f4ae5
JK		 1169 if (lch_head == lch_queue) {
1170 dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1171 CCR(lch_head));
1172 return;
1173 }
5e1c5ff4
TL		 1174 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1175 BUG();
1176 return;
1177 }
1178
1179 if (dma_chan[lch_head].next_lch != lch_queue ||
1180 dma_chan[lch_head].next_lch == -1) {
1a8bfa1e
TL		 1181 printk(KERN_ERR "omap_dma: trying to unlink "
1182 "non linked channels\n");
5e1c5ff4
TL		 1183 dump_stack();
1184 }
1185
5e1c5ff4 1186 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
247421fd 1187 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1a8bfa1e
TL		 1188 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1189 "before unlinking\n");
5e1c5ff4
TL		 1190 dump_stack();
1191 }
1192
1193 dma_chan[lch_head].next_lch = -1;
1194}
97b7f715
TL		 1195EXPORT_SYMBOL(omap_dma_unlink_lch);
1196
1197/*----------------------------------------------------------------------------*/
5e1c5ff4 1198
f8151e5c
AG		 1199#ifndef CONFIG_ARCH_OMAP1
1200/* Create chain of DMA channesls */
1201static void create_dma_lch_chain(int lch_head, int lch_queue)
1202{
0499bdeb 1203 u32 l;
f8151e5c
AG		 1204
1205 /* Check if this is the first link in chain */
1206 if (dma_chan[lch_head].next_linked_ch == -1) {
1207 dma_chan[lch_head].next_linked_ch = lch_queue;
1208 dma_chan[lch_head].prev_linked_ch = lch_queue;
1209 dma_chan[lch_queue].next_linked_ch = lch_head;
1210 dma_chan[lch_queue].prev_linked_ch = lch_head;
1211 }
1212
1213 /* a link exists, link the new channel in circular chain */
1214 else {
1215 dma_chan[lch_queue].next_linked_ch =
1216 dma_chan[lch_head].next_linked_ch;
1217 dma_chan[lch_queue].prev_linked_ch = lch_head;
1218 dma_chan[lch_head].next_linked_ch = lch_queue;
1219 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1220 lch_queue;
1221 }
1222
0499bdeb
TL		 1223 l = dma_read(CLNK_CTRL(lch_head));
1224 l &= ~(0x1f);
1225 l |= lch_queue;
1226 dma_write(l, CLNK_CTRL(lch_head));
f8151e5c 1227
0499bdeb
TL		 1228 l = dma_read(CLNK_CTRL(lch_queue));
1229 l &= ~(0x1f);
1230 l |= (dma_chan[lch_queue].next_linked_ch);
1231 dma_write(l, CLNK_CTRL(lch_queue));
f8151e5c
AG		 1232}
1233
1234/**
1235 * @brief omap_request_dma_chain : Request a chain of DMA channels
1236 *
1237 * @param dev_id - Device id using the dma channel
1238 * @param dev_name - Device name
1239 * @param callback - Call back function
1240 * @chain_id -
1241 * @no_of_chans - Number of channels requested
1242 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1243 * OMAP_DMA_DYNAMIC_CHAIN
1244 * @params - Channel parameters
1245 *
af901ca1 1246 * @return - Success : 0
f8151e5c
AG		 1247 * Failure: -EINVAL/-ENOMEM
1248 */
1249int omap_request_dma_chain(int dev_id, const char *dev_name,
279b918d 1250 void (*callback) (int lch, u16 ch_status,
f8151e5c
AG		 1251 void *data),
1252 int *chain_id, int no_of_chans, int chain_mode,
1253 struct omap_dma_channel_params params)
1254{
1255 int *channels;
1256 int i, err;
1257
1258 /* Is the chain mode valid ? */
1259 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1260 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1261 printk(KERN_ERR "Invalid chain mode requested\n");
1262 return -EINVAL;
1263 }
1264
1265 if (unlikely((no_of_chans < 1
4d96372e 1266 || no_of_chans > dma_lch_count))) {
f8151e5c
AG		 1267 printk(KERN_ERR "Invalid Number of channels requested\n");
1268 return -EINVAL;
1269 }
1270
1271 /* Allocate a queue to maintain the status of the channels
1272 * in the chain */
1273 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1274 if (channels == NULL) {
1275 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1276 return -ENOMEM;
1277 }
1278
1279 /* request and reserve DMA channels for the chain */
1280 for (i = 0; i < no_of_chans; i++) {
1281 err = omap_request_dma(dev_id, dev_name,
c0fc18c5 1282 callback, NULL, &channels[i]);
f8151e5c
AG		 1283 if (err < 0) {
1284 int j;
1285 for (j = 0; j < i; j++)
1286 omap_free_dma(channels[j]);
1287 kfree(channels);
1288 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1289 return err;
1290 }
f8151e5c
AG		 1291 dma_chan[channels[i]].prev_linked_ch = -1;
1292 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1293
1294 /*
1295 * Allowing client drivers to set common parameters now,
1296 * so that later only relevant (src_start, dest_start
1297 * and element count) can be set
1298 */
1299 omap_set_dma_params(channels[i], &params);
1300 }
1301
1302 *chain_id = channels[0];
1303 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1304 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1305 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1306 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1307
1308 for (i = 0; i < no_of_chans; i++)
1309 dma_chan[channels[i]].chain_id = *chain_id;
1310
1311 /* Reset the Queue pointers */
1312 OMAP_DMA_CHAIN_QINIT(*chain_id);
1313
1314 /* Set up the chain */
1315 if (no_of_chans == 1)
1316 create_dma_lch_chain(channels[0], channels[0]);
1317 else {
1318 for (i = 0; i < (no_of_chans - 1); i++)
1319 create_dma_lch_chain(channels[i], channels[i + 1]);
1320 }
97b7f715 1321
f8151e5c
AG		 1322 return 0;
1323}
1324EXPORT_SYMBOL(omap_request_dma_chain);
1325
1326/**
1327 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1328 * params after setting it. Dont do this while dma is running!!
1329 *
1330 * @param chain_id - Chained logical channel id.
1331 * @param params
1332 *
1333 * @return - Success : 0
1334 * Failure : -EINVAL
1335 */
1336int omap_modify_dma_chain_params(int chain_id,
1337 struct omap_dma_channel_params params)
1338{
1339 int *channels;
1340 u32 i;
1341
1342 /* Check for input params */
1343 if (unlikely((chain_id < 0
4d96372e 1344 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1345 printk(KERN_ERR "Invalid chain id\n");
1346 return -EINVAL;
1347 }
1348
1349 /* Check if the chain exists */
1350 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1351 printk(KERN_ERR "Chain doesn't exists\n");
1352 return -EINVAL;
1353 }
1354 channels = dma_linked_lch[chain_id].linked_dmach_q;
1355
1356 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1357 /*
1358 * Allowing client drivers to set common parameters now,
1359 * so that later only relevant (src_start, dest_start
1360 * and element count) can be set
1361 */
1362 omap_set_dma_params(channels[i], &params);
1363 }
97b7f715 1364
f8151e5c
AG		 1365 return 0;
1366}
1367EXPORT_SYMBOL(omap_modify_dma_chain_params);
1368
1369/**
1370 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1371 *
1372 * @param chain_id
1373 *
1374 * @return - Success : 0
1375 * Failure : -EINVAL
1376 */
1377int omap_free_dma_chain(int chain_id)
1378{
1379 int *channels;
1380 u32 i;
1381
1382 /* Check for input params */
4d96372e 1383 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1384 printk(KERN_ERR "Invalid chain id\n");
1385 return -EINVAL;
1386 }
1387
1388 /* Check if the chain exists */
1389 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1390 printk(KERN_ERR "Chain doesn't exists\n");
1391 return -EINVAL;
1392 }
1393
1394 channels = dma_linked_lch[chain_id].linked_dmach_q;
1395 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1396 dma_chan[channels[i]].next_linked_ch = -1;
1397 dma_chan[channels[i]].prev_linked_ch = -1;
1398 dma_chan[channels[i]].chain_id = -1;
1399 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1400 omap_free_dma(channels[i]);
1401 }
1402
1403 kfree(channels);
1404
1405 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1406 dma_linked_lch[chain_id].chain_mode = -1;
1407 dma_linked_lch[chain_id].chain_state = -1;
97b7f715 1408
f8151e5c
AG		 1409 return (0);
1410}
1411EXPORT_SYMBOL(omap_free_dma_chain);
1412
1413/**
1414 * @brief omap_dma_chain_status - Check if the chain is in
1415 * active / inactive state.
1416 * @param chain_id
1417 *
1418 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1419 * Failure : -EINVAL
1420 */
1421int omap_dma_chain_status(int chain_id)
1422{
1423 /* Check for input params */
4d96372e 1424 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1425 printk(KERN_ERR "Invalid chain id\n");
1426 return -EINVAL;
1427 }
1428
1429 /* Check if the chain exists */
1430 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1431 printk(KERN_ERR "Chain doesn't exists\n");
1432 return -EINVAL;
1433 }
1434 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1435 dma_linked_lch[chain_id].q_count);
1436
1437 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1438 return OMAP_DMA_CHAIN_INACTIVE;
97b7f715 1439
f8151e5c
AG		 1440 return OMAP_DMA_CHAIN_ACTIVE;
1441}
1442EXPORT_SYMBOL(omap_dma_chain_status);
1443
1444/**
1445 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1446 * set the params and start the transfer.
1447 *
1448 * @param chain_id
1449 * @param src_start - buffer start address
1450 * @param dest_start - Dest address
1451 * @param elem_count
1452 * @param frame_count
1453 * @param callbk_data - channel callback parameter data.
1454 *
f4b6a7ef 1455 * @return - Success : 0
f8151e5c
AG		 1456 * Failure: -EINVAL/-EBUSY
1457 */
1458int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1459 int elem_count, int frame_count, void *callbk_data)
1460{
1461 int *channels;
0499bdeb 1462 u32 l, lch;
f8151e5c
AG		 1463 int start_dma = 0;
1464
97b7f715
TL		 1465 /*
1466 * if buffer size is less than 1 then there is
1467 * no use of starting the chain
1468 */
f8151e5c
AG		 1469 if (elem_count < 1) {
1470 printk(KERN_ERR "Invalid buffer size\n");
1471 return -EINVAL;
1472 }
1473
1474 /* Check for input params */
1475 if (unlikely((chain_id < 0
4d96372e 1476 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1477 printk(KERN_ERR "Invalid chain id\n");
1478 return -EINVAL;
1479 }
1480
1481 /* Check if the chain exists */
1482 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1483 printk(KERN_ERR "Chain doesn't exist\n");
1484 return -EINVAL;
1485 }
1486
1487 /* Check if all the channels in chain are in use */
1488 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1489 return -EBUSY;
1490
1491 /* Frame count may be negative in case of indexed transfers */
1492 channels = dma_linked_lch[chain_id].linked_dmach_q;
1493
1494 /* Get a free channel */
1495 lch = channels[dma_linked_lch[chain_id].q_tail];
1496
1497 /* Store the callback data */
1498 dma_chan[lch].data = callbk_data;
1499
1500 /* Increment the q_tail */
1501 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1502
1503 /* Set the params to the free channel */
1504 if (src_start != 0)
0499bdeb 1505 dma_write(src_start, CSSA(lch));
f8151e5c 1506 if (dest_start != 0)
0499bdeb 1507 dma_write(dest_start, CDSA(lch));
f8151e5c
AG		 1508
1509 /* Write the buffer size */
0499bdeb
TL		 1510 dma_write(elem_count, CEN(lch));
1511 dma_write(frame_count, CFN(lch));
f8151e5c 1512
97b7f715
TL		 1513 /*
1514 * If the chain is dynamically linked,
1515 * then we may have to start the chain if its not active
1516 */
f8151e5c
AG		 1517 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1518
97b7f715
TL		 1519 /*
1520 * In Dynamic chain, if the chain is not started,
1521 * queue the channel
1522 */
f8151e5c
AG		 1523 if (dma_linked_lch[chain_id].chain_state ==
1524 DMA_CHAIN_NOTSTARTED) {
1525 /* Enable the link in previous channel */
1526 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1527 DMA_CH_QUEUED)
1528 enable_lnk(dma_chan[lch].prev_linked_ch);
1529 dma_chan[lch].state = DMA_CH_QUEUED;
1530 }
1531
97b7f715
TL		 1532 /*
1533 * Chain is already started, make sure its active,
1534 * if not then start the chain
1535 */
f8151e5c
AG		 1536 else {
1537 start_dma = 1;
1538
1539 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1540 DMA_CH_STARTED) {
1541 enable_lnk(dma_chan[lch].prev_linked_ch);
1542 dma_chan[lch].state = DMA_CH_QUEUED;
1543 start_dma = 0;
0499bdeb
TL		 1544 if (0 == ((1 << 7) & dma_read(
1545 CCR(dma_chan[lch].prev_linked_ch)))) {
f8151e5c
AG		 1546 disable_lnk(dma_chan[lch].
1547 prev_linked_ch);
1548 pr_debug("\n prev ch is stopped\n");
1549 start_dma = 1;
1550 }
1551 }
1552
1553 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1554 == DMA_CH_QUEUED) {
1555 enable_lnk(dma_chan[lch].prev_linked_ch);
1556 dma_chan[lch].state = DMA_CH_QUEUED;
1557 start_dma = 0;
1558 }
1559 omap_enable_channel_irq(lch);
1560
0499bdeb 1561 l = dma_read(CCR(lch));
f8151e5c 1562
0499bdeb
TL		 1563 if ((0 == (l & (1 << 24))))
1564 l &= ~(1 << 25);
f8151e5c 1565 else
0499bdeb 1566 l |= (1 << 25);
f8151e5c 1567 if (start_dma == 1) {
0499bdeb
TL		 1568 if (0 == (l & (1 << 7))) {
1569 l |= (1 << 7);
f8151e5c
AG		 1570 dma_chan[lch].state = DMA_CH_STARTED;
1571 pr_debug("starting %d\n", lch);
0499bdeb 1572 dma_write(l, CCR(lch));
f8151e5c
AG		 1573 } else
1574 start_dma = 0;
1575 } else {
0499bdeb
TL		 1576 if (0 == (l & (1 << 7)))
1577 dma_write(l, CCR(lch));
f8151e5c
AG		 1578 }
1579 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1580 }
1581 }
97b7f715 1582
f4b6a7ef 1583 return 0;
f8151e5c
AG		 1584}
1585EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1586
1587/**
1588 * @brief omap_start_dma_chain_transfers - Start the chain
1589 *
1590 * @param chain_id
1591 *
1592 * @return - Success : 0
1593 * Failure : -EINVAL/-EBUSY
1594 */
1595int omap_start_dma_chain_transfers(int chain_id)
1596{
1597 int *channels;
0499bdeb 1598 u32 l, i;
f8151e5c 1599
4d96372e 1600 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1601 printk(KERN_ERR "Invalid chain id\n");
1602 return -EINVAL;
1603 }
1604
1605 channels = dma_linked_lch[chain_id].linked_dmach_q;
1606
1607 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1608 printk(KERN_ERR "Chain is already started\n");
1609 return -EBUSY;
1610 }
1611
1612 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1613 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1614 i++) {
1615 enable_lnk(channels[i]);
1616 omap_enable_channel_irq(channels[i]);
1617 }
1618 } else {
1619 omap_enable_channel_irq(channels[0]);
1620 }
1621
0499bdeb
TL		 1622 l = dma_read(CCR(channels[0]));
1623 l |= (1 << 7);
f8151e5c
AG		 1624 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1625 dma_chan[channels[0]].state = DMA_CH_STARTED;
1626
0499bdeb
TL		 1627 if ((0 == (l & (1 << 24))))
1628 l &= ~(1 << 25);
f8151e5c 1629 else
0499bdeb
TL		 1630 l |= (1 << 25);
1631 dma_write(l, CCR(channels[0]));
f8151e5c
AG		 1632
1633 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
97b7f715 1634
f8151e5c
AG		 1635 return 0;
1636}
1637EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1638
1639/**
1640 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1641 *
1642 * @param chain_id
1643 *
1644 * @return - Success : 0
1645 * Failure : EINVAL
1646 */
1647int omap_stop_dma_chain_transfers(int chain_id)
1648{
1649 int *channels;
0499bdeb 1650 u32 l, i;
f8151e5c
AG		 1651 u32 sys_cf;
1652
1653 /* Check for input params */
4d96372e 1654 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1655 printk(KERN_ERR "Invalid chain id\n");
1656 return -EINVAL;
1657 }
1658
1659 /* Check if the chain exists */
1660 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1661 printk(KERN_ERR "Chain doesn't exists\n");
1662 return -EINVAL;
1663 }
1664 channels = dma_linked_lch[chain_id].linked_dmach_q;
1665
97b7f715
TL		 1666 /*
1667 * DMA Errata:
f8151e5c
AG		 1668 * Special programming model needed to disable DMA before end of block
1669 */
0499bdeb
TL		 1670 sys_cf = dma_read(OCP_SYSCONFIG);
1671 l = sys_cf;
f8151e5c 1672 /* Middle mode reg set no Standby */
0499bdeb
TL		 1673 l &= ~((1 << 12)|(1 << 13));
1674 dma_write(l, OCP_SYSCONFIG);
f8151e5c
AG		 1675
1676 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1677
1678 /* Stop the Channel transmission */
0499bdeb
TL		 1679 l = dma_read(CCR(channels[i]));
1680 l &= ~(1 << 7);
1681 dma_write(l, CCR(channels[i]));
f8151e5c
AG		 1682
1683 /* Disable the link in all the channels */
1684 disable_lnk(channels[i]);
1685 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1686
1687 }
1688 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1689
1690 /* Reset the Queue pointers */
1691 OMAP_DMA_CHAIN_QINIT(chain_id);
1692
1693 /* Errata - put in the old value */
0499bdeb 1694 dma_write(sys_cf, OCP_SYSCONFIG);
97b7f715 1695
f8151e5c
AG		 1696 return 0;
1697}
1698EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1699
1700/* Get the index of the ongoing DMA in chain */
1701/**
1702 * @brief omap_get_dma_chain_index - Get the element and frame index
1703 * of the ongoing DMA in chain
1704 *
1705 * @param chain_id
1706 * @param ei - Element index
1707 * @param fi - Frame index
1708 *
1709 * @return - Success : 0
1710 * Failure : -EINVAL
1711 */
1712int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1713{
1714 int lch;
1715 int *channels;
1716
1717 /* Check for input params */
4d96372e 1718 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1719 printk(KERN_ERR "Invalid chain id\n");
1720 return -EINVAL;
1721 }
1722
1723 /* Check if the chain exists */
1724 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1725 printk(KERN_ERR "Chain doesn't exists\n");
1726 return -EINVAL;
1727 }
1728 if ((!ei) || (!fi))
1729 return -EINVAL;
1730
1731 channels = dma_linked_lch[chain_id].linked_dmach_q;
1732
1733 /* Get the current channel */
1734 lch = channels[dma_linked_lch[chain_id].q_head];
1735
0499bdeb
TL		 1736 *ei = dma_read(CCEN(lch));
1737 *fi = dma_read(CCFN(lch));
f8151e5c
AG		 1738
1739 return 0;
1740}
1741EXPORT_SYMBOL(omap_get_dma_chain_index);
1742
1743/**
1744 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1745 * ongoing DMA in chain
1746 *
1747 * @param chain_id
1748 *
1749 * @return - Success : Destination position
1750 * Failure : -EINVAL
1751 */
1752int omap_get_dma_chain_dst_pos(int chain_id)
1753{
1754 int lch;
1755 int *channels;
1756
1757 /* Check for input params */
4d96372e 1758 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1759 printk(KERN_ERR "Invalid chain id\n");
1760 return -EINVAL;
1761 }
1762
1763 /* Check if the chain exists */
1764 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1765 printk(KERN_ERR "Chain doesn't exists\n");
1766 return -EINVAL;
1767 }
1768
1769 channels = dma_linked_lch[chain_id].linked_dmach_q;
1770
1771 /* Get the current channel */
1772 lch = channels[dma_linked_lch[chain_id].q_head];
1773
0499bdeb 1774 return dma_read(CDAC(lch));
f8151e5c
AG		 1775}
1776EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1777
1778/**
1779 * @brief omap_get_dma_chain_src_pos - Get the source position
1780 * of the ongoing DMA in chain
1781 * @param chain_id
1782 *
1783 * @return - Success : Destination position
1784 * Failure : -EINVAL
1785 */
1786int omap_get_dma_chain_src_pos(int chain_id)
1787{
1788 int lch;
1789 int *channels;
1790
1791 /* Check for input params */
4d96372e 1792 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1793 printk(KERN_ERR "Invalid chain id\n");
1794 return -EINVAL;
1795 }
1796
1797 /* Check if the chain exists */
1798 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1799 printk(KERN_ERR "Chain doesn't exists\n");
1800 return -EINVAL;
1801 }
1802
1803 channels = dma_linked_lch[chain_id].linked_dmach_q;
1804
1805 /* Get the current channel */
1806 lch = channels[dma_linked_lch[chain_id].q_head];
1807
0499bdeb 1808 return dma_read(CSAC(lch));
f8151e5c
AG		 1809}
1810EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
97b7f715 1811#endif /* ifndef CONFIG_ARCH_OMAP1 */
f8151e5c 1812
1a8bfa1e
TL		 1813/*----------------------------------------------------------------------------*/
1814
1815#ifdef CONFIG_ARCH_OMAP1
1816
1817static int omap1_dma_handle_ch(int ch)
1818{
0499bdeb 1819 u32 csr;
1a8bfa1e
TL		 1820
1821 if (enable_1510_mode && ch >= 6) {
1822 csr = dma_chan[ch].saved_csr;
1823 dma_chan[ch].saved_csr = 0;
1824 } else
0499bdeb 1825 csr = dma_read(CSR(ch));
1a8bfa1e
TL		 1826 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1827 dma_chan[ch + 6].saved_csr = csr >> 7;
1828 csr &= 0x7f;
1829 }
1830 if ((csr & 0x3f) == 0)
1831 return 0;
1832 if (unlikely(dma_chan[ch].dev_id == -1)) {
1833 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1834 "%d (CSR %04x)\n", ch, csr);
1835 return 0;
1836 }
7ff879db 1837 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1a8bfa1e
TL		 1838 printk(KERN_WARNING "DMA timeout with device %d\n",
1839 dma_chan[ch].dev_id);
1840 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1841 printk(KERN_WARNING "DMA synchronization event drop occurred "
1842 "with device %d\n", dma_chan[ch].dev_id);
1843 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1844 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1845 if (likely(dma_chan[ch].callback != NULL))
1846 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
97b7f715 1847
1a8bfa1e
TL		 1848 return 1;
1849}
1850
0cd61b68 1851static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1a8bfa1e
TL		 1852{
1853 int ch = ((int) dev_id) - 1;
1854 int handled = 0;
1855
1856 for (;;) {
1857 int handled_now = 0;
1858
1859 handled_now += omap1_dma_handle_ch(ch);
1860 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1861 handled_now += omap1_dma_handle_ch(ch + 6);
1862 if (!handled_now)
1863 break;
1864 handled += handled_now;
1865 }
1866
1867 return handled ? IRQ_HANDLED : IRQ_NONE;
1868}
1869
1870#else
1871#define omap1_dma_irq_handler NULL
1872#endif
1873
140455fa 1874#ifdef CONFIG_ARCH_OMAP2PLUS
1a8bfa1e
TL		 1875
1876static int omap2_dma_handle_ch(int ch)
1877{
0499bdeb 1878 u32 status = dma_read(CSR(ch));
1a8bfa1e 1879
3151369d
JY		 1880 if (!status) {
1881 if (printk_ratelimit())
97b7f715
TL		 1882 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1883 ch);
0499bdeb 1884 dma_write(1 << ch, IRQSTATUS_L0);
1a8bfa1e 1885 return 0;
3151369d
JY		 1886 }
1887 if (unlikely(dma_chan[ch].dev_id == -1)) {
1888 if (printk_ratelimit())
1889 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1890 "channel %d\n", status, ch);
1a8bfa1e 1891 return 0;
3151369d 1892 }
1a8bfa1e
TL		 1893 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1894 printk(KERN_INFO
1895 "DMA synchronization event drop occurred with device "
1896 "%d\n", dma_chan[ch].dev_id);
a50f18c7 1897 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1a8bfa1e
TL		 1898 printk(KERN_INFO "DMA transaction error with device %d\n",
1899 dma_chan[ch].dev_id);
a50f18c7
SS		 1900 if (cpu_class_is_omap2()) {
1901 /* Errata: sDMA Channel is not disabled
1902 * after a transaction error. So we explicitely
1903 * disable the channel
1904 */
1905 u32 ccr;
1906
1907 ccr = dma_read(CCR(ch));
1908 ccr &= ~OMAP_DMA_CCR_EN;
1909 dma_write(ccr, CCR(ch));
1910 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1911 }
1912 }
7ff879db
TL		 1913 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1914 printk(KERN_INFO "DMA secure error with device %d\n",
1915 dma_chan[ch].dev_id);
1916 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1917 printk(KERN_INFO "DMA misaligned error with device %d\n",
1918 dma_chan[ch].dev_id);
1a8bfa1e 1919
0499bdeb
TL		 1920 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1921 dma_write(1 << ch, IRQSTATUS_L0);
1a8bfa1e 1922
f8151e5c
AG		 1923 /* If the ch is not chained then chain_id will be -1 */
1924 if (dma_chan[ch].chain_id != -1) {
1925 int chain_id = dma_chan[ch].chain_id;
1926 dma_chan[ch].state = DMA_CH_NOTSTARTED;
0499bdeb 1927 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
f8151e5c
AG		 1928 dma_chan[dma_chan[ch].next_linked_ch].state =
1929 DMA_CH_STARTED;
1930 if (dma_linked_lch[chain_id].chain_mode ==
1931 OMAP_DMA_DYNAMIC_CHAIN)
1932 disable_lnk(ch);
1933
1934 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1935 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1936
0499bdeb 1937 status = dma_read(CSR(ch));
f8151e5c
AG		 1938 }
1939
320ce6f6
JY		 1940 dma_write(status, CSR(ch));
1941
538528de
JN		 1942 if (likely(dma_chan[ch].callback != NULL))
1943 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
f8151e5c 1944
1a8bfa1e
TL		 1945 return 0;
1946}
1947
1948/* STATUS register count is from 1-32 while our is 0-31 */
0cd61b68 1949static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1a8bfa1e 1950{
52176e70 1951 u32 val, enable_reg;
1a8bfa1e
TL		 1952 int i;
1953
0499bdeb 1954 val = dma_read(IRQSTATUS_L0);
3151369d
JY		 1955 if (val == 0) {
1956 if (printk_ratelimit())
1957 printk(KERN_WARNING "Spurious DMA IRQ\n");
1958 return IRQ_HANDLED;
1959 }
52176e70
SS		 1960 enable_reg = dma_read(IRQENABLE_L0);
1961 val &= enable_reg; /* Dispatch only relevant interrupts */
4d96372e 1962 for (i = 0; i < dma_lch_count && val != 0; i++) {
3151369d
JY		 1963 if (val & 1)
1964 omap2_dma_handle_ch(i);
1965 val >>= 1;
1a8bfa1e
TL		 1966 }
1967
1968 return IRQ_HANDLED;
1969}
1970
1971static struct irqaction omap24xx_dma_irq = {
1972 .name = "DMA",
1973 .handler = omap2_dma_irq_handler,
52e405ea 1974 .flags = IRQF_DISABLED
1a8bfa1e
TL		 1975};
1976
1977#else
1978static struct irqaction omap24xx_dma_irq;
1979#endif
1980
1981/*----------------------------------------------------------------------------*/
5e1c5ff4 1982
f2d11858
TK		 1983void omap_dma_global_context_save(void)
1984{
1985 omap_dma_global_context.dma_irqenable_l0 =
1986 dma_read(IRQENABLE_L0);
1987 omap_dma_global_context.dma_ocp_sysconfig =
1988 dma_read(OCP_SYSCONFIG);
1989 omap_dma_global_context.dma_gcr = dma_read(GCR);
1990}
1991
1992void omap_dma_global_context_restore(void)
1993{
bf07c9f2
AK		 1994 int ch;
1995
f2d11858
TK		 1996 dma_write(omap_dma_global_context.dma_gcr, GCR);
1997 dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1998 OCP_SYSCONFIG);
1999 dma_write(omap_dma_global_context.dma_irqenable_l0,
2000 IRQENABLE_L0);
f2d11858 2001
ba50ea7e
KJ		 2002 /*
2003 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
2004 * after secure sram context save and restore. Hence we need to
2005 * manually clear those IRQs to avoid spurious interrupts. This
2006 * affects only secure devices.
2007 */
2008 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
2009 dma_write(0x3 , IRQSTATUS_L0);
bf07c9f2
AK		 2010
2011 for (ch = 0; ch < dma_chan_count; ch++)
2012 if (dma_chan[ch].dev_id != -1)
2013 omap_clear_dma(ch);
f2d11858
TK		 2014}
2015
1a8bfa1e 2016/*----------------------------------------------------------------------------*/
bb13b5fd 2017
5e1c5ff4
TL		 2018static int __init omap_init_dma(void)
2019{
7e9bf847 2020 unsigned long base;
5e1c5ff4
TL		 2021 int ch, r;
2022
0499bdeb 2023 if (cpu_class_is_omap1()) {
7e9bf847 2024 base = OMAP1_DMA_BASE;
4d96372e 2025 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
0499bdeb 2026 } else if (cpu_is_omap24xx()) {
7e9bf847 2027 base = OMAP24XX_DMA4_BASE;
4d96372e 2028 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
0499bdeb 2029 } else if (cpu_is_omap34xx()) {
7e9bf847 2030 base = OMAP34XX_DMA4_BASE;
0499bdeb 2031 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
44169075 2032 } else if (cpu_is_omap44xx()) {
7e9bf847 2033 base = OMAP44XX_DMA4_BASE;
44169075 2034 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
0499bdeb
TL		 2035 } else {
2036 pr_err("DMA init failed for unsupported omap\n");
2037 return -ENODEV;
2038 }
4d96372e 2039
7e9bf847
TL		 2040 omap_dma_base = ioremap(base, SZ_4K);
2041 BUG_ON(!omap_dma_base);
2042
2263f022
SS		 2043 if (cpu_class_is_omap2() && omap_dma_reserve_channels
2044 && (omap_dma_reserve_channels <= dma_lch_count))
2045 dma_lch_count = omap_dma_reserve_channels;
2046
4d96372e
TL		 2047 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2048 GFP_KERNEL);
7e9bf847
TL		 2049 if (!dma_chan) {
2050 r = -ENOMEM;
2051 goto out_unmap;
2052 }
4d96372e
TL		 2053
2054 if (cpu_class_is_omap2()) {
2055 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2056 dma_lch_count, GFP_KERNEL);
2057 if (!dma_linked_lch) {
7e9bf847
TL		 2058 r = -ENOMEM;
2059 goto out_free;
4d96372e
TL		 2060 }
2061 }
2062
1a8bfa1e
TL		 2063 if (cpu_is_omap15xx()) {
2064 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
5e1c5ff4
TL		 2065 dma_chan_count = 9;
2066 enable_1510_mode = 1;
557096fe 2067 } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
5e1c5ff4 2068 printk(KERN_INFO "OMAP DMA hardware version %d\n",
0499bdeb 2069 dma_read(HW_ID));
5e1c5ff4 2070 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
0499bdeb
TL		 2071 (dma_read(CAPS_0_U) << 16) |
2072 dma_read(CAPS_0_L),
2073 (dma_read(CAPS_1_U) << 16) |
2074 dma_read(CAPS_1_L),
2075 dma_read(CAPS_2), dma_read(CAPS_3),
2076 dma_read(CAPS_4));
5e1c5ff4
TL		 2077 if (!enable_1510_mode) {
2078 u16 w;
2079
2080 /* Disable OMAP 3.0/3.1 compatibility mode. */
0499bdeb 2081 w = dma_read(GSCR);
5e1c5ff4 2082 w |= 1 << 3;
0499bdeb 2083 dma_write(w, GSCR);
5e1c5ff4
TL		 2084 dma_chan_count = 16;
2085 } else
2086 dma_chan_count = 9;
f8151e5c 2087 } else if (cpu_class_is_omap2()) {
0499bdeb 2088 u8 revision = dma_read(REVISION) & 0xff;
1a8bfa1e
TL		 2089 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2090 revision >> 4, revision & 0xf);
2263f022 2091 dma_chan_count = dma_lch_count;
5e1c5ff4
TL		 2092 } else {
2093 dma_chan_count = 0;
2094 return 0;
2095 }
2096
5e1c5ff4 2097 spin_lock_init(&dma_chan_lock);
5e1c5ff4
TL		 2098
2099 for (ch = 0; ch < dma_chan_count; ch++) {
1a8bfa1e 2100 omap_clear_dma(ch);
5e1c5ff4
TL		 2101 dma_chan[ch].dev_id = -1;
2102 dma_chan[ch].next_lch = -1;
2103
2104 if (ch >= 6 && enable_1510_mode)
2105 continue;
2106
1a8bfa1e 2107 if (cpu_class_is_omap1()) {
97b7f715
TL		 2108 /*
2109 * request_irq() doesn't like dev_id (ie. ch) being
2110 * zero, so we have to kludge around this.
2111 */
1a8bfa1e
TL		 2112 r = request_irq(omap1_dma_irq[ch],
2113 omap1_dma_irq_handler, 0, "DMA",
2114 (void *) (ch + 1));
2115 if (r != 0) {
2116 int i;
2117
2118 printk(KERN_ERR "unable to request IRQ %d "
2119 "for DMA (error %d)\n",
2120 omap1_dma_irq[ch], r);
2121 for (i = 0; i < ch; i++)
2122 free_irq(omap1_dma_irq[i],
2123 (void *) (i + 1));
7e9bf847 2124 goto out_free;
1a8bfa1e
TL		 2125 }
2126 }
2127 }
2128
44169075 2129 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
f8151e5c
AG		 2130 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2131 DMA_DEFAULT_FIFO_DEPTH, 0);
2132
44169075
SS		 2133 if (cpu_class_is_omap2()) {
2134 int irq;
2135 if (cpu_is_omap44xx())
5772ca7d 2136 irq = OMAP44XX_IRQ_SDMA_0;
44169075
SS		 2137 else
2138 irq = INT_24XX_SDMA_IRQ0;
2139 setup_irq(irq, &omap24xx_dma_irq);
2140 }
1a8bfa1e 2141
1ce0f9d4 2142 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
ba50ea7e 2143 /* Enable smartidle idlemodes and autoidle */
aecedb94
KJ		 2144 u32 v = dma_read(OCP_SYSCONFIG);
2145 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2146 DMA_SYSCONFIG_SIDLEMODE_MASK |
2147 DMA_SYSCONFIG_AUTOIDLE);
2148 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2149 DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2150 DMA_SYSCONFIG_AUTOIDLE);
2151 dma_write(v , OCP_SYSCONFIG);
ba50ea7e 2152 /* reserve dma channels 0 and 1 in high security devices */
35c0dc38
SS		 2153 if (cpu_is_omap34xx() &&
2154 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
ba50ea7e
KJ		 2155 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2156 "HS ROM code\n");
2157 dma_chan[0].dev_id = 0;
2158 dma_chan[1].dev_id = 1;
2159 }
aecedb94
KJ		 2160 }
2161
5e1c5ff4 2162 return 0;
7e9bf847
TL		 2163
2164out_free:
2165 kfree(dma_chan);
2166
2167out_unmap:
2168 iounmap(omap_dma_base);
2169
2170 return r;
5e1c5ff4
TL		 2171}
2172
2173arch_initcall(omap_init_dma);
2174
2263f022
SS		 2175/*
2176 * Reserve the omap SDMA channels using cmdline bootarg
2177 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2178 */
2179static int __init omap_dma_cmdline_reserve_ch(char *str)
2180{
2181 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2182 omap_dma_reserve_channels = 0;
2183 return 1;
2184}
2185
2186__setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2187
5e1c5ff4 2188
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