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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5e1c5ff4 TL |
2 | /* |
3 | * linux/arch/arm/plat-omap/dma.c | |
4 | * | |
97b7f715 | 5 | * Copyright (C) 2003 - 2008 Nokia Corporation |
96de0e25 | 6 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 TL |
7 | * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> |
8 | * Graphics DMA and LCD DMA graphics tranformations | |
9 | * by Imre Deak <imre.deak@nokia.com> | |
f8151e5c | 10 | * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. |
1a8bfa1e | 11 | * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> |
5e1c5ff4 TL |
12 | * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. |
13 | * | |
44169075 SS |
14 | * Copyright (C) 2009 Texas Instruments |
15 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
16 | * | |
5e1c5ff4 TL |
17 | * Support functions for the OMAP internal DMA channels. |
18 | * | |
e9dbebaf | 19 | * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ |
f31cc962 MK |
20 | * Converted DMA library into DMA platform driver. |
21 | * - G, Manjunath Kondaiah <manjugk@ti.com> | |
5e1c5ff4 TL |
22 | */ |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/interrupt.h> | |
418ca1f0 | 30 | #include <linux/irq.h> |
97b7f715 | 31 | #include <linux/io.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
0e4905c0 | 33 | #include <linux/delay.h> |
5e1c5ff4 | 34 | |
45c3eb7d | 35 | #include <linux/omap-dma.h> |
5e1c5ff4 | 36 | |
685e2d08 TL |
37 | #ifdef CONFIG_ARCH_OMAP1 |
38 | #include <mach/soc.h> | |
39 | #endif | |
40 | ||
bc4d8b5f PW |
41 | /* |
42 | * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA | |
43 | * channels that an instance of the SDMA IP block can support. Used | |
44 | * to size arrays. (The actual maximum on a particular SoC may be less | |
45 | * than this -- for example, OMAP1 SDMA instances only support 17 logical | |
46 | * DMA channels.) | |
47 | */ | |
48 | #define MAX_LOGICAL_DMA_CH_COUNT 32 | |
49 | ||
f8151e5c AG |
50 | #undef DEBUG |
51 | ||
52 | #ifndef CONFIG_ARCH_OMAP1 | |
53 | enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED, | |
54 | DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED | |
55 | }; | |
56 | ||
57 | enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; | |
1a8bfa1e | 58 | #endif |
5e1c5ff4 | 59 | |
97b7f715 | 60 | #define OMAP_DMA_ACTIVE 0x01 |
4fb699b4 | 61 | #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff |
5e1c5ff4 | 62 | |
97b7f715 | 63 | #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) |
5e1c5ff4 | 64 | |
f31cc962 MK |
65 | static struct omap_system_dma_plat_info *p; |
66 | static struct omap_dma_dev_attr *d; | |
175655bd | 67 | static void omap_clear_dma(int lch); |
97b7f715 | 68 | static int enable_1510_mode; |
d3c9be2f | 69 | static u32 errata; |
5e1c5ff4 | 70 | |
f8151e5c AG |
71 | struct dma_link_info { |
72 | int *linked_dmach_q; | |
73 | int no_of_lchs_linked; | |
74 | ||
75 | int q_count; | |
76 | int q_tail; | |
77 | int q_head; | |
78 | ||
79 | int chain_state; | |
80 | int chain_mode; | |
81 | ||
82 | }; | |
83 | ||
4d96372e | 84 | static int dma_lch_count; |
5e1c5ff4 | 85 | static int dma_chan_count; |
2263f022 | 86 | static int omap_dma_reserve_channels; |
5e1c5ff4 TL |
87 | |
88 | static spinlock_t dma_chan_lock; | |
4d96372e | 89 | static struct omap_dma_lch *dma_chan; |
5e1c5ff4 | 90 | |
f8151e5c AG |
91 | static inline void disable_lnk(int lch); |
92 | static void omap_disable_channel_irq(int lch); | |
93 | static inline void omap_enable_channel_irq(int lch); | |
94 | ||
1a8bfa1e TL |
95 | #ifdef CONFIG_ARCH_OMAP15XX |
96 | /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ | |
c7767582 | 97 | static int omap_dma_in_1510_mode(void) |
1a8bfa1e TL |
98 | { |
99 | return enable_1510_mode; | |
100 | } | |
101 | #else | |
102 | #define omap_dma_in_1510_mode() 0 | |
103 | #endif | |
104 | ||
105 | #ifdef CONFIG_ARCH_OMAP1 | |
5e1c5ff4 TL |
106 | static inline void set_gdma_dev(int req, int dev) |
107 | { | |
108 | u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; | |
109 | int shift = ((req - 1) % 5) * 6; | |
110 | u32 l; | |
111 | ||
112 | l = omap_readl(reg); | |
113 | l &= ~(0x3f << shift); | |
114 | l |= (dev - 1) << shift; | |
115 | omap_writel(l, reg); | |
116 | } | |
1a8bfa1e TL |
117 | #else |
118 | #define set_gdma_dev(req, dev) do {} while (0) | |
2c799cef TL |
119 | #define omap_readl(reg) 0 |
120 | #define omap_writel(val, reg) do {} while (0) | |
1a8bfa1e | 121 | #endif |
5e1c5ff4 | 122 | |
54b693d4 | 123 | #ifdef CONFIG_ARCH_OMAP1 |
709eb3e5 | 124 | void omap_set_dma_priority(int lch, int dst_port, int priority) |
5e1c5ff4 TL |
125 | { |
126 | unsigned long reg; | |
127 | u32 l; | |
128 | ||
82809601 | 129 | if (dma_omap1()) { |
709eb3e5 TL |
130 | switch (dst_port) { |
131 | case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ | |
132 | reg = OMAP_TC_OCPT1_PRIOR; | |
133 | break; | |
134 | case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ | |
135 | reg = OMAP_TC_OCPT2_PRIOR; | |
136 | break; | |
137 | case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ | |
138 | reg = OMAP_TC_EMIFF_PRIOR; | |
139 | break; | |
140 | case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ | |
141 | reg = OMAP_TC_EMIFS_PRIOR; | |
142 | break; | |
143 | default: | |
144 | BUG(); | |
145 | return; | |
146 | } | |
147 | l = omap_readl(reg); | |
148 | l &= ~(0xf << 8); | |
149 | l |= (priority & 0xf) << 8; | |
150 | omap_writel(l, reg); | |
151 | } | |
54b693d4 TL |
152 | } |
153 | #endif | |
709eb3e5 | 154 | |
54b693d4 TL |
155 | #ifdef CONFIG_ARCH_OMAP2PLUS |
156 | void omap_set_dma_priority(int lch, int dst_port, int priority) | |
157 | { | |
158 | u32 ccr; | |
159 | ||
160 | ccr = p->dma_read(CCR, lch); | |
161 | if (priority) | |
162 | ccr |= (1 << 6); | |
163 | else | |
164 | ccr &= ~(1 << 6); | |
165 | p->dma_write(ccr, CCR, lch); | |
5e1c5ff4 | 166 | } |
54b693d4 | 167 | #endif |
97b7f715 | 168 | EXPORT_SYMBOL(omap_set_dma_priority); |
5e1c5ff4 TL |
169 | |
170 | void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, | |
1a8bfa1e TL |
171 | int frame_count, int sync_mode, |
172 | int dma_trigger, int src_or_dst_synch) | |
5e1c5ff4 | 173 | { |
0499bdeb TL |
174 | u32 l; |
175 | ||
f31cc962 | 176 | l = p->dma_read(CSDP, lch); |
0499bdeb TL |
177 | l &= ~0x03; |
178 | l |= data_type; | |
f31cc962 | 179 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 180 | |
82809601 | 181 | if (dma_omap1()) { |
0499bdeb TL |
182 | u16 ccr; |
183 | ||
f31cc962 | 184 | ccr = p->dma_read(CCR, lch); |
0499bdeb | 185 | ccr &= ~(1 << 5); |
1a8bfa1e | 186 | if (sync_mode == OMAP_DMA_SYNC_FRAME) |
0499bdeb | 187 | ccr |= 1 << 5; |
f31cc962 | 188 | p->dma_write(ccr, CCR, lch); |
1a8bfa1e | 189 | |
f31cc962 | 190 | ccr = p->dma_read(CCR2, lch); |
0499bdeb | 191 | ccr &= ~(1 << 2); |
1a8bfa1e | 192 | if (sync_mode == OMAP_DMA_SYNC_BLOCK) |
0499bdeb | 193 | ccr |= 1 << 2; |
f31cc962 | 194 | p->dma_write(ccr, CCR2, lch); |
1a8bfa1e TL |
195 | } |
196 | ||
82809601 | 197 | if (dma_omap2plus() && dma_trigger) { |
0499bdeb | 198 | u32 val; |
1a8bfa1e | 199 | |
f31cc962 | 200 | val = p->dma_read(CCR, lch); |
4b3cf448 AG |
201 | |
202 | /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ | |
72a1179e | 203 | val &= ~((1 << 23) | (3 << 19) | 0x1f); |
4b3cf448 AG |
204 | val |= (dma_trigger & ~0x1f) << 14; |
205 | val |= dma_trigger & 0x1f; | |
5e1c5ff4 | 206 | |
1a8bfa1e TL |
207 | if (sync_mode & OMAP_DMA_SYNC_FRAME) |
208 | val |= 1 << 5; | |
eca9e56e PU |
209 | else |
210 | val &= ~(1 << 5); | |
5e1c5ff4 | 211 | |
1a8bfa1e TL |
212 | if (sync_mode & OMAP_DMA_SYNC_BLOCK) |
213 | val |= 1 << 18; | |
eca9e56e PU |
214 | else |
215 | val &= ~(1 << 18); | |
5e1c5ff4 | 216 | |
72a1179e SO |
217 | if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) { |
218 | val &= ~(1 << 24); /* dest synch */ | |
219 | val |= (1 << 23); /* Prefetch */ | |
220 | } else if (src_or_dst_synch) { | |
1a8bfa1e | 221 | val |= 1 << 24; /* source synch */ |
72a1179e | 222 | } else { |
1a8bfa1e | 223 | val &= ~(1 << 24); /* dest synch */ |
72a1179e | 224 | } |
f31cc962 | 225 | p->dma_write(val, CCR, lch); |
1a8bfa1e TL |
226 | } |
227 | ||
f31cc962 MK |
228 | p->dma_write(elem_count, CEN, lch); |
229 | p->dma_write(frame_count, CFN, lch); | |
5e1c5ff4 | 230 | } |
97b7f715 | 231 | EXPORT_SYMBOL(omap_set_dma_transfer_params); |
1a8bfa1e | 232 | |
0499bdeb TL |
233 | void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) |
234 | { | |
82809601 | 235 | if (dma_omap1() && !dma_omap15xx()) { |
0499bdeb TL |
236 | u32 l; |
237 | ||
f31cc962 | 238 | l = p->dma_read(LCH_CTRL, lch); |
0499bdeb TL |
239 | l &= ~0x7; |
240 | l |= mode; | |
f31cc962 | 241 | p->dma_write(l, LCH_CTRL, lch); |
0499bdeb TL |
242 | } |
243 | } | |
244 | EXPORT_SYMBOL(omap_set_dma_channel_mode); | |
245 | ||
1a8bfa1e | 246 | /* Note that src_port is only for omap1 */ |
5e1c5ff4 | 247 | void omap_set_dma_src_params(int lch, int src_port, int src_amode, |
1a8bfa1e TL |
248 | unsigned long src_start, |
249 | int src_ei, int src_fi) | |
5e1c5ff4 | 250 | { |
97b7f715 TL |
251 | u32 l; |
252 | ||
82809601 | 253 | if (dma_omap1()) { |
0499bdeb | 254 | u16 w; |
1a8bfa1e | 255 | |
f31cc962 | 256 | w = p->dma_read(CSDP, lch); |
0499bdeb TL |
257 | w &= ~(0x1f << 2); |
258 | w |= src_port << 2; | |
f31cc962 | 259 | p->dma_write(w, CSDP, lch); |
97b7f715 | 260 | } |
1a8bfa1e | 261 | |
f31cc962 | 262 | l = p->dma_read(CCR, lch); |
97b7f715 TL |
263 | l &= ~(0x03 << 12); |
264 | l |= src_amode << 12; | |
f31cc962 | 265 | p->dma_write(l, CCR, lch); |
0499bdeb | 266 | |
f31cc962 | 267 | p->dma_write(src_start, CSSA, lch); |
5e1c5ff4 | 268 | |
f31cc962 MK |
269 | p->dma_write(src_ei, CSEI, lch); |
270 | p->dma_write(src_fi, CSFI, lch); | |
1a8bfa1e | 271 | } |
97b7f715 | 272 | EXPORT_SYMBOL(omap_set_dma_src_params); |
5e1c5ff4 | 273 | |
5e1c5ff4 TL |
274 | void omap_set_dma_src_data_pack(int lch, int enable) |
275 | { | |
0499bdeb TL |
276 | u32 l; |
277 | ||
f31cc962 | 278 | l = p->dma_read(CSDP, lch); |
0499bdeb | 279 | l &= ~(1 << 6); |
1a8bfa1e | 280 | if (enable) |
0499bdeb | 281 | l |= (1 << 6); |
f31cc962 | 282 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 283 | } |
97b7f715 | 284 | EXPORT_SYMBOL(omap_set_dma_src_data_pack); |
5e1c5ff4 TL |
285 | |
286 | void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |
287 | { | |
6dc3c8f2 | 288 | unsigned int burst = 0; |
0499bdeb TL |
289 | u32 l; |
290 | ||
f31cc962 | 291 | l = p->dma_read(CSDP, lch); |
0499bdeb | 292 | l &= ~(0x03 << 7); |
5e1c5ff4 | 293 | |
5e1c5ff4 TL |
294 | switch (burst_mode) { |
295 | case OMAP_DMA_DATA_BURST_DIS: | |
296 | break; | |
297 | case OMAP_DMA_DATA_BURST_4: | |
82809601 | 298 | if (dma_omap2plus()) |
6dc3c8f2 KP |
299 | burst = 0x1; |
300 | else | |
301 | burst = 0x2; | |
5e1c5ff4 TL |
302 | break; |
303 | case OMAP_DMA_DATA_BURST_8: | |
82809601 | 304 | if (dma_omap2plus()) { |
6dc3c8f2 KP |
305 | burst = 0x2; |
306 | break; | |
307 | } | |
ea221a6a | 308 | /* |
309 | * not supported by current hardware on OMAP1 | |
5e1c5ff4 | 310 | * w |= (0x03 << 7); |
5e1c5ff4 | 311 | */ |
df561f66 | 312 | fallthrough; |
6dc3c8f2 | 313 | case OMAP_DMA_DATA_BURST_16: |
82809601 | 314 | if (dma_omap2plus()) { |
6dc3c8f2 KP |
315 | burst = 0x3; |
316 | break; | |
317 | } | |
3da6bd94 | 318 | /* OMAP1 don't support burst 16 */ |
df561f66 | 319 | fallthrough; |
5e1c5ff4 TL |
320 | default: |
321 | BUG(); | |
322 | } | |
0499bdeb TL |
323 | |
324 | l |= (burst << 7); | |
f31cc962 | 325 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 326 | } |
97b7f715 | 327 | EXPORT_SYMBOL(omap_set_dma_src_burst_mode); |
5e1c5ff4 | 328 | |
1a8bfa1e | 329 | /* Note that dest_port is only for OMAP1 */ |
5e1c5ff4 | 330 | void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, |
1a8bfa1e TL |
331 | unsigned long dest_start, |
332 | int dst_ei, int dst_fi) | |
5e1c5ff4 | 333 | { |
0499bdeb TL |
334 | u32 l; |
335 | ||
82809601 | 336 | if (dma_omap1()) { |
f31cc962 | 337 | l = p->dma_read(CSDP, lch); |
0499bdeb TL |
338 | l &= ~(0x1f << 9); |
339 | l |= dest_port << 9; | |
f31cc962 | 340 | p->dma_write(l, CSDP, lch); |
1a8bfa1e | 341 | } |
5e1c5ff4 | 342 | |
f31cc962 | 343 | l = p->dma_read(CCR, lch); |
0499bdeb TL |
344 | l &= ~(0x03 << 14); |
345 | l |= dest_amode << 14; | |
f31cc962 | 346 | p->dma_write(l, CCR, lch); |
5e1c5ff4 | 347 | |
f31cc962 | 348 | p->dma_write(dest_start, CDSA, lch); |
5e1c5ff4 | 349 | |
f31cc962 MK |
350 | p->dma_write(dst_ei, CDEI, lch); |
351 | p->dma_write(dst_fi, CDFI, lch); | |
5e1c5ff4 | 352 | } |
97b7f715 | 353 | EXPORT_SYMBOL(omap_set_dma_dest_params); |
5e1c5ff4 | 354 | |
5e1c5ff4 TL |
355 | void omap_set_dma_dest_data_pack(int lch, int enable) |
356 | { | |
0499bdeb TL |
357 | u32 l; |
358 | ||
f31cc962 | 359 | l = p->dma_read(CSDP, lch); |
0499bdeb | 360 | l &= ~(1 << 13); |
1a8bfa1e | 361 | if (enable) |
0499bdeb | 362 | l |= 1 << 13; |
f31cc962 | 363 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 364 | } |
97b7f715 | 365 | EXPORT_SYMBOL(omap_set_dma_dest_data_pack); |
5e1c5ff4 TL |
366 | |
367 | void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |
368 | { | |
6dc3c8f2 | 369 | unsigned int burst = 0; |
0499bdeb TL |
370 | u32 l; |
371 | ||
f31cc962 | 372 | l = p->dma_read(CSDP, lch); |
0499bdeb | 373 | l &= ~(0x03 << 14); |
5e1c5ff4 | 374 | |
5e1c5ff4 TL |
375 | switch (burst_mode) { |
376 | case OMAP_DMA_DATA_BURST_DIS: | |
377 | break; | |
378 | case OMAP_DMA_DATA_BURST_4: | |
82809601 | 379 | if (dma_omap2plus()) |
6dc3c8f2 KP |
380 | burst = 0x1; |
381 | else | |
382 | burst = 0x2; | |
5e1c5ff4 TL |
383 | break; |
384 | case OMAP_DMA_DATA_BURST_8: | |
82809601 | 385 | if (dma_omap2plus()) |
6dc3c8f2 KP |
386 | burst = 0x2; |
387 | else | |
388 | burst = 0x3; | |
5e1c5ff4 | 389 | break; |
6dc3c8f2 | 390 | case OMAP_DMA_DATA_BURST_16: |
82809601 | 391 | if (dma_omap2plus()) { |
6dc3c8f2 KP |
392 | burst = 0x3; |
393 | break; | |
394 | } | |
3da6bd94 | 395 | /* OMAP1 don't support burst 16 */ |
df561f66 | 396 | fallthrough; |
5e1c5ff4 TL |
397 | default: |
398 | printk(KERN_ERR "Invalid DMA burst mode\n"); | |
399 | BUG(); | |
400 | return; | |
401 | } | |
0499bdeb | 402 | l |= (burst << 14); |
f31cc962 | 403 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 404 | } |
97b7f715 | 405 | EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); |
5e1c5ff4 | 406 | |
1a8bfa1e | 407 | static inline void omap_enable_channel_irq(int lch) |
5e1c5ff4 | 408 | { |
7ff879db | 409 | /* Clear CSR */ |
82809601 | 410 | if (dma_omap1()) |
bedfb7ad OM |
411 | p->dma_read(CSR, lch); |
412 | else | |
f31cc962 | 413 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); |
1a8bfa1e | 414 | |
5e1c5ff4 | 415 | /* Enable some nice interrupts. */ |
f31cc962 | 416 | p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); |
5e1c5ff4 TL |
417 | } |
418 | ||
bedfb7ad | 419 | static inline void omap_disable_channel_irq(int lch) |
5e1c5ff4 | 420 | { |
bedfb7ad OM |
421 | /* disable channel interrupts */ |
422 | p->dma_write(0, CICR, lch); | |
423 | /* Clear CSR */ | |
82809601 | 424 | if (dma_omap1()) |
bedfb7ad OM |
425 | p->dma_read(CSR, lch); |
426 | else | |
427 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); | |
1a8bfa1e TL |
428 | } |
429 | ||
1a8bfa1e TL |
430 | void omap_disable_dma_irq(int lch, u16 bits) |
431 | { | |
432 | dma_chan[lch].enabled_irqs &= ~bits; | |
433 | } | |
97b7f715 | 434 | EXPORT_SYMBOL(omap_disable_dma_irq); |
1a8bfa1e TL |
435 | |
436 | static inline void enable_lnk(int lch) | |
437 | { | |
0499bdeb TL |
438 | u32 l; |
439 | ||
f31cc962 | 440 | l = p->dma_read(CLNK_CTRL, lch); |
0499bdeb | 441 | |
82809601 | 442 | if (dma_omap1()) |
0499bdeb | 443 | l &= ~(1 << 14); |
5e1c5ff4 | 444 | |
1a8bfa1e | 445 | /* Set the ENABLE_LNK bits */ |
5e1c5ff4 | 446 | if (dma_chan[lch].next_lch != -1) |
0499bdeb | 447 | l = dma_chan[lch].next_lch | (1 << 15); |
f8151e5c | 448 | |
f31cc962 | 449 | p->dma_write(l, CLNK_CTRL, lch); |
5e1c5ff4 TL |
450 | } |
451 | ||
452 | static inline void disable_lnk(int lch) | |
453 | { | |
0499bdeb TL |
454 | u32 l; |
455 | ||
f31cc962 | 456 | l = p->dma_read(CLNK_CTRL, lch); |
0499bdeb | 457 | |
5e1c5ff4 | 458 | /* Disable interrupts */ |
bedfb7ad OM |
459 | omap_disable_channel_irq(lch); |
460 | ||
82809601 | 461 | if (dma_omap1()) { |
1a8bfa1e | 462 | /* Set the STOP_LNK bit */ |
0499bdeb | 463 | l |= 1 << 14; |
1a8bfa1e | 464 | } |
5e1c5ff4 | 465 | |
82809601 | 466 | if (dma_omap2plus()) { |
1a8bfa1e | 467 | /* Clear the ENABLE_LNK bit */ |
0499bdeb | 468 | l &= ~(1 << 15); |
1a8bfa1e | 469 | } |
5e1c5ff4 | 470 | |
f31cc962 | 471 | p->dma_write(l, CLNK_CTRL, lch); |
5e1c5ff4 TL |
472 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
473 | } | |
474 | ||
1a8bfa1e | 475 | int omap_request_dma(int dev_id, const char *dev_name, |
97b7f715 | 476 | void (*callback)(int lch, u16 ch_status, void *data), |
1a8bfa1e TL |
477 | void *data, int *dma_ch_out) |
478 | { | |
479 | int ch, free_ch = -1; | |
480 | unsigned long flags; | |
481 | struct omap_dma_lch *chan; | |
482 | ||
5c65c360 RK |
483 | WARN(strcmp(dev_name, "DMA engine"), "Using deprecated platform DMA API - please update to DMA engine"); |
484 | ||
1a8bfa1e TL |
485 | spin_lock_irqsave(&dma_chan_lock, flags); |
486 | for (ch = 0; ch < dma_chan_count; ch++) { | |
487 | if (free_ch == -1 && dma_chan[ch].dev_id == -1) { | |
488 | free_ch = ch; | |
03a6d4a0 S |
489 | /* Exit after first free channel found */ |
490 | break; | |
1a8bfa1e TL |
491 | } |
492 | } | |
493 | if (free_ch == -1) { | |
494 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
495 | return -EBUSY; | |
496 | } | |
497 | chan = dma_chan + free_ch; | |
498 | chan->dev_id = dev_id; | |
499 | ||
f31cc962 MK |
500 | if (p->clear_lch_regs) |
501 | p->clear_lch_regs(free_ch); | |
5e1c5ff4 | 502 | |
1a8bfa1e TL |
503 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
504 | ||
505 | chan->dev_name = dev_name; | |
506 | chan->callback = callback; | |
507 | chan->data = data; | |
a92fda19 | 508 | chan->flags = 0; |
97b7f715 | 509 | |
7ff879db | 510 | chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; |
1a8bfa1e | 511 | |
82809601 | 512 | if (dma_omap1()) |
7ff879db | 513 | chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; |
1a8bfa1e | 514 | |
82809601 | 515 | if (dma_omap16xx()) { |
1a8bfa1e TL |
516 | /* If the sync device is set, configure it dynamically. */ |
517 | if (dev_id != 0) { | |
518 | set_gdma_dev(free_ch + 1, dev_id); | |
519 | dev_id = free_ch + 1; | |
520 | } | |
97b7f715 TL |
521 | /* |
522 | * Disable the 1510 compatibility mode and set the sync device | |
523 | * id. | |
524 | */ | |
f31cc962 | 525 | p->dma_write(dev_id | (1 << 10), CCR, free_ch); |
82809601 | 526 | } else if (dma_omap1()) { |
f31cc962 | 527 | p->dma_write(dev_id, CCR, free_ch); |
1a8bfa1e TL |
528 | } |
529 | ||
1a8bfa1e TL |
530 | *dma_ch_out = free_ch; |
531 | ||
532 | return 0; | |
533 | } | |
97b7f715 | 534 | EXPORT_SYMBOL(omap_request_dma); |
1a8bfa1e TL |
535 | |
536 | void omap_free_dma(int lch) | |
537 | { | |
538 | unsigned long flags; | |
539 | ||
1a8bfa1e | 540 | if (dma_chan[lch].dev_id == -1) { |
97b7f715 | 541 | pr_err("omap_dma: trying to free unallocated DMA channel %d\n", |
1a8bfa1e | 542 | lch); |
1a8bfa1e TL |
543 | return; |
544 | } | |
97b7f715 | 545 | |
bedfb7ad OM |
546 | /* Disable all DMA interrupts for the channel. */ |
547 | omap_disable_channel_irq(lch); | |
1a8bfa1e | 548 | |
bedfb7ad OM |
549 | /* Make sure the DMA transfer is stopped. */ |
550 | p->dma_write(0, CCR, lch); | |
1a8bfa1e | 551 | |
da1b94e6 SS |
552 | spin_lock_irqsave(&dma_chan_lock, flags); |
553 | dma_chan[lch].dev_id = -1; | |
554 | dma_chan[lch].next_lch = -1; | |
555 | dma_chan[lch].callback = NULL; | |
556 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
1a8bfa1e | 557 | } |
97b7f715 | 558 | EXPORT_SYMBOL(omap_free_dma); |
1a8bfa1e TL |
559 | |
560 | /* | |
561 | * Clears any DMA state so the DMA engine is ready to restart with new buffers | |
562 | * through omap_start_dma(). Any buffers in flight are discarded. | |
563 | */ | |
175655bd | 564 | static void omap_clear_dma(int lch) |
1a8bfa1e TL |
565 | { |
566 | unsigned long flags; | |
567 | ||
568 | local_irq_save(flags); | |
f31cc962 | 569 | p->clear_dma(lch); |
1a8bfa1e TL |
570 | local_irq_restore(flags); |
571 | } | |
572 | ||
573 | void omap_start_dma(int lch) | |
574 | { | |
0499bdeb TL |
575 | u32 l; |
576 | ||
519e6166 | 577 | /* |
578 | * The CPC/CDAC register needs to be initialized to zero | |
579 | * before starting dma transfer. | |
580 | */ | |
82809601 | 581 | if (dma_omap15xx()) |
f31cc962 | 582 | p->dma_write(0, CPC, lch); |
519e6166 | 583 | else |
f31cc962 | 584 | p->dma_write(0, CDAC, lch); |
519e6166 | 585 | |
5e1c5ff4 TL |
586 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
587 | int next_lch, cur_lch; | |
bc4d8b5f | 588 | char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; |
5e1c5ff4 | 589 | |
5e1c5ff4 TL |
590 | /* Set the link register of the first channel */ |
591 | enable_lnk(lch); | |
592 | ||
593 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | |
f0a3ff27 S |
594 | dma_chan_link_map[lch] = 1; |
595 | ||
5e1c5ff4 TL |
596 | cur_lch = dma_chan[lch].next_lch; |
597 | do { | |
598 | next_lch = dma_chan[cur_lch].next_lch; | |
599 | ||
1a8bfa1e | 600 | /* The loop case: we've been here already */ |
5e1c5ff4 TL |
601 | if (dma_chan_link_map[cur_lch]) |
602 | break; | |
603 | /* Mark the current channel */ | |
604 | dma_chan_link_map[cur_lch] = 1; | |
605 | ||
606 | enable_lnk(cur_lch); | |
1a8bfa1e | 607 | omap_enable_channel_irq(cur_lch); |
5e1c5ff4 TL |
608 | |
609 | cur_lch = next_lch; | |
610 | } while (next_lch != -1); | |
d3c9be2f | 611 | } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS)) |
f31cc962 | 612 | p->dma_write(lch, CLNK_CTRL, lch); |
5e1c5ff4 | 613 | |
1a8bfa1e TL |
614 | omap_enable_channel_irq(lch); |
615 | ||
f31cc962 | 616 | l = p->dma_read(CCR, lch); |
0499bdeb | 617 | |
d3c9be2f MK |
618 | if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING)) |
619 | l |= OMAP_DMA_CCR_BUFFERING_DISABLE; | |
0499bdeb | 620 | l |= OMAP_DMA_CCR_EN; |
d3c9be2f | 621 | |
35453584 RK |
622 | /* |
623 | * As dma_write() uses IO accessors which are weakly ordered, there | |
624 | * is no guarantee that data in coherent DMA memory will be visible | |
625 | * to the DMA device. Add a memory barrier here to ensure that any | |
626 | * such data is visible prior to enabling DMA. | |
627 | */ | |
628 | mb(); | |
f31cc962 | 629 | p->dma_write(l, CCR, lch); |
5e1c5ff4 | 630 | |
5e1c5ff4 TL |
631 | dma_chan[lch].flags |= OMAP_DMA_ACTIVE; |
632 | } | |
97b7f715 | 633 | EXPORT_SYMBOL(omap_start_dma); |
5e1c5ff4 TL |
634 | |
635 | void omap_stop_dma(int lch) | |
636 | { | |
0499bdeb TL |
637 | u32 l; |
638 | ||
9da65a99 | 639 | /* Disable all interrupts on the channel */ |
bedfb7ad | 640 | omap_disable_channel_irq(lch); |
9da65a99 | 641 | |
f31cc962 | 642 | l = p->dma_read(CCR, lch); |
d3c9be2f MK |
643 | if (IS_DMA_ERRATA(DMA_ERRATA_i541) && |
644 | (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { | |
0e4905c0 PU |
645 | int i = 0; |
646 | u32 sys_cf; | |
647 | ||
648 | /* Configure No-Standby */ | |
f31cc962 | 649 | l = p->dma_read(OCP_SYSCONFIG, lch); |
0e4905c0 PU |
650 | sys_cf = l; |
651 | l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; | |
652 | l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | |
f31cc962 | 653 | p->dma_write(l , OCP_SYSCONFIG, 0); |
0e4905c0 | 654 | |
f31cc962 | 655 | l = p->dma_read(CCR, lch); |
0e4905c0 | 656 | l &= ~OMAP_DMA_CCR_EN; |
f31cc962 | 657 | p->dma_write(l, CCR, lch); |
0e4905c0 PU |
658 | |
659 | /* Wait for sDMA FIFO drain */ | |
f31cc962 | 660 | l = p->dma_read(CCR, lch); |
0e4905c0 PU |
661 | while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | |
662 | OMAP_DMA_CCR_WR_ACTIVE))) { | |
663 | udelay(5); | |
664 | i++; | |
f31cc962 | 665 | l = p->dma_read(CCR, lch); |
0e4905c0 PU |
666 | } |
667 | if (i >= 100) | |
7852ec05 | 668 | pr_err("DMA drain did not complete on lch %d\n", lch); |
0e4905c0 | 669 | /* Restore OCP_SYSCONFIG */ |
f31cc962 | 670 | p->dma_write(sys_cf, OCP_SYSCONFIG, lch); |
0e4905c0 PU |
671 | } else { |
672 | l &= ~OMAP_DMA_CCR_EN; | |
f31cc962 | 673 | p->dma_write(l, CCR, lch); |
0e4905c0 | 674 | } |
9da65a99 | 675 | |
35453584 RK |
676 | /* |
677 | * Ensure that data transferred by DMA is visible to any access | |
678 | * after DMA has been disabled. This is important for coherent | |
679 | * DMA regions. | |
680 | */ | |
681 | mb(); | |
682 | ||
5e1c5ff4 TL |
683 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
684 | int next_lch, cur_lch = lch; | |
bc4d8b5f | 685 | char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; |
5e1c5ff4 TL |
686 | |
687 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | |
688 | do { | |
689 | /* The loop case: we've been here already */ | |
690 | if (dma_chan_link_map[cur_lch]) | |
691 | break; | |
692 | /* Mark the current channel */ | |
693 | dma_chan_link_map[cur_lch] = 1; | |
694 | ||
695 | disable_lnk(cur_lch); | |
696 | ||
697 | next_lch = dma_chan[cur_lch].next_lch; | |
698 | cur_lch = next_lch; | |
699 | } while (next_lch != -1); | |
5e1c5ff4 | 700 | } |
1a8bfa1e | 701 | |
5e1c5ff4 TL |
702 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
703 | } | |
97b7f715 | 704 | EXPORT_SYMBOL(omap_stop_dma); |
5e1c5ff4 | 705 | |
709eb3e5 TL |
706 | /* |
707 | * Allows changing the DMA callback function or data. This may be needed if | |
708 | * the driver shares a single DMA channel for multiple dma triggers. | |
709 | */ | |
1a8bfa1e TL |
710 | /* |
711 | * Returns current physical source address for the given DMA channel. | |
712 | * If the channel is running the caller must disable interrupts prior calling | |
713 | * this function and process the returned value before re-enabling interrupt to | |
714 | * prevent races with the interrupt handler. Note that in continuous mode there | |
25985edc | 715 | * is a chance for CSSA_L register overflow between the two reads resulting |
1a8bfa1e TL |
716 | * in incorrect return value. |
717 | */ | |
718 | dma_addr_t omap_get_dma_src_pos(int lch) | |
5e1c5ff4 | 719 | { |
0695de32 | 720 | dma_addr_t offset = 0; |
5e1c5ff4 | 721 | |
82809601 | 722 | if (dma_omap15xx()) |
f31cc962 | 723 | offset = p->dma_read(CPC, lch); |
0499bdeb | 724 | else |
f31cc962 | 725 | offset = p->dma_read(CSAC, lch); |
5e1c5ff4 | 726 | |
d3c9be2f | 727 | if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0) |
f31cc962 | 728 | offset = p->dma_read(CSAC, lch); |
0499bdeb | 729 | |
82809601 | 730 | if (!dma_omap15xx()) { |
7ba96680 PU |
731 | /* |
732 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
733 | * not been started (no data has been transferred so far). | |
734 | * Return the programmed source start address in this case. | |
735 | */ | |
736 | if (likely(p->dma_read(CDAC, lch))) | |
737 | offset = p->dma_read(CSAC, lch); | |
738 | else | |
739 | offset = p->dma_read(CSSA, lch); | |
740 | } | |
741 | ||
82809601 | 742 | if (dma_omap1()) |
f31cc962 | 743 | offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000); |
5e1c5ff4 | 744 | |
1a8bfa1e | 745 | return offset; |
5e1c5ff4 | 746 | } |
97b7f715 | 747 | EXPORT_SYMBOL(omap_get_dma_src_pos); |
5e1c5ff4 | 748 | |
1a8bfa1e TL |
749 | /* |
750 | * Returns current physical destination address for the given DMA channel. | |
751 | * If the channel is running the caller must disable interrupts prior calling | |
752 | * this function and process the returned value before re-enabling interrupt to | |
753 | * prevent races with the interrupt handler. Note that in continuous mode there | |
25985edc | 754 | * is a chance for CDSA_L register overflow between the two reads resulting |
1a8bfa1e TL |
755 | * in incorrect return value. |
756 | */ | |
757 | dma_addr_t omap_get_dma_dst_pos(int lch) | |
5e1c5ff4 | 758 | { |
0695de32 | 759 | dma_addr_t offset = 0; |
5e1c5ff4 | 760 | |
82809601 | 761 | if (dma_omap15xx()) |
f31cc962 | 762 | offset = p->dma_read(CPC, lch); |
0499bdeb | 763 | else |
f31cc962 | 764 | offset = p->dma_read(CDAC, lch); |
5e1c5ff4 | 765 | |
0499bdeb TL |
766 | /* |
767 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | |
768 | * read before the DMA controller finished disabling the channel. | |
769 | */ | |
82809601 | 770 | if (!dma_omap15xx() && offset == 0) { |
f31cc962 | 771 | offset = p->dma_read(CDAC, lch); |
06e8077b PU |
772 | /* |
773 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
774 | * not been started (no data has been transferred so far). | |
775 | * Return the programmed destination start address in this case. | |
776 | */ | |
777 | if (unlikely(!offset)) | |
778 | offset = p->dma_read(CDSA, lch); | |
779 | } | |
0499bdeb | 780 | |
82809601 | 781 | if (dma_omap1()) |
f31cc962 | 782 | offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); |
5e1c5ff4 | 783 | |
1a8bfa1e | 784 | return offset; |
5e1c5ff4 | 785 | } |
97b7f715 | 786 | EXPORT_SYMBOL(omap_get_dma_dst_pos); |
0499bdeb TL |
787 | |
788 | int omap_get_dma_active_status(int lch) | |
789 | { | |
f31cc962 | 790 | return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0; |
5e1c5ff4 | 791 | } |
0499bdeb | 792 | EXPORT_SYMBOL(omap_get_dma_active_status); |
5e1c5ff4 | 793 | |
1a8bfa1e | 794 | int omap_dma_running(void) |
5e1c5ff4 | 795 | { |
1a8bfa1e | 796 | int lch; |
5e1c5ff4 | 797 | |
82809601 | 798 | if (dma_omap1()) |
f8e9e984 | 799 | if (omap_lcd_dma_running()) |
1a8bfa1e | 800 | return 1; |
5e1c5ff4 | 801 | |
1a8bfa1e | 802 | for (lch = 0; lch < dma_chan_count; lch++) |
f31cc962 | 803 | if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) |
1a8bfa1e | 804 | return 1; |
5e1c5ff4 | 805 | |
1a8bfa1e | 806 | return 0; |
5e1c5ff4 TL |
807 | } |
808 | ||
1a8bfa1e TL |
809 | /*----------------------------------------------------------------------------*/ |
810 | ||
811 | #ifdef CONFIG_ARCH_OMAP1 | |
812 | ||
813 | static int omap1_dma_handle_ch(int ch) | |
814 | { | |
0499bdeb | 815 | u32 csr; |
1a8bfa1e TL |
816 | |
817 | if (enable_1510_mode && ch >= 6) { | |
818 | csr = dma_chan[ch].saved_csr; | |
819 | dma_chan[ch].saved_csr = 0; | |
820 | } else | |
f31cc962 | 821 | csr = p->dma_read(CSR, ch); |
1a8bfa1e TL |
822 | if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { |
823 | dma_chan[ch + 6].saved_csr = csr >> 7; | |
824 | csr &= 0x7f; | |
825 | } | |
826 | if ((csr & 0x3f) == 0) | |
827 | return 0; | |
828 | if (unlikely(dma_chan[ch].dev_id == -1)) { | |
7852ec05 PW |
829 | pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n", |
830 | ch, csr); | |
1a8bfa1e TL |
831 | return 0; |
832 | } | |
7ff879db | 833 | if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) |
7852ec05 | 834 | pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id); |
1a8bfa1e | 835 | if (unlikely(csr & OMAP_DMA_DROP_IRQ)) |
7852ec05 PW |
836 | pr_warn("DMA synchronization event drop occurred with device %d\n", |
837 | dma_chan[ch].dev_id); | |
1a8bfa1e TL |
838 | if (likely(csr & OMAP_DMA_BLOCK_IRQ)) |
839 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; | |
840 | if (likely(dma_chan[ch].callback != NULL)) | |
841 | dma_chan[ch].callback(ch, csr, dma_chan[ch].data); | |
97b7f715 | 842 | |
1a8bfa1e TL |
843 | return 1; |
844 | } | |
845 | ||
0cd61b68 | 846 | static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) |
1a8bfa1e TL |
847 | { |
848 | int ch = ((int) dev_id) - 1; | |
849 | int handled = 0; | |
850 | ||
851 | for (;;) { | |
852 | int handled_now = 0; | |
853 | ||
854 | handled_now += omap1_dma_handle_ch(ch); | |
855 | if (enable_1510_mode && dma_chan[ch + 6].saved_csr) | |
856 | handled_now += omap1_dma_handle_ch(ch + 6); | |
857 | if (!handled_now) | |
858 | break; | |
859 | handled += handled_now; | |
860 | } | |
861 | ||
862 | return handled ? IRQ_HANDLED : IRQ_NONE; | |
863 | } | |
864 | ||
865 | #else | |
866 | #define omap1_dma_irq_handler NULL | |
867 | #endif | |
868 | ||
1b416c4b RK |
869 | struct omap_system_dma_plat_info *omap_get_plat_info(void) |
870 | { | |
871 | return p; | |
872 | } | |
873 | EXPORT_SYMBOL_GPL(omap_get_plat_info); | |
874 | ||
351a102d | 875 | static int omap_system_dma_probe(struct platform_device *pdev) |
d3c9be2f | 876 | { |
f31cc962 MK |
877 | int ch, ret = 0; |
878 | int dma_irq; | |
879 | char irq_name[4]; | |
f31cc962 MK |
880 | |
881 | p = pdev->dev.platform_data; | |
882 | if (!p) { | |
7852ec05 PW |
883 | dev_err(&pdev->dev, |
884 | "%s: System DMA initialized without platform data\n", | |
885 | __func__); | |
f31cc962 | 886 | return -EINVAL; |
0499bdeb | 887 | } |
4d96372e | 888 | |
f31cc962 MK |
889 | d = p->dma_attr; |
890 | errata = p->errata; | |
a4c537c7 | 891 | |
f31cc962 | 892 | if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels |
e78f9606 | 893 | && (omap_dma_reserve_channels < d->lch_count)) |
f31cc962 | 894 | d->lch_count = omap_dma_reserve_channels; |
2263f022 | 895 | |
f31cc962 MK |
896 | dma_lch_count = d->lch_count; |
897 | dma_chan_count = dma_lch_count; | |
f31cc962 | 898 | enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; |
4d96372e | 899 | |
9834f813 | 900 | dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count, |
16e7ea53 | 901 | sizeof(*dma_chan), GFP_KERNEL); |
d679950c | 902 | if (!dma_chan) |
9834f813 | 903 | return -ENOMEM; |
9834f813 | 904 | |
5e1c5ff4 | 905 | spin_lock_init(&dma_chan_lock); |
5e1c5ff4 | 906 | for (ch = 0; ch < dma_chan_count; ch++) { |
1a8bfa1e | 907 | omap_clear_dma(ch); |
ada8d4a5 | 908 | |
5e1c5ff4 TL |
909 | dma_chan[ch].dev_id = -1; |
910 | dma_chan[ch].next_lch = -1; | |
911 | ||
912 | if (ch >= 6 && enable_1510_mode) | |
913 | continue; | |
914 | ||
82809601 | 915 | if (dma_omap1()) { |
97b7f715 TL |
916 | /* |
917 | * request_irq() doesn't like dev_id (ie. ch) being | |
918 | * zero, so we have to kludge around this. | |
919 | */ | |
f31cc962 MK |
920 | sprintf(&irq_name[0], "%d", ch); |
921 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
922 | ||
923 | if (dma_irq < 0) { | |
924 | ret = dma_irq; | |
925 | goto exit_dma_irq_fail; | |
926 | } | |
927 | ||
928 | /* INT_DMA_LCD is handled in lcd_dma.c */ | |
929 | if (dma_irq == INT_DMA_LCD) | |
930 | continue; | |
931 | ||
932 | ret = request_irq(dma_irq, | |
1a8bfa1e TL |
933 | omap1_dma_irq_handler, 0, "DMA", |
934 | (void *) (ch + 1)); | |
f31cc962 MK |
935 | if (ret != 0) |
936 | goto exit_dma_irq_fail; | |
1a8bfa1e TL |
937 | } |
938 | } | |
939 | ||
82809601 TL |
940 | /* reserve dma channels 0 and 1 in high security devices on 34xx */ |
941 | if (d->dev_caps & HS_CHANNELS_RESERVED) { | |
7852ec05 | 942 | pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n"); |
f31cc962 MK |
943 | dma_chan[0].dev_id = 0; |
944 | dma_chan[1].dev_id = 1; | |
945 | } | |
946 | p->show_dma_caps(); | |
5e1c5ff4 | 947 | return 0; |
7e9bf847 | 948 | |
f31cc962 | 949 | exit_dma_irq_fail: |
f31cc962 MK |
950 | return ret; |
951 | } | |
7e9bf847 | 952 | |
351a102d | 953 | static int omap_system_dma_remove(struct platform_device *pdev) |
f31cc962 | 954 | { |
755cbfd8 | 955 | int dma_irq, irq_rel = 0; |
7e9bf847 | 956 | |
755cbfd8 TL |
957 | if (dma_omap2plus()) |
958 | return 0; | |
959 | ||
960 | for ( ; irq_rel < dma_chan_count; irq_rel++) { | |
961 | dma_irq = platform_get_irq(pdev, irq_rel); | |
962 | free_irq(dma_irq, (void *)(irq_rel + 1)); | |
f31cc962 | 963 | } |
755cbfd8 | 964 | |
f31cc962 MK |
965 | return 0; |
966 | } | |
967 | ||
968 | static struct platform_driver omap_system_dma_driver = { | |
969 | .probe = omap_system_dma_probe, | |
351a102d | 970 | .remove = omap_system_dma_remove, |
f31cc962 MK |
971 | .driver = { |
972 | .name = "omap_dma_system" | |
973 | }, | |
974 | }; | |
975 | ||
976 | static int __init omap_system_dma_init(void) | |
977 | { | |
978 | return platform_driver_register(&omap_system_dma_driver); | |
979 | } | |
980 | arch_initcall(omap_system_dma_init); | |
981 | ||
982 | static void __exit omap_system_dma_exit(void) | |
983 | { | |
984 | platform_driver_unregister(&omap_system_dma_driver); | |
5e1c5ff4 TL |
985 | } |
986 | ||
f31cc962 MK |
987 | MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER"); |
988 | MODULE_LICENSE("GPL"); | |
f31cc962 | 989 | MODULE_AUTHOR("Texas Instruments Inc"); |
5e1c5ff4 | 990 | |
2263f022 SS |
991 | /* |
992 | * Reserve the omap SDMA channels using cmdline bootarg | |
993 | * "omap_dma_reserve_ch=". The valid range is 1 to 32 | |
994 | */ | |
995 | static int __init omap_dma_cmdline_reserve_ch(char *str) | |
996 | { | |
997 | if (get_option(&str, &omap_dma_reserve_channels) != 1) | |
998 | omap_dma_reserve_channels = 0; | |
999 | return 1; | |
1000 | } | |
1001 | ||
1002 | __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch); | |
1003 | ||
5e1c5ff4 | 1004 |