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Commit | Line | Data |
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92105bb7 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dmtimer.c | |
3 | * | |
4 | * OMAP Dual-Mode Timers | |
5 | * | |
97933d6c TKD |
6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
7 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> | |
8 | * Thara Gopinath <thara@ti.com> | |
9 | * | |
10 | * dmtimer adaptation to platform_driver. | |
11 | * | |
92105bb7 | 12 | * Copyright (C) 2005 Nokia Corporation |
77900a2f TT |
13 | * OMAP2 support by Juha Yrjola |
14 | * API improvements and OMAP2 clock framework support by Timo Teras | |
92105bb7 | 15 | * |
44169075 SS |
16 | * Copyright (C) 2009 Texas Instruments |
17 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
18 | * | |
92105bb7 TL |
19 | * This program is free software; you can redistribute it and/or modify it |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
27 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
28 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License along | |
34 | * with this program; if not, write to the Free Software Foundation, Inc., | |
35 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
36 | */ | |
37 | ||
869dec15 | 38 | #include <linux/module.h> |
fced80c7 | 39 | #include <linux/io.h> |
df28472a | 40 | #include <linux/slab.h> |
3392cdd3 | 41 | #include <linux/err.h> |
ffe07cea | 42 | #include <linux/pm_runtime.h> |
44169075 | 43 | |
3392cdd3 | 44 | #include <plat/dmtimer.h> |
0b30ec1c | 45 | #include <plat/omap-pm.h> |
471b3aa7 | 46 | |
2c799cef TL |
47 | #include <mach/hardware.h> |
48 | ||
b7b4ff76 | 49 | static u32 omap_reserved_systimers; |
df28472a | 50 | static LIST_HEAD(omap_timer_list); |
3392cdd3 | 51 | static DEFINE_SPINLOCK(dm_timer_lock); |
92105bb7 | 52 | |
3392cdd3 TKD |
53 | /** |
54 | * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode | |
55 | * @timer: timer pointer over which read operation to perform | |
56 | * @reg: lowest byte holds the register offset | |
57 | * | |
58 | * The posted mode bit is encoded in reg. Note that in posted mode write | |
59 | * pending bit must be checked. Otherwise a read of a non completed write | |
60 | * will produce an error. | |
0f0d0807 RW |
61 | */ |
62 | static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) | |
77900a2f | 63 | { |
ee17f114 TL |
64 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
65 | return __omap_dm_timer_read(timer, reg, timer->posted); | |
77900a2f | 66 | } |
92105bb7 | 67 | |
3392cdd3 TKD |
68 | /** |
69 | * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode | |
70 | * @timer: timer pointer over which write operation is to perform | |
71 | * @reg: lowest byte holds the register offset | |
72 | * @value: data to write into the register | |
73 | * | |
74 | * The posted mode bit is encoded in reg. Note that in posted mode the write | |
75 | * pending bit must be checked. Otherwise a write on a register which has a | |
76 | * pending write will be lost. | |
0f0d0807 RW |
77 | */ |
78 | static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, | |
79 | u32 value) | |
92105bb7 | 80 | { |
ee17f114 TL |
81 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
82 | __omap_dm_timer_write(timer, reg, value, timer->posted); | |
92105bb7 TL |
83 | } |
84 | ||
b481113a TKD |
85 | static void omap_timer_restore_context(struct omap_dm_timer *timer) |
86 | { | |
dffc9dae | 87 | if (timer->revision == 1) |
b481113a TKD |
88 | __raw_writel(timer->context.tistat, timer->sys_stat); |
89 | ||
90 | __raw_writel(timer->context.tisr, timer->irq_stat); | |
91 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, | |
92 | timer->context.twer); | |
93 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, | |
94 | timer->context.tcrr); | |
95 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, | |
96 | timer->context.tldr); | |
97 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, | |
98 | timer->context.tmar); | |
99 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, | |
100 | timer->context.tsicr); | |
101 | __raw_writel(timer->context.tier, timer->irq_ena); | |
102 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, | |
103 | timer->context.tclr); | |
104 | } | |
105 | ||
77900a2f | 106 | static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) |
92105bb7 | 107 | { |
77900a2f TT |
108 | int c; |
109 | ||
ee17f114 TL |
110 | if (!timer->sys_stat) |
111 | return; | |
112 | ||
77900a2f | 113 | c = 0; |
ee17f114 | 114 | while (!(__raw_readl(timer->sys_stat) & 1)) { |
77900a2f TT |
115 | c++; |
116 | if (c > 100000) { | |
117 | printk(KERN_ERR "Timer failed to reset\n"); | |
118 | return; | |
119 | } | |
120 | } | |
92105bb7 TL |
121 | } |
122 | ||
77900a2f TT |
123 | static void omap_dm_timer_reset(struct omap_dm_timer *timer) |
124 | { | |
b481113a | 125 | omap_dm_timer_enable(timer); |
3392cdd3 | 126 | if (timer->pdev->id != 1) { |
e32f7ec2 TT |
127 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
128 | omap_dm_timer_wait_for_reset(timer); | |
129 | } | |
0f0d0807 | 130 | |
3392cdd3 | 131 | __omap_dm_timer_reset(timer, 0, 0); |
b481113a | 132 | omap_dm_timer_disable(timer); |
0f0d0807 | 133 | timer->posted = 1; |
77900a2f TT |
134 | } |
135 | ||
3392cdd3 | 136 | int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
77900a2f | 137 | { |
3392cdd3 TKD |
138 | struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data; |
139 | int ret; | |
140 | ||
141 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); | |
142 | if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) { | |
143 | timer->fclk = NULL; | |
144 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); | |
145 | return -EINVAL; | |
146 | } | |
147 | ||
3392cdd3 TKD |
148 | if (pdata->needs_manual_reset) |
149 | omap_dm_timer_reset(timer); | |
150 | ||
151 | ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); | |
152 | ||
153 | timer->posted = 1; | |
154 | return ret; | |
77900a2f TT |
155 | } |
156 | ||
b7b4ff76 JH |
157 | static inline u32 omap_dm_timer_reserved_systimer(int id) |
158 | { | |
159 | return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; | |
160 | } | |
161 | ||
162 | int omap_dm_timer_reserve_systimer(int id) | |
163 | { | |
164 | if (omap_dm_timer_reserved_systimer(id)) | |
165 | return -ENODEV; | |
166 | ||
167 | omap_reserved_systimers |= (1 << (id - 1)); | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
77900a2f TT |
172 | struct omap_dm_timer *omap_dm_timer_request(void) |
173 | { | |
3392cdd3 | 174 | struct omap_dm_timer *timer = NULL, *t; |
77900a2f | 175 | unsigned long flags; |
3392cdd3 | 176 | int ret = 0; |
77900a2f TT |
177 | |
178 | spin_lock_irqsave(&dm_timer_lock, flags); | |
3392cdd3 TKD |
179 | list_for_each_entry(t, &omap_timer_list, node) { |
180 | if (t->reserved) | |
77900a2f TT |
181 | continue; |
182 | ||
3392cdd3 | 183 | timer = t; |
83379c81 | 184 | timer->reserved = 1; |
77900a2f TT |
185 | break; |
186 | } | |
3392cdd3 TKD |
187 | |
188 | if (timer) { | |
189 | ret = omap_dm_timer_prepare(timer); | |
190 | if (ret) { | |
191 | timer->reserved = 0; | |
192 | timer = NULL; | |
193 | } | |
194 | } | |
77900a2f TT |
195 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
196 | ||
3392cdd3 TKD |
197 | if (!timer) |
198 | pr_debug("%s: timer request failed!\n", __func__); | |
83379c81 | 199 | |
77900a2f TT |
200 | return timer; |
201 | } | |
6c366e32 | 202 | EXPORT_SYMBOL_GPL(omap_dm_timer_request); |
77900a2f TT |
203 | |
204 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |
92105bb7 | 205 | { |
3392cdd3 | 206 | struct omap_dm_timer *timer = NULL, *t; |
77900a2f | 207 | unsigned long flags; |
3392cdd3 | 208 | int ret = 0; |
92105bb7 | 209 | |
77900a2f | 210 | spin_lock_irqsave(&dm_timer_lock, flags); |
3392cdd3 TKD |
211 | list_for_each_entry(t, &omap_timer_list, node) { |
212 | if (t->pdev->id == id && !t->reserved) { | |
213 | timer = t; | |
214 | timer->reserved = 1; | |
215 | break; | |
216 | } | |
77900a2f | 217 | } |
92105bb7 | 218 | |
3392cdd3 TKD |
219 | if (timer) { |
220 | ret = omap_dm_timer_prepare(timer); | |
221 | if (ret) { | |
222 | timer->reserved = 0; | |
223 | timer = NULL; | |
224 | } | |
225 | } | |
77900a2f TT |
226 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
227 | ||
3392cdd3 TKD |
228 | if (!timer) |
229 | pr_debug("%s: timer%d request failed!\n", __func__, id); | |
83379c81 | 230 | |
77900a2f | 231 | return timer; |
92105bb7 | 232 | } |
6c366e32 | 233 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); |
92105bb7 | 234 | |
ab4eb8b0 | 235 | int omap_dm_timer_free(struct omap_dm_timer *timer) |
77900a2f | 236 | { |
ab4eb8b0 TKD |
237 | if (unlikely(!timer)) |
238 | return -EINVAL; | |
239 | ||
3392cdd3 | 240 | clk_put(timer->fclk); |
fa4bb626 | 241 | |
77900a2f TT |
242 | WARN_ON(!timer->reserved); |
243 | timer->reserved = 0; | |
ab4eb8b0 | 244 | return 0; |
77900a2f | 245 | } |
6c366e32 | 246 | EXPORT_SYMBOL_GPL(omap_dm_timer_free); |
77900a2f | 247 | |
12583a70 TT |
248 | void omap_dm_timer_enable(struct omap_dm_timer *timer) |
249 | { | |
ffe07cea | 250 | pm_runtime_get_sync(&timer->pdev->dev); |
12583a70 | 251 | } |
6c366e32 | 252 | EXPORT_SYMBOL_GPL(omap_dm_timer_enable); |
12583a70 TT |
253 | |
254 | void omap_dm_timer_disable(struct omap_dm_timer *timer) | |
255 | { | |
ffe07cea | 256 | pm_runtime_put(&timer->pdev->dev); |
12583a70 | 257 | } |
6c366e32 | 258 | EXPORT_SYMBOL_GPL(omap_dm_timer_disable); |
12583a70 | 259 | |
77900a2f TT |
260 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) |
261 | { | |
ab4eb8b0 TKD |
262 | if (timer) |
263 | return timer->irq; | |
264 | return -EINVAL; | |
77900a2f | 265 | } |
6c366e32 | 266 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); |
77900a2f TT |
267 | |
268 | #if defined(CONFIG_ARCH_OMAP1) | |
269 | ||
a569c6ec TL |
270 | /** |
271 | * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR | |
272 | * @inputmask: current value of idlect mask | |
273 | */ | |
274 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |
275 | { | |
3392cdd3 TKD |
276 | int i = 0; |
277 | struct omap_dm_timer *timer = NULL; | |
278 | unsigned long flags; | |
a569c6ec TL |
279 | |
280 | /* If ARMXOR cannot be idled this function call is unnecessary */ | |
281 | if (!(inputmask & (1 << 1))) | |
282 | return inputmask; | |
283 | ||
284 | /* If any active timer is using ARMXOR return modified mask */ | |
3392cdd3 TKD |
285 | spin_lock_irqsave(&dm_timer_lock, flags); |
286 | list_for_each_entry(timer, &omap_timer_list, node) { | |
77900a2f TT |
287 | u32 l; |
288 | ||
3392cdd3 | 289 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
290 | if (l & OMAP_TIMER_CTRL_ST) { |
291 | if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) | |
a569c6ec TL |
292 | inputmask &= ~(1 << 1); |
293 | else | |
294 | inputmask &= ~(1 << 2); | |
295 | } | |
3392cdd3 | 296 | i++; |
77900a2f | 297 | } |
3392cdd3 | 298 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
a569c6ec TL |
299 | |
300 | return inputmask; | |
301 | } | |
6c366e32 | 302 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
a569c6ec | 303 | |
140455fa | 304 | #else |
a569c6ec | 305 | |
77900a2f | 306 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
92105bb7 | 307 | { |
ab4eb8b0 TKD |
308 | if (timer) |
309 | return timer->fclk; | |
310 | return NULL; | |
77900a2f | 311 | } |
6c366e32 | 312 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); |
92105bb7 | 313 | |
77900a2f TT |
314 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
315 | { | |
316 | BUG(); | |
2121880e DB |
317 | |
318 | return 0; | |
92105bb7 | 319 | } |
6c366e32 | 320 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
92105bb7 | 321 | |
77900a2f | 322 | #endif |
92105bb7 | 323 | |
ab4eb8b0 | 324 | int omap_dm_timer_trigger(struct omap_dm_timer *timer) |
92105bb7 | 325 | { |
ab4eb8b0 TKD |
326 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
327 | pr_err("%s: timer not available or enabled.\n", __func__); | |
328 | return -EINVAL; | |
b481113a TKD |
329 | } |
330 | ||
77900a2f | 331 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
ab4eb8b0 | 332 | return 0; |
92105bb7 | 333 | } |
6c366e32 | 334 | EXPORT_SYMBOL_GPL(omap_dm_timer_trigger); |
92105bb7 | 335 | |
ab4eb8b0 | 336 | int omap_dm_timer_start(struct omap_dm_timer *timer) |
77900a2f TT |
337 | { |
338 | u32 l; | |
92105bb7 | 339 | |
ab4eb8b0 TKD |
340 | if (unlikely(!timer)) |
341 | return -EINVAL; | |
342 | ||
b481113a TKD |
343 | omap_dm_timer_enable(timer); |
344 | ||
1c2d076b | 345 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
0b30ec1c JH |
346 | if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) != |
347 | timer->ctx_loss_count) | |
b481113a TKD |
348 | omap_timer_restore_context(timer); |
349 | } | |
350 | ||
77900a2f TT |
351 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
352 | if (!(l & OMAP_TIMER_CTRL_ST)) { | |
353 | l |= OMAP_TIMER_CTRL_ST; | |
354 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
355 | } | |
b481113a TKD |
356 | |
357 | /* Save the context */ | |
358 | timer->context.tclr = l; | |
ab4eb8b0 | 359 | return 0; |
77900a2f | 360 | } |
6c366e32 | 361 | EXPORT_SYMBOL_GPL(omap_dm_timer_start); |
92105bb7 | 362 | |
ab4eb8b0 | 363 | int omap_dm_timer_stop(struct omap_dm_timer *timer) |
92105bb7 | 364 | { |
caf64f2f | 365 | unsigned long rate = 0; |
eeb3711b | 366 | struct dmtimer_platform_data *pdata; |
92105bb7 | 367 | |
ab4eb8b0 TKD |
368 | if (unlikely(!timer)) |
369 | return -EINVAL; | |
370 | ||
eeb3711b | 371 | pdata = timer->pdev->dev.platform_data; |
3392cdd3 TKD |
372 | if (!pdata->needs_manual_reset) |
373 | rate = clk_get_rate(timer->fclk); | |
caf64f2f | 374 | |
ee17f114 | 375 | __omap_dm_timer_stop(timer, timer->posted, rate); |
ab4eb8b0 | 376 | |
0b30ec1c | 377 | if (!(timer->capability & OMAP_TIMER_ALWON)) |
dffc9dae | 378 | timer->ctx_loss_count = |
0b30ec1c | 379 | omap_pm_get_dev_context_loss_count(&timer->pdev->dev); |
dffc9dae TKD |
380 | |
381 | /* | |
382 | * Since the register values are computed and written within | |
383 | * __omap_dm_timer_stop, we need to use read to retrieve the | |
384 | * context. | |
385 | */ | |
386 | timer->context.tclr = | |
387 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
388 | timer->context.tisr = __raw_readl(timer->irq_stat); | |
389 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 390 | return 0; |
92105bb7 | 391 | } |
6c366e32 | 392 | EXPORT_SYMBOL_GPL(omap_dm_timer_stop); |
92105bb7 | 393 | |
f248076c | 394 | int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
92105bb7 | 395 | { |
3392cdd3 | 396 | int ret; |
ab4eb8b0 TKD |
397 | struct dmtimer_platform_data *pdata; |
398 | ||
399 | if (unlikely(!timer)) | |
400 | return -EINVAL; | |
401 | ||
402 | pdata = timer->pdev->dev.platform_data; | |
3392cdd3 | 403 | |
77900a2f | 404 | if (source < 0 || source >= 3) |
f248076c | 405 | return -EINVAL; |
77900a2f | 406 | |
3392cdd3 | 407 | ret = pdata->set_timer_src(timer->pdev, source); |
3392cdd3 TKD |
408 | |
409 | return ret; | |
92105bb7 | 410 | } |
6c366e32 | 411 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); |
92105bb7 | 412 | |
ab4eb8b0 | 413 | int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, |
77900a2f | 414 | unsigned int load) |
92105bb7 TL |
415 | { |
416 | u32 l; | |
77900a2f | 417 | |
ab4eb8b0 TKD |
418 | if (unlikely(!timer)) |
419 | return -EINVAL; | |
420 | ||
b481113a | 421 | omap_dm_timer_enable(timer); |
92105bb7 | 422 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
423 | if (autoreload) |
424 | l |= OMAP_TIMER_CTRL_AR; | |
425 | else | |
426 | l &= ~OMAP_TIMER_CTRL_AR; | |
92105bb7 | 427 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 428 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
0f0d0807 | 429 | |
77900a2f | 430 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
b481113a TKD |
431 | /* Save the context */ |
432 | timer->context.tclr = l; | |
433 | timer->context.tldr = load; | |
434 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 435 | return 0; |
92105bb7 | 436 | } |
6c366e32 | 437 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load); |
92105bb7 | 438 | |
3fddd09e | 439 | /* Optimized set_load which removes costly spin wait in timer_start */ |
ab4eb8b0 | 440 | int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, |
3fddd09e RW |
441 | unsigned int load) |
442 | { | |
443 | u32 l; | |
444 | ||
ab4eb8b0 TKD |
445 | if (unlikely(!timer)) |
446 | return -EINVAL; | |
447 | ||
b481113a TKD |
448 | omap_dm_timer_enable(timer); |
449 | ||
1c2d076b | 450 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
0b30ec1c JH |
451 | if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) != |
452 | timer->ctx_loss_count) | |
b481113a TKD |
453 | omap_timer_restore_context(timer); |
454 | } | |
455 | ||
3fddd09e | 456 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
64ce2907 | 457 | if (autoreload) { |
3fddd09e | 458 | l |= OMAP_TIMER_CTRL_AR; |
64ce2907 PW |
459 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
460 | } else { | |
3fddd09e | 461 | l &= ~OMAP_TIMER_CTRL_AR; |
64ce2907 | 462 | } |
3fddd09e RW |
463 | l |= OMAP_TIMER_CTRL_ST; |
464 | ||
ee17f114 | 465 | __omap_dm_timer_load_start(timer, l, load, timer->posted); |
b481113a TKD |
466 | |
467 | /* Save the context */ | |
468 | timer->context.tclr = l; | |
469 | timer->context.tldr = load; | |
470 | timer->context.tcrr = load; | |
ab4eb8b0 | 471 | return 0; |
3fddd09e | 472 | } |
6c366e32 | 473 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); |
3fddd09e | 474 | |
ab4eb8b0 | 475 | int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
77900a2f | 476 | unsigned int match) |
92105bb7 TL |
477 | { |
478 | u32 l; | |
479 | ||
ab4eb8b0 TKD |
480 | if (unlikely(!timer)) |
481 | return -EINVAL; | |
482 | ||
b481113a | 483 | omap_dm_timer_enable(timer); |
92105bb7 | 484 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
83379c81 | 485 | if (enable) |
77900a2f TT |
486 | l |= OMAP_TIMER_CTRL_CE; |
487 | else | |
488 | l &= ~OMAP_TIMER_CTRL_CE; | |
92105bb7 | 489 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 490 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
b481113a TKD |
491 | |
492 | /* Save the context */ | |
493 | timer->context.tclr = l; | |
494 | timer->context.tmar = match; | |
495 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 496 | return 0; |
92105bb7 | 497 | } |
6c366e32 | 498 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_match); |
92105bb7 | 499 | |
ab4eb8b0 | 500 | int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
77900a2f | 501 | int toggle, int trigger) |
92105bb7 TL |
502 | { |
503 | u32 l; | |
504 | ||
ab4eb8b0 TKD |
505 | if (unlikely(!timer)) |
506 | return -EINVAL; | |
507 | ||
b481113a | 508 | omap_dm_timer_enable(timer); |
92105bb7 | 509 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
510 | l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
511 | OMAP_TIMER_CTRL_PT | (0x03 << 10)); | |
512 | if (def_on) | |
513 | l |= OMAP_TIMER_CTRL_SCPWM; | |
514 | if (toggle) | |
515 | l |= OMAP_TIMER_CTRL_PT; | |
516 | l |= trigger << 10; | |
92105bb7 | 517 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
518 | |
519 | /* Save the context */ | |
520 | timer->context.tclr = l; | |
521 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 522 | return 0; |
92105bb7 | 523 | } |
6c366e32 | 524 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm); |
92105bb7 | 525 | |
ab4eb8b0 | 526 | int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) |
92105bb7 TL |
527 | { |
528 | u32 l; | |
529 | ||
ab4eb8b0 TKD |
530 | if (unlikely(!timer)) |
531 | return -EINVAL; | |
532 | ||
b481113a | 533 | omap_dm_timer_enable(timer); |
92105bb7 | 534 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
535 | l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
536 | if (prescaler >= 0x00 && prescaler <= 0x07) { | |
537 | l |= OMAP_TIMER_CTRL_PRE; | |
538 | l |= prescaler << 2; | |
539 | } | |
92105bb7 | 540 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
541 | |
542 | /* Save the context */ | |
543 | timer->context.tclr = l; | |
544 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 545 | return 0; |
92105bb7 | 546 | } |
6c366e32 | 547 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler); |
92105bb7 | 548 | |
ab4eb8b0 | 549 | int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
77900a2f | 550 | unsigned int value) |
92105bb7 | 551 | { |
ab4eb8b0 TKD |
552 | if (unlikely(!timer)) |
553 | return -EINVAL; | |
554 | ||
b481113a | 555 | omap_dm_timer_enable(timer); |
ee17f114 | 556 | __omap_dm_timer_int_enable(timer, value); |
b481113a TKD |
557 | |
558 | /* Save the context */ | |
559 | timer->context.tier = value; | |
560 | timer->context.twer = value; | |
561 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 562 | return 0; |
92105bb7 | 563 | } |
6c366e32 | 564 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); |
92105bb7 | 565 | |
77900a2f | 566 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
92105bb7 | 567 | { |
fa4bb626 TT |
568 | unsigned int l; |
569 | ||
ab4eb8b0 TKD |
570 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
571 | pr_err("%s: timer not available or enabled.\n", __func__); | |
b481113a TKD |
572 | return 0; |
573 | } | |
574 | ||
ee17f114 | 575 | l = __raw_readl(timer->irq_stat); |
fa4bb626 TT |
576 | |
577 | return l; | |
92105bb7 | 578 | } |
6c366e32 | 579 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_status); |
92105bb7 | 580 | |
ab4eb8b0 | 581 | int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
92105bb7 | 582 | { |
ab4eb8b0 TKD |
583 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) |
584 | return -EINVAL; | |
585 | ||
ee17f114 | 586 | __omap_dm_timer_write_status(timer, value); |
b481113a TKD |
587 | /* Save the context */ |
588 | timer->context.tisr = value; | |
ab4eb8b0 | 589 | return 0; |
92105bb7 | 590 | } |
6c366e32 | 591 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); |
92105bb7 | 592 | |
77900a2f | 593 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
92105bb7 | 594 | { |
ab4eb8b0 TKD |
595 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
596 | pr_err("%s: timer not iavailable or enabled.\n", __func__); | |
b481113a TKD |
597 | return 0; |
598 | } | |
599 | ||
ee17f114 | 600 | return __omap_dm_timer_read_counter(timer, timer->posted); |
92105bb7 | 601 | } |
6c366e32 | 602 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); |
92105bb7 | 603 | |
ab4eb8b0 | 604 | int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
83379c81 | 605 | { |
ab4eb8b0 TKD |
606 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
607 | pr_err("%s: timer not available or enabled.\n", __func__); | |
608 | return -EINVAL; | |
b481113a TKD |
609 | } |
610 | ||
fa4bb626 | 611 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
b481113a TKD |
612 | |
613 | /* Save the context */ | |
614 | timer->context.tcrr = value; | |
ab4eb8b0 | 615 | return 0; |
83379c81 | 616 | } |
6c366e32 | 617 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter); |
83379c81 | 618 | |
77900a2f | 619 | int omap_dm_timers_active(void) |
92105bb7 | 620 | { |
3392cdd3 | 621 | struct omap_dm_timer *timer; |
12583a70 | 622 | |
3392cdd3 | 623 | list_for_each_entry(timer, &omap_timer_list, node) { |
ffe07cea | 624 | if (!timer->reserved) |
12583a70 TT |
625 | continue; |
626 | ||
77900a2f | 627 | if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
fa4bb626 | 628 | OMAP_TIMER_CTRL_ST) { |
77900a2f | 629 | return 1; |
fa4bb626 | 630 | } |
77900a2f TT |
631 | } |
632 | return 0; | |
633 | } | |
6c366e32 | 634 | EXPORT_SYMBOL_GPL(omap_dm_timers_active); |
92105bb7 | 635 | |
df28472a TKD |
636 | /** |
637 | * omap_dm_timer_probe - probe function called for every registered device | |
638 | * @pdev: pointer to current timer platform device | |
639 | * | |
640 | * Called by driver framework at the end of device registration for all | |
641 | * timer devices. | |
642 | */ | |
643 | static int __devinit omap_dm_timer_probe(struct platform_device *pdev) | |
644 | { | |
645 | int ret; | |
646 | unsigned long flags; | |
647 | struct omap_dm_timer *timer; | |
648 | struct resource *mem, *irq, *ioarea; | |
649 | struct dmtimer_platform_data *pdata = pdev->dev.platform_data; | |
650 | ||
651 | if (!pdata) { | |
652 | dev_err(&pdev->dev, "%s: no platform data.\n", __func__); | |
653 | return -ENODEV; | |
654 | } | |
655 | ||
656 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
657 | if (unlikely(!irq)) { | |
658 | dev_err(&pdev->dev, "%s: no IRQ resource.\n", __func__); | |
659 | return -ENODEV; | |
660 | } | |
661 | ||
662 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
663 | if (unlikely(!mem)) { | |
664 | dev_err(&pdev->dev, "%s: no memory resource.\n", __func__); | |
665 | return -ENODEV; | |
666 | } | |
667 | ||
668 | ioarea = request_mem_region(mem->start, resource_size(mem), | |
669 | pdev->name); | |
670 | if (!ioarea) { | |
671 | dev_err(&pdev->dev, "%s: region already claimed.\n", __func__); | |
672 | return -EBUSY; | |
673 | } | |
674 | ||
675 | timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL); | |
676 | if (!timer) { | |
677 | dev_err(&pdev->dev, "%s: no memory for omap_dm_timer.\n", | |
678 | __func__); | |
679 | ret = -ENOMEM; | |
680 | goto err_free_ioregion; | |
681 | } | |
682 | ||
683 | timer->io_base = ioremap(mem->start, resource_size(mem)); | |
684 | if (!timer->io_base) { | |
685 | dev_err(&pdev->dev, "%s: ioremap failed.\n", __func__); | |
686 | ret = -ENOMEM; | |
687 | goto err_free_mem; | |
688 | } | |
689 | ||
690 | timer->id = pdev->id; | |
691 | timer->irq = irq->start; | |
b7b4ff76 | 692 | timer->reserved = omap_dm_timer_reserved_systimer(timer->id); |
df28472a | 693 | timer->pdev = pdev; |
d1c1691b | 694 | timer->capability = pdata->timer_capability; |
df28472a | 695 | |
ffe07cea TKD |
696 | /* Skip pm_runtime_enable for OMAP1 */ |
697 | if (!pdata->needs_manual_reset) { | |
698 | pm_runtime_enable(&pdev->dev); | |
699 | pm_runtime_irq_safe(&pdev->dev); | |
700 | } | |
701 | ||
0dad9fae TL |
702 | if (!timer->reserved) { |
703 | pm_runtime_get_sync(&pdev->dev); | |
704 | __omap_dm_timer_init_regs(timer); | |
705 | pm_runtime_put(&pdev->dev); | |
706 | } | |
707 | ||
df28472a TKD |
708 | /* add the timer element to the list */ |
709 | spin_lock_irqsave(&dm_timer_lock, flags); | |
710 | list_add_tail(&timer->node, &omap_timer_list); | |
711 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
712 | ||
713 | dev_dbg(&pdev->dev, "Device Probed.\n"); | |
714 | ||
715 | return 0; | |
716 | ||
717 | err_free_mem: | |
718 | kfree(timer); | |
719 | ||
720 | err_free_ioregion: | |
721 | release_mem_region(mem->start, resource_size(mem)); | |
722 | ||
723 | return ret; | |
724 | } | |
725 | ||
726 | /** | |
727 | * omap_dm_timer_remove - cleanup a registered timer device | |
728 | * @pdev: pointer to current timer platform device | |
729 | * | |
730 | * Called by driver framework whenever a timer device is unregistered. | |
731 | * In addition to freeing platform resources it also deletes the timer | |
732 | * entry from the local list. | |
733 | */ | |
734 | static int __devexit omap_dm_timer_remove(struct platform_device *pdev) | |
735 | { | |
736 | struct omap_dm_timer *timer; | |
737 | unsigned long flags; | |
738 | int ret = -EINVAL; | |
739 | ||
740 | spin_lock_irqsave(&dm_timer_lock, flags); | |
741 | list_for_each_entry(timer, &omap_timer_list, node) | |
742 | if (timer->pdev->id == pdev->id) { | |
743 | list_del(&timer->node); | |
744 | kfree(timer); | |
745 | ret = 0; | |
746 | break; | |
747 | } | |
748 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
749 | ||
750 | return ret; | |
751 | } | |
752 | ||
753 | static struct platform_driver omap_dm_timer_driver = { | |
754 | .probe = omap_dm_timer_probe, | |
4c23c8da | 755 | .remove = __devexit_p(omap_dm_timer_remove), |
df28472a TKD |
756 | .driver = { |
757 | .name = "omap_timer", | |
758 | }, | |
759 | }; | |
760 | ||
761 | static int __init omap_dm_timer_driver_init(void) | |
762 | { | |
763 | return platform_driver_register(&omap_dm_timer_driver); | |
764 | } | |
765 | ||
766 | static void __exit omap_dm_timer_driver_exit(void) | |
767 | { | |
768 | platform_driver_unregister(&omap_dm_timer_driver); | |
769 | } | |
770 | ||
771 | early_platform_init("earlytimer", &omap_dm_timer_driver); | |
772 | module_init(omap_dm_timer_driver_init); | |
773 | module_exit(omap_dm_timer_driver_exit); | |
774 | ||
775 | MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); | |
776 | MODULE_LICENSE("GPL"); | |
777 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
778 | MODULE_AUTHOR("Texas Instruments Inc"); |