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Commit | Line | Data |
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92105bb7 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dmtimer.c | |
3 | * | |
4 | * OMAP Dual-Mode Timers | |
5 | * | |
97933d6c TKD |
6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
7 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> | |
8 | * Thara Gopinath <thara@ti.com> | |
9 | * | |
10 | * dmtimer adaptation to platform_driver. | |
11 | * | |
92105bb7 | 12 | * Copyright (C) 2005 Nokia Corporation |
77900a2f TT |
13 | * OMAP2 support by Juha Yrjola |
14 | * API improvements and OMAP2 clock framework support by Timo Teras | |
92105bb7 | 15 | * |
44169075 SS |
16 | * Copyright (C) 2009 Texas Instruments |
17 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
18 | * | |
92105bb7 TL |
19 | * This program is free software; you can redistribute it and/or modify it |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
27 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
28 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License along | |
34 | * with this program; if not, write to the Free Software Foundation, Inc., | |
35 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
36 | */ | |
37 | ||
b1538832 | 38 | #include <linux/clk.h> |
869dec15 | 39 | #include <linux/module.h> |
fced80c7 | 40 | #include <linux/io.h> |
74dd9ec6 | 41 | #include <linux/device.h> |
3392cdd3 | 42 | #include <linux/err.h> |
ffe07cea | 43 | #include <linux/pm_runtime.h> |
9725f445 JH |
44 | #include <linux/of.h> |
45 | #include <linux/of_device.h> | |
44169075 | 46 | |
3392cdd3 | 47 | #include <plat/dmtimer.h> |
2c799cef | 48 | |
b7b4ff76 | 49 | static u32 omap_reserved_systimers; |
df28472a | 50 | static LIST_HEAD(omap_timer_list); |
3392cdd3 | 51 | static DEFINE_SPINLOCK(dm_timer_lock); |
92105bb7 | 52 | |
3392cdd3 TKD |
53 | /** |
54 | * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode | |
55 | * @timer: timer pointer over which read operation to perform | |
56 | * @reg: lowest byte holds the register offset | |
57 | * | |
58 | * The posted mode bit is encoded in reg. Note that in posted mode write | |
59 | * pending bit must be checked. Otherwise a read of a non completed write | |
60 | * will produce an error. | |
0f0d0807 RW |
61 | */ |
62 | static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) | |
77900a2f | 63 | { |
ee17f114 TL |
64 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
65 | return __omap_dm_timer_read(timer, reg, timer->posted); | |
77900a2f | 66 | } |
92105bb7 | 67 | |
3392cdd3 TKD |
68 | /** |
69 | * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode | |
70 | * @timer: timer pointer over which write operation is to perform | |
71 | * @reg: lowest byte holds the register offset | |
72 | * @value: data to write into the register | |
73 | * | |
74 | * The posted mode bit is encoded in reg. Note that in posted mode the write | |
75 | * pending bit must be checked. Otherwise a write on a register which has a | |
76 | * pending write will be lost. | |
0f0d0807 RW |
77 | */ |
78 | static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, | |
79 | u32 value) | |
92105bb7 | 80 | { |
ee17f114 TL |
81 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
82 | __omap_dm_timer_write(timer, reg, value, timer->posted); | |
92105bb7 TL |
83 | } |
84 | ||
b481113a TKD |
85 | static void omap_timer_restore_context(struct omap_dm_timer *timer) |
86 | { | |
b481113a TKD |
87 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, |
88 | timer->context.twer); | |
89 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, | |
90 | timer->context.tcrr); | |
91 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, | |
92 | timer->context.tldr); | |
93 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, | |
94 | timer->context.tmar); | |
95 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, | |
96 | timer->context.tsicr); | |
97 | __raw_writel(timer->context.tier, timer->irq_ena); | |
98 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, | |
99 | timer->context.tclr); | |
100 | } | |
101 | ||
ae6672cb | 102 | static int omap_dm_timer_reset(struct omap_dm_timer *timer) |
92105bb7 | 103 | { |
ae6672cb | 104 | u32 l, timeout = 100000; |
77900a2f | 105 | |
ae6672cb JH |
106 | if (timer->revision != 1) |
107 | return -EINVAL; | |
ee17f114 | 108 | |
ae6672cb JH |
109 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
110 | ||
111 | do { | |
112 | l = __omap_dm_timer_read(timer, | |
113 | OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); | |
114 | } while (!l && timeout--); | |
115 | ||
116 | if (!timeout) { | |
117 | dev_err(&timer->pdev->dev, "Timer failed to reset\n"); | |
118 | return -ETIMEDOUT; | |
77900a2f | 119 | } |
92105bb7 | 120 | |
ae6672cb JH |
121 | /* Configure timer for smart-idle mode */ |
122 | l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); | |
123 | l |= 0x2 << 0x3; | |
124 | __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); | |
125 | ||
126 | timer->posted = 0; | |
127 | ||
128 | return 0; | |
77900a2f TT |
129 | } |
130 | ||
b0cadb3c | 131 | static int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
77900a2f | 132 | { |
ae6672cb JH |
133 | int rc; |
134 | ||
bca45808 JH |
135 | /* |
136 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | |
137 | * do not call clk_get() for these devices. | |
138 | */ | |
139 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { | |
140 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); | |
141 | if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) { | |
142 | timer->fclk = NULL; | |
143 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); | |
144 | return -EINVAL; | |
145 | } | |
3392cdd3 TKD |
146 | } |
147 | ||
7b44cf2c JH |
148 | omap_dm_timer_enable(timer); |
149 | ||
ae6672cb JH |
150 | if (timer->capability & OMAP_TIMER_NEEDS_RESET) { |
151 | rc = omap_dm_timer_reset(timer); | |
152 | if (rc) { | |
153 | omap_dm_timer_disable(timer); | |
154 | return rc; | |
155 | } | |
156 | } | |
3392cdd3 | 157 | |
7b44cf2c JH |
158 | __omap_dm_timer_enable_posted(timer); |
159 | omap_dm_timer_disable(timer); | |
3392cdd3 | 160 | |
7b44cf2c | 161 | return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); |
77900a2f TT |
162 | } |
163 | ||
b7b4ff76 JH |
164 | static inline u32 omap_dm_timer_reserved_systimer(int id) |
165 | { | |
166 | return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; | |
167 | } | |
168 | ||
169 | int omap_dm_timer_reserve_systimer(int id) | |
170 | { | |
171 | if (omap_dm_timer_reserved_systimer(id)) | |
172 | return -ENODEV; | |
173 | ||
174 | omap_reserved_systimers |= (1 << (id - 1)); | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
77900a2f TT |
179 | struct omap_dm_timer *omap_dm_timer_request(void) |
180 | { | |
3392cdd3 | 181 | struct omap_dm_timer *timer = NULL, *t; |
77900a2f | 182 | unsigned long flags; |
3392cdd3 | 183 | int ret = 0; |
77900a2f TT |
184 | |
185 | spin_lock_irqsave(&dm_timer_lock, flags); | |
3392cdd3 TKD |
186 | list_for_each_entry(t, &omap_timer_list, node) { |
187 | if (t->reserved) | |
77900a2f TT |
188 | continue; |
189 | ||
3392cdd3 | 190 | timer = t; |
83379c81 | 191 | timer->reserved = 1; |
77900a2f TT |
192 | break; |
193 | } | |
c5491d1a | 194 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
3392cdd3 TKD |
195 | |
196 | if (timer) { | |
197 | ret = omap_dm_timer_prepare(timer); | |
198 | if (ret) { | |
199 | timer->reserved = 0; | |
200 | timer = NULL; | |
201 | } | |
202 | } | |
77900a2f | 203 | |
3392cdd3 TKD |
204 | if (!timer) |
205 | pr_debug("%s: timer request failed!\n", __func__); | |
83379c81 | 206 | |
77900a2f TT |
207 | return timer; |
208 | } | |
6c366e32 | 209 | EXPORT_SYMBOL_GPL(omap_dm_timer_request); |
77900a2f TT |
210 | |
211 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |
92105bb7 | 212 | { |
3392cdd3 | 213 | struct omap_dm_timer *timer = NULL, *t; |
77900a2f | 214 | unsigned long flags; |
3392cdd3 | 215 | int ret = 0; |
92105bb7 | 216 | |
9725f445 JH |
217 | /* Requesting timer by ID is not supported when device tree is used */ |
218 | if (of_have_populated_dt()) { | |
219 | pr_warn("%s: Please use omap_dm_timer_request_by_cap()\n", | |
220 | __func__); | |
221 | return NULL; | |
222 | } | |
223 | ||
77900a2f | 224 | spin_lock_irqsave(&dm_timer_lock, flags); |
3392cdd3 TKD |
225 | list_for_each_entry(t, &omap_timer_list, node) { |
226 | if (t->pdev->id == id && !t->reserved) { | |
227 | timer = t; | |
228 | timer->reserved = 1; | |
229 | break; | |
230 | } | |
77900a2f | 231 | } |
c5491d1a | 232 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
92105bb7 | 233 | |
3392cdd3 TKD |
234 | if (timer) { |
235 | ret = omap_dm_timer_prepare(timer); | |
236 | if (ret) { | |
237 | timer->reserved = 0; | |
238 | timer = NULL; | |
239 | } | |
240 | } | |
77900a2f | 241 | |
3392cdd3 TKD |
242 | if (!timer) |
243 | pr_debug("%s: timer%d request failed!\n", __func__, id); | |
83379c81 | 244 | |
77900a2f | 245 | return timer; |
92105bb7 | 246 | } |
6c366e32 | 247 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); |
92105bb7 | 248 | |
373fe0bd JH |
249 | /** |
250 | * omap_dm_timer_request_by_cap - Request a timer by capability | |
251 | * @cap: Bit mask of capabilities to match | |
252 | * | |
253 | * Find a timer based upon capabilities bit mask. Callers of this function | |
254 | * should use the definitions found in the plat/dmtimer.h file under the | |
255 | * comment "timer capabilities used in hwmod database". Returns pointer to | |
256 | * timer handle on success and a NULL pointer on failure. | |
257 | */ | |
258 | struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) | |
259 | { | |
260 | struct omap_dm_timer *timer = NULL, *t; | |
261 | unsigned long flags; | |
262 | ||
263 | if (!cap) | |
264 | return NULL; | |
265 | ||
266 | spin_lock_irqsave(&dm_timer_lock, flags); | |
267 | list_for_each_entry(t, &omap_timer_list, node) { | |
268 | if ((!t->reserved) && ((t->capability & cap) == cap)) { | |
269 | /* | |
270 | * If timer is not NULL, we have already found one timer | |
271 | * but it was not an exact match because it had more | |
272 | * capabilites that what was required. Therefore, | |
273 | * unreserve the last timer found and see if this one | |
274 | * is a better match. | |
275 | */ | |
276 | if (timer) | |
277 | timer->reserved = 0; | |
278 | ||
279 | timer = t; | |
280 | timer->reserved = 1; | |
281 | ||
282 | /* Exit loop early if we find an exact match */ | |
283 | if (t->capability == cap) | |
284 | break; | |
285 | } | |
286 | } | |
287 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
288 | ||
289 | if (timer && omap_dm_timer_prepare(timer)) { | |
290 | timer->reserved = 0; | |
291 | timer = NULL; | |
292 | } | |
293 | ||
294 | if (!timer) | |
295 | pr_debug("%s: timer request failed!\n", __func__); | |
296 | ||
297 | return timer; | |
298 | } | |
299 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap); | |
300 | ||
ab4eb8b0 | 301 | int omap_dm_timer_free(struct omap_dm_timer *timer) |
77900a2f | 302 | { |
ab4eb8b0 TKD |
303 | if (unlikely(!timer)) |
304 | return -EINVAL; | |
305 | ||
3392cdd3 | 306 | clk_put(timer->fclk); |
fa4bb626 | 307 | |
77900a2f TT |
308 | WARN_ON(!timer->reserved); |
309 | timer->reserved = 0; | |
ab4eb8b0 | 310 | return 0; |
77900a2f | 311 | } |
6c366e32 | 312 | EXPORT_SYMBOL_GPL(omap_dm_timer_free); |
77900a2f | 313 | |
12583a70 TT |
314 | void omap_dm_timer_enable(struct omap_dm_timer *timer) |
315 | { | |
ffe07cea | 316 | pm_runtime_get_sync(&timer->pdev->dev); |
12583a70 | 317 | } |
6c366e32 | 318 | EXPORT_SYMBOL_GPL(omap_dm_timer_enable); |
12583a70 TT |
319 | |
320 | void omap_dm_timer_disable(struct omap_dm_timer *timer) | |
321 | { | |
54f32a35 | 322 | pm_runtime_put_sync(&timer->pdev->dev); |
12583a70 | 323 | } |
6c366e32 | 324 | EXPORT_SYMBOL_GPL(omap_dm_timer_disable); |
12583a70 | 325 | |
77900a2f TT |
326 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) |
327 | { | |
ab4eb8b0 TKD |
328 | if (timer) |
329 | return timer->irq; | |
330 | return -EINVAL; | |
77900a2f | 331 | } |
6c366e32 | 332 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); |
77900a2f TT |
333 | |
334 | #if defined(CONFIG_ARCH_OMAP1) | |
7136f8d8 | 335 | #include <mach/hardware.h> |
a569c6ec TL |
336 | /** |
337 | * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR | |
338 | * @inputmask: current value of idlect mask | |
339 | */ | |
340 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |
341 | { | |
3392cdd3 TKD |
342 | int i = 0; |
343 | struct omap_dm_timer *timer = NULL; | |
344 | unsigned long flags; | |
a569c6ec TL |
345 | |
346 | /* If ARMXOR cannot be idled this function call is unnecessary */ | |
347 | if (!(inputmask & (1 << 1))) | |
348 | return inputmask; | |
349 | ||
350 | /* If any active timer is using ARMXOR return modified mask */ | |
3392cdd3 TKD |
351 | spin_lock_irqsave(&dm_timer_lock, flags); |
352 | list_for_each_entry(timer, &omap_timer_list, node) { | |
77900a2f TT |
353 | u32 l; |
354 | ||
3392cdd3 | 355 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
356 | if (l & OMAP_TIMER_CTRL_ST) { |
357 | if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) | |
a569c6ec TL |
358 | inputmask &= ~(1 << 1); |
359 | else | |
360 | inputmask &= ~(1 << 2); | |
361 | } | |
3392cdd3 | 362 | i++; |
77900a2f | 363 | } |
3392cdd3 | 364 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
a569c6ec TL |
365 | |
366 | return inputmask; | |
367 | } | |
6c366e32 | 368 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
a569c6ec | 369 | |
140455fa | 370 | #else |
a569c6ec | 371 | |
77900a2f | 372 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
92105bb7 | 373 | { |
ab4eb8b0 TKD |
374 | if (timer) |
375 | return timer->fclk; | |
376 | return NULL; | |
77900a2f | 377 | } |
6c366e32 | 378 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); |
92105bb7 | 379 | |
77900a2f TT |
380 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
381 | { | |
382 | BUG(); | |
2121880e DB |
383 | |
384 | return 0; | |
92105bb7 | 385 | } |
6c366e32 | 386 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
92105bb7 | 387 | |
77900a2f | 388 | #endif |
92105bb7 | 389 | |
ab4eb8b0 | 390 | int omap_dm_timer_trigger(struct omap_dm_timer *timer) |
92105bb7 | 391 | { |
ab4eb8b0 TKD |
392 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
393 | pr_err("%s: timer not available or enabled.\n", __func__); | |
394 | return -EINVAL; | |
b481113a TKD |
395 | } |
396 | ||
77900a2f | 397 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
ab4eb8b0 | 398 | return 0; |
92105bb7 | 399 | } |
6c366e32 | 400 | EXPORT_SYMBOL_GPL(omap_dm_timer_trigger); |
92105bb7 | 401 | |
ab4eb8b0 | 402 | int omap_dm_timer_start(struct omap_dm_timer *timer) |
77900a2f TT |
403 | { |
404 | u32 l; | |
92105bb7 | 405 | |
ab4eb8b0 TKD |
406 | if (unlikely(!timer)) |
407 | return -EINVAL; | |
408 | ||
b481113a TKD |
409 | omap_dm_timer_enable(timer); |
410 | ||
1c2d076b | 411 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
6e740f9a TL |
412 | if (timer->get_context_loss_count && |
413 | timer->get_context_loss_count(&timer->pdev->dev) != | |
0b30ec1c | 414 | timer->ctx_loss_count) |
b481113a TKD |
415 | omap_timer_restore_context(timer); |
416 | } | |
417 | ||
77900a2f TT |
418 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
419 | if (!(l & OMAP_TIMER_CTRL_ST)) { | |
420 | l |= OMAP_TIMER_CTRL_ST; | |
421 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
422 | } | |
b481113a TKD |
423 | |
424 | /* Save the context */ | |
425 | timer->context.tclr = l; | |
ab4eb8b0 | 426 | return 0; |
77900a2f | 427 | } |
6c366e32 | 428 | EXPORT_SYMBOL_GPL(omap_dm_timer_start); |
92105bb7 | 429 | |
ab4eb8b0 | 430 | int omap_dm_timer_stop(struct omap_dm_timer *timer) |
92105bb7 | 431 | { |
caf64f2f | 432 | unsigned long rate = 0; |
92105bb7 | 433 | |
ab4eb8b0 TKD |
434 | if (unlikely(!timer)) |
435 | return -EINVAL; | |
436 | ||
6615975b | 437 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) |
3392cdd3 | 438 | rate = clk_get_rate(timer->fclk); |
caf64f2f | 439 | |
ee17f114 | 440 | __omap_dm_timer_stop(timer, timer->posted, rate); |
ab4eb8b0 | 441 | |
6e740f9a TL |
442 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
443 | if (timer->get_context_loss_count) | |
444 | timer->ctx_loss_count = | |
445 | timer->get_context_loss_count(&timer->pdev->dev); | |
446 | } | |
dffc9dae TKD |
447 | |
448 | /* | |
449 | * Since the register values are computed and written within | |
450 | * __omap_dm_timer_stop, we need to use read to retrieve the | |
451 | * context. | |
452 | */ | |
453 | timer->context.tclr = | |
454 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
dffc9dae | 455 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 456 | return 0; |
92105bb7 | 457 | } |
6c366e32 | 458 | EXPORT_SYMBOL_GPL(omap_dm_timer_stop); |
92105bb7 | 459 | |
f248076c | 460 | int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
92105bb7 | 461 | { |
3392cdd3 | 462 | int ret; |
2b2d3523 | 463 | char *parent_name = NULL; |
d7aba554 | 464 | struct clk *parent; |
ab4eb8b0 TKD |
465 | struct dmtimer_platform_data *pdata; |
466 | ||
467 | if (unlikely(!timer)) | |
468 | return -EINVAL; | |
469 | ||
470 | pdata = timer->pdev->dev.platform_data; | |
3392cdd3 | 471 | |
77900a2f | 472 | if (source < 0 || source >= 3) |
f248076c | 473 | return -EINVAL; |
77900a2f | 474 | |
2b2d3523 JH |
475 | /* |
476 | * FIXME: Used for OMAP1 devices only because they do not currently | |
477 | * use the clock framework to set the parent clock. To be removed | |
478 | * once OMAP1 migrated to using clock framework for dmtimers | |
479 | */ | |
9725f445 | 480 | if (pdata && pdata->set_timer_src) |
2b2d3523 JH |
481 | return pdata->set_timer_src(timer->pdev, source); |
482 | ||
d7aba554 | 483 | if (!timer->fclk) |
2b2d3523 | 484 | return -EINVAL; |
2b2d3523 JH |
485 | |
486 | switch (source) { | |
487 | case OMAP_TIMER_SRC_SYS_CLK: | |
c59b537d | 488 | parent_name = "timer_sys_ck"; |
2b2d3523 JH |
489 | break; |
490 | ||
491 | case OMAP_TIMER_SRC_32_KHZ: | |
c59b537d | 492 | parent_name = "timer_32k_ck"; |
2b2d3523 JH |
493 | break; |
494 | ||
495 | case OMAP_TIMER_SRC_EXT_CLK: | |
c59b537d | 496 | parent_name = "timer_ext_ck"; |
2b2d3523 JH |
497 | break; |
498 | } | |
499 | ||
500 | parent = clk_get(&timer->pdev->dev, parent_name); | |
501 | if (IS_ERR_OR_NULL(parent)) { | |
502 | pr_err("%s: %s not found\n", __func__, parent_name); | |
d7aba554 | 503 | return -EINVAL; |
2b2d3523 JH |
504 | } |
505 | ||
d7aba554 | 506 | ret = clk_set_parent(timer->fclk, parent); |
2b2d3523 JH |
507 | if (IS_ERR_VALUE(ret)) |
508 | pr_err("%s: failed to set %s as parent\n", __func__, | |
509 | parent_name); | |
510 | ||
511 | clk_put(parent); | |
3392cdd3 TKD |
512 | |
513 | return ret; | |
92105bb7 | 514 | } |
6c366e32 | 515 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); |
92105bb7 | 516 | |
ab4eb8b0 | 517 | int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, |
77900a2f | 518 | unsigned int load) |
92105bb7 TL |
519 | { |
520 | u32 l; | |
77900a2f | 521 | |
ab4eb8b0 TKD |
522 | if (unlikely(!timer)) |
523 | return -EINVAL; | |
524 | ||
b481113a | 525 | omap_dm_timer_enable(timer); |
92105bb7 | 526 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
527 | if (autoreload) |
528 | l |= OMAP_TIMER_CTRL_AR; | |
529 | else | |
530 | l &= ~OMAP_TIMER_CTRL_AR; | |
92105bb7 | 531 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 532 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
0f0d0807 | 533 | |
77900a2f | 534 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
b481113a TKD |
535 | /* Save the context */ |
536 | timer->context.tclr = l; | |
537 | timer->context.tldr = load; | |
538 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 539 | return 0; |
92105bb7 | 540 | } |
6c366e32 | 541 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load); |
92105bb7 | 542 | |
3fddd09e | 543 | /* Optimized set_load which removes costly spin wait in timer_start */ |
ab4eb8b0 | 544 | int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, |
3fddd09e RW |
545 | unsigned int load) |
546 | { | |
547 | u32 l; | |
548 | ||
ab4eb8b0 TKD |
549 | if (unlikely(!timer)) |
550 | return -EINVAL; | |
551 | ||
b481113a TKD |
552 | omap_dm_timer_enable(timer); |
553 | ||
1c2d076b | 554 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
6e740f9a TL |
555 | if (timer->get_context_loss_count && |
556 | timer->get_context_loss_count(&timer->pdev->dev) != | |
0b30ec1c | 557 | timer->ctx_loss_count) |
b481113a TKD |
558 | omap_timer_restore_context(timer); |
559 | } | |
560 | ||
3fddd09e | 561 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
64ce2907 | 562 | if (autoreload) { |
3fddd09e | 563 | l |= OMAP_TIMER_CTRL_AR; |
64ce2907 PW |
564 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
565 | } else { | |
3fddd09e | 566 | l &= ~OMAP_TIMER_CTRL_AR; |
64ce2907 | 567 | } |
3fddd09e RW |
568 | l |= OMAP_TIMER_CTRL_ST; |
569 | ||
ee17f114 | 570 | __omap_dm_timer_load_start(timer, l, load, timer->posted); |
b481113a TKD |
571 | |
572 | /* Save the context */ | |
573 | timer->context.tclr = l; | |
574 | timer->context.tldr = load; | |
575 | timer->context.tcrr = load; | |
ab4eb8b0 | 576 | return 0; |
3fddd09e | 577 | } |
6c366e32 | 578 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); |
3fddd09e | 579 | |
ab4eb8b0 | 580 | int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
77900a2f | 581 | unsigned int match) |
92105bb7 TL |
582 | { |
583 | u32 l; | |
584 | ||
ab4eb8b0 TKD |
585 | if (unlikely(!timer)) |
586 | return -EINVAL; | |
587 | ||
b481113a | 588 | omap_dm_timer_enable(timer); |
92105bb7 | 589 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
83379c81 | 590 | if (enable) |
77900a2f TT |
591 | l |= OMAP_TIMER_CTRL_CE; |
592 | else | |
593 | l &= ~OMAP_TIMER_CTRL_CE; | |
77900a2f | 594 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
991ad16a | 595 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
596 | |
597 | /* Save the context */ | |
598 | timer->context.tclr = l; | |
599 | timer->context.tmar = match; | |
600 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 601 | return 0; |
92105bb7 | 602 | } |
6c366e32 | 603 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_match); |
92105bb7 | 604 | |
ab4eb8b0 | 605 | int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
77900a2f | 606 | int toggle, int trigger) |
92105bb7 TL |
607 | { |
608 | u32 l; | |
609 | ||
ab4eb8b0 TKD |
610 | if (unlikely(!timer)) |
611 | return -EINVAL; | |
612 | ||
b481113a | 613 | omap_dm_timer_enable(timer); |
92105bb7 | 614 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
615 | l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
616 | OMAP_TIMER_CTRL_PT | (0x03 << 10)); | |
617 | if (def_on) | |
618 | l |= OMAP_TIMER_CTRL_SCPWM; | |
619 | if (toggle) | |
620 | l |= OMAP_TIMER_CTRL_PT; | |
621 | l |= trigger << 10; | |
92105bb7 | 622 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
623 | |
624 | /* Save the context */ | |
625 | timer->context.tclr = l; | |
626 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 627 | return 0; |
92105bb7 | 628 | } |
6c366e32 | 629 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm); |
92105bb7 | 630 | |
ab4eb8b0 | 631 | int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) |
92105bb7 TL |
632 | { |
633 | u32 l; | |
634 | ||
ab4eb8b0 TKD |
635 | if (unlikely(!timer)) |
636 | return -EINVAL; | |
637 | ||
b481113a | 638 | omap_dm_timer_enable(timer); |
92105bb7 | 639 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
640 | l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
641 | if (prescaler >= 0x00 && prescaler <= 0x07) { | |
642 | l |= OMAP_TIMER_CTRL_PRE; | |
643 | l |= prescaler << 2; | |
644 | } | |
92105bb7 | 645 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
646 | |
647 | /* Save the context */ | |
648 | timer->context.tclr = l; | |
649 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 650 | return 0; |
92105bb7 | 651 | } |
6c366e32 | 652 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler); |
92105bb7 | 653 | |
ab4eb8b0 | 654 | int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
77900a2f | 655 | unsigned int value) |
92105bb7 | 656 | { |
ab4eb8b0 TKD |
657 | if (unlikely(!timer)) |
658 | return -EINVAL; | |
659 | ||
b481113a | 660 | omap_dm_timer_enable(timer); |
ee17f114 | 661 | __omap_dm_timer_int_enable(timer, value); |
b481113a TKD |
662 | |
663 | /* Save the context */ | |
664 | timer->context.tier = value; | |
665 | timer->context.twer = value; | |
666 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 667 | return 0; |
92105bb7 | 668 | } |
6c366e32 | 669 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); |
92105bb7 | 670 | |
4249d96c JH |
671 | /** |
672 | * omap_dm_timer_set_int_disable - disable timer interrupts | |
673 | * @timer: pointer to timer handle | |
674 | * @mask: bit mask of interrupts to be disabled | |
675 | * | |
676 | * Disables the specified timer interrupts for a timer. | |
677 | */ | |
678 | int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) | |
679 | { | |
680 | u32 l = mask; | |
681 | ||
682 | if (unlikely(!timer)) | |
683 | return -EINVAL; | |
684 | ||
685 | omap_dm_timer_enable(timer); | |
686 | ||
687 | if (timer->revision == 1) | |
688 | l = __raw_readl(timer->irq_ena) & ~mask; | |
689 | ||
690 | __raw_writel(l, timer->irq_dis); | |
691 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; | |
692 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); | |
693 | ||
694 | /* Save the context */ | |
695 | timer->context.tier &= ~mask; | |
696 | timer->context.twer &= ~mask; | |
697 | omap_dm_timer_disable(timer); | |
698 | return 0; | |
699 | } | |
700 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable); | |
701 | ||
77900a2f | 702 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
92105bb7 | 703 | { |
fa4bb626 TT |
704 | unsigned int l; |
705 | ||
ab4eb8b0 TKD |
706 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
707 | pr_err("%s: timer not available or enabled.\n", __func__); | |
b481113a TKD |
708 | return 0; |
709 | } | |
710 | ||
ee17f114 | 711 | l = __raw_readl(timer->irq_stat); |
fa4bb626 TT |
712 | |
713 | return l; | |
92105bb7 | 714 | } |
6c366e32 | 715 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_status); |
92105bb7 | 716 | |
ab4eb8b0 | 717 | int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
92105bb7 | 718 | { |
ab4eb8b0 TKD |
719 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) |
720 | return -EINVAL; | |
721 | ||
ee17f114 | 722 | __omap_dm_timer_write_status(timer, value); |
1eaff710 | 723 | |
ab4eb8b0 | 724 | return 0; |
92105bb7 | 725 | } |
6c366e32 | 726 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); |
92105bb7 | 727 | |
77900a2f | 728 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
92105bb7 | 729 | { |
ab4eb8b0 TKD |
730 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
731 | pr_err("%s: timer not iavailable or enabled.\n", __func__); | |
b481113a TKD |
732 | return 0; |
733 | } | |
734 | ||
ee17f114 | 735 | return __omap_dm_timer_read_counter(timer, timer->posted); |
92105bb7 | 736 | } |
6c366e32 | 737 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); |
92105bb7 | 738 | |
ab4eb8b0 | 739 | int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
83379c81 | 740 | { |
ab4eb8b0 TKD |
741 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
742 | pr_err("%s: timer not available or enabled.\n", __func__); | |
743 | return -EINVAL; | |
b481113a TKD |
744 | } |
745 | ||
fa4bb626 | 746 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
b481113a TKD |
747 | |
748 | /* Save the context */ | |
749 | timer->context.tcrr = value; | |
ab4eb8b0 | 750 | return 0; |
83379c81 | 751 | } |
6c366e32 | 752 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter); |
83379c81 | 753 | |
77900a2f | 754 | int omap_dm_timers_active(void) |
92105bb7 | 755 | { |
3392cdd3 | 756 | struct omap_dm_timer *timer; |
12583a70 | 757 | |
3392cdd3 | 758 | list_for_each_entry(timer, &omap_timer_list, node) { |
ffe07cea | 759 | if (!timer->reserved) |
12583a70 TT |
760 | continue; |
761 | ||
77900a2f | 762 | if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
fa4bb626 | 763 | OMAP_TIMER_CTRL_ST) { |
77900a2f | 764 | return 1; |
fa4bb626 | 765 | } |
77900a2f TT |
766 | } |
767 | return 0; | |
768 | } | |
6c366e32 | 769 | EXPORT_SYMBOL_GPL(omap_dm_timers_active); |
92105bb7 | 770 | |
df28472a TKD |
771 | /** |
772 | * omap_dm_timer_probe - probe function called for every registered device | |
773 | * @pdev: pointer to current timer platform device | |
774 | * | |
775 | * Called by driver framework at the end of device registration for all | |
776 | * timer devices. | |
777 | */ | |
778 | static int __devinit omap_dm_timer_probe(struct platform_device *pdev) | |
779 | { | |
df28472a TKD |
780 | unsigned long flags; |
781 | struct omap_dm_timer *timer; | |
74dd9ec6 TKD |
782 | struct resource *mem, *irq; |
783 | struct device *dev = &pdev->dev; | |
df28472a TKD |
784 | struct dmtimer_platform_data *pdata = pdev->dev.platform_data; |
785 | ||
9725f445 | 786 | if (!pdata && !dev->of_node) { |
74dd9ec6 | 787 | dev_err(dev, "%s: no platform data.\n", __func__); |
df28472a TKD |
788 | return -ENODEV; |
789 | } | |
790 | ||
791 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
792 | if (unlikely(!irq)) { | |
74dd9ec6 | 793 | dev_err(dev, "%s: no IRQ resource.\n", __func__); |
df28472a TKD |
794 | return -ENODEV; |
795 | } | |
796 | ||
797 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
798 | if (unlikely(!mem)) { | |
74dd9ec6 | 799 | dev_err(dev, "%s: no memory resource.\n", __func__); |
df28472a TKD |
800 | return -ENODEV; |
801 | } | |
802 | ||
74dd9ec6 | 803 | timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL); |
df28472a | 804 | if (!timer) { |
74dd9ec6 TKD |
805 | dev_err(dev, "%s: memory alloc failed!\n", __func__); |
806 | return -ENOMEM; | |
df28472a TKD |
807 | } |
808 | ||
74dd9ec6 | 809 | timer->io_base = devm_request_and_ioremap(dev, mem); |
df28472a | 810 | if (!timer->io_base) { |
74dd9ec6 TKD |
811 | dev_err(dev, "%s: region already claimed.\n", __func__); |
812 | return -ENOMEM; | |
df28472a TKD |
813 | } |
814 | ||
9725f445 JH |
815 | if (dev->of_node) { |
816 | if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) | |
817 | timer->capability |= OMAP_TIMER_ALWON; | |
818 | if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) | |
819 | timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; | |
820 | if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) | |
821 | timer->capability |= OMAP_TIMER_HAS_PWM; | |
822 | if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) | |
823 | timer->capability |= OMAP_TIMER_SECURE; | |
824 | } else { | |
825 | timer->id = pdev->id; | |
bfd6d021 | 826 | timer->errata = pdata->timer_errata; |
9725f445 JH |
827 | timer->capability = pdata->timer_capability; |
828 | timer->reserved = omap_dm_timer_reserved_systimer(timer->id); | |
f56f52e0 | 829 | timer->get_context_loss_count = pdata->get_context_loss_count; |
9725f445 JH |
830 | } |
831 | ||
df28472a TKD |
832 | timer->irq = irq->start; |
833 | timer->pdev = pdev; | |
df28472a | 834 | |
ffe07cea | 835 | /* Skip pm_runtime_enable for OMAP1 */ |
6615975b | 836 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { |
74dd9ec6 TKD |
837 | pm_runtime_enable(dev); |
838 | pm_runtime_irq_safe(dev); | |
ffe07cea TKD |
839 | } |
840 | ||
0dad9fae | 841 | if (!timer->reserved) { |
74dd9ec6 | 842 | pm_runtime_get_sync(dev); |
0dad9fae | 843 | __omap_dm_timer_init_regs(timer); |
74dd9ec6 | 844 | pm_runtime_put(dev); |
0dad9fae TL |
845 | } |
846 | ||
df28472a TKD |
847 | /* add the timer element to the list */ |
848 | spin_lock_irqsave(&dm_timer_lock, flags); | |
849 | list_add_tail(&timer->node, &omap_timer_list); | |
850 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
851 | ||
74dd9ec6 | 852 | dev_dbg(dev, "Device Probed.\n"); |
df28472a TKD |
853 | |
854 | return 0; | |
df28472a TKD |
855 | } |
856 | ||
857 | /** | |
858 | * omap_dm_timer_remove - cleanup a registered timer device | |
859 | * @pdev: pointer to current timer platform device | |
860 | * | |
861 | * Called by driver framework whenever a timer device is unregistered. | |
862 | * In addition to freeing platform resources it also deletes the timer | |
863 | * entry from the local list. | |
864 | */ | |
865 | static int __devexit omap_dm_timer_remove(struct platform_device *pdev) | |
866 | { | |
867 | struct omap_dm_timer *timer; | |
868 | unsigned long flags; | |
869 | int ret = -EINVAL; | |
870 | ||
871 | spin_lock_irqsave(&dm_timer_lock, flags); | |
872 | list_for_each_entry(timer, &omap_timer_list, node) | |
9725f445 JH |
873 | if (!strcmp(dev_name(&timer->pdev->dev), |
874 | dev_name(&pdev->dev))) { | |
df28472a | 875 | list_del(&timer->node); |
df28472a TKD |
876 | ret = 0; |
877 | break; | |
878 | } | |
879 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
880 | ||
881 | return ret; | |
882 | } | |
883 | ||
9725f445 JH |
884 | static const struct of_device_id omap_timer_match[] = { |
885 | { .compatible = "ti,omap2-timer", }, | |
886 | {}, | |
887 | }; | |
888 | MODULE_DEVICE_TABLE(of, omap_timer_match); | |
889 | ||
df28472a TKD |
890 | static struct platform_driver omap_dm_timer_driver = { |
891 | .probe = omap_dm_timer_probe, | |
4c23c8da | 892 | .remove = __devexit_p(omap_dm_timer_remove), |
df28472a TKD |
893 | .driver = { |
894 | .name = "omap_timer", | |
9725f445 | 895 | .of_match_table = of_match_ptr(omap_timer_match), |
df28472a TKD |
896 | }, |
897 | }; | |
898 | ||
899 | static int __init omap_dm_timer_driver_init(void) | |
900 | { | |
901 | return platform_driver_register(&omap_dm_timer_driver); | |
902 | } | |
903 | ||
904 | static void __exit omap_dm_timer_driver_exit(void) | |
905 | { | |
906 | platform_driver_unregister(&omap_dm_timer_driver); | |
907 | } | |
908 | ||
909 | early_platform_init("earlytimer", &omap_dm_timer_driver); | |
910 | module_init(omap_dm_timer_driver_init); | |
911 | module_exit(omap_dm_timer_driver_exit); | |
912 | ||
913 | MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); | |
914 | MODULE_LICENSE("GPL"); | |
915 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
916 | MODULE_AUTHOR("Texas Instruments Inc"); |