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Commit | Line | Data |
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92105bb7 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dmtimer.c | |
3 | * | |
4 | * OMAP Dual-Mode Timers | |
5 | * | |
97933d6c TKD |
6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
7 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> | |
8 | * Thara Gopinath <thara@ti.com> | |
9 | * | |
10 | * dmtimer adaptation to platform_driver. | |
11 | * | |
92105bb7 | 12 | * Copyright (C) 2005 Nokia Corporation |
77900a2f TT |
13 | * OMAP2 support by Juha Yrjola |
14 | * API improvements and OMAP2 clock framework support by Timo Teras | |
92105bb7 | 15 | * |
44169075 SS |
16 | * Copyright (C) 2009 Texas Instruments |
17 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
18 | * | |
92105bb7 TL |
19 | * This program is free software; you can redistribute it and/or modify it |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
27 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
28 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License along | |
34 | * with this program; if not, write to the Free Software Foundation, Inc., | |
35 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
36 | */ | |
37 | ||
b1538832 | 38 | #include <linux/clk.h> |
869dec15 | 39 | #include <linux/module.h> |
fced80c7 | 40 | #include <linux/io.h> |
74dd9ec6 | 41 | #include <linux/device.h> |
3392cdd3 | 42 | #include <linux/err.h> |
ffe07cea | 43 | #include <linux/pm_runtime.h> |
9725f445 JH |
44 | #include <linux/of.h> |
45 | #include <linux/of_device.h> | |
40fc3bb5 JH |
46 | #include <linux/platform_device.h> |
47 | #include <linux/platform_data/dmtimer-omap.h> | |
44169075 | 48 | |
3392cdd3 | 49 | #include <plat/dmtimer.h> |
2c799cef | 50 | |
b7b4ff76 | 51 | static u32 omap_reserved_systimers; |
df28472a | 52 | static LIST_HEAD(omap_timer_list); |
3392cdd3 | 53 | static DEFINE_SPINLOCK(dm_timer_lock); |
92105bb7 | 54 | |
3392cdd3 TKD |
55 | /** |
56 | * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode | |
57 | * @timer: timer pointer over which read operation to perform | |
58 | * @reg: lowest byte holds the register offset | |
59 | * | |
60 | * The posted mode bit is encoded in reg. Note that in posted mode write | |
61 | * pending bit must be checked. Otherwise a read of a non completed write | |
62 | * will produce an error. | |
0f0d0807 RW |
63 | */ |
64 | static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) | |
77900a2f | 65 | { |
ee17f114 TL |
66 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
67 | return __omap_dm_timer_read(timer, reg, timer->posted); | |
77900a2f | 68 | } |
92105bb7 | 69 | |
3392cdd3 TKD |
70 | /** |
71 | * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode | |
72 | * @timer: timer pointer over which write operation is to perform | |
73 | * @reg: lowest byte holds the register offset | |
74 | * @value: data to write into the register | |
75 | * | |
76 | * The posted mode bit is encoded in reg. Note that in posted mode the write | |
77 | * pending bit must be checked. Otherwise a write on a register which has a | |
78 | * pending write will be lost. | |
0f0d0807 RW |
79 | */ |
80 | static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, | |
81 | u32 value) | |
92105bb7 | 82 | { |
ee17f114 TL |
83 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
84 | __omap_dm_timer_write(timer, reg, value, timer->posted); | |
92105bb7 TL |
85 | } |
86 | ||
b481113a TKD |
87 | static void omap_timer_restore_context(struct omap_dm_timer *timer) |
88 | { | |
b481113a TKD |
89 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, |
90 | timer->context.twer); | |
91 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, | |
92 | timer->context.tcrr); | |
93 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, | |
94 | timer->context.tldr); | |
95 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, | |
96 | timer->context.tmar); | |
97 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, | |
98 | timer->context.tsicr); | |
99 | __raw_writel(timer->context.tier, timer->irq_ena); | |
100 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, | |
101 | timer->context.tclr); | |
102 | } | |
103 | ||
ae6672cb | 104 | static int omap_dm_timer_reset(struct omap_dm_timer *timer) |
92105bb7 | 105 | { |
ae6672cb | 106 | u32 l, timeout = 100000; |
77900a2f | 107 | |
ae6672cb JH |
108 | if (timer->revision != 1) |
109 | return -EINVAL; | |
ee17f114 | 110 | |
ae6672cb JH |
111 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
112 | ||
113 | do { | |
114 | l = __omap_dm_timer_read(timer, | |
115 | OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); | |
116 | } while (!l && timeout--); | |
117 | ||
118 | if (!timeout) { | |
119 | dev_err(&timer->pdev->dev, "Timer failed to reset\n"); | |
120 | return -ETIMEDOUT; | |
77900a2f | 121 | } |
92105bb7 | 122 | |
ae6672cb JH |
123 | /* Configure timer for smart-idle mode */ |
124 | l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); | |
125 | l |= 0x2 << 0x3; | |
126 | __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); | |
127 | ||
128 | timer->posted = 0; | |
129 | ||
130 | return 0; | |
77900a2f TT |
131 | } |
132 | ||
b0cadb3c | 133 | static int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
77900a2f | 134 | { |
ae6672cb JH |
135 | int rc; |
136 | ||
bca45808 JH |
137 | /* |
138 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | |
139 | * do not call clk_get() for these devices. | |
140 | */ | |
141 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { | |
142 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); | |
143 | if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) { | |
144 | timer->fclk = NULL; | |
145 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); | |
146 | return -EINVAL; | |
147 | } | |
3392cdd3 TKD |
148 | } |
149 | ||
7b44cf2c JH |
150 | omap_dm_timer_enable(timer); |
151 | ||
ae6672cb JH |
152 | if (timer->capability & OMAP_TIMER_NEEDS_RESET) { |
153 | rc = omap_dm_timer_reset(timer); | |
154 | if (rc) { | |
155 | omap_dm_timer_disable(timer); | |
156 | return rc; | |
157 | } | |
158 | } | |
3392cdd3 | 159 | |
7b44cf2c JH |
160 | __omap_dm_timer_enable_posted(timer); |
161 | omap_dm_timer_disable(timer); | |
3392cdd3 | 162 | |
7b44cf2c | 163 | return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); |
77900a2f TT |
164 | } |
165 | ||
b7b4ff76 JH |
166 | static inline u32 omap_dm_timer_reserved_systimer(int id) |
167 | { | |
168 | return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; | |
169 | } | |
170 | ||
171 | int omap_dm_timer_reserve_systimer(int id) | |
172 | { | |
173 | if (omap_dm_timer_reserved_systimer(id)) | |
174 | return -ENODEV; | |
175 | ||
176 | omap_reserved_systimers |= (1 << (id - 1)); | |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
77900a2f TT |
181 | struct omap_dm_timer *omap_dm_timer_request(void) |
182 | { | |
3392cdd3 | 183 | struct omap_dm_timer *timer = NULL, *t; |
77900a2f | 184 | unsigned long flags; |
3392cdd3 | 185 | int ret = 0; |
77900a2f TT |
186 | |
187 | spin_lock_irqsave(&dm_timer_lock, flags); | |
3392cdd3 TKD |
188 | list_for_each_entry(t, &omap_timer_list, node) { |
189 | if (t->reserved) | |
77900a2f TT |
190 | continue; |
191 | ||
3392cdd3 | 192 | timer = t; |
83379c81 | 193 | timer->reserved = 1; |
77900a2f TT |
194 | break; |
195 | } | |
c5491d1a | 196 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
3392cdd3 TKD |
197 | |
198 | if (timer) { | |
199 | ret = omap_dm_timer_prepare(timer); | |
200 | if (ret) { | |
201 | timer->reserved = 0; | |
202 | timer = NULL; | |
203 | } | |
204 | } | |
77900a2f | 205 | |
3392cdd3 TKD |
206 | if (!timer) |
207 | pr_debug("%s: timer request failed!\n", __func__); | |
83379c81 | 208 | |
77900a2f TT |
209 | return timer; |
210 | } | |
6c366e32 | 211 | EXPORT_SYMBOL_GPL(omap_dm_timer_request); |
77900a2f TT |
212 | |
213 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |
92105bb7 | 214 | { |
3392cdd3 | 215 | struct omap_dm_timer *timer = NULL, *t; |
77900a2f | 216 | unsigned long flags; |
3392cdd3 | 217 | int ret = 0; |
92105bb7 | 218 | |
9725f445 JH |
219 | /* Requesting timer by ID is not supported when device tree is used */ |
220 | if (of_have_populated_dt()) { | |
221 | pr_warn("%s: Please use omap_dm_timer_request_by_cap()\n", | |
222 | __func__); | |
223 | return NULL; | |
224 | } | |
225 | ||
77900a2f | 226 | spin_lock_irqsave(&dm_timer_lock, flags); |
3392cdd3 TKD |
227 | list_for_each_entry(t, &omap_timer_list, node) { |
228 | if (t->pdev->id == id && !t->reserved) { | |
229 | timer = t; | |
230 | timer->reserved = 1; | |
231 | break; | |
232 | } | |
77900a2f | 233 | } |
c5491d1a | 234 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
92105bb7 | 235 | |
3392cdd3 TKD |
236 | if (timer) { |
237 | ret = omap_dm_timer_prepare(timer); | |
238 | if (ret) { | |
239 | timer->reserved = 0; | |
240 | timer = NULL; | |
241 | } | |
242 | } | |
77900a2f | 243 | |
3392cdd3 TKD |
244 | if (!timer) |
245 | pr_debug("%s: timer%d request failed!\n", __func__, id); | |
83379c81 | 246 | |
77900a2f | 247 | return timer; |
92105bb7 | 248 | } |
6c366e32 | 249 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); |
92105bb7 | 250 | |
373fe0bd JH |
251 | /** |
252 | * omap_dm_timer_request_by_cap - Request a timer by capability | |
253 | * @cap: Bit mask of capabilities to match | |
254 | * | |
255 | * Find a timer based upon capabilities bit mask. Callers of this function | |
256 | * should use the definitions found in the plat/dmtimer.h file under the | |
257 | * comment "timer capabilities used in hwmod database". Returns pointer to | |
258 | * timer handle on success and a NULL pointer on failure. | |
259 | */ | |
260 | struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) | |
261 | { | |
262 | struct omap_dm_timer *timer = NULL, *t; | |
263 | unsigned long flags; | |
264 | ||
265 | if (!cap) | |
266 | return NULL; | |
267 | ||
268 | spin_lock_irqsave(&dm_timer_lock, flags); | |
269 | list_for_each_entry(t, &omap_timer_list, node) { | |
270 | if ((!t->reserved) && ((t->capability & cap) == cap)) { | |
271 | /* | |
272 | * If timer is not NULL, we have already found one timer | |
273 | * but it was not an exact match because it had more | |
274 | * capabilites that what was required. Therefore, | |
275 | * unreserve the last timer found and see if this one | |
276 | * is a better match. | |
277 | */ | |
278 | if (timer) | |
279 | timer->reserved = 0; | |
280 | ||
281 | timer = t; | |
282 | timer->reserved = 1; | |
283 | ||
284 | /* Exit loop early if we find an exact match */ | |
285 | if (t->capability == cap) | |
286 | break; | |
287 | } | |
288 | } | |
289 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
290 | ||
291 | if (timer && omap_dm_timer_prepare(timer)) { | |
292 | timer->reserved = 0; | |
293 | timer = NULL; | |
294 | } | |
295 | ||
296 | if (!timer) | |
297 | pr_debug("%s: timer request failed!\n", __func__); | |
298 | ||
299 | return timer; | |
300 | } | |
301 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap); | |
302 | ||
ab4eb8b0 | 303 | int omap_dm_timer_free(struct omap_dm_timer *timer) |
77900a2f | 304 | { |
ab4eb8b0 TKD |
305 | if (unlikely(!timer)) |
306 | return -EINVAL; | |
307 | ||
3392cdd3 | 308 | clk_put(timer->fclk); |
fa4bb626 | 309 | |
77900a2f TT |
310 | WARN_ON(!timer->reserved); |
311 | timer->reserved = 0; | |
ab4eb8b0 | 312 | return 0; |
77900a2f | 313 | } |
6c366e32 | 314 | EXPORT_SYMBOL_GPL(omap_dm_timer_free); |
77900a2f | 315 | |
12583a70 TT |
316 | void omap_dm_timer_enable(struct omap_dm_timer *timer) |
317 | { | |
ffe07cea | 318 | pm_runtime_get_sync(&timer->pdev->dev); |
12583a70 | 319 | } |
6c366e32 | 320 | EXPORT_SYMBOL_GPL(omap_dm_timer_enable); |
12583a70 TT |
321 | |
322 | void omap_dm_timer_disable(struct omap_dm_timer *timer) | |
323 | { | |
54f32a35 | 324 | pm_runtime_put_sync(&timer->pdev->dev); |
12583a70 | 325 | } |
6c366e32 | 326 | EXPORT_SYMBOL_GPL(omap_dm_timer_disable); |
12583a70 | 327 | |
77900a2f TT |
328 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) |
329 | { | |
ab4eb8b0 TKD |
330 | if (timer) |
331 | return timer->irq; | |
332 | return -EINVAL; | |
77900a2f | 333 | } |
6c366e32 | 334 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); |
77900a2f TT |
335 | |
336 | #if defined(CONFIG_ARCH_OMAP1) | |
7136f8d8 | 337 | #include <mach/hardware.h> |
a569c6ec TL |
338 | /** |
339 | * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR | |
340 | * @inputmask: current value of idlect mask | |
341 | */ | |
342 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |
343 | { | |
3392cdd3 TKD |
344 | int i = 0; |
345 | struct omap_dm_timer *timer = NULL; | |
346 | unsigned long flags; | |
a569c6ec TL |
347 | |
348 | /* If ARMXOR cannot be idled this function call is unnecessary */ | |
349 | if (!(inputmask & (1 << 1))) | |
350 | return inputmask; | |
351 | ||
352 | /* If any active timer is using ARMXOR return modified mask */ | |
3392cdd3 TKD |
353 | spin_lock_irqsave(&dm_timer_lock, flags); |
354 | list_for_each_entry(timer, &omap_timer_list, node) { | |
77900a2f TT |
355 | u32 l; |
356 | ||
3392cdd3 | 357 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
358 | if (l & OMAP_TIMER_CTRL_ST) { |
359 | if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) | |
a569c6ec TL |
360 | inputmask &= ~(1 << 1); |
361 | else | |
362 | inputmask &= ~(1 << 2); | |
363 | } | |
3392cdd3 | 364 | i++; |
77900a2f | 365 | } |
3392cdd3 | 366 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
a569c6ec TL |
367 | |
368 | return inputmask; | |
369 | } | |
6c366e32 | 370 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
a569c6ec | 371 | |
140455fa | 372 | #else |
a569c6ec | 373 | |
77900a2f | 374 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
92105bb7 | 375 | { |
ab4eb8b0 TKD |
376 | if (timer) |
377 | return timer->fclk; | |
378 | return NULL; | |
77900a2f | 379 | } |
6c366e32 | 380 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); |
92105bb7 | 381 | |
77900a2f TT |
382 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
383 | { | |
384 | BUG(); | |
2121880e DB |
385 | |
386 | return 0; | |
92105bb7 | 387 | } |
6c366e32 | 388 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
92105bb7 | 389 | |
77900a2f | 390 | #endif |
92105bb7 | 391 | |
ab4eb8b0 | 392 | int omap_dm_timer_trigger(struct omap_dm_timer *timer) |
92105bb7 | 393 | { |
ab4eb8b0 TKD |
394 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
395 | pr_err("%s: timer not available or enabled.\n", __func__); | |
396 | return -EINVAL; | |
b481113a TKD |
397 | } |
398 | ||
77900a2f | 399 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
ab4eb8b0 | 400 | return 0; |
92105bb7 | 401 | } |
6c366e32 | 402 | EXPORT_SYMBOL_GPL(omap_dm_timer_trigger); |
92105bb7 | 403 | |
ab4eb8b0 | 404 | int omap_dm_timer_start(struct omap_dm_timer *timer) |
77900a2f TT |
405 | { |
406 | u32 l; | |
92105bb7 | 407 | |
ab4eb8b0 TKD |
408 | if (unlikely(!timer)) |
409 | return -EINVAL; | |
410 | ||
b481113a TKD |
411 | omap_dm_timer_enable(timer); |
412 | ||
1c2d076b | 413 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
6e740f9a TL |
414 | if (timer->get_context_loss_count && |
415 | timer->get_context_loss_count(&timer->pdev->dev) != | |
0b30ec1c | 416 | timer->ctx_loss_count) |
b481113a TKD |
417 | omap_timer_restore_context(timer); |
418 | } | |
419 | ||
77900a2f TT |
420 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
421 | if (!(l & OMAP_TIMER_CTRL_ST)) { | |
422 | l |= OMAP_TIMER_CTRL_ST; | |
423 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
424 | } | |
b481113a TKD |
425 | |
426 | /* Save the context */ | |
427 | timer->context.tclr = l; | |
ab4eb8b0 | 428 | return 0; |
77900a2f | 429 | } |
6c366e32 | 430 | EXPORT_SYMBOL_GPL(omap_dm_timer_start); |
92105bb7 | 431 | |
ab4eb8b0 | 432 | int omap_dm_timer_stop(struct omap_dm_timer *timer) |
92105bb7 | 433 | { |
caf64f2f | 434 | unsigned long rate = 0; |
92105bb7 | 435 | |
ab4eb8b0 TKD |
436 | if (unlikely(!timer)) |
437 | return -EINVAL; | |
438 | ||
6615975b | 439 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) |
3392cdd3 | 440 | rate = clk_get_rate(timer->fclk); |
caf64f2f | 441 | |
ee17f114 | 442 | __omap_dm_timer_stop(timer, timer->posted, rate); |
ab4eb8b0 | 443 | |
6e740f9a TL |
444 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
445 | if (timer->get_context_loss_count) | |
446 | timer->ctx_loss_count = | |
447 | timer->get_context_loss_count(&timer->pdev->dev); | |
448 | } | |
dffc9dae TKD |
449 | |
450 | /* | |
451 | * Since the register values are computed and written within | |
452 | * __omap_dm_timer_stop, we need to use read to retrieve the | |
453 | * context. | |
454 | */ | |
455 | timer->context.tclr = | |
456 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
dffc9dae | 457 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 458 | return 0; |
92105bb7 | 459 | } |
6c366e32 | 460 | EXPORT_SYMBOL_GPL(omap_dm_timer_stop); |
92105bb7 | 461 | |
f248076c | 462 | int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
92105bb7 | 463 | { |
3392cdd3 | 464 | int ret; |
2b2d3523 | 465 | char *parent_name = NULL; |
d7aba554 | 466 | struct clk *parent; |
ab4eb8b0 TKD |
467 | struct dmtimer_platform_data *pdata; |
468 | ||
469 | if (unlikely(!timer)) | |
470 | return -EINVAL; | |
471 | ||
472 | pdata = timer->pdev->dev.platform_data; | |
3392cdd3 | 473 | |
77900a2f | 474 | if (source < 0 || source >= 3) |
f248076c | 475 | return -EINVAL; |
77900a2f | 476 | |
2b2d3523 JH |
477 | /* |
478 | * FIXME: Used for OMAP1 devices only because they do not currently | |
479 | * use the clock framework to set the parent clock. To be removed | |
480 | * once OMAP1 migrated to using clock framework for dmtimers | |
481 | */ | |
9725f445 | 482 | if (pdata && pdata->set_timer_src) |
2b2d3523 JH |
483 | return pdata->set_timer_src(timer->pdev, source); |
484 | ||
d7aba554 | 485 | if (!timer->fclk) |
2b2d3523 | 486 | return -EINVAL; |
2b2d3523 JH |
487 | |
488 | switch (source) { | |
489 | case OMAP_TIMER_SRC_SYS_CLK: | |
c59b537d | 490 | parent_name = "timer_sys_ck"; |
2b2d3523 JH |
491 | break; |
492 | ||
493 | case OMAP_TIMER_SRC_32_KHZ: | |
c59b537d | 494 | parent_name = "timer_32k_ck"; |
2b2d3523 JH |
495 | break; |
496 | ||
497 | case OMAP_TIMER_SRC_EXT_CLK: | |
c59b537d | 498 | parent_name = "timer_ext_ck"; |
2b2d3523 JH |
499 | break; |
500 | } | |
501 | ||
502 | parent = clk_get(&timer->pdev->dev, parent_name); | |
503 | if (IS_ERR_OR_NULL(parent)) { | |
504 | pr_err("%s: %s not found\n", __func__, parent_name); | |
d7aba554 | 505 | return -EINVAL; |
2b2d3523 JH |
506 | } |
507 | ||
d7aba554 | 508 | ret = clk_set_parent(timer->fclk, parent); |
2b2d3523 JH |
509 | if (IS_ERR_VALUE(ret)) |
510 | pr_err("%s: failed to set %s as parent\n", __func__, | |
511 | parent_name); | |
512 | ||
513 | clk_put(parent); | |
3392cdd3 TKD |
514 | |
515 | return ret; | |
92105bb7 | 516 | } |
6c366e32 | 517 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); |
92105bb7 | 518 | |
ab4eb8b0 | 519 | int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, |
77900a2f | 520 | unsigned int load) |
92105bb7 TL |
521 | { |
522 | u32 l; | |
77900a2f | 523 | |
ab4eb8b0 TKD |
524 | if (unlikely(!timer)) |
525 | return -EINVAL; | |
526 | ||
b481113a | 527 | omap_dm_timer_enable(timer); |
92105bb7 | 528 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
529 | if (autoreload) |
530 | l |= OMAP_TIMER_CTRL_AR; | |
531 | else | |
532 | l &= ~OMAP_TIMER_CTRL_AR; | |
92105bb7 | 533 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 534 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
0f0d0807 | 535 | |
77900a2f | 536 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
b481113a TKD |
537 | /* Save the context */ |
538 | timer->context.tclr = l; | |
539 | timer->context.tldr = load; | |
540 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 541 | return 0; |
92105bb7 | 542 | } |
6c366e32 | 543 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load); |
92105bb7 | 544 | |
3fddd09e | 545 | /* Optimized set_load which removes costly spin wait in timer_start */ |
ab4eb8b0 | 546 | int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, |
3fddd09e RW |
547 | unsigned int load) |
548 | { | |
549 | u32 l; | |
550 | ||
ab4eb8b0 TKD |
551 | if (unlikely(!timer)) |
552 | return -EINVAL; | |
553 | ||
b481113a TKD |
554 | omap_dm_timer_enable(timer); |
555 | ||
1c2d076b | 556 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
6e740f9a TL |
557 | if (timer->get_context_loss_count && |
558 | timer->get_context_loss_count(&timer->pdev->dev) != | |
0b30ec1c | 559 | timer->ctx_loss_count) |
b481113a TKD |
560 | omap_timer_restore_context(timer); |
561 | } | |
562 | ||
3fddd09e | 563 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
64ce2907 | 564 | if (autoreload) { |
3fddd09e | 565 | l |= OMAP_TIMER_CTRL_AR; |
64ce2907 PW |
566 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
567 | } else { | |
3fddd09e | 568 | l &= ~OMAP_TIMER_CTRL_AR; |
64ce2907 | 569 | } |
3fddd09e RW |
570 | l |= OMAP_TIMER_CTRL_ST; |
571 | ||
ee17f114 | 572 | __omap_dm_timer_load_start(timer, l, load, timer->posted); |
b481113a TKD |
573 | |
574 | /* Save the context */ | |
575 | timer->context.tclr = l; | |
576 | timer->context.tldr = load; | |
577 | timer->context.tcrr = load; | |
ab4eb8b0 | 578 | return 0; |
3fddd09e | 579 | } |
6c366e32 | 580 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); |
3fddd09e | 581 | |
ab4eb8b0 | 582 | int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
77900a2f | 583 | unsigned int match) |
92105bb7 TL |
584 | { |
585 | u32 l; | |
586 | ||
ab4eb8b0 TKD |
587 | if (unlikely(!timer)) |
588 | return -EINVAL; | |
589 | ||
b481113a | 590 | omap_dm_timer_enable(timer); |
92105bb7 | 591 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
83379c81 | 592 | if (enable) |
77900a2f TT |
593 | l |= OMAP_TIMER_CTRL_CE; |
594 | else | |
595 | l &= ~OMAP_TIMER_CTRL_CE; | |
77900a2f | 596 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
991ad16a | 597 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
598 | |
599 | /* Save the context */ | |
600 | timer->context.tclr = l; | |
601 | timer->context.tmar = match; | |
602 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 603 | return 0; |
92105bb7 | 604 | } |
6c366e32 | 605 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_match); |
92105bb7 | 606 | |
ab4eb8b0 | 607 | int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
77900a2f | 608 | int toggle, int trigger) |
92105bb7 TL |
609 | { |
610 | u32 l; | |
611 | ||
ab4eb8b0 TKD |
612 | if (unlikely(!timer)) |
613 | return -EINVAL; | |
614 | ||
b481113a | 615 | omap_dm_timer_enable(timer); |
92105bb7 | 616 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
617 | l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
618 | OMAP_TIMER_CTRL_PT | (0x03 << 10)); | |
619 | if (def_on) | |
620 | l |= OMAP_TIMER_CTRL_SCPWM; | |
621 | if (toggle) | |
622 | l |= OMAP_TIMER_CTRL_PT; | |
623 | l |= trigger << 10; | |
92105bb7 | 624 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
625 | |
626 | /* Save the context */ | |
627 | timer->context.tclr = l; | |
628 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 629 | return 0; |
92105bb7 | 630 | } |
6c366e32 | 631 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm); |
92105bb7 | 632 | |
ab4eb8b0 | 633 | int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) |
92105bb7 TL |
634 | { |
635 | u32 l; | |
636 | ||
ab4eb8b0 TKD |
637 | if (unlikely(!timer)) |
638 | return -EINVAL; | |
639 | ||
b481113a | 640 | omap_dm_timer_enable(timer); |
92105bb7 | 641 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
642 | l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
643 | if (prescaler >= 0x00 && prescaler <= 0x07) { | |
644 | l |= OMAP_TIMER_CTRL_PRE; | |
645 | l |= prescaler << 2; | |
646 | } | |
92105bb7 | 647 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
648 | |
649 | /* Save the context */ | |
650 | timer->context.tclr = l; | |
651 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 652 | return 0; |
92105bb7 | 653 | } |
6c366e32 | 654 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler); |
92105bb7 | 655 | |
ab4eb8b0 | 656 | int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
77900a2f | 657 | unsigned int value) |
92105bb7 | 658 | { |
ab4eb8b0 TKD |
659 | if (unlikely(!timer)) |
660 | return -EINVAL; | |
661 | ||
b481113a | 662 | omap_dm_timer_enable(timer); |
ee17f114 | 663 | __omap_dm_timer_int_enable(timer, value); |
b481113a TKD |
664 | |
665 | /* Save the context */ | |
666 | timer->context.tier = value; | |
667 | timer->context.twer = value; | |
668 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 669 | return 0; |
92105bb7 | 670 | } |
6c366e32 | 671 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); |
92105bb7 | 672 | |
4249d96c JH |
673 | /** |
674 | * omap_dm_timer_set_int_disable - disable timer interrupts | |
675 | * @timer: pointer to timer handle | |
676 | * @mask: bit mask of interrupts to be disabled | |
677 | * | |
678 | * Disables the specified timer interrupts for a timer. | |
679 | */ | |
680 | int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) | |
681 | { | |
682 | u32 l = mask; | |
683 | ||
684 | if (unlikely(!timer)) | |
685 | return -EINVAL; | |
686 | ||
687 | omap_dm_timer_enable(timer); | |
688 | ||
689 | if (timer->revision == 1) | |
690 | l = __raw_readl(timer->irq_ena) & ~mask; | |
691 | ||
692 | __raw_writel(l, timer->irq_dis); | |
693 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; | |
694 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); | |
695 | ||
696 | /* Save the context */ | |
697 | timer->context.tier &= ~mask; | |
698 | timer->context.twer &= ~mask; | |
699 | omap_dm_timer_disable(timer); | |
700 | return 0; | |
701 | } | |
702 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable); | |
703 | ||
77900a2f | 704 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
92105bb7 | 705 | { |
fa4bb626 TT |
706 | unsigned int l; |
707 | ||
ab4eb8b0 TKD |
708 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
709 | pr_err("%s: timer not available or enabled.\n", __func__); | |
b481113a TKD |
710 | return 0; |
711 | } | |
712 | ||
ee17f114 | 713 | l = __raw_readl(timer->irq_stat); |
fa4bb626 TT |
714 | |
715 | return l; | |
92105bb7 | 716 | } |
6c366e32 | 717 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_status); |
92105bb7 | 718 | |
ab4eb8b0 | 719 | int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
92105bb7 | 720 | { |
ab4eb8b0 TKD |
721 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) |
722 | return -EINVAL; | |
723 | ||
ee17f114 | 724 | __omap_dm_timer_write_status(timer, value); |
1eaff710 | 725 | |
ab4eb8b0 | 726 | return 0; |
92105bb7 | 727 | } |
6c366e32 | 728 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); |
92105bb7 | 729 | |
77900a2f | 730 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
92105bb7 | 731 | { |
ab4eb8b0 TKD |
732 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
733 | pr_err("%s: timer not iavailable or enabled.\n", __func__); | |
b481113a TKD |
734 | return 0; |
735 | } | |
736 | ||
ee17f114 | 737 | return __omap_dm_timer_read_counter(timer, timer->posted); |
92105bb7 | 738 | } |
6c366e32 | 739 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); |
92105bb7 | 740 | |
ab4eb8b0 | 741 | int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
83379c81 | 742 | { |
ab4eb8b0 TKD |
743 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
744 | pr_err("%s: timer not available or enabled.\n", __func__); | |
745 | return -EINVAL; | |
b481113a TKD |
746 | } |
747 | ||
fa4bb626 | 748 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
b481113a TKD |
749 | |
750 | /* Save the context */ | |
751 | timer->context.tcrr = value; | |
ab4eb8b0 | 752 | return 0; |
83379c81 | 753 | } |
6c366e32 | 754 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter); |
83379c81 | 755 | |
77900a2f | 756 | int omap_dm_timers_active(void) |
92105bb7 | 757 | { |
3392cdd3 | 758 | struct omap_dm_timer *timer; |
12583a70 | 759 | |
3392cdd3 | 760 | list_for_each_entry(timer, &omap_timer_list, node) { |
ffe07cea | 761 | if (!timer->reserved) |
12583a70 TT |
762 | continue; |
763 | ||
77900a2f | 764 | if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
fa4bb626 | 765 | OMAP_TIMER_CTRL_ST) { |
77900a2f | 766 | return 1; |
fa4bb626 | 767 | } |
77900a2f TT |
768 | } |
769 | return 0; | |
770 | } | |
6c366e32 | 771 | EXPORT_SYMBOL_GPL(omap_dm_timers_active); |
92105bb7 | 772 | |
df28472a TKD |
773 | /** |
774 | * omap_dm_timer_probe - probe function called for every registered device | |
775 | * @pdev: pointer to current timer platform device | |
776 | * | |
777 | * Called by driver framework at the end of device registration for all | |
778 | * timer devices. | |
779 | */ | |
351a102d | 780 | static int omap_dm_timer_probe(struct platform_device *pdev) |
df28472a | 781 | { |
df28472a TKD |
782 | unsigned long flags; |
783 | struct omap_dm_timer *timer; | |
74dd9ec6 TKD |
784 | struct resource *mem, *irq; |
785 | struct device *dev = &pdev->dev; | |
df28472a TKD |
786 | struct dmtimer_platform_data *pdata = pdev->dev.platform_data; |
787 | ||
9725f445 | 788 | if (!pdata && !dev->of_node) { |
74dd9ec6 | 789 | dev_err(dev, "%s: no platform data.\n", __func__); |
df28472a TKD |
790 | return -ENODEV; |
791 | } | |
792 | ||
793 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
794 | if (unlikely(!irq)) { | |
74dd9ec6 | 795 | dev_err(dev, "%s: no IRQ resource.\n", __func__); |
df28472a TKD |
796 | return -ENODEV; |
797 | } | |
798 | ||
799 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
800 | if (unlikely(!mem)) { | |
74dd9ec6 | 801 | dev_err(dev, "%s: no memory resource.\n", __func__); |
df28472a TKD |
802 | return -ENODEV; |
803 | } | |
804 | ||
74dd9ec6 | 805 | timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL); |
df28472a | 806 | if (!timer) { |
74dd9ec6 TKD |
807 | dev_err(dev, "%s: memory alloc failed!\n", __func__); |
808 | return -ENOMEM; | |
df28472a TKD |
809 | } |
810 | ||
74dd9ec6 | 811 | timer->io_base = devm_request_and_ioremap(dev, mem); |
df28472a | 812 | if (!timer->io_base) { |
74dd9ec6 TKD |
813 | dev_err(dev, "%s: region already claimed.\n", __func__); |
814 | return -ENOMEM; | |
df28472a TKD |
815 | } |
816 | ||
9725f445 JH |
817 | if (dev->of_node) { |
818 | if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) | |
819 | timer->capability |= OMAP_TIMER_ALWON; | |
820 | if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) | |
821 | timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; | |
822 | if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) | |
823 | timer->capability |= OMAP_TIMER_HAS_PWM; | |
824 | if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) | |
825 | timer->capability |= OMAP_TIMER_SECURE; | |
826 | } else { | |
827 | timer->id = pdev->id; | |
bfd6d021 | 828 | timer->errata = pdata->timer_errata; |
9725f445 JH |
829 | timer->capability = pdata->timer_capability; |
830 | timer->reserved = omap_dm_timer_reserved_systimer(timer->id); | |
f56f52e0 | 831 | timer->get_context_loss_count = pdata->get_context_loss_count; |
9725f445 JH |
832 | } |
833 | ||
df28472a TKD |
834 | timer->irq = irq->start; |
835 | timer->pdev = pdev; | |
df28472a | 836 | |
ffe07cea | 837 | /* Skip pm_runtime_enable for OMAP1 */ |
6615975b | 838 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { |
74dd9ec6 TKD |
839 | pm_runtime_enable(dev); |
840 | pm_runtime_irq_safe(dev); | |
ffe07cea TKD |
841 | } |
842 | ||
0dad9fae | 843 | if (!timer->reserved) { |
74dd9ec6 | 844 | pm_runtime_get_sync(dev); |
0dad9fae | 845 | __omap_dm_timer_init_regs(timer); |
74dd9ec6 | 846 | pm_runtime_put(dev); |
0dad9fae TL |
847 | } |
848 | ||
df28472a TKD |
849 | /* add the timer element to the list */ |
850 | spin_lock_irqsave(&dm_timer_lock, flags); | |
851 | list_add_tail(&timer->node, &omap_timer_list); | |
852 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
853 | ||
74dd9ec6 | 854 | dev_dbg(dev, "Device Probed.\n"); |
df28472a TKD |
855 | |
856 | return 0; | |
df28472a TKD |
857 | } |
858 | ||
859 | /** | |
860 | * omap_dm_timer_remove - cleanup a registered timer device | |
861 | * @pdev: pointer to current timer platform device | |
862 | * | |
863 | * Called by driver framework whenever a timer device is unregistered. | |
864 | * In addition to freeing platform resources it also deletes the timer | |
865 | * entry from the local list. | |
866 | */ | |
351a102d | 867 | static int omap_dm_timer_remove(struct platform_device *pdev) |
df28472a TKD |
868 | { |
869 | struct omap_dm_timer *timer; | |
870 | unsigned long flags; | |
871 | int ret = -EINVAL; | |
872 | ||
873 | spin_lock_irqsave(&dm_timer_lock, flags); | |
874 | list_for_each_entry(timer, &omap_timer_list, node) | |
9725f445 JH |
875 | if (!strcmp(dev_name(&timer->pdev->dev), |
876 | dev_name(&pdev->dev))) { | |
df28472a | 877 | list_del(&timer->node); |
df28472a TKD |
878 | ret = 0; |
879 | break; | |
880 | } | |
881 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
882 | ||
883 | return ret; | |
884 | } | |
885 | ||
9725f445 JH |
886 | static const struct of_device_id omap_timer_match[] = { |
887 | { .compatible = "ti,omap2-timer", }, | |
888 | {}, | |
889 | }; | |
890 | MODULE_DEVICE_TABLE(of, omap_timer_match); | |
891 | ||
df28472a TKD |
892 | static struct platform_driver omap_dm_timer_driver = { |
893 | .probe = omap_dm_timer_probe, | |
351a102d | 894 | .remove = omap_dm_timer_remove, |
df28472a TKD |
895 | .driver = { |
896 | .name = "omap_timer", | |
9725f445 | 897 | .of_match_table = of_match_ptr(omap_timer_match), |
df28472a TKD |
898 | }, |
899 | }; | |
900 | ||
df28472a | 901 | early_platform_init("earlytimer", &omap_dm_timer_driver); |
e4e9f7ea | 902 | module_platform_driver(omap_dm_timer_driver); |
df28472a TKD |
903 | |
904 | MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); | |
905 | MODULE_LICENSE("GPL"); | |
906 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
907 | MODULE_AUTHOR("Texas Instruments Inc"); |