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Commit | Line | Data |
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92105bb7 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dmtimer.c | |
3 | * | |
4 | * OMAP Dual-Mode Timers | |
5 | * | |
97933d6c TKD |
6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
7 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> | |
8 | * Thara Gopinath <thara@ti.com> | |
9 | * | |
10 | * dmtimer adaptation to platform_driver. | |
11 | * | |
92105bb7 | 12 | * Copyright (C) 2005 Nokia Corporation |
77900a2f TT |
13 | * OMAP2 support by Juha Yrjola |
14 | * API improvements and OMAP2 clock framework support by Timo Teras | |
92105bb7 | 15 | * |
44169075 SS |
16 | * Copyright (C) 2009 Texas Instruments |
17 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
18 | * | |
92105bb7 TL |
19 | * This program is free software; you can redistribute it and/or modify it |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
27 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
28 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License along | |
34 | * with this program; if not, write to the Free Software Foundation, Inc., | |
35 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
36 | */ | |
37 | ||
b1538832 | 38 | #include <linux/clk.h> |
ea05d2ea | 39 | #include <linux/clk-provider.h> |
869dec15 | 40 | #include <linux/module.h> |
fced80c7 | 41 | #include <linux/io.h> |
74dd9ec6 | 42 | #include <linux/device.h> |
3392cdd3 | 43 | #include <linux/err.h> |
ffe07cea | 44 | #include <linux/pm_runtime.h> |
9725f445 JH |
45 | #include <linux/of.h> |
46 | #include <linux/of_device.h> | |
40fc3bb5 JH |
47 | #include <linux/platform_device.h> |
48 | #include <linux/platform_data/dmtimer-omap.h> | |
44169075 | 49 | |
3392cdd3 | 50 | #include <plat/dmtimer.h> |
2c799cef | 51 | |
b7b4ff76 | 52 | static u32 omap_reserved_systimers; |
df28472a | 53 | static LIST_HEAD(omap_timer_list); |
3392cdd3 | 54 | static DEFINE_SPINLOCK(dm_timer_lock); |
92105bb7 | 55 | |
8fc7fcb5 JH |
56 | enum { |
57 | REQUEST_ANY = 0, | |
58 | REQUEST_BY_ID, | |
59 | REQUEST_BY_CAP, | |
60 | REQUEST_BY_NODE, | |
61 | }; | |
62 | ||
3392cdd3 TKD |
63 | /** |
64 | * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode | |
65 | * @timer: timer pointer over which read operation to perform | |
66 | * @reg: lowest byte holds the register offset | |
67 | * | |
68 | * The posted mode bit is encoded in reg. Note that in posted mode write | |
69 | * pending bit must be checked. Otherwise a read of a non completed write | |
70 | * will produce an error. | |
0f0d0807 RW |
71 | */ |
72 | static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) | |
77900a2f | 73 | { |
ee17f114 TL |
74 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
75 | return __omap_dm_timer_read(timer, reg, timer->posted); | |
77900a2f | 76 | } |
92105bb7 | 77 | |
3392cdd3 TKD |
78 | /** |
79 | * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode | |
80 | * @timer: timer pointer over which write operation is to perform | |
81 | * @reg: lowest byte holds the register offset | |
82 | * @value: data to write into the register | |
83 | * | |
84 | * The posted mode bit is encoded in reg. Note that in posted mode the write | |
85 | * pending bit must be checked. Otherwise a write on a register which has a | |
86 | * pending write will be lost. | |
0f0d0807 RW |
87 | */ |
88 | static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, | |
89 | u32 value) | |
92105bb7 | 90 | { |
ee17f114 TL |
91 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
92 | __omap_dm_timer_write(timer, reg, value, timer->posted); | |
92105bb7 TL |
93 | } |
94 | ||
b481113a TKD |
95 | static void omap_timer_restore_context(struct omap_dm_timer *timer) |
96 | { | |
b481113a TKD |
97 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, |
98 | timer->context.twer); | |
99 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, | |
100 | timer->context.tcrr); | |
101 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, | |
102 | timer->context.tldr); | |
103 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, | |
104 | timer->context.tmar); | |
105 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, | |
106 | timer->context.tsicr); | |
834cacfb | 107 | writel_relaxed(timer->context.tier, timer->irq_ena); |
b481113a TKD |
108 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, |
109 | timer->context.tclr); | |
110 | } | |
111 | ||
ae6672cb | 112 | static int omap_dm_timer_reset(struct omap_dm_timer *timer) |
92105bb7 | 113 | { |
ae6672cb | 114 | u32 l, timeout = 100000; |
77900a2f | 115 | |
ae6672cb JH |
116 | if (timer->revision != 1) |
117 | return -EINVAL; | |
ee17f114 | 118 | |
ae6672cb JH |
119 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
120 | ||
121 | do { | |
122 | l = __omap_dm_timer_read(timer, | |
123 | OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); | |
124 | } while (!l && timeout--); | |
125 | ||
126 | if (!timeout) { | |
127 | dev_err(&timer->pdev->dev, "Timer failed to reset\n"); | |
128 | return -ETIMEDOUT; | |
77900a2f | 129 | } |
92105bb7 | 130 | |
ae6672cb JH |
131 | /* Configure timer for smart-idle mode */ |
132 | l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); | |
133 | l |= 0x2 << 0x3; | |
134 | __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); | |
135 | ||
136 | timer->posted = 0; | |
137 | ||
138 | return 0; | |
77900a2f TT |
139 | } |
140 | ||
31a7448f NA |
141 | static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer) |
142 | { | |
143 | int ret; | |
144 | struct clk *parent; | |
145 | ||
146 | /* | |
147 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | |
148 | * do not call clk_get() for these devices. | |
149 | */ | |
150 | if (!timer->fclk) | |
151 | return -ENODEV; | |
152 | ||
153 | parent = clk_get(&timer->pdev->dev, NULL); | |
154 | if (IS_ERR(parent)) | |
155 | return -ENODEV; | |
156 | ||
157 | ret = clk_set_parent(timer->fclk, parent); | |
158 | if (ret < 0) | |
159 | pr_err("%s: failed to set parent\n", __func__); | |
160 | ||
161 | clk_put(parent); | |
162 | ||
163 | return ret; | |
164 | } | |
165 | ||
b0cadb3c | 166 | static int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
77900a2f | 167 | { |
ae6672cb JH |
168 | int rc; |
169 | ||
bca45808 JH |
170 | /* |
171 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | |
172 | * do not call clk_get() for these devices. | |
173 | */ | |
174 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { | |
175 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); | |
86287958 | 176 | if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { |
bca45808 JH |
177 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); |
178 | return -EINVAL; | |
179 | } | |
3392cdd3 TKD |
180 | } |
181 | ||
7b44cf2c JH |
182 | omap_dm_timer_enable(timer); |
183 | ||
ae6672cb JH |
184 | if (timer->capability & OMAP_TIMER_NEEDS_RESET) { |
185 | rc = omap_dm_timer_reset(timer); | |
186 | if (rc) { | |
187 | omap_dm_timer_disable(timer); | |
188 | return rc; | |
189 | } | |
190 | } | |
3392cdd3 | 191 | |
7b44cf2c JH |
192 | __omap_dm_timer_enable_posted(timer); |
193 | omap_dm_timer_disable(timer); | |
3392cdd3 | 194 | |
31a7448f NA |
195 | rc = omap_dm_timer_of_set_source(timer); |
196 | if (rc == -ENODEV) | |
197 | return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); | |
198 | ||
199 | return rc; | |
77900a2f TT |
200 | } |
201 | ||
b7b4ff76 JH |
202 | static inline u32 omap_dm_timer_reserved_systimer(int id) |
203 | { | |
204 | return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; | |
205 | } | |
206 | ||
207 | int omap_dm_timer_reserve_systimer(int id) | |
208 | { | |
209 | if (omap_dm_timer_reserved_systimer(id)) | |
210 | return -ENODEV; | |
211 | ||
212 | omap_reserved_systimers |= (1 << (id - 1)); | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
8fc7fcb5 | 217 | static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data) |
77900a2f | 218 | { |
3392cdd3 | 219 | struct omap_dm_timer *timer = NULL, *t; |
8fc7fcb5 | 220 | struct device_node *np = NULL; |
77900a2f | 221 | unsigned long flags; |
8fc7fcb5 JH |
222 | u32 cap = 0; |
223 | int id = 0; | |
224 | ||
225 | switch (req_type) { | |
226 | case REQUEST_BY_ID: | |
227 | id = *(int *)data; | |
228 | break; | |
229 | case REQUEST_BY_CAP: | |
230 | cap = *(u32 *)data; | |
231 | break; | |
232 | case REQUEST_BY_NODE: | |
233 | np = (struct device_node *)data; | |
234 | break; | |
235 | default: | |
236 | /* REQUEST_ANY */ | |
237 | break; | |
238 | } | |
77900a2f TT |
239 | |
240 | spin_lock_irqsave(&dm_timer_lock, flags); | |
3392cdd3 TKD |
241 | list_for_each_entry(t, &omap_timer_list, node) { |
242 | if (t->reserved) | |
77900a2f TT |
243 | continue; |
244 | ||
8fc7fcb5 JH |
245 | switch (req_type) { |
246 | case REQUEST_BY_ID: | |
247 | if (id == t->pdev->id) { | |
248 | timer = t; | |
249 | timer->reserved = 1; | |
250 | goto found; | |
251 | } | |
252 | break; | |
253 | case REQUEST_BY_CAP: | |
254 | if (cap == (t->capability & cap)) { | |
255 | /* | |
256 | * If timer is not NULL, we have already found | |
28fd7e99 ME |
257 | * one timer. But it was not an exact match |
258 | * because it had more capabilities than what | |
8fc7fcb5 JH |
259 | * was required. Therefore, unreserve the last |
260 | * timer found and see if this one is a better | |
261 | * match. | |
262 | */ | |
263 | if (timer) | |
264 | timer->reserved = 0; | |
265 | timer = t; | |
266 | timer->reserved = 1; | |
267 | ||
268 | /* Exit loop early if we find an exact match */ | |
269 | if (t->capability == cap) | |
270 | goto found; | |
271 | } | |
272 | break; | |
273 | case REQUEST_BY_NODE: | |
274 | if (np == t->pdev->dev.of_node) { | |
275 | timer = t; | |
276 | timer->reserved = 1; | |
277 | goto found; | |
278 | } | |
279 | break; | |
280 | default: | |
281 | /* REQUEST_ANY */ | |
282 | timer = t; | |
283 | timer->reserved = 1; | |
284 | goto found; | |
285 | } | |
77900a2f | 286 | } |
8fc7fcb5 | 287 | found: |
c5491d1a | 288 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
3392cdd3 | 289 | |
8fc7fcb5 JH |
290 | if (timer && omap_dm_timer_prepare(timer)) { |
291 | timer->reserved = 0; | |
292 | timer = NULL; | |
3392cdd3 | 293 | } |
77900a2f | 294 | |
3392cdd3 TKD |
295 | if (!timer) |
296 | pr_debug("%s: timer request failed!\n", __func__); | |
83379c81 | 297 | |
77900a2f TT |
298 | return timer; |
299 | } | |
8fc7fcb5 JH |
300 | |
301 | struct omap_dm_timer *omap_dm_timer_request(void) | |
302 | { | |
303 | return _omap_dm_timer_request(REQUEST_ANY, NULL); | |
304 | } | |
77900a2f TT |
305 | |
306 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |
92105bb7 | 307 | { |
9725f445 JH |
308 | /* Requesting timer by ID is not supported when device tree is used */ |
309 | if (of_have_populated_dt()) { | |
8fc7fcb5 | 310 | pr_warn("%s: Please use omap_dm_timer_request_by_cap/node()\n", |
9725f445 JH |
311 | __func__); |
312 | return NULL; | |
313 | } | |
314 | ||
8fc7fcb5 | 315 | return _omap_dm_timer_request(REQUEST_BY_ID, &id); |
92105bb7 TL |
316 | } |
317 | ||
373fe0bd JH |
318 | /** |
319 | * omap_dm_timer_request_by_cap - Request a timer by capability | |
320 | * @cap: Bit mask of capabilities to match | |
321 | * | |
322 | * Find a timer based upon capabilities bit mask. Callers of this function | |
323 | * should use the definitions found in the plat/dmtimer.h file under the | |
324 | * comment "timer capabilities used in hwmod database". Returns pointer to | |
325 | * timer handle on success and a NULL pointer on failure. | |
326 | */ | |
327 | struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) | |
328 | { | |
8fc7fcb5 JH |
329 | return _omap_dm_timer_request(REQUEST_BY_CAP, &cap); |
330 | } | |
373fe0bd | 331 | |
8fc7fcb5 JH |
332 | /** |
333 | * omap_dm_timer_request_by_node - Request a timer by device-tree node | |
334 | * @np: Pointer to device-tree timer node | |
335 | * | |
336 | * Request a timer based upon a device node pointer. Returns pointer to | |
337 | * timer handle on success and a NULL pointer on failure. | |
338 | */ | |
339 | struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np) | |
340 | { | |
341 | if (!np) | |
373fe0bd JH |
342 | return NULL; |
343 | ||
8fc7fcb5 | 344 | return _omap_dm_timer_request(REQUEST_BY_NODE, np); |
373fe0bd | 345 | } |
373fe0bd | 346 | |
ab4eb8b0 | 347 | int omap_dm_timer_free(struct omap_dm_timer *timer) |
77900a2f | 348 | { |
ab4eb8b0 TKD |
349 | if (unlikely(!timer)) |
350 | return -EINVAL; | |
351 | ||
3392cdd3 | 352 | clk_put(timer->fclk); |
fa4bb626 | 353 | |
77900a2f TT |
354 | WARN_ON(!timer->reserved); |
355 | timer->reserved = 0; | |
ab4eb8b0 | 356 | return 0; |
77900a2f TT |
357 | } |
358 | ||
12583a70 TT |
359 | void omap_dm_timer_enable(struct omap_dm_timer *timer) |
360 | { | |
9cc268d5 N |
361 | int c; |
362 | ||
ffe07cea | 363 | pm_runtime_get_sync(&timer->pdev->dev); |
9cc268d5 N |
364 | |
365 | if (!(timer->capability & OMAP_TIMER_ALWON)) { | |
366 | if (timer->get_context_loss_count) { | |
367 | c = timer->get_context_loss_count(&timer->pdev->dev); | |
368 | if (c != timer->ctx_loss_count) { | |
369 | omap_timer_restore_context(timer); | |
370 | timer->ctx_loss_count = c; | |
371 | } | |
385c4c7b JH |
372 | } else { |
373 | omap_timer_restore_context(timer); | |
9cc268d5 N |
374 | } |
375 | } | |
12583a70 TT |
376 | } |
377 | ||
378 | void omap_dm_timer_disable(struct omap_dm_timer *timer) | |
379 | { | |
54f32a35 | 380 | pm_runtime_put_sync(&timer->pdev->dev); |
12583a70 TT |
381 | } |
382 | ||
77900a2f TT |
383 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) |
384 | { | |
ab4eb8b0 TKD |
385 | if (timer) |
386 | return timer->irq; | |
387 | return -EINVAL; | |
77900a2f TT |
388 | } |
389 | ||
390 | #if defined(CONFIG_ARCH_OMAP1) | |
7136f8d8 | 391 | #include <mach/hardware.h> |
a569c6ec TL |
392 | /** |
393 | * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR | |
394 | * @inputmask: current value of idlect mask | |
395 | */ | |
396 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |
397 | { | |
3392cdd3 TKD |
398 | int i = 0; |
399 | struct omap_dm_timer *timer = NULL; | |
400 | unsigned long flags; | |
a569c6ec TL |
401 | |
402 | /* If ARMXOR cannot be idled this function call is unnecessary */ | |
403 | if (!(inputmask & (1 << 1))) | |
404 | return inputmask; | |
405 | ||
406 | /* If any active timer is using ARMXOR return modified mask */ | |
3392cdd3 TKD |
407 | spin_lock_irqsave(&dm_timer_lock, flags); |
408 | list_for_each_entry(timer, &omap_timer_list, node) { | |
77900a2f TT |
409 | u32 l; |
410 | ||
3392cdd3 | 411 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
412 | if (l & OMAP_TIMER_CTRL_ST) { |
413 | if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) | |
a569c6ec TL |
414 | inputmask &= ~(1 << 1); |
415 | else | |
416 | inputmask &= ~(1 << 2); | |
417 | } | |
3392cdd3 | 418 | i++; |
77900a2f | 419 | } |
3392cdd3 | 420 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
a569c6ec TL |
421 | |
422 | return inputmask; | |
423 | } | |
424 | ||
140455fa | 425 | #else |
a569c6ec | 426 | |
77900a2f | 427 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
92105bb7 | 428 | { |
86287958 | 429 | if (timer && !IS_ERR(timer->fclk)) |
ab4eb8b0 TKD |
430 | return timer->fclk; |
431 | return NULL; | |
77900a2f | 432 | } |
92105bb7 | 433 | |
77900a2f TT |
434 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
435 | { | |
436 | BUG(); | |
2121880e DB |
437 | |
438 | return 0; | |
92105bb7 TL |
439 | } |
440 | ||
77900a2f | 441 | #endif |
92105bb7 | 442 | |
ab4eb8b0 | 443 | int omap_dm_timer_trigger(struct omap_dm_timer *timer) |
92105bb7 | 444 | { |
ab4eb8b0 TKD |
445 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
446 | pr_err("%s: timer not available or enabled.\n", __func__); | |
447 | return -EINVAL; | |
b481113a TKD |
448 | } |
449 | ||
77900a2f | 450 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
ab4eb8b0 | 451 | return 0; |
92105bb7 TL |
452 | } |
453 | ||
ab4eb8b0 | 454 | int omap_dm_timer_start(struct omap_dm_timer *timer) |
77900a2f TT |
455 | { |
456 | u32 l; | |
92105bb7 | 457 | |
ab4eb8b0 TKD |
458 | if (unlikely(!timer)) |
459 | return -EINVAL; | |
460 | ||
b481113a TKD |
461 | omap_dm_timer_enable(timer); |
462 | ||
77900a2f TT |
463 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
464 | if (!(l & OMAP_TIMER_CTRL_ST)) { | |
465 | l |= OMAP_TIMER_CTRL_ST; | |
466 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
467 | } | |
b481113a TKD |
468 | |
469 | /* Save the context */ | |
470 | timer->context.tclr = l; | |
ab4eb8b0 | 471 | return 0; |
77900a2f | 472 | } |
92105bb7 | 473 | |
ab4eb8b0 | 474 | int omap_dm_timer_stop(struct omap_dm_timer *timer) |
92105bb7 | 475 | { |
caf64f2f | 476 | unsigned long rate = 0; |
92105bb7 | 477 | |
ab4eb8b0 TKD |
478 | if (unlikely(!timer)) |
479 | return -EINVAL; | |
480 | ||
6615975b | 481 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) |
3392cdd3 | 482 | rate = clk_get_rate(timer->fclk); |
caf64f2f | 483 | |
ee17f114 | 484 | __omap_dm_timer_stop(timer, timer->posted, rate); |
ab4eb8b0 | 485 | |
dffc9dae TKD |
486 | /* |
487 | * Since the register values are computed and written within | |
488 | * __omap_dm_timer_stop, we need to use read to retrieve the | |
489 | * context. | |
490 | */ | |
491 | timer->context.tclr = | |
492 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
dffc9dae | 493 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 494 | return 0; |
92105bb7 TL |
495 | } |
496 | ||
f248076c | 497 | int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
92105bb7 | 498 | { |
3392cdd3 | 499 | int ret; |
2b2d3523 | 500 | char *parent_name = NULL; |
d7aba554 | 501 | struct clk *parent; |
ab4eb8b0 TKD |
502 | struct dmtimer_platform_data *pdata; |
503 | ||
504 | if (unlikely(!timer)) | |
505 | return -EINVAL; | |
506 | ||
507 | pdata = timer->pdev->dev.platform_data; | |
3392cdd3 | 508 | |
77900a2f | 509 | if (source < 0 || source >= 3) |
f248076c | 510 | return -EINVAL; |
77900a2f | 511 | |
2b2d3523 JH |
512 | /* |
513 | * FIXME: Used for OMAP1 devices only because they do not currently | |
514 | * use the clock framework to set the parent clock. To be removed | |
515 | * once OMAP1 migrated to using clock framework for dmtimers | |
516 | */ | |
9725f445 | 517 | if (pdata && pdata->set_timer_src) |
2b2d3523 JH |
518 | return pdata->set_timer_src(timer->pdev, source); |
519 | ||
86287958 | 520 | if (IS_ERR(timer->fclk)) |
2b2d3523 | 521 | return -EINVAL; |
2b2d3523 | 522 | |
ea05d2ea SA |
523 | #if defined(CONFIG_COMMON_CLK) |
524 | /* Check if the clock has configurable parents */ | |
525 | if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) | |
526 | return 0; | |
527 | #endif | |
528 | ||
2b2d3523 JH |
529 | switch (source) { |
530 | case OMAP_TIMER_SRC_SYS_CLK: | |
c59b537d | 531 | parent_name = "timer_sys_ck"; |
2b2d3523 JH |
532 | break; |
533 | ||
534 | case OMAP_TIMER_SRC_32_KHZ: | |
c59b537d | 535 | parent_name = "timer_32k_ck"; |
2b2d3523 JH |
536 | break; |
537 | ||
538 | case OMAP_TIMER_SRC_EXT_CLK: | |
c59b537d | 539 | parent_name = "timer_ext_ck"; |
2b2d3523 JH |
540 | break; |
541 | } | |
542 | ||
543 | parent = clk_get(&timer->pdev->dev, parent_name); | |
86287958 | 544 | if (IS_ERR(parent)) { |
2b2d3523 | 545 | pr_err("%s: %s not found\n", __func__, parent_name); |
d7aba554 | 546 | return -EINVAL; |
2b2d3523 JH |
547 | } |
548 | ||
d7aba554 | 549 | ret = clk_set_parent(timer->fclk, parent); |
c48cd659 | 550 | if (ret < 0) |
2b2d3523 JH |
551 | pr_err("%s: failed to set %s as parent\n", __func__, |
552 | parent_name); | |
553 | ||
554 | clk_put(parent); | |
3392cdd3 TKD |
555 | |
556 | return ret; | |
92105bb7 TL |
557 | } |
558 | ||
ab4eb8b0 | 559 | int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, |
77900a2f | 560 | unsigned int load) |
92105bb7 TL |
561 | { |
562 | u32 l; | |
77900a2f | 563 | |
ab4eb8b0 TKD |
564 | if (unlikely(!timer)) |
565 | return -EINVAL; | |
566 | ||
b481113a | 567 | omap_dm_timer_enable(timer); |
92105bb7 | 568 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
569 | if (autoreload) |
570 | l |= OMAP_TIMER_CTRL_AR; | |
571 | else | |
572 | l &= ~OMAP_TIMER_CTRL_AR; | |
92105bb7 | 573 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 574 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
0f0d0807 | 575 | |
77900a2f | 576 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
b481113a TKD |
577 | /* Save the context */ |
578 | timer->context.tclr = l; | |
579 | timer->context.tldr = load; | |
580 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 581 | return 0; |
92105bb7 TL |
582 | } |
583 | ||
3fddd09e | 584 | /* Optimized set_load which removes costly spin wait in timer_start */ |
ab4eb8b0 | 585 | int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, |
3fddd09e RW |
586 | unsigned int load) |
587 | { | |
588 | u32 l; | |
589 | ||
ab4eb8b0 TKD |
590 | if (unlikely(!timer)) |
591 | return -EINVAL; | |
592 | ||
b481113a TKD |
593 | omap_dm_timer_enable(timer); |
594 | ||
3fddd09e | 595 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
64ce2907 | 596 | if (autoreload) { |
3fddd09e | 597 | l |= OMAP_TIMER_CTRL_AR; |
64ce2907 PW |
598 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
599 | } else { | |
3fddd09e | 600 | l &= ~OMAP_TIMER_CTRL_AR; |
64ce2907 | 601 | } |
3fddd09e RW |
602 | l |= OMAP_TIMER_CTRL_ST; |
603 | ||
ee17f114 | 604 | __omap_dm_timer_load_start(timer, l, load, timer->posted); |
b481113a TKD |
605 | |
606 | /* Save the context */ | |
607 | timer->context.tclr = l; | |
608 | timer->context.tldr = load; | |
609 | timer->context.tcrr = load; | |
ab4eb8b0 | 610 | return 0; |
3fddd09e RW |
611 | } |
612 | ||
ab4eb8b0 | 613 | int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
77900a2f | 614 | unsigned int match) |
92105bb7 TL |
615 | { |
616 | u32 l; | |
617 | ||
ab4eb8b0 TKD |
618 | if (unlikely(!timer)) |
619 | return -EINVAL; | |
620 | ||
b481113a | 621 | omap_dm_timer_enable(timer); |
92105bb7 | 622 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
83379c81 | 623 | if (enable) |
77900a2f TT |
624 | l |= OMAP_TIMER_CTRL_CE; |
625 | else | |
626 | l &= ~OMAP_TIMER_CTRL_CE; | |
77900a2f | 627 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
991ad16a | 628 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
629 | |
630 | /* Save the context */ | |
631 | timer->context.tclr = l; | |
632 | timer->context.tmar = match; | |
633 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 634 | return 0; |
92105bb7 TL |
635 | } |
636 | ||
ab4eb8b0 | 637 | int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
77900a2f | 638 | int toggle, int trigger) |
92105bb7 TL |
639 | { |
640 | u32 l; | |
641 | ||
ab4eb8b0 TKD |
642 | if (unlikely(!timer)) |
643 | return -EINVAL; | |
644 | ||
b481113a | 645 | omap_dm_timer_enable(timer); |
92105bb7 | 646 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
647 | l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
648 | OMAP_TIMER_CTRL_PT | (0x03 << 10)); | |
649 | if (def_on) | |
650 | l |= OMAP_TIMER_CTRL_SCPWM; | |
651 | if (toggle) | |
652 | l |= OMAP_TIMER_CTRL_PT; | |
653 | l |= trigger << 10; | |
92105bb7 | 654 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
655 | |
656 | /* Save the context */ | |
657 | timer->context.tclr = l; | |
658 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 659 | return 0; |
92105bb7 TL |
660 | } |
661 | ||
ab4eb8b0 | 662 | int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) |
92105bb7 TL |
663 | { |
664 | u32 l; | |
665 | ||
ab4eb8b0 TKD |
666 | if (unlikely(!timer)) |
667 | return -EINVAL; | |
668 | ||
b481113a | 669 | omap_dm_timer_enable(timer); |
92105bb7 | 670 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
671 | l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
672 | if (prescaler >= 0x00 && prescaler <= 0x07) { | |
673 | l |= OMAP_TIMER_CTRL_PRE; | |
674 | l |= prescaler << 2; | |
675 | } | |
92105bb7 | 676 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
677 | |
678 | /* Save the context */ | |
679 | timer->context.tclr = l; | |
680 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 681 | return 0; |
92105bb7 TL |
682 | } |
683 | ||
ab4eb8b0 | 684 | int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
77900a2f | 685 | unsigned int value) |
92105bb7 | 686 | { |
ab4eb8b0 TKD |
687 | if (unlikely(!timer)) |
688 | return -EINVAL; | |
689 | ||
b481113a | 690 | omap_dm_timer_enable(timer); |
ee17f114 | 691 | __omap_dm_timer_int_enable(timer, value); |
b481113a TKD |
692 | |
693 | /* Save the context */ | |
694 | timer->context.tier = value; | |
695 | timer->context.twer = value; | |
696 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 697 | return 0; |
92105bb7 TL |
698 | } |
699 | ||
4249d96c JH |
700 | /** |
701 | * omap_dm_timer_set_int_disable - disable timer interrupts | |
702 | * @timer: pointer to timer handle | |
703 | * @mask: bit mask of interrupts to be disabled | |
704 | * | |
705 | * Disables the specified timer interrupts for a timer. | |
706 | */ | |
707 | int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) | |
708 | { | |
709 | u32 l = mask; | |
710 | ||
711 | if (unlikely(!timer)) | |
712 | return -EINVAL; | |
713 | ||
714 | omap_dm_timer_enable(timer); | |
715 | ||
716 | if (timer->revision == 1) | |
834cacfb | 717 | l = readl_relaxed(timer->irq_ena) & ~mask; |
4249d96c | 718 | |
834cacfb | 719 | writel_relaxed(l, timer->irq_dis); |
4249d96c JH |
720 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; |
721 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); | |
722 | ||
723 | /* Save the context */ | |
724 | timer->context.tier &= ~mask; | |
725 | timer->context.twer &= ~mask; | |
726 | omap_dm_timer_disable(timer); | |
727 | return 0; | |
728 | } | |
4249d96c | 729 | |
77900a2f | 730 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
92105bb7 | 731 | { |
fa4bb626 TT |
732 | unsigned int l; |
733 | ||
ab4eb8b0 TKD |
734 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
735 | pr_err("%s: timer not available or enabled.\n", __func__); | |
b481113a TKD |
736 | return 0; |
737 | } | |
738 | ||
834cacfb | 739 | l = readl_relaxed(timer->irq_stat); |
fa4bb626 TT |
740 | |
741 | return l; | |
92105bb7 TL |
742 | } |
743 | ||
ab4eb8b0 | 744 | int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
92105bb7 | 745 | { |
ab4eb8b0 TKD |
746 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) |
747 | return -EINVAL; | |
748 | ||
ee17f114 | 749 | __omap_dm_timer_write_status(timer, value); |
1eaff710 | 750 | |
ab4eb8b0 | 751 | return 0; |
92105bb7 TL |
752 | } |
753 | ||
77900a2f | 754 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
92105bb7 | 755 | { |
ab4eb8b0 TKD |
756 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
757 | pr_err("%s: timer not iavailable or enabled.\n", __func__); | |
b481113a TKD |
758 | return 0; |
759 | } | |
760 | ||
ee17f114 | 761 | return __omap_dm_timer_read_counter(timer, timer->posted); |
92105bb7 TL |
762 | } |
763 | ||
ab4eb8b0 | 764 | int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
83379c81 | 765 | { |
ab4eb8b0 TKD |
766 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
767 | pr_err("%s: timer not available or enabled.\n", __func__); | |
768 | return -EINVAL; | |
b481113a TKD |
769 | } |
770 | ||
fa4bb626 | 771 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
b481113a TKD |
772 | |
773 | /* Save the context */ | |
774 | timer->context.tcrr = value; | |
ab4eb8b0 | 775 | return 0; |
83379c81 TT |
776 | } |
777 | ||
77900a2f | 778 | int omap_dm_timers_active(void) |
92105bb7 | 779 | { |
3392cdd3 | 780 | struct omap_dm_timer *timer; |
12583a70 | 781 | |
3392cdd3 | 782 | list_for_each_entry(timer, &omap_timer_list, node) { |
ffe07cea | 783 | if (!timer->reserved) |
12583a70 TT |
784 | continue; |
785 | ||
77900a2f | 786 | if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
fa4bb626 | 787 | OMAP_TIMER_CTRL_ST) { |
77900a2f | 788 | return 1; |
fa4bb626 | 789 | } |
77900a2f TT |
790 | } |
791 | return 0; | |
792 | } | |
92105bb7 | 793 | |
d1c6ccfe JH |
794 | static const struct of_device_id omap_timer_match[]; |
795 | ||
df28472a TKD |
796 | /** |
797 | * omap_dm_timer_probe - probe function called for every registered device | |
798 | * @pdev: pointer to current timer platform device | |
799 | * | |
800 | * Called by driver framework at the end of device registration for all | |
801 | * timer devices. | |
802 | */ | |
351a102d | 803 | static int omap_dm_timer_probe(struct platform_device *pdev) |
df28472a | 804 | { |
df28472a TKD |
805 | unsigned long flags; |
806 | struct omap_dm_timer *timer; | |
74dd9ec6 TKD |
807 | struct resource *mem, *irq; |
808 | struct device *dev = &pdev->dev; | |
d1c6ccfe JH |
809 | const struct of_device_id *match; |
810 | const struct dmtimer_platform_data *pdata; | |
a76fc9dd | 811 | int ret; |
d1c6ccfe JH |
812 | |
813 | match = of_match_device(of_match_ptr(omap_timer_match), dev); | |
814 | pdata = match ? match->data : dev->platform_data; | |
df28472a | 815 | |
9725f445 | 816 | if (!pdata && !dev->of_node) { |
74dd9ec6 | 817 | dev_err(dev, "%s: no platform data.\n", __func__); |
df28472a TKD |
818 | return -ENODEV; |
819 | } | |
820 | ||
821 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
822 | if (unlikely(!irq)) { | |
74dd9ec6 | 823 | dev_err(dev, "%s: no IRQ resource.\n", __func__); |
df28472a TKD |
824 | return -ENODEV; |
825 | } | |
826 | ||
827 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
828 | if (unlikely(!mem)) { | |
74dd9ec6 | 829 | dev_err(dev, "%s: no memory resource.\n", __func__); |
df28472a TKD |
830 | return -ENODEV; |
831 | } | |
832 | ||
16e7ea53 | 833 | timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL); |
d679950c | 834 | if (!timer) |
74dd9ec6 | 835 | return -ENOMEM; |
df28472a | 836 | |
86287958 | 837 | timer->fclk = ERR_PTR(-ENODEV); |
5857bd98 TR |
838 | timer->io_base = devm_ioremap_resource(dev, mem); |
839 | if (IS_ERR(timer->io_base)) | |
840 | return PTR_ERR(timer->io_base); | |
df28472a | 841 | |
9725f445 JH |
842 | if (dev->of_node) { |
843 | if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) | |
844 | timer->capability |= OMAP_TIMER_ALWON; | |
845 | if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) | |
846 | timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; | |
847 | if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) | |
848 | timer->capability |= OMAP_TIMER_HAS_PWM; | |
849 | if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) | |
850 | timer->capability |= OMAP_TIMER_SECURE; | |
851 | } else { | |
852 | timer->id = pdev->id; | |
853 | timer->capability = pdata->timer_capability; | |
854 | timer->reserved = omap_dm_timer_reserved_systimer(timer->id); | |
f56f52e0 | 855 | timer->get_context_loss_count = pdata->get_context_loss_count; |
9725f445 JH |
856 | } |
857 | ||
d1c6ccfe JH |
858 | if (pdata) |
859 | timer->errata = pdata->timer_errata; | |
860 | ||
df28472a TKD |
861 | timer->irq = irq->start; |
862 | timer->pdev = pdev; | |
df28472a | 863 | |
ba688783 TL |
864 | pm_runtime_enable(dev); |
865 | pm_runtime_irq_safe(dev); | |
ffe07cea | 866 | |
0dad9fae | 867 | if (!timer->reserved) { |
a76fc9dd SA |
868 | ret = pm_runtime_get_sync(dev); |
869 | if (ret < 0) { | |
870 | dev_err(dev, "%s: pm_runtime_get_sync failed!\n", | |
871 | __func__); | |
872 | goto err_get_sync; | |
873 | } | |
0dad9fae | 874 | __omap_dm_timer_init_regs(timer); |
74dd9ec6 | 875 | pm_runtime_put(dev); |
0dad9fae TL |
876 | } |
877 | ||
df28472a TKD |
878 | /* add the timer element to the list */ |
879 | spin_lock_irqsave(&dm_timer_lock, flags); | |
880 | list_add_tail(&timer->node, &omap_timer_list); | |
881 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
882 | ||
74dd9ec6 | 883 | dev_dbg(dev, "Device Probed.\n"); |
df28472a TKD |
884 | |
885 | return 0; | |
a76fc9dd SA |
886 | |
887 | err_get_sync: | |
888 | pm_runtime_put_noidle(dev); | |
889 | pm_runtime_disable(dev); | |
890 | return ret; | |
df28472a TKD |
891 | } |
892 | ||
893 | /** | |
894 | * omap_dm_timer_remove - cleanup a registered timer device | |
895 | * @pdev: pointer to current timer platform device | |
896 | * | |
897 | * Called by driver framework whenever a timer device is unregistered. | |
898 | * In addition to freeing platform resources it also deletes the timer | |
899 | * entry from the local list. | |
900 | */ | |
351a102d | 901 | static int omap_dm_timer_remove(struct platform_device *pdev) |
df28472a TKD |
902 | { |
903 | struct omap_dm_timer *timer; | |
904 | unsigned long flags; | |
905 | int ret = -EINVAL; | |
906 | ||
907 | spin_lock_irqsave(&dm_timer_lock, flags); | |
908 | list_for_each_entry(timer, &omap_timer_list, node) | |
9725f445 JH |
909 | if (!strcmp(dev_name(&timer->pdev->dev), |
910 | dev_name(&pdev->dev))) { | |
df28472a | 911 | list_del(&timer->node); |
df28472a TKD |
912 | ret = 0; |
913 | break; | |
914 | } | |
915 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
916 | ||
51b7e572 SA |
917 | pm_runtime_disable(&pdev->dev); |
918 | ||
df28472a TKD |
919 | return ret; |
920 | } | |
921 | ||
d1c6ccfe JH |
922 | static const struct dmtimer_platform_data omap3plus_pdata = { |
923 | .timer_errata = OMAP_TIMER_ERRATA_I103_I767, | |
924 | }; | |
925 | ||
9725f445 | 926 | static const struct of_device_id omap_timer_match[] = { |
d1c6ccfe JH |
927 | { |
928 | .compatible = "ti,omap2420-timer", | |
929 | }, | |
930 | { | |
931 | .compatible = "ti,omap3430-timer", | |
932 | .data = &omap3plus_pdata, | |
933 | }, | |
934 | { | |
935 | .compatible = "ti,omap4430-timer", | |
936 | .data = &omap3plus_pdata, | |
937 | }, | |
938 | { | |
939 | .compatible = "ti,omap5430-timer", | |
940 | .data = &omap3plus_pdata, | |
941 | }, | |
942 | { | |
943 | .compatible = "ti,am335x-timer", | |
944 | .data = &omap3plus_pdata, | |
945 | }, | |
946 | { | |
947 | .compatible = "ti,am335x-timer-1ms", | |
948 | .data = &omap3plus_pdata, | |
949 | }, | |
8c0cabd7 NA |
950 | { |
951 | .compatible = "ti,dm816-timer", | |
952 | .data = &omap3plus_pdata, | |
953 | }, | |
9725f445 JH |
954 | {}, |
955 | }; | |
956 | MODULE_DEVICE_TABLE(of, omap_timer_match); | |
957 | ||
df28472a TKD |
958 | static struct platform_driver omap_dm_timer_driver = { |
959 | .probe = omap_dm_timer_probe, | |
351a102d | 960 | .remove = omap_dm_timer_remove, |
df28472a TKD |
961 | .driver = { |
962 | .name = "omap_timer", | |
9725f445 | 963 | .of_match_table = of_match_ptr(omap_timer_match), |
df28472a TKD |
964 | }, |
965 | }; | |
966 | ||
df28472a | 967 | early_platform_init("earlytimer", &omap_dm_timer_driver); |
e4e9f7ea | 968 | module_platform_driver(omap_dm_timer_driver); |
df28472a TKD |
969 | |
970 | MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); | |
971 | MODULE_LICENSE("GPL"); | |
972 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
973 | MODULE_AUTHOR("Texas Instruments Inc"); |