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ARM: OMAP: make legacy gpio request/free calls superfluous
[mirror_ubuntu-zesty-kernel.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
5e1c5ff4
TL		 14#include <linux/init.h>
15#include <linux/module.h>
5e1c5ff4 16#include <linux/interrupt.h>
92105bb7
TL		 17#include <linux/sysdev.h>
18#include <linux/err.h>
f8ce2547 19#include <linux/clk.h>
fced80c7 20#include <linux/io.h>
5e1c5ff4 21
a09e64fb 22#include <mach/hardware.h>
5e1c5ff4 23#include <asm/irq.h>
a09e64fb
RK		 24#include <mach/irqs.h>
25#include <mach/gpio.h>
5e1c5ff4
TL		 26#include <asm/mach/irq.h>
27
5e1c5ff4
TL		 28/*
29 * OMAP1510 GPIO registers
30 */
7c7095aa 31#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
5e1c5ff4
TL		 32#define OMAP1510_GPIO_DATA_INPUT 0x00
33#define OMAP1510_GPIO_DATA_OUTPUT 0x04
34#define OMAP1510_GPIO_DIR_CONTROL 0x08
35#define OMAP1510_GPIO_INT_CONTROL 0x0c
36#define OMAP1510_GPIO_INT_MASK 0x10
37#define OMAP1510_GPIO_INT_STATUS 0x14
38#define OMAP1510_GPIO_PIN_CONTROL 0x18
39
40#define OMAP1510_IH_GPIO_BASE 64
41
42/*
43 * OMAP1610 specific GPIO registers
44 */
7c7095aa
RK		 45#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
5e1c5ff4
TL		 49#define OMAP1610_GPIO_REVISION 0x0000
50#define OMAP1610_GPIO_SYSCONFIG 0x0010
51#define OMAP1610_GPIO_SYSSTATUS 0x0014
52#define OMAP1610_GPIO_IRQSTATUS1 0x0018
53#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 54#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 55#define OMAP1610_GPIO_DATAIN 0x002c
56#define OMAP1610_GPIO_DATAOUT 0x0030
57#define OMAP1610_GPIO_DIRECTION 0x0034
58#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 61#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 62#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 64#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 65#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
66
67/*
68 * OMAP730 specific GPIO registers
69 */
7c7095aa
RK		 70#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
5e1c5ff4
TL		 76#define OMAP730_GPIO_DATA_INPUT 0x00
77#define OMAP730_GPIO_DATA_OUTPUT 0x04
78#define OMAP730_GPIO_DIR_CONTROL 0x08
79#define OMAP730_GPIO_INT_CONTROL 0x0c
80#define OMAP730_GPIO_INT_MASK 0x10
81#define OMAP730_GPIO_INT_STATUS 0x14
82
92105bb7
TL		 83/*
84 * omap24xx specific GPIO registers
85 */
7c7095aa
RK		 86#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
56a25641 90
7c7095aa
RK		 91#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
56a25641 96
92105bb7
TL		 97#define OMAP24XX_GPIO_REVISION 0x0000
98#define OMAP24XX_GPIO_SYSCONFIG 0x0010
99#define OMAP24XX_GPIO_SYSSTATUS 0x0014
100#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 101#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7 103#define OMAP24XX_GPIO_IRQENABLE1 0x001c
723fdb78 104#define OMAP24XX_GPIO_WAKE_EN 0x0020
92105bb7
TL		 105#define OMAP24XX_GPIO_CTRL 0x0030
106#define OMAP24XX_GPIO_OE 0x0034
107#define OMAP24XX_GPIO_DATAIN 0x0038
108#define OMAP24XX_GPIO_DATAOUT 0x003c
109#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111#define OMAP24XX_GPIO_RISINGDETECT 0x0048
112#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 113#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 115#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118#define OMAP24XX_GPIO_SETWKUENA 0x0084
119#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120#define OMAP24XX_GPIO_SETDATAOUT 0x0094
121
5492fb1a
SMK		 122/*
123 * omap34xx specific GPIO registers
124 */
125
7c7095aa
RK		 126#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
127#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
128#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
129#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
130#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
131#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
5492fb1a 132
7c7095aa 133#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
5492fb1a 134
5e1c5ff4 135struct gpio_bank {
92105bb7 136 void __iomem *base;
5e1c5ff4
TL		 137 u16 irq;
138 u16 virtual_irq_start;
92105bb7 139 int method;
5492fb1a 140#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 141 u32 suspend_wakeup;
142 u32 saved_wakeup;
3ac4fa99 143#endif
5492fb1a 144#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
147
148 u32 saved_datain;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
151#endif
b144ff6f 152 u32 level_mask;
5e1c5ff4 153 spinlock_t lock;
52e31344 154 struct gpio_chip chip;
89db9482 155 struct clk *dbck;
5e1c5ff4
TL		 156};
157
158#define METHOD_MPUIO 0
159#define METHOD_GPIO_1510 1
160#define METHOD_GPIO_1610 2
161#define METHOD_GPIO_730 3
92105bb7 162#define METHOD_GPIO_24XX 4
5e1c5ff4 163
92105bb7 164#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 165static struct gpio_bank gpio_bank_1610[5] = {
7c7095aa 166 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
5e1c5ff4
TL		 167 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
169 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
170 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
171};
172#endif
173
1a8bfa1e 174#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 175static struct gpio_bank gpio_bank_1510[2] = {
7c7095aa 176 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
5e1c5ff4
TL		 177 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
178};
179#endif
180
181#ifdef CONFIG_ARCH_OMAP730
182static struct gpio_bank gpio_bank_730[7] = {
7c7095aa 183 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
5e1c5ff4
TL		 184 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
185 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
186 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
187 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
188 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
189 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
190};
191#endif
192
92105bb7 193#ifdef CONFIG_ARCH_OMAP24XX
56a25641
SMK		 194
195static struct gpio_bank gpio_bank_242x[4] = {
196 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
198 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
199 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
92105bb7 200};
56a25641
SMK		 201
202static struct gpio_bank gpio_bank_243x[5] = {
203 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
206 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
207 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
208};
209
92105bb7
TL		 210#endif
211
5492fb1a
SMK		 212#ifdef CONFIG_ARCH_OMAP34XX
213static struct gpio_bank gpio_bank_34xx[6] = {
214 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
218 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
219 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
220};
221
222#endif
223
5e1c5ff4
TL		 224static struct gpio_bank *gpio_bank;
225static int gpio_bank_count;
226
227static inline struct gpio_bank *get_gpio_bank(int gpio)
228{
6e60e79a 229 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 230 if (OMAP_GPIO_IS_MPUIO(gpio))
231 return &gpio_bank[0];
232 return &gpio_bank[1];
233 }
5e1c5ff4
TL		 234 if (cpu_is_omap16xx()) {
235 if (OMAP_GPIO_IS_MPUIO(gpio))
236 return &gpio_bank[0];
237 return &gpio_bank[1 + (gpio >> 4)];
238 }
5e1c5ff4
TL		 239 if (cpu_is_omap730()) {
240 if (OMAP_GPIO_IS_MPUIO(gpio))
241 return &gpio_bank[0];
242 return &gpio_bank[1 + (gpio >> 5)];
243 }
92105bb7
TL		 244 if (cpu_is_omap24xx())
245 return &gpio_bank[gpio >> 5];
5492fb1a
SMK		 246 if (cpu_is_omap34xx())
247 return &gpio_bank[gpio >> 5];
5e1c5ff4
TL		 248}
249
250static inline int get_gpio_index(int gpio)
251{
252 if (cpu_is_omap730())
253 return gpio & 0x1f;
92105bb7
TL		 254 if (cpu_is_omap24xx())
255 return gpio & 0x1f;
5492fb1a
SMK		 256 if (cpu_is_omap34xx())
257 return gpio & 0x1f;
92105bb7 258 return gpio & 0x0f;
5e1c5ff4
TL		 259}
260
261static inline int gpio_valid(int gpio)
262{
263 if (gpio < 0)
264 return -1;
d11ac979 265 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 266 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 267 return -1;
268 return 0;
269 }
6e60e79a 270 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 271 return 0;
5e1c5ff4
TL		 272 if ((cpu_is_omap16xx()) && gpio < 64)
273 return 0;
5e1c5ff4
TL		 274 if (cpu_is_omap730() && gpio < 192)
275 return 0;
92105bb7
TL		 276 if (cpu_is_omap24xx() && gpio < 128)
277 return 0;
5492fb1a
SMK		 278 if (cpu_is_omap34xx() && gpio < 160)
279 return 0;
5e1c5ff4
TL		 280 return -1;
281}
282
283static int check_gpio(int gpio)
284{
285 if (unlikely(gpio_valid(gpio)) < 0) {
286 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
287 dump_stack();
288 return -1;
289 }
290 return 0;
291}
292
293static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
294{
92105bb7 295 void __iomem *reg = bank->base;
5e1c5ff4
TL		 296 u32 l;
297
298 switch (bank->method) {
e5c56ed3 299#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 300 case METHOD_MPUIO:
301 reg += OMAP_MPUIO_IO_CNTL;
302 break;
e5c56ed3
DB		 303#endif
304#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 305 case METHOD_GPIO_1510:
306 reg += OMAP1510_GPIO_DIR_CONTROL;
307 break;
e5c56ed3
DB		 308#endif
309#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 310 case METHOD_GPIO_1610:
311 reg += OMAP1610_GPIO_DIRECTION;
312 break;
e5c56ed3
DB		 313#endif
314#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 315 case METHOD_GPIO_730:
316 reg += OMAP730_GPIO_DIR_CONTROL;
317 break;
e5c56ed3 318#endif
5492fb1a 319#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 320 case METHOD_GPIO_24XX:
321 reg += OMAP24XX_GPIO_OE;
322 break;
e5c56ed3
DB		 323#endif
324 default:
325 WARN_ON(1);
326 return;
5e1c5ff4
TL		 327 }
328 l = __raw_readl(reg);
329 if (is_input)
330 l |= 1 << gpio;
331 else
332 l &= ~(1 << gpio);
333 __raw_writel(l, reg);
334}
335
5e1c5ff4
TL		 336static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
337{
92105bb7 338 void __iomem *reg = bank->base;
5e1c5ff4
TL		 339 u32 l = 0;
340
341 switch (bank->method) {
e5c56ed3 342#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 343 case METHOD_MPUIO:
344 reg += OMAP_MPUIO_OUTPUT;
345 l = __raw_readl(reg);
346 if (enable)
347 l |= 1 << gpio;
348 else
349 l &= ~(1 << gpio);
350 break;
e5c56ed3
DB		 351#endif
352#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 353 case METHOD_GPIO_1510:
354 reg += OMAP1510_GPIO_DATA_OUTPUT;
355 l = __raw_readl(reg);
356 if (enable)
357 l |= 1 << gpio;
358 else
359 l &= ~(1 << gpio);
360 break;
e5c56ed3
DB		 361#endif
362#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 363 case METHOD_GPIO_1610:
364 if (enable)
365 reg += OMAP1610_GPIO_SET_DATAOUT;
366 else
367 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
368 l = 1 << gpio;
369 break;
e5c56ed3
DB		 370#endif
371#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 372 case METHOD_GPIO_730:
373 reg += OMAP730_GPIO_DATA_OUTPUT;
374 l = __raw_readl(reg);
375 if (enable)
376 l |= 1 << gpio;
377 else
378 l &= ~(1 << gpio);
379 break;
e5c56ed3 380#endif
5492fb1a 381#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 382 case METHOD_GPIO_24XX:
383 if (enable)
384 reg += OMAP24XX_GPIO_SETDATAOUT;
385 else
386 reg += OMAP24XX_GPIO_CLEARDATAOUT;
387 l = 1 << gpio;
388 break;
e5c56ed3 389#endif
5e1c5ff4 390 default:
e5c56ed3 391 WARN_ON(1);
5e1c5ff4
TL		 392 return;
393 }
394 __raw_writel(l, reg);
395}
396
0b84b5ca 397static int __omap_get_gpio_datain(int gpio)
5e1c5ff4
TL		 398{
399 struct gpio_bank *bank;
92105bb7 400 void __iomem *reg;
5e1c5ff4
TL		 401
402 if (check_gpio(gpio) < 0)
e5c56ed3 403 return -EINVAL;
5e1c5ff4
TL		 404 bank = get_gpio_bank(gpio);
405 reg = bank->base;
406 switch (bank->method) {
e5c56ed3 407#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 408 case METHOD_MPUIO:
409 reg += OMAP_MPUIO_INPUT_LATCH;
410 break;
e5c56ed3
DB		 411#endif
412#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 413 case METHOD_GPIO_1510:
414 reg += OMAP1510_GPIO_DATA_INPUT;
415 break;
e5c56ed3
DB		 416#endif
417#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 418 case METHOD_GPIO_1610:
419 reg += OMAP1610_GPIO_DATAIN;
420 break;
e5c56ed3
DB		 421#endif
422#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 423 case METHOD_GPIO_730:
424 reg += OMAP730_GPIO_DATA_INPUT;
425 break;
e5c56ed3 426#endif
5492fb1a 427#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 428 case METHOD_GPIO_24XX:
429 reg += OMAP24XX_GPIO_DATAIN;
430 break;
e5c56ed3 431#endif
5e1c5ff4 432 default:
e5c56ed3 433 return -EINVAL;
5e1c5ff4 434 }
92105bb7
TL		 435 return (__raw_readl(reg)
436 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 437}
438
92105bb7
TL		 439#define MOD_REG_BIT(reg, bit_mask, set) \
440do { \
441 int l = __raw_readl(base + reg); \
442 if (set) l |= bit_mask; \
443 else l &= ~bit_mask; \
444 __raw_writel(l, base + reg); \
445} while(0)
446
5eb3bb9c
KH		 447void omap_set_gpio_debounce(int gpio, int enable)
448{
449 struct gpio_bank *bank;
450 void __iomem *reg;
451 u32 val, l = 1 << get_gpio_index(gpio);
452
453 if (cpu_class_is_omap1())
454 return;
455
456 bank = get_gpio_bank(gpio);
457 reg = bank->base;
458
459 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
460 val = __raw_readl(reg);
461
89db9482 462 if (enable && !(val & l))
5eb3bb9c 463 val |= l;
89db9482 464 else if (!enable && val & l)
5eb3bb9c 465 val &= ~l;
89db9482
JH		 466 else
467 return;
468
469 if (cpu_is_omap34xx())
470 enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
5eb3bb9c
KH		 471
472 __raw_writel(val, reg);
473}
474EXPORT_SYMBOL(omap_set_gpio_debounce);
475
476void omap_set_gpio_debounce_time(int gpio, int enc_time)
477{
478 struct gpio_bank *bank;
479 void __iomem *reg;
480
481 if (cpu_class_is_omap1())
482 return;
483
484 bank = get_gpio_bank(gpio);
485 reg = bank->base;
486
487 enc_time &= 0xff;
488 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
489 __raw_writel(enc_time, reg);
490}
491EXPORT_SYMBOL(omap_set_gpio_debounce_time);
492
5492fb1a 493#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
5eb3bb9c
KH		 494static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
495 int trigger)
5e1c5ff4 496{
3ac4fa99 497 void __iomem *base = bank->base;
92105bb7
TL		 498 u32 gpio_bit = 1 << gpio;
499
500 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
6cab4860 501 trigger & IRQ_TYPE_LEVEL_LOW);
92105bb7 502 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
6cab4860 503 trigger & IRQ_TYPE_LEVEL_HIGH);
92105bb7 504 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
6cab4860 505 trigger & IRQ_TYPE_EDGE_RISING);
92105bb7 506 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
6cab4860 507 trigger & IRQ_TYPE_EDGE_FALLING);
5eb3bb9c 508
3ac4fa99
JY		 509 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
510 if (trigger != 0)
5eb3bb9c
KH		 511 __raw_writel(1 << gpio, bank->base
512 + OMAP24XX_GPIO_SETWKUENA);
3ac4fa99 513 else
5eb3bb9c
KH		 514 __raw_writel(1 << gpio, bank->base
515 + OMAP24XX_GPIO_CLEARWKUENA);
3ac4fa99
JY		 516 } else {
517 if (trigger != 0)
518 bank->enabled_non_wakeup_gpios |= gpio_bit;
519 else
520 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
521 }
5eb3bb9c 522
b144ff6f
KH		 523 bank->level_mask =
524 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
525 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
92105bb7 526}
3ac4fa99 527#endif
92105bb7
TL		 528
529static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
530{
531 void __iomem *reg = bank->base;
532 u32 l = 0;
5e1c5ff4
TL		 533
534 switch (bank->method) {
e5c56ed3 535#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 536 case METHOD_MPUIO:
537 reg += OMAP_MPUIO_GPIO_INT_EDGE;
538 l = __raw_readl(reg);
6cab4860 539 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 540 l |= 1 << gpio;
6cab4860 541 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 542 l &= ~(1 << gpio);
92105bb7
TL		 543 else
544 goto bad;
5e1c5ff4 545 break;
e5c56ed3
DB		 546#endif
547#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 548 case METHOD_GPIO_1510:
549 reg += OMAP1510_GPIO_INT_CONTROL;
550 l = __raw_readl(reg);
6cab4860 551 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 552 l |= 1 << gpio;
6cab4860 553 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 554 l &= ~(1 << gpio);
92105bb7
TL		 555 else
556 goto bad;
5e1c5ff4 557 break;
e5c56ed3 558#endif
3ac4fa99 559#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 560 case METHOD_GPIO_1610:
5e1c5ff4
TL		 561 if (gpio & 0x08)
562 reg += OMAP1610_GPIO_EDGE_CTRL2;
563 else
564 reg += OMAP1610_GPIO_EDGE_CTRL1;
565 gpio &= 0x07;
566 l = __raw_readl(reg);
567 l &= ~(3 << (gpio << 1));
6cab4860 568 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 569 l |= 2 << (gpio << 1);
6cab4860 570 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 571 l |= 1 << (gpio << 1);
3ac4fa99
JY		 572 if (trigger)
573 /* Enable wake-up during idle for dynamic tick */
574 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
575 else
576 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 577 break;
3ac4fa99
JY		 578#endif
579#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 580 case METHOD_GPIO_730:
581 reg += OMAP730_GPIO_INT_CONTROL;
582 l = __raw_readl(reg);
6cab4860 583 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 584 l |= 1 << gpio;
6cab4860 585 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 586 l &= ~(1 << gpio);
92105bb7
TL		 587 else
588 goto bad;
589 break;
3ac4fa99 590#endif
5492fb1a 591#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 592 case METHOD_GPIO_24XX:
3ac4fa99 593 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 594 break;
3ac4fa99 595#endif
5e1c5ff4 596 default:
92105bb7 597 goto bad;
5e1c5ff4 598 }
92105bb7
TL		 599 __raw_writel(l, reg);
600 return 0;
601bad:
602 return -EINVAL;
5e1c5ff4
TL		 603}
604
92105bb7 605static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 606{
607 struct gpio_bank *bank;
92105bb7
TL		 608 unsigned gpio;
609 int retval;
a6472533 610 unsigned long flags;
92105bb7 611
5492fb1a 612 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 613 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
614 else
615 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 616
617 if (check_gpio(gpio) < 0)
92105bb7
TL		 618 return -EINVAL;
619
e5c56ed3 620 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 621 return -EINVAL;
e5c56ed3
DB		 622
623 /* OMAP1 allows only only edge triggering */
5492fb1a 624 if (!cpu_class_is_omap2()
e5c56ed3 625 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 626 return -EINVAL;
627
58781016 628 bank = get_irq_chip_data(irq);
a6472533 629 spin_lock_irqsave(&bank->lock, flags);
92105bb7 630 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 631 if (retval == 0) {
632 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
633 irq_desc[irq].status |= type;
634 }
a6472533 635 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 636
637 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
638 __set_irq_handler_unlocked(irq, handle_level_irq);
639 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
640 __set_irq_handler_unlocked(irq, handle_edge_irq);
641
92105bb7 642 return retval;
5e1c5ff4
TL		 643}
644
645static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
646{
92105bb7 647 void __iomem *reg = bank->base;
5e1c5ff4
TL		 648
649 switch (bank->method) {
e5c56ed3 650#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 651 case METHOD_MPUIO:
652 /* MPUIO irqstatus is reset by reading the status register,
653 * so do nothing here */
654 return;
e5c56ed3
DB		 655#endif
656#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 657 case METHOD_GPIO_1510:
658 reg += OMAP1510_GPIO_INT_STATUS;
659 break;
e5c56ed3
DB		 660#endif
661#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 662 case METHOD_GPIO_1610:
663 reg += OMAP1610_GPIO_IRQSTATUS1;
664 break;
e5c56ed3
DB		 665#endif
666#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 667 case METHOD_GPIO_730:
668 reg += OMAP730_GPIO_INT_STATUS;
669 break;
e5c56ed3 670#endif
5492fb1a 671#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 672 case METHOD_GPIO_24XX:
673 reg += OMAP24XX_GPIO_IRQSTATUS1;
674 break;
e5c56ed3 675#endif
5e1c5ff4 676 default:
e5c56ed3 677 WARN_ON(1);
5e1c5ff4
TL		 678 return;
679 }
680 __raw_writel(gpio_mask, reg);
bee7930f
HD		 681
682 /* Workaround for clearing DSP GPIO interrupts to allow retention */
5492fb1a
SMK		 683#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
684 if (cpu_is_omap24xx() || cpu_is_omap34xx())
bee7930f 685 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
5492fb1a 686#endif
5e1c5ff4
TL		 687}
688
689static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
690{
691 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
692}
693
ea6dedd7
ID		 694static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
695{
696 void __iomem *reg = bank->base;
99c47707
ID		 697 int inv = 0;
698 u32 l;
699 u32 mask;
ea6dedd7
ID		 700
701 switch (bank->method) {
e5c56ed3 702#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 703 case METHOD_MPUIO:
704 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 705 mask = 0xffff;
706 inv = 1;
ea6dedd7 707 break;
e5c56ed3
DB		 708#endif
709#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 710 case METHOD_GPIO_1510:
711 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 712 mask = 0xffff;
713 inv = 1;
ea6dedd7 714 break;
e5c56ed3
DB		 715#endif
716#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 717 case METHOD_GPIO_1610:
718 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 719 mask = 0xffff;
ea6dedd7 720 break;
e5c56ed3
DB		 721#endif
722#ifdef CONFIG_ARCH_OMAP730
ea6dedd7
ID		 723 case METHOD_GPIO_730:
724 reg += OMAP730_GPIO_INT_MASK;
99c47707
ID		 725 mask = 0xffffffff;
726 inv = 1;
ea6dedd7 727 break;
e5c56ed3 728#endif
5492fb1a 729#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
ea6dedd7
ID		 730 case METHOD_GPIO_24XX:
731 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 732 mask = 0xffffffff;
ea6dedd7 733 break;
e5c56ed3 734#endif
ea6dedd7 735 default:
e5c56ed3 736 WARN_ON(1);
ea6dedd7
ID		 737 return 0;
738 }
739
99c47707
ID		 740 l = __raw_readl(reg);
741 if (inv)
742 l = ~l;
743 l &= mask;
744 return l;
ea6dedd7
ID		 745}
746
5e1c5ff4
TL		 747static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
748{
92105bb7 749 void __iomem *reg = bank->base;
5e1c5ff4
TL		 750 u32 l;
751
752 switch (bank->method) {
e5c56ed3 753#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 754 case METHOD_MPUIO:
755 reg += OMAP_MPUIO_GPIO_MASKIT;
756 l = __raw_readl(reg);
757 if (enable)
758 l &= ~(gpio_mask);
759 else
760 l |= gpio_mask;
761 break;
e5c56ed3
DB		 762#endif
763#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 764 case METHOD_GPIO_1510:
765 reg += OMAP1510_GPIO_INT_MASK;
766 l = __raw_readl(reg);
767 if (enable)
768 l &= ~(gpio_mask);
769 else
770 l |= gpio_mask;
771 break;
e5c56ed3
DB		 772#endif
773#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 774 case METHOD_GPIO_1610:
775 if (enable)
776 reg += OMAP1610_GPIO_SET_IRQENABLE1;
777 else
778 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
779 l = gpio_mask;
780 break;
e5c56ed3
DB		 781#endif
782#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 783 case METHOD_GPIO_730:
784 reg += OMAP730_GPIO_INT_MASK;
785 l = __raw_readl(reg);
786 if (enable)
787 l &= ~(gpio_mask);
788 else
789 l |= gpio_mask;
790 break;
e5c56ed3 791#endif
5492fb1a 792#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 793 case METHOD_GPIO_24XX:
794 if (enable)
795 reg += OMAP24XX_GPIO_SETIRQENABLE1;
796 else
797 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
798 l = gpio_mask;
799 break;
e5c56ed3 800#endif
5e1c5ff4 801 default:
e5c56ed3 802 WARN_ON(1);
5e1c5ff4
TL		 803 return;
804 }
805 __raw_writel(l, reg);
806}
807
808static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
809{
810 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
811}
812
92105bb7
TL		 813/*
814 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
815 * 1510 does not seem to have a wake-up register. If JTAG is connected
816 * to the target, system will wake up always on GPIO events. While
817 * system is running all registered GPIO interrupts need to have wake-up
818 * enabled. When system is suspended, only selected GPIO interrupts need
819 * to have wake-up enabled.
820 */
821static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
822{
a6472533
DB		 823 unsigned long flags;
824
92105bb7 825 switch (bank->method) {
3ac4fa99 826#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 827 case METHOD_MPUIO:
92105bb7 828 case METHOD_GPIO_1610:
a6472533 829 spin_lock_irqsave(&bank->lock, flags);
11a78b79 830 if (enable) {
92105bb7 831 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 832 enable_irq_wake(bank->irq);
833 } else {
834 disable_irq_wake(bank->irq);
92105bb7 835 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 836 }
a6472533 837 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 838 return 0;
3ac4fa99 839#endif
5492fb1a 840#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 841 case METHOD_GPIO_24XX:
11a78b79
DB		 842 if (bank->non_wakeup_gpios & (1 << gpio)) {
843 printk(KERN_ERR "Unable to modify wakeup on "
844 "non-wakeup GPIO%d\n",
845 (bank - gpio_bank) * 32 + gpio);
846 return -EINVAL;
847 }
a6472533 848 spin_lock_irqsave(&bank->lock, flags);
3ac4fa99 849 if (enable) {
3ac4fa99 850 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 851 enable_irq_wake(bank->irq);
852 } else {
853 disable_irq_wake(bank->irq);
3ac4fa99 854 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 855 }
a6472533 856 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 857 return 0;
858#endif
92105bb7
TL		 859 default:
860 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
861 bank->method);
862 return -EINVAL;
863 }
864}
865
4196dd6b
TL		 866static void _reset_gpio(struct gpio_bank *bank, int gpio)
867{
868 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
869 _set_gpio_irqenable(bank, gpio, 0);
870 _clear_gpio_irqstatus(bank, gpio);
6cab4860 871 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 872}
873
92105bb7
TL		 874/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
875static int gpio_wake_enable(unsigned int irq, unsigned int enable)
876{
877 unsigned int gpio = irq - IH_GPIO_BASE;
878 struct gpio_bank *bank;
879 int retval;
880
881 if (check_gpio(gpio) < 0)
882 return -ENODEV;
58781016 883 bank = get_irq_chip_data(irq);
92105bb7 884 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 885
886 return retval;
887}
888
3ff164e1 889static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 890{
3ff164e1 891 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 892 unsigned long flags;
52e31344 893
a6472533 894 spin_lock_irqsave(&bank->lock, flags);
92105bb7 895
4196dd6b
TL		 896 /* Set trigger to none. You need to enable the desired trigger with
897 * request_irq() or set_irq_type().
898 */
3ff164e1 899 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 900
1a8bfa1e 901#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 902 if (bank->method == METHOD_GPIO_1510) {
92105bb7 903 void __iomem *reg;
5e1c5ff4 904
92105bb7 905 /* Claim the pin for MPU */
5e1c5ff4 906 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 907 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 908 }
909#endif
a6472533 910 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 911
912 return 0;
913}
914
3ff164e1 915static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 916{
3ff164e1 917 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 918 unsigned long flags;
5e1c5ff4 919
a6472533 920 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 921#ifdef CONFIG_ARCH_OMAP16XX
922 if (bank->method == METHOD_GPIO_1610) {
923 /* Disable wake-up during idle for dynamic tick */
924 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 925 __raw_writel(1 << offset, reg);
92105bb7
TL		 926 }
927#endif
5492fb1a 928#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 929 if (bank->method == METHOD_GPIO_24XX) {
930 /* Disable wake-up during idle for dynamic tick */
931 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 932 __raw_writel(1 << offset, reg);
92105bb7
TL		 933 }
934#endif
3ff164e1 935 _reset_gpio(bank, bank->chip.base + offset);
a6472533 936 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 937}
938
939/*
940 * We need to unmask the GPIO bank interrupt as soon as possible to
941 * avoid missing GPIO interrupts for other lines in the bank.
942 * Then we need to mask-read-clear-unmask the triggered GPIO lines
943 * in the bank to avoid missing nested interrupts for a GPIO line.
944 * If we wait to unmask individual GPIO lines in the bank after the
945 * line's interrupt handler has been run, we may miss some nested
946 * interrupts.
947 */
10dd5ce2 948static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 949{
92105bb7 950 void __iomem *isr_reg = NULL;
5e1c5ff4
TL		 951 u32 isr;
952 unsigned int gpio_irq;
953 struct gpio_bank *bank;
ea6dedd7
ID		 954 u32 retrigger = 0;
955 int unmasked = 0;
5e1c5ff4
TL		 956
957 desc->chip->ack(irq);
958
418ca1f0 959 bank = get_irq_data(irq);
e5c56ed3 960#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 961 if (bank->method == METHOD_MPUIO)
962 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 963#endif
1a8bfa1e 964#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 965 if (bank->method == METHOD_GPIO_1510)
966 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
967#endif
968#if defined(CONFIG_ARCH_OMAP16XX)
969 if (bank->method == METHOD_GPIO_1610)
970 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
971#endif
972#ifdef CONFIG_ARCH_OMAP730
973 if (bank->method == METHOD_GPIO_730)
974 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
975#endif
5492fb1a 976#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 977 if (bank->method == METHOD_GPIO_24XX)
978 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
979#endif
92105bb7 980 while(1) {
6e60e79a 981 u32 isr_saved, level_mask = 0;
ea6dedd7 982 u32 enabled;
6e60e79a 983
ea6dedd7
ID		 984 enabled = _get_gpio_irqbank_mask(bank);
985 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 986
987 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
988 isr &= 0x0000ffff;
989
5492fb1a 990 if (cpu_class_is_omap2()) {
b144ff6f 991 level_mask = bank->level_mask & enabled;
ea6dedd7 992 }
6e60e79a
TL		 993
994 /* clear edge sensitive interrupts before handler(s) are
995 called so that we don't miss any interrupt occurred while
996 executing them */
997 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
998 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
999 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1000
1001 /* if there is only edge sensitive GPIO pin interrupts
1002 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1003 if (!level_mask && !unmasked) {
1004 unmasked = 1;
6e60e79a 1005 desc->chip->unmask(irq);
ea6dedd7 1006 }
92105bb7 1007
ea6dedd7
ID		 1008 isr |= retrigger;
1009 retrigger = 0;
92105bb7
TL		 1010 if (!isr)
1011 break;
1012
1013 gpio_irq = bank->virtual_irq_start;
1014 for (; isr != 0; isr >>= 1, gpio_irq++) {
92105bb7
TL		 1015 if (!(isr & 1))
1016 continue;
29454dde 1017
d8aa0251 1018 generic_handle_irq(gpio_irq);
92105bb7 1019 }
1a8bfa1e 1020 }
ea6dedd7
ID		 1021 /* if bank has any level sensitive GPIO pin interrupt
1022 configured, we must unmask the bank interrupt only after
1023 handler(s) are executed in order to avoid spurious bank
1024 interrupt */
1025 if (!unmasked)
1026 desc->chip->unmask(irq);
1027
5e1c5ff4
TL		 1028}
1029
4196dd6b
TL		 1030static void gpio_irq_shutdown(unsigned int irq)
1031{
1032 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1033 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1034
1035 _reset_gpio(bank, gpio);
1036}
1037
5e1c5ff4
TL		 1038static void gpio_ack_irq(unsigned int irq)
1039{
1040 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1041 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1042
1043 _clear_gpio_irqstatus(bank, gpio);
1044}
1045
1046static void gpio_mask_irq(unsigned int irq)
1047{
1048 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1049 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1050
1051 _set_gpio_irqenable(bank, gpio, 0);
1052}
1053
1054static void gpio_unmask_irq(unsigned int irq)
1055{
1056 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1057 struct gpio_bank *bank = get_irq_chip_data(irq);
b144ff6f
KH		 1058 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1059
1060 /* For level-triggered GPIOs, the clearing must be done after
1061 * the HW source is cleared, thus after the handler has run */
1062 if (bank->level_mask & irq_mask) {
1063 _set_gpio_irqenable(bank, gpio, 0);
1064 _clear_gpio_irqstatus(bank, gpio);
1065 }
5e1c5ff4 1066
4de8c75b 1067 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1068}
1069
e5c56ed3
DB		 1070static struct irq_chip gpio_irq_chip = {
1071 .name = "GPIO",
1072 .shutdown = gpio_irq_shutdown,
1073 .ack = gpio_ack_irq,
1074 .mask = gpio_mask_irq,
1075 .unmask = gpio_unmask_irq,
1076 .set_type = gpio_irq_type,
1077 .set_wake = gpio_wake_enable,
1078};
1079
1080/*---------------------------------------------------------------------*/
1081
1082#ifdef CONFIG_ARCH_OMAP1
1083
1084/* MPUIO uses the always-on 32k clock */
1085
5e1c5ff4
TL		 1086static void mpuio_ack_irq(unsigned int irq)
1087{
1088 /* The ISR is reset automatically, so do nothing here. */
1089}
1090
1091static void mpuio_mask_irq(unsigned int irq)
1092{
1093 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1094 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1095
1096 _set_gpio_irqenable(bank, gpio, 0);
1097}
1098
1099static void mpuio_unmask_irq(unsigned int irq)
1100{
1101 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1102 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1103
1104 _set_gpio_irqenable(bank, gpio, 1);
1105}
1106
e5c56ed3
DB		 1107static struct irq_chip mpuio_irq_chip = {
1108 .name = "MPUIO",
1109 .ack = mpuio_ack_irq,
1110 .mask = mpuio_mask_irq,
1111 .unmask = mpuio_unmask_irq,
92105bb7 1112 .set_type = gpio_irq_type,
11a78b79
DB		 1113#ifdef CONFIG_ARCH_OMAP16XX
1114 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1115 .set_wake = gpio_wake_enable,
1116#endif
5e1c5ff4
TL		 1117};
1118
e5c56ed3
DB		 1119
1120#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1121
11a78b79
DB		 1122
1123#ifdef CONFIG_ARCH_OMAP16XX
1124
1125#include <linux/platform_device.h>
1126
1127static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1128{
1129 struct gpio_bank *bank = platform_get_drvdata(pdev);
1130 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1131 unsigned long flags;
11a78b79 1132
a6472533 1133 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1134 bank->saved_wakeup = __raw_readl(mask_reg);
1135 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1136 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1137
1138 return 0;
1139}
1140
1141static int omap_mpuio_resume_early(struct platform_device *pdev)
1142{
1143 struct gpio_bank *bank = platform_get_drvdata(pdev);
1144 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1145 unsigned long flags;
11a78b79 1146
a6472533 1147 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1148 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1149 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1150
1151 return 0;
1152}
1153
1154/* use platform_driver for this, now that there's no longer any
1155 * point to sys_device (other than not disturbing old code).
1156 */
1157static struct platform_driver omap_mpuio_driver = {
1158 .suspend_late = omap_mpuio_suspend_late,
1159 .resume_early = omap_mpuio_resume_early,
1160 .driver = {
1161 .name = "mpuio",
1162 },
1163};
1164
1165static struct platform_device omap_mpuio_device = {
1166 .name = "mpuio",
1167 .id = -1,
1168 .dev = {
1169 .driver = &omap_mpuio_driver.driver,
1170 }
1171 /* could list the /proc/iomem resources */
1172};
1173
1174static inline void mpuio_init(void)
1175{
fcf126d8
DB		 1176 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1177
11a78b79
DB		 1178 if (platform_driver_register(&omap_mpuio_driver) == 0)
1179 (void) platform_device_register(&omap_mpuio_device);
1180}
1181
1182#else
1183static inline void mpuio_init(void) {}
1184#endif /* 16xx */
1185
e5c56ed3
DB		 1186#else
1187
1188extern struct irq_chip mpuio_irq_chip;
1189
1190#define bank_is_mpuio(bank) 0
11a78b79 1191static inline void mpuio_init(void) {}
e5c56ed3
DB		 1192
1193#endif
1194
1195/*---------------------------------------------------------------------*/
5e1c5ff4 1196
52e31344
DB		 1197/* REVISIT these are stupid implementations! replace by ones that
1198 * don't switch on METHOD_* and which mostly avoid spinlocks
1199 */
1200
1201static int gpio_input(struct gpio_chip *chip, unsigned offset)
1202{
1203 struct gpio_bank *bank;
1204 unsigned long flags;
1205
1206 bank = container_of(chip, struct gpio_bank, chip);
1207 spin_lock_irqsave(&bank->lock, flags);
1208 _set_gpio_direction(bank, offset, 1);
1209 spin_unlock_irqrestore(&bank->lock, flags);
1210 return 0;
1211}
1212
1213static int gpio_get(struct gpio_chip *chip, unsigned offset)
1214{
0b84b5ca 1215 return __omap_get_gpio_datain(chip->base + offset);
52e31344
DB		 1216}
1217
1218static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1219{
1220 struct gpio_bank *bank;
1221 unsigned long flags;
1222
1223 bank = container_of(chip, struct gpio_bank, chip);
1224 spin_lock_irqsave(&bank->lock, flags);
1225 _set_gpio_dataout(bank, offset, value);
1226 _set_gpio_direction(bank, offset, 0);
1227 spin_unlock_irqrestore(&bank->lock, flags);
1228 return 0;
1229}
1230
1231static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1232{
1233 struct gpio_bank *bank;
1234 unsigned long flags;
1235
1236 bank = container_of(chip, struct gpio_bank, chip);
1237 spin_lock_irqsave(&bank->lock, flags);
1238 _set_gpio_dataout(bank, offset, value);
1239 spin_unlock_irqrestore(&bank->lock, flags);
1240}
1241
a007b709
DB		 1242static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1243{
1244 struct gpio_bank *bank;
1245
1246 bank = container_of(chip, struct gpio_bank, chip);
1247 return bank->virtual_irq_start + offset;
1248}
1249
52e31344
DB		 1250/*---------------------------------------------------------------------*/
1251
1a8bfa1e 1252static int initialized;
5492fb1a 1253#if !defined(CONFIG_ARCH_OMAP3)
1a8bfa1e 1254static struct clk * gpio_ick;
5492fb1a
SMK		 1255#endif
1256
1257#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1258static struct clk * gpio_fck;
5492fb1a 1259#endif
5e1c5ff4 1260
5492fb1a 1261#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1262static struct clk * gpio5_ick;
1263static struct clk * gpio5_fck;
1264#endif
1265
5492fb1a 1266#if defined(CONFIG_ARCH_OMAP3)
5492fb1a
SMK		 1267static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1268#endif
1269
8ba55c5c
DB		 1270/* This lock class tells lockdep that GPIO irqs are in a different
1271 * category than their parents, so it won't report false recursion.
1272 */
1273static struct lock_class_key gpio_lock_class;
1274
5e1c5ff4
TL		 1275static int __init _omap_gpio_init(void)
1276{
1277 int i;
52e31344 1278 int gpio = 0;
5e1c5ff4 1279 struct gpio_bank *bank;
5492fb1a 1280 char clk_name[11];
5e1c5ff4
TL		 1281
1282 initialized = 1;
1283
5492fb1a 1284#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1285 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1286 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1287 if (IS_ERR(gpio_ick))
92105bb7
TL		 1288 printk("Could not get arm_gpio_ck\n");
1289 else
30ff720b 1290 clk_enable(gpio_ick);
1a8bfa1e 1291 }
5492fb1a
SMK		 1292#endif
1293#if defined(CONFIG_ARCH_OMAP2)
1294 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1295 gpio_ick = clk_get(NULL, "gpios_ick");
1296 if (IS_ERR(gpio_ick))
1297 printk("Could not get gpios_ick\n");
1298 else
30ff720b 1299 clk_enable(gpio_ick);
1a8bfa1e 1300 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1301 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1302 printk("Could not get gpios_fck\n");
1303 else
30ff720b 1304 clk_enable(gpio_fck);
56a25641
SMK		 1305
1306 /*
5492fb1a 1307 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1308 */
5492fb1a 1309#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1310 if (cpu_is_omap2430()) {
1311 gpio5_ick = clk_get(NULL, "gpio5_ick");
1312 if (IS_ERR(gpio5_ick))
1313 printk("Could not get gpio5_ick\n");
1314 else
1315 clk_enable(gpio5_ick);
1316 gpio5_fck = clk_get(NULL, "gpio5_fck");
1317 if (IS_ERR(gpio5_fck))
1318 printk("Could not get gpio5_fck\n");
1319 else
1320 clk_enable(gpio5_fck);
1321 }
1322#endif
5492fb1a
SMK		 1323 }
1324#endif
1325
1326#if defined(CONFIG_ARCH_OMAP3)
1327 if (cpu_is_omap34xx()) {
1328 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1329 sprintf(clk_name, "gpio%d_ick", i + 1);
1330 gpio_iclks[i] = clk_get(NULL, clk_name);
1331 if (IS_ERR(gpio_iclks[i]))
1332 printk(KERN_ERR "Could not get %s\n", clk_name);
1333 else
1334 clk_enable(gpio_iclks[i]);
5492fb1a
SMK		 1335 }
1336 }
1337#endif
1338
92105bb7 1339
1a8bfa1e 1340#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1341 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1342 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1343 gpio_bank_count = 2;
1344 gpio_bank = gpio_bank_1510;
1345 }
1346#endif
1347#if defined(CONFIG_ARCH_OMAP16XX)
1348 if (cpu_is_omap16xx()) {
92105bb7 1349 u32 rev;
5e1c5ff4
TL		 1350
1351 gpio_bank_count = 5;
1352 gpio_bank = gpio_bank_1610;
7c7095aa 1353 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
5e1c5ff4
TL		 1354 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1355 (rev >> 4) & 0x0f, rev & 0x0f);
1356 }
1357#endif
1358#ifdef CONFIG_ARCH_OMAP730
1359 if (cpu_is_omap730()) {
1360 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1361 gpio_bank_count = 7;
1362 gpio_bank = gpio_bank_730;
1363 }
92105bb7 1364#endif
56a25641 1365
92105bb7 1366#ifdef CONFIG_ARCH_OMAP24XX
56a25641 1367 if (cpu_is_omap242x()) {
92105bb7
TL		 1368 int rev;
1369
1370 gpio_bank_count = 4;
56a25641 1371 gpio_bank = gpio_bank_242x;
7c7095aa 1372 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641
SMK		 1373 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1374 (rev >> 4) & 0x0f, rev & 0x0f);
1375 }
1376 if (cpu_is_omap243x()) {
1377 int rev;
1378
1379 gpio_bank_count = 5;
1380 gpio_bank = gpio_bank_243x;
7c7095aa 1381 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641 1382 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
92105bb7
TL		 1383 (rev >> 4) & 0x0f, rev & 0x0f);
1384 }
5492fb1a
SMK		 1385#endif
1386#ifdef CONFIG_ARCH_OMAP34XX
1387 if (cpu_is_omap34xx()) {
1388 int rev;
1389
1390 gpio_bank_count = OMAP34XX_NR_GPIOS;
1391 gpio_bank = gpio_bank_34xx;
7c7095aa 1392 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
5492fb1a
SMK		 1393 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1394 (rev >> 4) & 0x0f, rev & 0x0f);
1395 }
5e1c5ff4
TL		 1396#endif
1397 for (i = 0; i < gpio_bank_count; i++) {
1398 int j, gpio_count = 16;
1399
1400 bank = &gpio_bank[i];
5e1c5ff4 1401 spin_lock_init(&bank->lock);
e5c56ed3 1402 if (bank_is_mpuio(bank))
7c7095aa 1403 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
d11ac979 1404 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
5e1c5ff4
TL		 1405 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1406 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1407 }
d11ac979 1408 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
5e1c5ff4
TL		 1409 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1410 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1411 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4 1412 }
d11ac979 1413 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
5e1c5ff4
TL		 1414 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1415 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1416
1417 gpio_count = 32; /* 730 has 32-bit GPIOs */
1418 }
d11ac979 1419
5492fb1a 1420#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1421 if (bank->method == METHOD_GPIO_24XX) {
3ac4fa99
JY		 1422 static const u32 non_wakeup_gpios[] = {
1423 0xe203ffc0, 0x08700040
1424 };
1425
92105bb7
TL		 1426 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1427 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
14f1c3bf
JY		 1428 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1429
1430 /* Initialize interface clock ungated, module enabled */
1431 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
3ac4fa99
JY		 1432 if (i < ARRAY_SIZE(non_wakeup_gpios))
1433 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1434 gpio_count = 32;
1435 }
5e1c5ff4 1436#endif
52e31344
DB		 1437
1438 /* REVISIT eventually switch from OMAP-specific gpio structs
1439 * over to the generic ones
1440 */
3ff164e1
JN		 1441 bank->chip.request = omap_gpio_request;
1442 bank->chip.free = omap_gpio_free;
52e31344
DB		 1443 bank->chip.direction_input = gpio_input;
1444 bank->chip.get = gpio_get;
1445 bank->chip.direction_output = gpio_output;
1446 bank->chip.set = gpio_set;
a007b709 1447 bank->chip.to_irq = gpio_2irq;
52e31344
DB		 1448 if (bank_is_mpuio(bank)) {
1449 bank->chip.label = "mpuio";
69114a47 1450#ifdef CONFIG_ARCH_OMAP16XX
d8f388d8
DB		 1451 bank->chip.dev = &omap_mpuio_device.dev;
1452#endif
52e31344
DB		 1453 bank->chip.base = OMAP_MPUIO(0);
1454 } else {
1455 bank->chip.label = "gpio";
1456 bank->chip.base = gpio;
1457 gpio += gpio_count;
1458 }
1459 bank->chip.ngpio = gpio_count;
1460
1461 gpiochip_add(&bank->chip);
1462
5e1c5ff4
TL		 1463 for (j = bank->virtual_irq_start;
1464 j < bank->virtual_irq_start + gpio_count; j++) {
8ba55c5c 1465 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
58781016 1466 set_irq_chip_data(j, bank);
e5c56ed3 1467 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1468 set_irq_chip(j, &mpuio_irq_chip);
1469 else
1470 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1471 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1472 set_irq_flags(j, IRQF_VALID);
1473 }
1474 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1475 set_irq_data(bank->irq, bank);
89db9482
JH		 1476
1477 if (cpu_is_omap34xx()) {
1478 sprintf(clk_name, "gpio%d_dbck", i + 1);
1479 bank->dbck = clk_get(NULL, clk_name);
1480 if (IS_ERR(bank->dbck))
1481 printk(KERN_ERR "Could not get %s\n", clk_name);
1482 }
5e1c5ff4
TL		 1483 }
1484
1485 /* Enable system clock for GPIO module.
1486 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1487 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1488 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1489
14f1c3bf
JY		 1490 /* Enable autoidle for the OCP interface */
1491 if (cpu_is_omap24xx())
1492 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1493 if (cpu_is_omap34xx())
1494 omap_writel(1 << 0, 0x48306814);
d11ac979 1495
5e1c5ff4
TL		 1496 return 0;
1497}
1498
5492fb1a 1499#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1500static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1501{
1502 int i;
1503
5492fb1a 1504 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1505 return 0;
1506
1507 for (i = 0; i < gpio_bank_count; i++) {
1508 struct gpio_bank *bank = &gpio_bank[i];
1509 void __iomem *wake_status;
1510 void __iomem *wake_clear;
1511 void __iomem *wake_set;
a6472533 1512 unsigned long flags;
92105bb7
TL		 1513
1514 switch (bank->method) {
e5c56ed3 1515#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1516 case METHOD_GPIO_1610:
1517 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1518 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1519 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1520 break;
e5c56ed3 1521#endif
5492fb1a 1522#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1523 case METHOD_GPIO_24XX:
723fdb78 1524 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1525 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1526 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1527 break;
e5c56ed3 1528#endif
92105bb7
TL		 1529 default:
1530 continue;
1531 }
1532
a6472533 1533 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1534 bank->saved_wakeup = __raw_readl(wake_status);
1535 __raw_writel(0xffffffff, wake_clear);
1536 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1537 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1538 }
1539
1540 return 0;
1541}
1542
1543static int omap_gpio_resume(struct sys_device *dev)
1544{
1545 int i;
1546
723fdb78 1547 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1548 return 0;
1549
1550 for (i = 0; i < gpio_bank_count; i++) {
1551 struct gpio_bank *bank = &gpio_bank[i];
1552 void __iomem *wake_clear;
1553 void __iomem *wake_set;
a6472533 1554 unsigned long flags;
92105bb7
TL		 1555
1556 switch (bank->method) {
e5c56ed3 1557#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1558 case METHOD_GPIO_1610:
1559 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1560 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1561 break;
e5c56ed3 1562#endif
5492fb1a 1563#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1564 case METHOD_GPIO_24XX:
0d9356cb
TL		 1565 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1566 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1567 break;
e5c56ed3 1568#endif
92105bb7
TL		 1569 default:
1570 continue;
1571 }
1572
a6472533 1573 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1574 __raw_writel(0xffffffff, wake_clear);
1575 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1576 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1577 }
1578
1579 return 0;
1580}
1581
1582static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1583 .name = "gpio",
92105bb7
TL		 1584 .suspend = omap_gpio_suspend,
1585 .resume = omap_gpio_resume,
1586};
1587
1588static struct sys_device omap_gpio_device = {
1589 .id = 0,
1590 .cls = &omap_gpio_sysclass,
1591};
3ac4fa99
JY		 1592
1593#endif
1594
5492fb1a 1595#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1596
1597static int workaround_enabled;
1598
1599void omap2_gpio_prepare_for_retention(void)
1600{
1601 int i, c = 0;
1602
1603 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1604 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1605 for (i = 0; i < gpio_bank_count; i++) {
1606 struct gpio_bank *bank = &gpio_bank[i];
1607 u32 l1, l2;
1608
1609 if (!(bank->enabled_non_wakeup_gpios))
1610 continue;
5492fb1a 1611#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1612 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1613 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1614 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1615#endif
3ac4fa99
JY		 1616 bank->saved_fallingdetect = l1;
1617 bank->saved_risingdetect = l2;
1618 l1 &= ~bank->enabled_non_wakeup_gpios;
1619 l2 &= ~bank->enabled_non_wakeup_gpios;
5492fb1a 1620#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1621 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1622 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1623#endif
3ac4fa99
JY		 1624 c++;
1625 }
1626 if (!c) {
1627 workaround_enabled = 0;
1628 return;
1629 }
1630 workaround_enabled = 1;
1631}
1632
1633void omap2_gpio_resume_after_retention(void)
1634{
1635 int i;
1636
1637 if (!workaround_enabled)
1638 return;
1639 for (i = 0; i < gpio_bank_count; i++) {
1640 struct gpio_bank *bank = &gpio_bank[i];
1641 u32 l;
1642
1643 if (!(bank->enabled_non_wakeup_gpios))
1644 continue;
5492fb1a 1645#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1646 __raw_writel(bank->saved_fallingdetect,
1647 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1648 __raw_writel(bank->saved_risingdetect,
1649 bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1650#endif
3ac4fa99
JY		 1651 /* Check if any of the non-wakeup interrupt GPIOs have changed
1652 * state. If so, generate an IRQ by software. This is
1653 * horribly racy, but it's the best we can do to work around
1654 * this silicon bug. */
5492fb1a 1655#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 1656 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
5492fb1a 1657#endif
3ac4fa99
JY		 1658 l ^= bank->saved_datain;
1659 l &= bank->non_wakeup_gpios;
1660 if (l) {
1661 u32 old0, old1;
5492fb1a 1662#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1663 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1664 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1665 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1666 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1667 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1668 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
5492fb1a 1669#endif
3ac4fa99
JY		 1670 }
1671 }
1672
1673}
1674
92105bb7
TL		 1675#endif
1676
5e1c5ff4
TL		 1677/*
1678 * This may get called early from board specific init
1a8bfa1e 1679 * for boards that have interrupts routed via FPGA.
5e1c5ff4 1680 */
277d58ef 1681int __init omap_gpio_init(void)
5e1c5ff4
TL		 1682{
1683 if (!initialized)
1684 return _omap_gpio_init();
1685 else
1686 return 0;
1687}
1688
92105bb7
TL		 1689static int __init omap_gpio_sysinit(void)
1690{
1691 int ret = 0;
1692
1693 if (!initialized)
1694 ret = _omap_gpio_init();
1695
11a78b79
DB		 1696 mpuio_init();
1697
5492fb1a
SMK		 1698#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1699 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 1700 if (ret == 0) {
1701 ret = sysdev_class_register(&omap_gpio_sysclass);
1702 if (ret == 0)
1703 ret = sysdev_register(&omap_gpio_device);
1704 }
1705 }
1706#endif
1707
1708 return ret;
1709}
1710
92105bb7 1711arch_initcall(omap_gpio_sysinit);
b9772a22
DB		 1712
1713
1714#ifdef CONFIG_DEBUG_FS
1715
1716#include <linux/debugfs.h>
1717#include <linux/seq_file.h>
1718
1719static int gpio_is_input(struct gpio_bank *bank, int mask)
1720{
1721 void __iomem *reg = bank->base;
1722
1723 switch (bank->method) {
1724 case METHOD_MPUIO:
1725 reg += OMAP_MPUIO_IO_CNTL;
1726 break;
1727 case METHOD_GPIO_1510:
1728 reg += OMAP1510_GPIO_DIR_CONTROL;
1729 break;
1730 case METHOD_GPIO_1610:
1731 reg += OMAP1610_GPIO_DIRECTION;
1732 break;
1733 case METHOD_GPIO_730:
1734 reg += OMAP730_GPIO_DIR_CONTROL;
1735 break;
1736 case METHOD_GPIO_24XX:
1737 reg += OMAP24XX_GPIO_OE;
1738 break;
1739 }
1740 return __raw_readl(reg) & mask;
1741}
1742
1743
1744static int dbg_gpio_show(struct seq_file *s, void *unused)
1745{
1746 unsigned i, j, gpio;
1747
1748 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1749 struct gpio_bank *bank = gpio_bank + i;
1750 unsigned bankwidth = 16;
1751 u32 mask = 1;
1752
e5c56ed3 1753 if (bank_is_mpuio(bank))
b9772a22 1754 gpio = OMAP_MPUIO(0);
5492fb1a 1755 else if (cpu_class_is_omap2() || cpu_is_omap730())
b9772a22
DB		 1756 bankwidth = 32;
1757
1758 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1759 unsigned irq, value, is_in, irqstat;
52e31344 1760 const char *label;
b9772a22 1761
52e31344
DB		 1762 label = gpiochip_is_requested(&bank->chip, j);
1763 if (!label)
b9772a22
DB		 1764 continue;
1765
1766 irq = bank->virtual_irq_start + j;
0b84b5ca 1767 value = gpio_get_value(gpio);
b9772a22
DB		 1768 is_in = gpio_is_input(bank, mask);
1769
e5c56ed3 1770 if (bank_is_mpuio(bank))
52e31344 1771 seq_printf(s, "MPUIO %2d ", j);
b9772a22 1772 else
52e31344 1773 seq_printf(s, "GPIO %3d ", gpio);
21c867f1 1774 seq_printf(s, "(%-20.20s): %s %s",
52e31344 1775 label,
b9772a22
DB		 1776 is_in ? "in " : "out",
1777 value ? "hi" : "lo");
1778
52e31344
DB		 1779/* FIXME for at least omap2, show pullup/pulldown state */
1780
b9772a22
DB		 1781 irqstat = irq_desc[irq].status;
1782 if (is_in && ((bank->suspend_wakeup & mask)
1783 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1784 char *trigger = NULL;
1785
1786 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1787 case IRQ_TYPE_EDGE_FALLING:
1788 trigger = "falling";
1789 break;
1790 case IRQ_TYPE_EDGE_RISING:
1791 trigger = "rising";
1792 break;
1793 case IRQ_TYPE_EDGE_BOTH:
1794 trigger = "bothedge";
1795 break;
1796 case IRQ_TYPE_LEVEL_LOW:
1797 trigger = "low";
1798 break;
1799 case IRQ_TYPE_LEVEL_HIGH:
1800 trigger = "high";
1801 break;
1802 case IRQ_TYPE_NONE:
52e31344 1803 trigger = "(?)";
b9772a22
DB		 1804 break;
1805 }
52e31344 1806 seq_printf(s, ", irq-%d %-8s%s",
b9772a22
DB		 1807 irq, trigger,
1808 (bank->suspend_wakeup & mask)
1809 ? " wakeup" : "");
1810 }
1811 seq_printf(s, "\n");
1812 }
1813
e5c56ed3 1814 if (bank_is_mpuio(bank)) {
b9772a22
DB		 1815 seq_printf(s, "\n");
1816 gpio = 0;
1817 }
1818 }
1819 return 0;
1820}
1821
1822static int dbg_gpio_open(struct inode *inode, struct file *file)
1823{
e5c56ed3 1824 return single_open(file, dbg_gpio_show, &inode->i_private);
b9772a22
DB		 1825}
1826
1827static const struct file_operations debug_fops = {
1828 .open = dbg_gpio_open,
1829 .read = seq_read,
1830 .llseek = seq_lseek,
1831 .release = single_release,
1832};
1833
1834static int __init omap_gpio_debuginit(void)
1835{
e5c56ed3
DB		 1836 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1837 NULL, NULL, &debug_fops);
b9772a22
DB		 1838 return 0;
1839}
1840late_initcall(omap_gpio_debuginit);
1841#endif
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