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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/gpio.c | |
3 | * | |
4 | * Support functions for OMAP GPIO | |
5 | * | |
92105bb7 | 6 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 8 | * |
44169075 SS |
9 | * Copyright (C) 2009 Texas Instruments |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
11 | * | |
5e1c5ff4 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
5e1c5ff4 TL |
17 | #include <linux/init.h> |
18 | #include <linux/module.h> | |
5e1c5ff4 | 19 | #include <linux/interrupt.h> |
92105bb7 TL |
20 | #include <linux/sysdev.h> |
21 | #include <linux/err.h> | |
f8ce2547 | 22 | #include <linux/clk.h> |
fced80c7 | 23 | #include <linux/io.h> |
5e1c5ff4 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e1c5ff4 | 26 | #include <asm/irq.h> |
a09e64fb RK |
27 | #include <mach/irqs.h> |
28 | #include <mach/gpio.h> | |
5e1c5ff4 TL |
29 | #include <asm/mach/irq.h> |
30 | ||
5e1c5ff4 TL |
31 | /* |
32 | * OMAP1510 GPIO registers | |
33 | */ | |
9f7065da | 34 | #define OMAP1510_GPIO_BASE 0xfffce000 |
5e1c5ff4 TL |
35 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
36 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | |
37 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | |
38 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | |
39 | #define OMAP1510_GPIO_INT_MASK 0x10 | |
40 | #define OMAP1510_GPIO_INT_STATUS 0x14 | |
41 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | |
42 | ||
43 | #define OMAP1510_IH_GPIO_BASE 64 | |
44 | ||
45 | /* | |
46 | * OMAP1610 specific GPIO registers | |
47 | */ | |
9f7065da TL |
48 | #define OMAP1610_GPIO1_BASE 0xfffbe400 |
49 | #define OMAP1610_GPIO2_BASE 0xfffbec00 | |
50 | #define OMAP1610_GPIO3_BASE 0xfffbb400 | |
51 | #define OMAP1610_GPIO4_BASE 0xfffbbc00 | |
5e1c5ff4 TL |
52 | #define OMAP1610_GPIO_REVISION 0x0000 |
53 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | |
54 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | |
55 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | |
56 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | |
92105bb7 | 57 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 |
5e1c5ff4 TL |
58 | #define OMAP1610_GPIO_DATAIN 0x002c |
59 | #define OMAP1610_GPIO_DATAOUT 0x0030 | |
60 | #define OMAP1610_GPIO_DIRECTION 0x0034 | |
61 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | |
62 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | |
63 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | |
92105bb7 | 64 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 |
5e1c5ff4 TL |
65 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 |
66 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | |
92105bb7 | 67 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 |
5e1c5ff4 TL |
68 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
69 | ||
70 | /* | |
7c006926 | 71 | * OMAP7XX specific GPIO registers |
5e1c5ff4 | 72 | */ |
9f7065da TL |
73 | #define OMAP7XX_GPIO1_BASE 0xfffbc000 |
74 | #define OMAP7XX_GPIO2_BASE 0xfffbc800 | |
75 | #define OMAP7XX_GPIO3_BASE 0xfffbd000 | |
76 | #define OMAP7XX_GPIO4_BASE 0xfffbd800 | |
77 | #define OMAP7XX_GPIO5_BASE 0xfffbe000 | |
78 | #define OMAP7XX_GPIO6_BASE 0xfffbe800 | |
7c006926 AB |
79 | #define OMAP7XX_GPIO_DATA_INPUT 0x00 |
80 | #define OMAP7XX_GPIO_DATA_OUTPUT 0x04 | |
81 | #define OMAP7XX_GPIO_DIR_CONTROL 0x08 | |
82 | #define OMAP7XX_GPIO_INT_CONTROL 0x0c | |
83 | #define OMAP7XX_GPIO_INT_MASK 0x10 | |
84 | #define OMAP7XX_GPIO_INT_STATUS 0x14 | |
5e1c5ff4 | 85 | |
9f7065da | 86 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE |
94113260 | 87 | |
92105bb7 TL |
88 | /* |
89 | * omap24xx specific GPIO registers | |
90 | */ | |
9f7065da TL |
91 | #define OMAP242X_GPIO1_BASE 0x48018000 |
92 | #define OMAP242X_GPIO2_BASE 0x4801a000 | |
93 | #define OMAP242X_GPIO3_BASE 0x4801c000 | |
94 | #define OMAP242X_GPIO4_BASE 0x4801e000 | |
56a25641 | 95 | |
9f7065da TL |
96 | #define OMAP243X_GPIO1_BASE 0x4900C000 |
97 | #define OMAP243X_GPIO2_BASE 0x4900E000 | |
98 | #define OMAP243X_GPIO3_BASE 0x49010000 | |
99 | #define OMAP243X_GPIO4_BASE 0x49012000 | |
100 | #define OMAP243X_GPIO5_BASE 0x480B6000 | |
56a25641 | 101 | |
92105bb7 TL |
102 | #define OMAP24XX_GPIO_REVISION 0x0000 |
103 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | |
104 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | |
105 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | |
bee7930f HD |
106 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
107 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | |
92105bb7 | 108 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c |
723fdb78 | 109 | #define OMAP24XX_GPIO_WAKE_EN 0x0020 |
92105bb7 TL |
110 | #define OMAP24XX_GPIO_CTRL 0x0030 |
111 | #define OMAP24XX_GPIO_OE 0x0034 | |
112 | #define OMAP24XX_GPIO_DATAIN 0x0038 | |
113 | #define OMAP24XX_GPIO_DATAOUT 0x003c | |
114 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | |
115 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | |
116 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | |
117 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | |
5eb3bb9c KH |
118 | #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 |
119 | #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 | |
92105bb7 TL |
120 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 |
121 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | |
122 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | |
123 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | |
124 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | |
125 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | |
126 | ||
78a1a6d3 SR |
127 | #define OMAP4_GPIO_REVISION 0x0000 |
128 | #define OMAP4_GPIO_SYSCONFIG 0x0010 | |
129 | #define OMAP4_GPIO_EOI 0x0020 | |
130 | #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 | |
131 | #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 | |
132 | #define OMAP4_GPIO_IRQSTATUS0 0x002c | |
133 | #define OMAP4_GPIO_IRQSTATUS1 0x0030 | |
134 | #define OMAP4_GPIO_IRQSTATUSSET0 0x0034 | |
135 | #define OMAP4_GPIO_IRQSTATUSSET1 0x0038 | |
136 | #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c | |
137 | #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 | |
138 | #define OMAP4_GPIO_IRQWAKEN0 0x0044 | |
139 | #define OMAP4_GPIO_IRQWAKEN1 0x0048 | |
140 | #define OMAP4_GPIO_SYSSTATUS 0x0104 | |
141 | #define OMAP4_GPIO_CTRL 0x0130 | |
142 | #define OMAP4_GPIO_OE 0x0134 | |
143 | #define OMAP4_GPIO_DATAIN 0x0138 | |
144 | #define OMAP4_GPIO_DATAOUT 0x013c | |
145 | #define OMAP4_GPIO_LEVELDETECT0 0x0140 | |
146 | #define OMAP4_GPIO_LEVELDETECT1 0x0144 | |
147 | #define OMAP4_GPIO_RISINGDETECT 0x0148 | |
148 | #define OMAP4_GPIO_FALLINGDETECT 0x014c | |
149 | #define OMAP4_GPIO_DEBOUNCENABLE 0x0150 | |
150 | #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 | |
151 | #define OMAP4_GPIO_CLEARDATAOUT 0x0190 | |
152 | #define OMAP4_GPIO_SETDATAOUT 0x0194 | |
5492fb1a SMK |
153 | /* |
154 | * omap34xx specific GPIO registers | |
155 | */ | |
156 | ||
9f7065da TL |
157 | #define OMAP34XX_GPIO1_BASE 0x48310000 |
158 | #define OMAP34XX_GPIO2_BASE 0x49050000 | |
159 | #define OMAP34XX_GPIO3_BASE 0x49052000 | |
160 | #define OMAP34XX_GPIO4_BASE 0x49054000 | |
161 | #define OMAP34XX_GPIO5_BASE 0x49056000 | |
162 | #define OMAP34XX_GPIO6_BASE 0x49058000 | |
5492fb1a | 163 | |
44169075 SS |
164 | /* |
165 | * OMAP44XX specific GPIO registers | |
166 | */ | |
9f7065da TL |
167 | #define OMAP44XX_GPIO1_BASE 0x4a310000 |
168 | #define OMAP44XX_GPIO2_BASE 0x48055000 | |
169 | #define OMAP44XX_GPIO3_BASE 0x48057000 | |
170 | #define OMAP44XX_GPIO4_BASE 0x48059000 | |
171 | #define OMAP44XX_GPIO5_BASE 0x4805B000 | |
172 | #define OMAP44XX_GPIO6_BASE 0x4805D000 | |
5492fb1a | 173 | |
5e1c5ff4 | 174 | struct gpio_bank { |
9f7065da | 175 | unsigned long pbase; |
92105bb7 | 176 | void __iomem *base; |
5e1c5ff4 TL |
177 | u16 irq; |
178 | u16 virtual_irq_start; | |
92105bb7 | 179 | int method; |
44169075 SS |
180 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ |
181 | defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) | |
92105bb7 TL |
182 | u32 suspend_wakeup; |
183 | u32 saved_wakeup; | |
3ac4fa99 | 184 | #endif |
44169075 SS |
185 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
186 | defined(CONFIG_ARCH_OMAP4) | |
3ac4fa99 JY |
187 | u32 non_wakeup_gpios; |
188 | u32 enabled_non_wakeup_gpios; | |
189 | ||
190 | u32 saved_datain; | |
191 | u32 saved_fallingdetect; | |
192 | u32 saved_risingdetect; | |
193 | #endif | |
b144ff6f | 194 | u32 level_mask; |
5e1c5ff4 | 195 | spinlock_t lock; |
52e31344 | 196 | struct gpio_chip chip; |
89db9482 | 197 | struct clk *dbck; |
058af1ea | 198 | u32 mod_usage; |
5e1c5ff4 TL |
199 | }; |
200 | ||
201 | #define METHOD_MPUIO 0 | |
202 | #define METHOD_GPIO_1510 1 | |
203 | #define METHOD_GPIO_1610 2 | |
7c006926 | 204 | #define METHOD_GPIO_7XX 3 |
56739a69 | 205 | #define METHOD_GPIO_24XX 5 |
5e1c5ff4 | 206 | |
92105bb7 | 207 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 208 | static struct gpio_bank gpio_bank_1610[5] = { |
9f7065da TL |
209 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, |
210 | METHOD_MPUIO }, | |
211 | { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | |
212 | METHOD_GPIO_1610 }, | |
213 | { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, | |
214 | METHOD_GPIO_1610 }, | |
215 | { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, | |
216 | METHOD_GPIO_1610 }, | |
217 | { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, | |
218 | METHOD_GPIO_1610 }, | |
5e1c5ff4 TL |
219 | }; |
220 | #endif | |
221 | ||
1a8bfa1e | 222 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 223 | static struct gpio_bank gpio_bank_1510[2] = { |
9f7065da TL |
224 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, |
225 | METHOD_MPUIO }, | |
226 | { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | |
227 | METHOD_GPIO_1510 } | |
5e1c5ff4 TL |
228 | }; |
229 | #endif | |
230 | ||
b718aa81 | 231 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 | 232 | static struct gpio_bank gpio_bank_7xx[7] = { |
9f7065da TL |
233 | { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE, |
234 | METHOD_MPUIO }, | |
235 | { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, | |
236 | METHOD_GPIO_7XX }, | |
237 | { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
238 | METHOD_GPIO_7XX }, | |
239 | { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
240 | METHOD_GPIO_7XX }, | |
241 | { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
242 | METHOD_GPIO_7XX }, | |
243 | { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
244 | METHOD_GPIO_7XX }, | |
245 | { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, | |
246 | METHOD_GPIO_7XX }, | |
5e1c5ff4 TL |
247 | }; |
248 | #endif | |
249 | ||
92105bb7 | 250 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 SMK |
251 | |
252 | static struct gpio_bank gpio_bank_242x[4] = { | |
9f7065da TL |
253 | { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
254 | METHOD_GPIO_24XX }, | |
255 | { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
256 | METHOD_GPIO_24XX }, | |
257 | { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
258 | METHOD_GPIO_24XX }, | |
259 | { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
260 | METHOD_GPIO_24XX }, | |
92105bb7 | 261 | }; |
56a25641 SMK |
262 | |
263 | static struct gpio_bank gpio_bank_243x[5] = { | |
9f7065da TL |
264 | { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
265 | METHOD_GPIO_24XX }, | |
266 | { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
267 | METHOD_GPIO_24XX }, | |
268 | { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
269 | METHOD_GPIO_24XX }, | |
270 | { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
271 | METHOD_GPIO_24XX }, | |
272 | { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
273 | METHOD_GPIO_24XX }, | |
56a25641 SMK |
274 | }; |
275 | ||
92105bb7 TL |
276 | #endif |
277 | ||
5492fb1a SMK |
278 | #ifdef CONFIG_ARCH_OMAP34XX |
279 | static struct gpio_bank gpio_bank_34xx[6] = { | |
9f7065da TL |
280 | { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, |
281 | METHOD_GPIO_24XX }, | |
282 | { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
283 | METHOD_GPIO_24XX }, | |
284 | { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
285 | METHOD_GPIO_24XX }, | |
286 | { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
287 | METHOD_GPIO_24XX }, | |
288 | { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
289 | METHOD_GPIO_24XX }, | |
290 | { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, | |
291 | METHOD_GPIO_24XX }, | |
5492fb1a SMK |
292 | }; |
293 | ||
40c670f0 RN |
294 | struct omap3_gpio_regs { |
295 | u32 sysconfig; | |
296 | u32 irqenable1; | |
297 | u32 irqenable2; | |
298 | u32 wake_en; | |
299 | u32 ctrl; | |
300 | u32 oe; | |
301 | u32 leveldetect0; | |
302 | u32 leveldetect1; | |
303 | u32 risingdetect; | |
304 | u32 fallingdetect; | |
305 | u32 dataout; | |
306 | u32 setwkuena; | |
307 | u32 setdataout; | |
5492fb1a SMK |
308 | }; |
309 | ||
40c670f0 | 310 | static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; |
5492fb1a SMK |
311 | #endif |
312 | ||
44169075 SS |
313 | #ifdef CONFIG_ARCH_OMAP4 |
314 | static struct gpio_bank gpio_bank_44xx[6] = { | |
9f7065da | 315 | { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, |
44169075 | 316 | METHOD_GPIO_24XX }, |
9f7065da | 317 | { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, |
44169075 | 318 | METHOD_GPIO_24XX }, |
9f7065da | 319 | { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, |
44169075 | 320 | METHOD_GPIO_24XX }, |
9f7065da | 321 | { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, |
44169075 | 322 | METHOD_GPIO_24XX }, |
9f7065da | 323 | { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, |
44169075 | 324 | METHOD_GPIO_24XX }, |
9f7065da | 325 | { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, |
44169075 SS |
326 | METHOD_GPIO_24XX }, |
327 | }; | |
328 | ||
329 | #endif | |
330 | ||
5e1c5ff4 TL |
331 | static struct gpio_bank *gpio_bank; |
332 | static int gpio_bank_count; | |
333 | ||
334 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
335 | { | |
6e60e79a | 336 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
337 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
338 | return &gpio_bank[0]; | |
339 | return &gpio_bank[1]; | |
340 | } | |
5e1c5ff4 TL |
341 | if (cpu_is_omap16xx()) { |
342 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
343 | return &gpio_bank[0]; | |
344 | return &gpio_bank[1 + (gpio >> 4)]; | |
345 | } | |
56739a69 | 346 | if (cpu_is_omap7xx()) { |
5e1c5ff4 TL |
347 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
348 | return &gpio_bank[0]; | |
349 | return &gpio_bank[1 + (gpio >> 5)]; | |
350 | } | |
92105bb7 TL |
351 | if (cpu_is_omap24xx()) |
352 | return &gpio_bank[gpio >> 5]; | |
44169075 | 353 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 354 | return &gpio_bank[gpio >> 5]; |
e031ab23 DB |
355 | BUG(); |
356 | return NULL; | |
5e1c5ff4 TL |
357 | } |
358 | ||
359 | static inline int get_gpio_index(int gpio) | |
360 | { | |
56739a69 | 361 | if (cpu_is_omap7xx()) |
5e1c5ff4 | 362 | return gpio & 0x1f; |
92105bb7 TL |
363 | if (cpu_is_omap24xx()) |
364 | return gpio & 0x1f; | |
44169075 | 365 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 366 | return gpio & 0x1f; |
92105bb7 | 367 | return gpio & 0x0f; |
5e1c5ff4 TL |
368 | } |
369 | ||
370 | static inline int gpio_valid(int gpio) | |
371 | { | |
372 | if (gpio < 0) | |
373 | return -1; | |
d11ac979 | 374 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 375 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
376 | return -1; |
377 | return 0; | |
378 | } | |
6e60e79a | 379 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 380 | return 0; |
5e1c5ff4 TL |
381 | if ((cpu_is_omap16xx()) && gpio < 64) |
382 | return 0; | |
56739a69 | 383 | if (cpu_is_omap7xx() && gpio < 192) |
5e1c5ff4 | 384 | return 0; |
92105bb7 TL |
385 | if (cpu_is_omap24xx() && gpio < 128) |
386 | return 0; | |
44169075 | 387 | if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) |
5492fb1a | 388 | return 0; |
5e1c5ff4 TL |
389 | return -1; |
390 | } | |
391 | ||
392 | static int check_gpio(int gpio) | |
393 | { | |
d32b20fc | 394 | if (unlikely(gpio_valid(gpio) < 0)) { |
5e1c5ff4 TL |
395 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); |
396 | dump_stack(); | |
397 | return -1; | |
398 | } | |
399 | return 0; | |
400 | } | |
401 | ||
402 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
403 | { | |
92105bb7 | 404 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
405 | u32 l; |
406 | ||
407 | switch (bank->method) { | |
e5c56ed3 | 408 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
409 | case METHOD_MPUIO: |
410 | reg += OMAP_MPUIO_IO_CNTL; | |
411 | break; | |
e5c56ed3 DB |
412 | #endif |
413 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
414 | case METHOD_GPIO_1510: |
415 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
416 | break; | |
e5c56ed3 DB |
417 | #endif |
418 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
419 | case METHOD_GPIO_1610: |
420 | reg += OMAP1610_GPIO_DIRECTION; | |
421 | break; | |
e5c56ed3 | 422 | #endif |
b718aa81 | 423 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
424 | case METHOD_GPIO_7XX: |
425 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
56739a69 ZM |
426 | break; |
427 | #endif | |
78a1a6d3 | 428 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
429 | case METHOD_GPIO_24XX: |
430 | reg += OMAP24XX_GPIO_OE; | |
431 | break; | |
78a1a6d3 SR |
432 | #endif |
433 | #if defined(CONFIG_ARCH_OMAP4) | |
434 | case METHOD_GPIO_24XX: | |
435 | reg += OMAP4_GPIO_OE; | |
436 | break; | |
e5c56ed3 DB |
437 | #endif |
438 | default: | |
439 | WARN_ON(1); | |
440 | return; | |
5e1c5ff4 TL |
441 | } |
442 | l = __raw_readl(reg); | |
443 | if (is_input) | |
444 | l |= 1 << gpio; | |
445 | else | |
446 | l &= ~(1 << gpio); | |
447 | __raw_writel(l, reg); | |
448 | } | |
449 | ||
5e1c5ff4 TL |
450 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) |
451 | { | |
92105bb7 | 452 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
453 | u32 l = 0; |
454 | ||
455 | switch (bank->method) { | |
e5c56ed3 | 456 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
457 | case METHOD_MPUIO: |
458 | reg += OMAP_MPUIO_OUTPUT; | |
459 | l = __raw_readl(reg); | |
460 | if (enable) | |
461 | l |= 1 << gpio; | |
462 | else | |
463 | l &= ~(1 << gpio); | |
464 | break; | |
e5c56ed3 DB |
465 | #endif |
466 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
467 | case METHOD_GPIO_1510: |
468 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
469 | l = __raw_readl(reg); | |
470 | if (enable) | |
471 | l |= 1 << gpio; | |
472 | else | |
473 | l &= ~(1 << gpio); | |
474 | break; | |
e5c56ed3 DB |
475 | #endif |
476 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
477 | case METHOD_GPIO_1610: |
478 | if (enable) | |
479 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
480 | else | |
481 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
482 | l = 1 << gpio; | |
483 | break; | |
e5c56ed3 | 484 | #endif |
b718aa81 | 485 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
486 | case METHOD_GPIO_7XX: |
487 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
56739a69 ZM |
488 | l = __raw_readl(reg); |
489 | if (enable) | |
490 | l |= 1 << gpio; | |
491 | else | |
492 | l &= ~(1 << gpio); | |
493 | break; | |
494 | #endif | |
78a1a6d3 | 495 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
496 | case METHOD_GPIO_24XX: |
497 | if (enable) | |
498 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
499 | else | |
500 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
501 | l = 1 << gpio; | |
502 | break; | |
78a1a6d3 SR |
503 | #endif |
504 | #ifdef CONFIG_ARCH_OMAP4 | |
505 | case METHOD_GPIO_24XX: | |
506 | if (enable) | |
507 | reg += OMAP4_GPIO_SETDATAOUT; | |
508 | else | |
509 | reg += OMAP4_GPIO_CLEARDATAOUT; | |
510 | l = 1 << gpio; | |
511 | break; | |
e5c56ed3 | 512 | #endif |
5e1c5ff4 | 513 | default: |
e5c56ed3 | 514 | WARN_ON(1); |
5e1c5ff4 TL |
515 | return; |
516 | } | |
517 | __raw_writel(l, reg); | |
518 | } | |
519 | ||
b37c45b8 | 520 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
5e1c5ff4 | 521 | { |
92105bb7 | 522 | void __iomem *reg; |
5e1c5ff4 TL |
523 | |
524 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 525 | return -EINVAL; |
5e1c5ff4 TL |
526 | reg = bank->base; |
527 | switch (bank->method) { | |
e5c56ed3 | 528 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
529 | case METHOD_MPUIO: |
530 | reg += OMAP_MPUIO_INPUT_LATCH; | |
531 | break; | |
e5c56ed3 DB |
532 | #endif |
533 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
534 | case METHOD_GPIO_1510: |
535 | reg += OMAP1510_GPIO_DATA_INPUT; | |
536 | break; | |
e5c56ed3 DB |
537 | #endif |
538 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
539 | case METHOD_GPIO_1610: |
540 | reg += OMAP1610_GPIO_DATAIN; | |
541 | break; | |
e5c56ed3 | 542 | #endif |
b718aa81 | 543 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
544 | case METHOD_GPIO_7XX: |
545 | reg += OMAP7XX_GPIO_DATA_INPUT; | |
56739a69 ZM |
546 | break; |
547 | #endif | |
78a1a6d3 | 548 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
549 | case METHOD_GPIO_24XX: |
550 | reg += OMAP24XX_GPIO_DATAIN; | |
551 | break; | |
78a1a6d3 SR |
552 | #endif |
553 | #ifdef CONFIG_ARCH_OMAP4 | |
554 | case METHOD_GPIO_24XX: | |
555 | reg += OMAP4_GPIO_DATAIN; | |
556 | break; | |
e5c56ed3 | 557 | #endif |
5e1c5ff4 | 558 | default: |
e5c56ed3 | 559 | return -EINVAL; |
5e1c5ff4 | 560 | } |
92105bb7 TL |
561 | return (__raw_readl(reg) |
562 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
563 | } |
564 | ||
b37c45b8 RQ |
565 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
566 | { | |
567 | void __iomem *reg; | |
568 | ||
569 | if (check_gpio(gpio) < 0) | |
570 | return -EINVAL; | |
571 | reg = bank->base; | |
572 | ||
573 | switch (bank->method) { | |
574 | #ifdef CONFIG_ARCH_OMAP1 | |
575 | case METHOD_MPUIO: | |
576 | reg += OMAP_MPUIO_OUTPUT; | |
577 | break; | |
578 | #endif | |
579 | #ifdef CONFIG_ARCH_OMAP15XX | |
580 | case METHOD_GPIO_1510: | |
581 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
582 | break; | |
583 | #endif | |
584 | #ifdef CONFIG_ARCH_OMAP16XX | |
585 | case METHOD_GPIO_1610: | |
586 | reg += OMAP1610_GPIO_DATAOUT; | |
587 | break; | |
588 | #endif | |
b718aa81 | 589 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
590 | case METHOD_GPIO_7XX: |
591 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
b37c45b8 RQ |
592 | break; |
593 | #endif | |
594 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | |
595 | defined(CONFIG_ARCH_OMAP4) | |
596 | case METHOD_GPIO_24XX: | |
597 | reg += OMAP24XX_GPIO_DATAOUT; | |
598 | break; | |
599 | #endif | |
600 | default: | |
601 | return -EINVAL; | |
602 | } | |
603 | ||
604 | return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; | |
605 | } | |
606 | ||
92105bb7 TL |
607 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
608 | do { \ | |
609 | int l = __raw_readl(base + reg); \ | |
610 | if (set) l |= bit_mask; \ | |
611 | else l &= ~bit_mask; \ | |
612 | __raw_writel(l, base + reg); \ | |
613 | } while(0) | |
614 | ||
5eb3bb9c KH |
615 | void omap_set_gpio_debounce(int gpio, int enable) |
616 | { | |
617 | struct gpio_bank *bank; | |
618 | void __iomem *reg; | |
e031ab23 | 619 | unsigned long flags; |
5eb3bb9c KH |
620 | u32 val, l = 1 << get_gpio_index(gpio); |
621 | ||
622 | if (cpu_class_is_omap1()) | |
623 | return; | |
624 | ||
625 | bank = get_gpio_bank(gpio); | |
626 | reg = bank->base; | |
78a1a6d3 SR |
627 | #ifdef CONFIG_ARCH_OMAP4 |
628 | reg += OMAP4_GPIO_DEBOUNCENABLE; | |
629 | #else | |
5eb3bb9c | 630 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; |
78a1a6d3 | 631 | #endif |
058af1ea C |
632 | if (!(bank->mod_usage & l)) { |
633 | printk(KERN_ERR "GPIO %d not requested\n", gpio); | |
634 | return; | |
635 | } | |
e031ab23 DB |
636 | |
637 | spin_lock_irqsave(&bank->lock, flags); | |
5eb3bb9c KH |
638 | val = __raw_readl(reg); |
639 | ||
89db9482 | 640 | if (enable && !(val & l)) |
5eb3bb9c | 641 | val |= l; |
e031ab23 | 642 | else if (!enable && (val & l)) |
5eb3bb9c | 643 | val &= ~l; |
89db9482 | 644 | else |
e031ab23 | 645 | goto done; |
89db9482 | 646 | |
44169075 | 647 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
e031ab23 DB |
648 | if (enable) |
649 | clk_enable(bank->dbck); | |
650 | else | |
651 | clk_disable(bank->dbck); | |
652 | } | |
5eb3bb9c KH |
653 | |
654 | __raw_writel(val, reg); | |
e031ab23 DB |
655 | done: |
656 | spin_unlock_irqrestore(&bank->lock, flags); | |
5eb3bb9c KH |
657 | } |
658 | EXPORT_SYMBOL(omap_set_gpio_debounce); | |
659 | ||
660 | void omap_set_gpio_debounce_time(int gpio, int enc_time) | |
661 | { | |
662 | struct gpio_bank *bank; | |
663 | void __iomem *reg; | |
664 | ||
665 | if (cpu_class_is_omap1()) | |
666 | return; | |
667 | ||
668 | bank = get_gpio_bank(gpio); | |
669 | reg = bank->base; | |
670 | ||
058af1ea C |
671 | if (!bank->mod_usage) { |
672 | printk(KERN_ERR "GPIO not requested\n"); | |
673 | return; | |
674 | } | |
675 | ||
5eb3bb9c | 676 | enc_time &= 0xff; |
78a1a6d3 SR |
677 | #ifdef CONFIG_ARCH_OMAP4 |
678 | reg += OMAP4_GPIO_DEBOUNCINGTIME; | |
679 | #else | |
5eb3bb9c | 680 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; |
78a1a6d3 | 681 | #endif |
5eb3bb9c KH |
682 | __raw_writel(enc_time, reg); |
683 | } | |
684 | EXPORT_SYMBOL(omap_set_gpio_debounce_time); | |
685 | ||
44169075 SS |
686 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
687 | defined(CONFIG_ARCH_OMAP4) | |
5eb3bb9c KH |
688 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
689 | int trigger) | |
5e1c5ff4 | 690 | { |
3ac4fa99 | 691 | void __iomem *base = bank->base; |
92105bb7 | 692 | u32 gpio_bit = 1 << gpio; |
78a1a6d3 | 693 | u32 val; |
92105bb7 | 694 | |
78a1a6d3 SR |
695 | if (cpu_is_omap44xx()) { |
696 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit, | |
697 | trigger & IRQ_TYPE_LEVEL_LOW); | |
698 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit, | |
699 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
700 | MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit, | |
701 | trigger & IRQ_TYPE_EDGE_RISING); | |
702 | MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit, | |
703 | trigger & IRQ_TYPE_EDGE_FALLING); | |
704 | } else { | |
705 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
706 | trigger & IRQ_TYPE_LEVEL_LOW); | |
707 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, | |
708 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
709 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, | |
710 | trigger & IRQ_TYPE_EDGE_RISING); | |
711 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, | |
712 | trigger & IRQ_TYPE_EDGE_FALLING); | |
713 | } | |
3ac4fa99 | 714 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
78a1a6d3 SR |
715 | if (cpu_is_omap44xx()) { |
716 | if (trigger != 0) | |
717 | __raw_writel(1 << gpio, bank->base+ | |
718 | OMAP4_GPIO_IRQWAKEN0); | |
719 | else { | |
720 | val = __raw_readl(bank->base + | |
721 | OMAP4_GPIO_IRQWAKEN0); | |
722 | __raw_writel(val & (~(1 << gpio)), bank->base + | |
723 | OMAP4_GPIO_IRQWAKEN0); | |
724 | } | |
725 | } else { | |
726 | if (trigger != 0) | |
727 | __raw_writel(1 << gpio, bank->base | |
5eb3bb9c | 728 | + OMAP24XX_GPIO_SETWKUENA); |
78a1a6d3 SR |
729 | else |
730 | __raw_writel(1 << gpio, bank->base | |
5eb3bb9c | 731 | + OMAP24XX_GPIO_CLEARWKUENA); |
78a1a6d3 | 732 | } |
3ac4fa99 JY |
733 | } else { |
734 | if (trigger != 0) | |
735 | bank->enabled_non_wakeup_gpios |= gpio_bit; | |
736 | else | |
737 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
738 | } | |
5eb3bb9c | 739 | |
78a1a6d3 SR |
740 | if (cpu_is_omap44xx()) { |
741 | bank->level_mask = | |
742 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | | |
743 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); | |
744 | } else { | |
745 | bank->level_mask = | |
746 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
747 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
748 | } | |
92105bb7 | 749 | } |
3ac4fa99 | 750 | #endif |
92105bb7 TL |
751 | |
752 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |
753 | { | |
754 | void __iomem *reg = bank->base; | |
755 | u32 l = 0; | |
5e1c5ff4 TL |
756 | |
757 | switch (bank->method) { | |
e5c56ed3 | 758 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
759 | case METHOD_MPUIO: |
760 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
761 | l = __raw_readl(reg); | |
6cab4860 | 762 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 763 | l |= 1 << gpio; |
6cab4860 | 764 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 765 | l &= ~(1 << gpio); |
92105bb7 TL |
766 | else |
767 | goto bad; | |
5e1c5ff4 | 768 | break; |
e5c56ed3 DB |
769 | #endif |
770 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
771 | case METHOD_GPIO_1510: |
772 | reg += OMAP1510_GPIO_INT_CONTROL; | |
773 | l = __raw_readl(reg); | |
6cab4860 | 774 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 775 | l |= 1 << gpio; |
6cab4860 | 776 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 777 | l &= ~(1 << gpio); |
92105bb7 TL |
778 | else |
779 | goto bad; | |
5e1c5ff4 | 780 | break; |
e5c56ed3 | 781 | #endif |
3ac4fa99 | 782 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 783 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
784 | if (gpio & 0x08) |
785 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
786 | else | |
787 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
788 | gpio &= 0x07; | |
789 | l = __raw_readl(reg); | |
790 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 791 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 792 | l |= 2 << (gpio << 1); |
6cab4860 | 793 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 794 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
795 | if (trigger) |
796 | /* Enable wake-up during idle for dynamic tick */ | |
797 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
798 | else | |
799 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 800 | break; |
3ac4fa99 | 801 | #endif |
b718aa81 | 802 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
803 | case METHOD_GPIO_7XX: |
804 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
56739a69 ZM |
805 | l = __raw_readl(reg); |
806 | if (trigger & IRQ_TYPE_EDGE_RISING) | |
807 | l |= 1 << gpio; | |
808 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | |
809 | l &= ~(1 << gpio); | |
810 | else | |
811 | goto bad; | |
812 | break; | |
813 | #endif | |
44169075 SS |
814 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
815 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 | 816 | case METHOD_GPIO_24XX: |
3ac4fa99 | 817 | set_24xx_gpio_triggering(bank, gpio, trigger); |
5e1c5ff4 | 818 | break; |
3ac4fa99 | 819 | #endif |
5e1c5ff4 | 820 | default: |
92105bb7 | 821 | goto bad; |
5e1c5ff4 | 822 | } |
92105bb7 TL |
823 | __raw_writel(l, reg); |
824 | return 0; | |
825 | bad: | |
826 | return -EINVAL; | |
5e1c5ff4 TL |
827 | } |
828 | ||
92105bb7 | 829 | static int gpio_irq_type(unsigned irq, unsigned type) |
5e1c5ff4 TL |
830 | { |
831 | struct gpio_bank *bank; | |
92105bb7 TL |
832 | unsigned gpio; |
833 | int retval; | |
a6472533 | 834 | unsigned long flags; |
92105bb7 | 835 | |
5492fb1a | 836 | if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) |
92105bb7 TL |
837 | gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); |
838 | else | |
839 | gpio = irq - IH_GPIO_BASE; | |
5e1c5ff4 TL |
840 | |
841 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
842 | return -EINVAL; |
843 | ||
e5c56ed3 | 844 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 845 | return -EINVAL; |
e5c56ed3 DB |
846 | |
847 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 848 | if (!cpu_class_is_omap2() |
e5c56ed3 | 849 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
850 | return -EINVAL; |
851 | ||
58781016 | 852 | bank = get_irq_chip_data(irq); |
a6472533 | 853 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 854 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
b9772a22 DB |
855 | if (retval == 0) { |
856 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
857 | irq_desc[irq].status |= type; | |
858 | } | |
a6472533 | 859 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
860 | |
861 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
862 | __set_irq_handler_unlocked(irq, handle_level_irq); | |
863 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
864 | __set_irq_handler_unlocked(irq, handle_edge_irq); | |
865 | ||
92105bb7 | 866 | return retval; |
5e1c5ff4 TL |
867 | } |
868 | ||
869 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
870 | { | |
92105bb7 | 871 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
872 | |
873 | switch (bank->method) { | |
e5c56ed3 | 874 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
875 | case METHOD_MPUIO: |
876 | /* MPUIO irqstatus is reset by reading the status register, | |
877 | * so do nothing here */ | |
878 | return; | |
e5c56ed3 DB |
879 | #endif |
880 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
881 | case METHOD_GPIO_1510: |
882 | reg += OMAP1510_GPIO_INT_STATUS; | |
883 | break; | |
e5c56ed3 DB |
884 | #endif |
885 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
886 | case METHOD_GPIO_1610: |
887 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
888 | break; | |
e5c56ed3 | 889 | #endif |
b718aa81 | 890 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
891 | case METHOD_GPIO_7XX: |
892 | reg += OMAP7XX_GPIO_INT_STATUS; | |
56739a69 ZM |
893 | break; |
894 | #endif | |
78a1a6d3 | 895 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
896 | case METHOD_GPIO_24XX: |
897 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
898 | break; | |
78a1a6d3 SR |
899 | #endif |
900 | #if defined(CONFIG_ARCH_OMAP4) | |
901 | case METHOD_GPIO_24XX: | |
902 | reg += OMAP4_GPIO_IRQSTATUS0; | |
903 | break; | |
e5c56ed3 | 904 | #endif |
5e1c5ff4 | 905 | default: |
e5c56ed3 | 906 | WARN_ON(1); |
5e1c5ff4 TL |
907 | return; |
908 | } | |
909 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
910 | |
911 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
5492fb1a | 912 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
bedfd154 | 913 | reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; |
78a1a6d3 SR |
914 | #endif |
915 | #if defined(CONFIG_ARCH_OMAP4) | |
916 | reg = bank->base + OMAP4_GPIO_IRQSTATUS1; | |
917 | #endif | |
918 | if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
bedfd154 RQ |
919 | __raw_writel(gpio_mask, reg); |
920 | ||
921 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
922 | __raw_readl(reg); | |
78a1a6d3 | 923 | } |
5e1c5ff4 TL |
924 | } |
925 | ||
926 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
927 | { | |
928 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
929 | } | |
930 | ||
ea6dedd7 ID |
931 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
932 | { | |
933 | void __iomem *reg = bank->base; | |
99c47707 ID |
934 | int inv = 0; |
935 | u32 l; | |
936 | u32 mask; | |
ea6dedd7 ID |
937 | |
938 | switch (bank->method) { | |
e5c56ed3 | 939 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 ID |
940 | case METHOD_MPUIO: |
941 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
99c47707 ID |
942 | mask = 0xffff; |
943 | inv = 1; | |
ea6dedd7 | 944 | break; |
e5c56ed3 DB |
945 | #endif |
946 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
947 | case METHOD_GPIO_1510: |
948 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
949 | mask = 0xffff; |
950 | inv = 1; | |
ea6dedd7 | 951 | break; |
e5c56ed3 DB |
952 | #endif |
953 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
954 | case METHOD_GPIO_1610: |
955 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 956 | mask = 0xffff; |
ea6dedd7 | 957 | break; |
e5c56ed3 | 958 | #endif |
b718aa81 | 959 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
960 | case METHOD_GPIO_7XX: |
961 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
962 | mask = 0xffffffff; |
963 | inv = 1; | |
964 | break; | |
965 | #endif | |
78a1a6d3 | 966 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
ea6dedd7 ID |
967 | case METHOD_GPIO_24XX: |
968 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 969 | mask = 0xffffffff; |
ea6dedd7 | 970 | break; |
78a1a6d3 SR |
971 | #endif |
972 | #if defined(CONFIG_ARCH_OMAP4) | |
973 | case METHOD_GPIO_24XX: | |
974 | reg += OMAP4_GPIO_IRQSTATUSSET0; | |
975 | mask = 0xffffffff; | |
976 | break; | |
e5c56ed3 | 977 | #endif |
ea6dedd7 | 978 | default: |
e5c56ed3 | 979 | WARN_ON(1); |
ea6dedd7 ID |
980 | return 0; |
981 | } | |
982 | ||
99c47707 ID |
983 | l = __raw_readl(reg); |
984 | if (inv) | |
985 | l = ~l; | |
986 | l &= mask; | |
987 | return l; | |
ea6dedd7 ID |
988 | } |
989 | ||
5e1c5ff4 TL |
990 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
991 | { | |
92105bb7 | 992 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
993 | u32 l; |
994 | ||
995 | switch (bank->method) { | |
e5c56ed3 | 996 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
997 | case METHOD_MPUIO: |
998 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
999 | l = __raw_readl(reg); | |
1000 | if (enable) | |
1001 | l &= ~(gpio_mask); | |
1002 | else | |
1003 | l |= gpio_mask; | |
1004 | break; | |
e5c56ed3 DB |
1005 | #endif |
1006 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
1007 | case METHOD_GPIO_1510: |
1008 | reg += OMAP1510_GPIO_INT_MASK; | |
1009 | l = __raw_readl(reg); | |
1010 | if (enable) | |
1011 | l &= ~(gpio_mask); | |
1012 | else | |
1013 | l |= gpio_mask; | |
1014 | break; | |
e5c56ed3 DB |
1015 | #endif |
1016 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
1017 | case METHOD_GPIO_1610: |
1018 | if (enable) | |
1019 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
1020 | else | |
1021 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
1022 | l = gpio_mask; | |
1023 | break; | |
e5c56ed3 | 1024 | #endif |
b718aa81 | 1025 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1026 | case METHOD_GPIO_7XX: |
1027 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
1028 | l = __raw_readl(reg); |
1029 | if (enable) | |
1030 | l &= ~(gpio_mask); | |
1031 | else | |
1032 | l |= gpio_mask; | |
1033 | break; | |
1034 | #endif | |
78a1a6d3 | 1035 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1036 | case METHOD_GPIO_24XX: |
1037 | if (enable) | |
1038 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
1039 | else | |
1040 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
1041 | l = gpio_mask; | |
1042 | break; | |
78a1a6d3 SR |
1043 | #endif |
1044 | #ifdef CONFIG_ARCH_OMAP4 | |
1045 | case METHOD_GPIO_24XX: | |
1046 | if (enable) | |
1047 | reg += OMAP4_GPIO_IRQSTATUSSET0; | |
1048 | else | |
1049 | reg += OMAP4_GPIO_IRQSTATUSCLR0; | |
1050 | l = gpio_mask; | |
1051 | break; | |
e5c56ed3 | 1052 | #endif |
5e1c5ff4 | 1053 | default: |
e5c56ed3 | 1054 | WARN_ON(1); |
5e1c5ff4 TL |
1055 | return; |
1056 | } | |
1057 | __raw_writel(l, reg); | |
1058 | } | |
1059 | ||
1060 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
1061 | { | |
1062 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
1063 | } | |
1064 | ||
92105bb7 TL |
1065 | /* |
1066 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
1067 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
1068 | * to the target, system will wake up always on GPIO events. While | |
1069 | * system is running all registered GPIO interrupts need to have wake-up | |
1070 | * enabled. When system is suspended, only selected GPIO interrupts need | |
1071 | * to have wake-up enabled. | |
1072 | */ | |
1073 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
1074 | { | |
a6472533 DB |
1075 | unsigned long flags; |
1076 | ||
92105bb7 | 1077 | switch (bank->method) { |
3ac4fa99 | 1078 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 1079 | case METHOD_MPUIO: |
92105bb7 | 1080 | case METHOD_GPIO_1610: |
a6472533 | 1081 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 1082 | if (enable) |
92105bb7 | 1083 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 1084 | else |
92105bb7 | 1085 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 1086 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1087 | return 0; |
3ac4fa99 | 1088 | #endif |
44169075 SS |
1089 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1090 | defined(CONFIG_ARCH_OMAP4) | |
3ac4fa99 | 1091 | case METHOD_GPIO_24XX: |
11a78b79 DB |
1092 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
1093 | printk(KERN_ERR "Unable to modify wakeup on " | |
1094 | "non-wakeup GPIO%d\n", | |
1095 | (bank - gpio_bank) * 32 + gpio); | |
1096 | return -EINVAL; | |
1097 | } | |
a6472533 | 1098 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 1099 | if (enable) |
3ac4fa99 | 1100 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 1101 | else |
3ac4fa99 | 1102 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 1103 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
1104 | return 0; |
1105 | #endif | |
92105bb7 TL |
1106 | default: |
1107 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
1108 | bank->method); | |
1109 | return -EINVAL; | |
1110 | } | |
1111 | } | |
1112 | ||
4196dd6b TL |
1113 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
1114 | { | |
1115 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
1116 | _set_gpio_irqenable(bank, gpio, 0); | |
1117 | _clear_gpio_irqstatus(bank, gpio); | |
6cab4860 | 1118 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
1119 | } |
1120 | ||
92105bb7 TL |
1121 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
1122 | static int gpio_wake_enable(unsigned int irq, unsigned int enable) | |
1123 | { | |
1124 | unsigned int gpio = irq - IH_GPIO_BASE; | |
1125 | struct gpio_bank *bank; | |
1126 | int retval; | |
1127 | ||
1128 | if (check_gpio(gpio) < 0) | |
1129 | return -ENODEV; | |
58781016 | 1130 | bank = get_irq_chip_data(irq); |
92105bb7 | 1131 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
1132 | |
1133 | return retval; | |
1134 | } | |
1135 | ||
3ff164e1 | 1136 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1137 | { |
3ff164e1 | 1138 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1139 | unsigned long flags; |
52e31344 | 1140 | |
a6472533 | 1141 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 1142 | |
4196dd6b TL |
1143 | /* Set trigger to none. You need to enable the desired trigger with |
1144 | * request_irq() or set_irq_type(). | |
1145 | */ | |
3ff164e1 | 1146 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 1147 | |
1a8bfa1e | 1148 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 1149 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 1150 | void __iomem *reg; |
5e1c5ff4 | 1151 | |
92105bb7 | 1152 | /* Claim the pin for MPU */ |
5e1c5ff4 | 1153 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 1154 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
1155 | } |
1156 | #endif | |
058af1ea C |
1157 | if (!cpu_class_is_omap1()) { |
1158 | if (!bank->mod_usage) { | |
1159 | u32 ctrl; | |
1160 | ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
1161 | ctrl &= 0xFFFFFFFE; | |
1162 | /* Module is enabled, clocks are not gated */ | |
1163 | __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL); | |
1164 | } | |
1165 | bank->mod_usage |= 1 << offset; | |
1166 | } | |
a6472533 | 1167 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1168 | |
1169 | return 0; | |
1170 | } | |
1171 | ||
3ff164e1 | 1172 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1173 | { |
3ff164e1 | 1174 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1175 | unsigned long flags; |
5e1c5ff4 | 1176 | |
a6472533 | 1177 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1178 | #ifdef CONFIG_ARCH_OMAP16XX |
1179 | if (bank->method == METHOD_GPIO_1610) { | |
1180 | /* Disable wake-up during idle for dynamic tick */ | |
1181 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 1182 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
1183 | } |
1184 | #endif | |
44169075 SS |
1185 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1186 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 TL |
1187 | if (bank->method == METHOD_GPIO_24XX) { |
1188 | /* Disable wake-up during idle for dynamic tick */ | |
1189 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 1190 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
1191 | } |
1192 | #endif | |
058af1ea C |
1193 | if (!cpu_class_is_omap1()) { |
1194 | bank->mod_usage &= ~(1 << offset); | |
1195 | if (!bank->mod_usage) { | |
1196 | u32 ctrl; | |
1197 | ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
1198 | /* Module is disabled, clocks are gated */ | |
1199 | ctrl |= 1; | |
1200 | __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL); | |
1201 | } | |
1202 | } | |
3ff164e1 | 1203 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 1204 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1205 | } |
1206 | ||
1207 | /* | |
1208 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
1209 | * avoid missing GPIO interrupts for other lines in the bank. | |
1210 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
1211 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
1212 | * If we wait to unmask individual GPIO lines in the bank after the | |
1213 | * line's interrupt handler has been run, we may miss some nested | |
1214 | * interrupts. | |
1215 | */ | |
10dd5ce2 | 1216 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 1217 | { |
92105bb7 | 1218 | void __iomem *isr_reg = NULL; |
5e1c5ff4 TL |
1219 | u32 isr; |
1220 | unsigned int gpio_irq; | |
1221 | struct gpio_bank *bank; | |
ea6dedd7 ID |
1222 | u32 retrigger = 0; |
1223 | int unmasked = 0; | |
5e1c5ff4 TL |
1224 | |
1225 | desc->chip->ack(irq); | |
1226 | ||
418ca1f0 | 1227 | bank = get_irq_data(irq); |
e5c56ed3 | 1228 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
1229 | if (bank->method == METHOD_MPUIO) |
1230 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | |
e5c56ed3 | 1231 | #endif |
1a8bfa1e | 1232 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
1233 | if (bank->method == METHOD_GPIO_1510) |
1234 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
1235 | #endif | |
1236 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1237 | if (bank->method == METHOD_GPIO_1610) | |
1238 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
1239 | #endif | |
b718aa81 | 1240 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1241 | if (bank->method == METHOD_GPIO_7XX) |
1242 | isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; | |
56739a69 | 1243 | #endif |
78a1a6d3 | 1244 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1245 | if (bank->method == METHOD_GPIO_24XX) |
1246 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
78a1a6d3 SR |
1247 | #endif |
1248 | #if defined(CONFIG_ARCH_OMAP4) | |
1249 | if (bank->method == METHOD_GPIO_24XX) | |
1250 | isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; | |
92105bb7 | 1251 | #endif |
92105bb7 | 1252 | while(1) { |
6e60e79a | 1253 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 1254 | u32 enabled; |
6e60e79a | 1255 | |
ea6dedd7 ID |
1256 | enabled = _get_gpio_irqbank_mask(bank); |
1257 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
1258 | |
1259 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
1260 | isr &= 0x0000ffff; | |
1261 | ||
5492fb1a | 1262 | if (cpu_class_is_omap2()) { |
b144ff6f | 1263 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 1264 | } |
6e60e79a TL |
1265 | |
1266 | /* clear edge sensitive interrupts before handler(s) are | |
1267 | called so that we don't miss any interrupt occurred while | |
1268 | executing them */ | |
1269 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1270 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1271 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1272 | ||
1273 | /* if there is only edge sensitive GPIO pin interrupts | |
1274 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1275 | if (!level_mask && !unmasked) { |
1276 | unmasked = 1; | |
6e60e79a | 1277 | desc->chip->unmask(irq); |
ea6dedd7 | 1278 | } |
92105bb7 | 1279 | |
ea6dedd7 ID |
1280 | isr |= retrigger; |
1281 | retrigger = 0; | |
92105bb7 TL |
1282 | if (!isr) |
1283 | break; | |
1284 | ||
1285 | gpio_irq = bank->virtual_irq_start; | |
1286 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
92105bb7 TL |
1287 | if (!(isr & 1)) |
1288 | continue; | |
29454dde | 1289 | |
d8aa0251 | 1290 | generic_handle_irq(gpio_irq); |
92105bb7 | 1291 | } |
1a8bfa1e | 1292 | } |
ea6dedd7 ID |
1293 | /* if bank has any level sensitive GPIO pin interrupt |
1294 | configured, we must unmask the bank interrupt only after | |
1295 | handler(s) are executed in order to avoid spurious bank | |
1296 | interrupt */ | |
1297 | if (!unmasked) | |
1298 | desc->chip->unmask(irq); | |
1299 | ||
5e1c5ff4 TL |
1300 | } |
1301 | ||
4196dd6b TL |
1302 | static void gpio_irq_shutdown(unsigned int irq) |
1303 | { | |
1304 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1305 | struct gpio_bank *bank = get_irq_chip_data(irq); |
4196dd6b TL |
1306 | |
1307 | _reset_gpio(bank, gpio); | |
1308 | } | |
1309 | ||
5e1c5ff4 TL |
1310 | static void gpio_ack_irq(unsigned int irq) |
1311 | { | |
1312 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1313 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1314 | |
1315 | _clear_gpio_irqstatus(bank, gpio); | |
1316 | } | |
1317 | ||
1318 | static void gpio_mask_irq(unsigned int irq) | |
1319 | { | |
1320 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1321 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1322 | |
1323 | _set_gpio_irqenable(bank, gpio, 0); | |
55b6019a | 1324 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
5e1c5ff4 TL |
1325 | } |
1326 | ||
1327 | static void gpio_unmask_irq(unsigned int irq) | |
1328 | { | |
1329 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1330 | struct gpio_bank *bank = get_irq_chip_data(irq); |
b144ff6f | 1331 | unsigned int irq_mask = 1 << get_gpio_index(gpio); |
55b6019a KH |
1332 | struct irq_desc *desc = irq_to_desc(irq); |
1333 | u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; | |
1334 | ||
1335 | if (trigger) | |
1336 | _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); | |
b144ff6f KH |
1337 | |
1338 | /* For level-triggered GPIOs, the clearing must be done after | |
1339 | * the HW source is cleared, thus after the handler has run */ | |
1340 | if (bank->level_mask & irq_mask) { | |
1341 | _set_gpio_irqenable(bank, gpio, 0); | |
1342 | _clear_gpio_irqstatus(bank, gpio); | |
1343 | } | |
5e1c5ff4 | 1344 | |
4de8c75b | 1345 | _set_gpio_irqenable(bank, gpio, 1); |
5e1c5ff4 TL |
1346 | } |
1347 | ||
e5c56ed3 DB |
1348 | static struct irq_chip gpio_irq_chip = { |
1349 | .name = "GPIO", | |
1350 | .shutdown = gpio_irq_shutdown, | |
1351 | .ack = gpio_ack_irq, | |
1352 | .mask = gpio_mask_irq, | |
1353 | .unmask = gpio_unmask_irq, | |
1354 | .set_type = gpio_irq_type, | |
1355 | .set_wake = gpio_wake_enable, | |
1356 | }; | |
1357 | ||
1358 | /*---------------------------------------------------------------------*/ | |
1359 | ||
1360 | #ifdef CONFIG_ARCH_OMAP1 | |
1361 | ||
1362 | /* MPUIO uses the always-on 32k clock */ | |
1363 | ||
5e1c5ff4 TL |
1364 | static void mpuio_ack_irq(unsigned int irq) |
1365 | { | |
1366 | /* The ISR is reset automatically, so do nothing here. */ | |
1367 | } | |
1368 | ||
1369 | static void mpuio_mask_irq(unsigned int irq) | |
1370 | { | |
1371 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1372 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1373 | |
1374 | _set_gpio_irqenable(bank, gpio, 0); | |
1375 | } | |
1376 | ||
1377 | static void mpuio_unmask_irq(unsigned int irq) | |
1378 | { | |
1379 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1380 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1381 | |
1382 | _set_gpio_irqenable(bank, gpio, 1); | |
1383 | } | |
1384 | ||
e5c56ed3 DB |
1385 | static struct irq_chip mpuio_irq_chip = { |
1386 | .name = "MPUIO", | |
1387 | .ack = mpuio_ack_irq, | |
1388 | .mask = mpuio_mask_irq, | |
1389 | .unmask = mpuio_unmask_irq, | |
92105bb7 | 1390 | .set_type = gpio_irq_type, |
11a78b79 DB |
1391 | #ifdef CONFIG_ARCH_OMAP16XX |
1392 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1393 | .set_wake = gpio_wake_enable, | |
1394 | #endif | |
5e1c5ff4 TL |
1395 | }; |
1396 | ||
e5c56ed3 DB |
1397 | |
1398 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1399 | ||
11a78b79 DB |
1400 | |
1401 | #ifdef CONFIG_ARCH_OMAP16XX | |
1402 | ||
1403 | #include <linux/platform_device.h> | |
1404 | ||
79ee031f | 1405 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 1406 | { |
79ee031f | 1407 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 DB |
1408 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
1409 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1410 | unsigned long flags; |
11a78b79 | 1411 | |
a6472533 | 1412 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1413 | bank->saved_wakeup = __raw_readl(mask_reg); |
1414 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1415 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1416 | |
1417 | return 0; | |
1418 | } | |
1419 | ||
79ee031f | 1420 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 1421 | { |
79ee031f | 1422 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 DB |
1423 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
1424 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1425 | unsigned long flags; |
11a78b79 | 1426 | |
a6472533 | 1427 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1428 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1429 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1430 | |
1431 | return 0; | |
1432 | } | |
1433 | ||
47145210 | 1434 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
1435 | .suspend_noirq = omap_mpuio_suspend_noirq, |
1436 | .resume_noirq = omap_mpuio_resume_noirq, | |
1437 | }; | |
1438 | ||
11a78b79 DB |
1439 | /* use platform_driver for this, now that there's no longer any |
1440 | * point to sys_device (other than not disturbing old code). | |
1441 | */ | |
1442 | static struct platform_driver omap_mpuio_driver = { | |
11a78b79 DB |
1443 | .driver = { |
1444 | .name = "mpuio", | |
79ee031f | 1445 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
1446 | }, |
1447 | }; | |
1448 | ||
1449 | static struct platform_device omap_mpuio_device = { | |
1450 | .name = "mpuio", | |
1451 | .id = -1, | |
1452 | .dev = { | |
1453 | .driver = &omap_mpuio_driver.driver, | |
1454 | } | |
1455 | /* could list the /proc/iomem resources */ | |
1456 | }; | |
1457 | ||
1458 | static inline void mpuio_init(void) | |
1459 | { | |
fcf126d8 DB |
1460 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); |
1461 | ||
11a78b79 DB |
1462 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1463 | (void) platform_device_register(&omap_mpuio_device); | |
1464 | } | |
1465 | ||
1466 | #else | |
1467 | static inline void mpuio_init(void) {} | |
1468 | #endif /* 16xx */ | |
1469 | ||
e5c56ed3 DB |
1470 | #else |
1471 | ||
1472 | extern struct irq_chip mpuio_irq_chip; | |
1473 | ||
1474 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1475 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1476 | |
1477 | #endif | |
1478 | ||
1479 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1480 | |
52e31344 DB |
1481 | /* REVISIT these are stupid implementations! replace by ones that |
1482 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1483 | */ | |
1484 | ||
1485 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1486 | { | |
1487 | struct gpio_bank *bank; | |
1488 | unsigned long flags; | |
1489 | ||
1490 | bank = container_of(chip, struct gpio_bank, chip); | |
1491 | spin_lock_irqsave(&bank->lock, flags); | |
1492 | _set_gpio_direction(bank, offset, 1); | |
1493 | spin_unlock_irqrestore(&bank->lock, flags); | |
1494 | return 0; | |
1495 | } | |
1496 | ||
b37c45b8 RQ |
1497 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
1498 | { | |
1499 | void __iomem *reg = bank->base; | |
1500 | ||
1501 | switch (bank->method) { | |
1502 | case METHOD_MPUIO: | |
1503 | reg += OMAP_MPUIO_IO_CNTL; | |
1504 | break; | |
1505 | case METHOD_GPIO_1510: | |
1506 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1507 | break; | |
1508 | case METHOD_GPIO_1610: | |
1509 | reg += OMAP1610_GPIO_DIRECTION; | |
1510 | break; | |
7c006926 AB |
1511 | case METHOD_GPIO_7XX: |
1512 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
b37c45b8 RQ |
1513 | break; |
1514 | case METHOD_GPIO_24XX: | |
1515 | reg += OMAP24XX_GPIO_OE; | |
1516 | break; | |
1517 | } | |
1518 | return __raw_readl(reg) & mask; | |
1519 | } | |
1520 | ||
52e31344 DB |
1521 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
1522 | { | |
b37c45b8 RQ |
1523 | struct gpio_bank *bank; |
1524 | void __iomem *reg; | |
1525 | int gpio; | |
1526 | u32 mask; | |
1527 | ||
1528 | gpio = chip->base + offset; | |
1529 | bank = get_gpio_bank(gpio); | |
1530 | reg = bank->base; | |
1531 | mask = 1 << get_gpio_index(gpio); | |
1532 | ||
1533 | if (gpio_is_input(bank, mask)) | |
1534 | return _get_gpio_datain(bank, gpio); | |
1535 | else | |
1536 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
1537 | } |
1538 | ||
1539 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1540 | { | |
1541 | struct gpio_bank *bank; | |
1542 | unsigned long flags; | |
1543 | ||
1544 | bank = container_of(chip, struct gpio_bank, chip); | |
1545 | spin_lock_irqsave(&bank->lock, flags); | |
1546 | _set_gpio_dataout(bank, offset, value); | |
1547 | _set_gpio_direction(bank, offset, 0); | |
1548 | spin_unlock_irqrestore(&bank->lock, flags); | |
1549 | return 0; | |
1550 | } | |
1551 | ||
1552 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
1553 | { | |
1554 | struct gpio_bank *bank; | |
1555 | unsigned long flags; | |
1556 | ||
1557 | bank = container_of(chip, struct gpio_bank, chip); | |
1558 | spin_lock_irqsave(&bank->lock, flags); | |
1559 | _set_gpio_dataout(bank, offset, value); | |
1560 | spin_unlock_irqrestore(&bank->lock, flags); | |
1561 | } | |
1562 | ||
a007b709 DB |
1563 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
1564 | { | |
1565 | struct gpio_bank *bank; | |
1566 | ||
1567 | bank = container_of(chip, struct gpio_bank, chip); | |
1568 | return bank->virtual_irq_start + offset; | |
1569 | } | |
1570 | ||
52e31344 DB |
1571 | /*---------------------------------------------------------------------*/ |
1572 | ||
1a8bfa1e | 1573 | static int initialized; |
44169075 | 1574 | #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)) |
1a8bfa1e | 1575 | static struct clk * gpio_ick; |
5492fb1a SMK |
1576 | #endif |
1577 | ||
1578 | #if defined(CONFIG_ARCH_OMAP2) | |
1a8bfa1e | 1579 | static struct clk * gpio_fck; |
5492fb1a | 1580 | #endif |
5e1c5ff4 | 1581 | |
5492fb1a | 1582 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1583 | static struct clk * gpio5_ick; |
1584 | static struct clk * gpio5_fck; | |
1585 | #endif | |
1586 | ||
44169075 | 1587 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
5492fb1a SMK |
1588 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; |
1589 | #endif | |
1590 | ||
9f7065da TL |
1591 | static void __init omap_gpio_show_rev(void) |
1592 | { | |
1593 | u32 rev; | |
1594 | ||
1595 | if (cpu_is_omap16xx()) | |
1596 | rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); | |
1597 | else if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1598 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | |
1599 | else if (cpu_is_omap44xx()) | |
1600 | rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION); | |
1601 | else | |
1602 | return; | |
1603 | ||
1604 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | |
1605 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1606 | } | |
1607 | ||
8ba55c5c DB |
1608 | /* This lock class tells lockdep that GPIO irqs are in a different |
1609 | * category than their parents, so it won't report false recursion. | |
1610 | */ | |
1611 | static struct lock_class_key gpio_lock_class; | |
1612 | ||
5e1c5ff4 TL |
1613 | static int __init _omap_gpio_init(void) |
1614 | { | |
1615 | int i; | |
52e31344 | 1616 | int gpio = 0; |
5e1c5ff4 | 1617 | struct gpio_bank *bank; |
9f7065da | 1618 | int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ |
5492fb1a | 1619 | char clk_name[11]; |
5e1c5ff4 TL |
1620 | |
1621 | initialized = 1; | |
1622 | ||
5492fb1a | 1623 | #if defined(CONFIG_ARCH_OMAP1) |
6e60e79a | 1624 | if (cpu_is_omap15xx()) { |
1a8bfa1e TL |
1625 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); |
1626 | if (IS_ERR(gpio_ick)) | |
92105bb7 TL |
1627 | printk("Could not get arm_gpio_ck\n"); |
1628 | else | |
30ff720b | 1629 | clk_enable(gpio_ick); |
1a8bfa1e | 1630 | } |
5492fb1a SMK |
1631 | #endif |
1632 | #if defined(CONFIG_ARCH_OMAP2) | |
1633 | if (cpu_class_is_omap2()) { | |
1a8bfa1e TL |
1634 | gpio_ick = clk_get(NULL, "gpios_ick"); |
1635 | if (IS_ERR(gpio_ick)) | |
1636 | printk("Could not get gpios_ick\n"); | |
1637 | else | |
30ff720b | 1638 | clk_enable(gpio_ick); |
1a8bfa1e | 1639 | gpio_fck = clk_get(NULL, "gpios_fck"); |
1630b52d | 1640 | if (IS_ERR(gpio_fck)) |
1a8bfa1e TL |
1641 | printk("Could not get gpios_fck\n"); |
1642 | else | |
30ff720b | 1643 | clk_enable(gpio_fck); |
56a25641 SMK |
1644 | |
1645 | /* | |
5492fb1a | 1646 | * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK |
56a25641 | 1647 | */ |
5492fb1a | 1648 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1649 | if (cpu_is_omap2430()) { |
1650 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | |
1651 | if (IS_ERR(gpio5_ick)) | |
1652 | printk("Could not get gpio5_ick\n"); | |
1653 | else | |
1654 | clk_enable(gpio5_ick); | |
1655 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | |
1656 | if (IS_ERR(gpio5_fck)) | |
1657 | printk("Could not get gpio5_fck\n"); | |
1658 | else | |
1659 | clk_enable(gpio5_fck); | |
1660 | } | |
1661 | #endif | |
5492fb1a SMK |
1662 | } |
1663 | #endif | |
1664 | ||
44169075 SS |
1665 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
1666 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
5492fb1a SMK |
1667 | for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { |
1668 | sprintf(clk_name, "gpio%d_ick", i + 1); | |
1669 | gpio_iclks[i] = clk_get(NULL, clk_name); | |
1670 | if (IS_ERR(gpio_iclks[i])) | |
1671 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1672 | else | |
1673 | clk_enable(gpio_iclks[i]); | |
5492fb1a SMK |
1674 | } |
1675 | } | |
1676 | #endif | |
1677 | ||
92105bb7 | 1678 | |
1a8bfa1e | 1679 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 1680 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
1681 | gpio_bank_count = 2; |
1682 | gpio_bank = gpio_bank_1510; | |
9f7065da | 1683 | bank_size = SZ_2K; |
5e1c5ff4 TL |
1684 | } |
1685 | #endif | |
1686 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1687 | if (cpu_is_omap16xx()) { | |
5e1c5ff4 TL |
1688 | gpio_bank_count = 5; |
1689 | gpio_bank = gpio_bank_1610; | |
9f7065da | 1690 | bank_size = SZ_2K; |
5e1c5ff4 TL |
1691 | } |
1692 | #endif | |
b718aa81 AB |
1693 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
1694 | if (cpu_is_omap7xx()) { | |
56739a69 | 1695 | gpio_bank_count = 7; |
7c006926 | 1696 | gpio_bank = gpio_bank_7xx; |
9f7065da | 1697 | bank_size = SZ_2K; |
56739a69 ZM |
1698 | } |
1699 | #endif | |
92105bb7 | 1700 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 | 1701 | if (cpu_is_omap242x()) { |
92105bb7 | 1702 | gpio_bank_count = 4; |
56a25641 | 1703 | gpio_bank = gpio_bank_242x; |
56a25641 SMK |
1704 | } |
1705 | if (cpu_is_omap243x()) { | |
56a25641 SMK |
1706 | gpio_bank_count = 5; |
1707 | gpio_bank = gpio_bank_243x; | |
92105bb7 | 1708 | } |
5492fb1a SMK |
1709 | #endif |
1710 | #ifdef CONFIG_ARCH_OMAP34XX | |
1711 | if (cpu_is_omap34xx()) { | |
5492fb1a SMK |
1712 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
1713 | gpio_bank = gpio_bank_34xx; | |
5492fb1a | 1714 | } |
44169075 SS |
1715 | #endif |
1716 | #ifdef CONFIG_ARCH_OMAP4 | |
1717 | if (cpu_is_omap44xx()) { | |
44169075 SS |
1718 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
1719 | gpio_bank = gpio_bank_44xx; | |
44169075 | 1720 | } |
5e1c5ff4 TL |
1721 | #endif |
1722 | for (i = 0; i < gpio_bank_count; i++) { | |
1723 | int j, gpio_count = 16; | |
1724 | ||
1725 | bank = &gpio_bank[i]; | |
5e1c5ff4 | 1726 | spin_lock_init(&bank->lock); |
9f7065da TL |
1727 | |
1728 | /* Static mapping, never released */ | |
1729 | bank->base = ioremap(bank->pbase, bank_size); | |
1730 | if (!bank->base) { | |
1731 | printk(KERN_ERR "Could not ioremap gpio bank%i\n", i); | |
1732 | continue; | |
1733 | } | |
1734 | ||
e5c56ed3 | 1735 | if (bank_is_mpuio(bank)) |
7c7095aa | 1736 | __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); |
d11ac979 | 1737 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
5e1c5ff4 TL |
1738 | __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); |
1739 | __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); | |
1740 | } | |
d11ac979 | 1741 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { |
5e1c5ff4 TL |
1742 | __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); |
1743 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | |
92105bb7 | 1744 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
5e1c5ff4 | 1745 | } |
7c006926 AB |
1746 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { |
1747 | __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK); | |
1748 | __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS); | |
5e1c5ff4 | 1749 | |
7c006926 | 1750 | gpio_count = 32; /* 7xx has 32-bit GPIOs */ |
5e1c5ff4 | 1751 | } |
d11ac979 | 1752 | |
44169075 SS |
1753 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1754 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 | 1755 | if (bank->method == METHOD_GPIO_24XX) { |
3ac4fa99 JY |
1756 | static const u32 non_wakeup_gpios[] = { |
1757 | 0xe203ffc0, 0x08700040 | |
1758 | }; | |
78a1a6d3 SR |
1759 | if (cpu_is_omap44xx()) { |
1760 | __raw_writel(0xffffffff, bank->base + | |
1761 | OMAP4_GPIO_IRQSTATUSCLR0); | |
1762 | __raw_writew(0x0015, bank->base + | |
1763 | OMAP4_GPIO_SYSCONFIG); | |
1764 | __raw_writel(0x00000000, bank->base + | |
1765 | OMAP4_GPIO_DEBOUNCENABLE); | |
1766 | /* Initialize interface clock ungated, module enabled */ | |
1767 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); | |
1768 | } else { | |
92105bb7 TL |
1769 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); |
1770 | __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); | |
14f1c3bf | 1771 | __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); |
cb5793db | 1772 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN); |
14f1c3bf JY |
1773 | |
1774 | /* Initialize interface clock ungated, module enabled */ | |
1775 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
78a1a6d3 | 1776 | } |
3ac4fa99 JY |
1777 | if (i < ARRAY_SIZE(non_wakeup_gpios)) |
1778 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; | |
92105bb7 TL |
1779 | gpio_count = 32; |
1780 | } | |
5e1c5ff4 | 1781 | #endif |
058af1ea C |
1782 | |
1783 | bank->mod_usage = 0; | |
52e31344 DB |
1784 | /* REVISIT eventually switch from OMAP-specific gpio structs |
1785 | * over to the generic ones | |
1786 | */ | |
3ff164e1 JN |
1787 | bank->chip.request = omap_gpio_request; |
1788 | bank->chip.free = omap_gpio_free; | |
52e31344 DB |
1789 | bank->chip.direction_input = gpio_input; |
1790 | bank->chip.get = gpio_get; | |
1791 | bank->chip.direction_output = gpio_output; | |
1792 | bank->chip.set = gpio_set; | |
a007b709 | 1793 | bank->chip.to_irq = gpio_2irq; |
52e31344 DB |
1794 | if (bank_is_mpuio(bank)) { |
1795 | bank->chip.label = "mpuio"; | |
69114a47 | 1796 | #ifdef CONFIG_ARCH_OMAP16XX |
d8f388d8 DB |
1797 | bank->chip.dev = &omap_mpuio_device.dev; |
1798 | #endif | |
52e31344 DB |
1799 | bank->chip.base = OMAP_MPUIO(0); |
1800 | } else { | |
1801 | bank->chip.label = "gpio"; | |
1802 | bank->chip.base = gpio; | |
1803 | gpio += gpio_count; | |
1804 | } | |
1805 | bank->chip.ngpio = gpio_count; | |
1806 | ||
1807 | gpiochip_add(&bank->chip); | |
1808 | ||
5e1c5ff4 TL |
1809 | for (j = bank->virtual_irq_start; |
1810 | j < bank->virtual_irq_start + gpio_count; j++) { | |
8ba55c5c | 1811 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); |
58781016 | 1812 | set_irq_chip_data(j, bank); |
e5c56ed3 | 1813 | if (bank_is_mpuio(bank)) |
5e1c5ff4 TL |
1814 | set_irq_chip(j, &mpuio_irq_chip); |
1815 | else | |
1816 | set_irq_chip(j, &gpio_irq_chip); | |
10dd5ce2 | 1817 | set_irq_handler(j, handle_simple_irq); |
5e1c5ff4 TL |
1818 | set_irq_flags(j, IRQF_VALID); |
1819 | } | |
1820 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | |
1821 | set_irq_data(bank->irq, bank); | |
89db9482 | 1822 | |
44169075 | 1823 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
89db9482 JH |
1824 | sprintf(clk_name, "gpio%d_dbck", i + 1); |
1825 | bank->dbck = clk_get(NULL, clk_name); | |
1826 | if (IS_ERR(bank->dbck)) | |
1827 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1828 | } | |
5e1c5ff4 TL |
1829 | } |
1830 | ||
1831 | /* Enable system clock for GPIO module. | |
1832 | * The CAM_CLK_CTRL *is* really the right place. */ | |
92105bb7 | 1833 | if (cpu_is_omap16xx()) |
5e1c5ff4 TL |
1834 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); |
1835 | ||
14f1c3bf JY |
1836 | /* Enable autoidle for the OCP interface */ |
1837 | if (cpu_is_omap24xx()) | |
1838 | omap_writel(1 << 0, 0x48019010); | |
5492fb1a SMK |
1839 | if (cpu_is_omap34xx()) |
1840 | omap_writel(1 << 0, 0x48306814); | |
d11ac979 | 1841 | |
9f7065da TL |
1842 | omap_gpio_show_rev(); |
1843 | ||
5e1c5ff4 TL |
1844 | return 0; |
1845 | } | |
1846 | ||
44169075 SS |
1847 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ |
1848 | defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) | |
92105bb7 TL |
1849 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) |
1850 | { | |
1851 | int i; | |
1852 | ||
5492fb1a | 1853 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1854 | return 0; |
1855 | ||
1856 | for (i = 0; i < gpio_bank_count; i++) { | |
1857 | struct gpio_bank *bank = &gpio_bank[i]; | |
1858 | void __iomem *wake_status; | |
1859 | void __iomem *wake_clear; | |
1860 | void __iomem *wake_set; | |
a6472533 | 1861 | unsigned long flags; |
92105bb7 TL |
1862 | |
1863 | switch (bank->method) { | |
e5c56ed3 | 1864 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1865 | case METHOD_GPIO_1610: |
1866 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1867 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1868 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1869 | break; | |
e5c56ed3 | 1870 | #endif |
78a1a6d3 | 1871 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1872 | case METHOD_GPIO_24XX: |
723fdb78 | 1873 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1874 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1875 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1876 | break; | |
78a1a6d3 SR |
1877 | #endif |
1878 | #ifdef CONFIG_ARCH_OMAP4 | |
1879 | case METHOD_GPIO_24XX: | |
1880 | wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1881 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1882 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1883 | break; | |
e5c56ed3 | 1884 | #endif |
92105bb7 TL |
1885 | default: |
1886 | continue; | |
1887 | } | |
1888 | ||
a6472533 | 1889 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1890 | bank->saved_wakeup = __raw_readl(wake_status); |
1891 | __raw_writel(0xffffffff, wake_clear); | |
1892 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1893 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1894 | } |
1895 | ||
1896 | return 0; | |
1897 | } | |
1898 | ||
1899 | static int omap_gpio_resume(struct sys_device *dev) | |
1900 | { | |
1901 | int i; | |
1902 | ||
723fdb78 | 1903 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1904 | return 0; |
1905 | ||
1906 | for (i = 0; i < gpio_bank_count; i++) { | |
1907 | struct gpio_bank *bank = &gpio_bank[i]; | |
1908 | void __iomem *wake_clear; | |
1909 | void __iomem *wake_set; | |
a6472533 | 1910 | unsigned long flags; |
92105bb7 TL |
1911 | |
1912 | switch (bank->method) { | |
e5c56ed3 | 1913 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1914 | case METHOD_GPIO_1610: |
1915 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1916 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1917 | break; | |
e5c56ed3 | 1918 | #endif |
78a1a6d3 | 1919 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1920 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1921 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1922 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1923 | break; |
78a1a6d3 SR |
1924 | #endif |
1925 | #ifdef CONFIG_ARCH_OMAP4 | |
1926 | case METHOD_GPIO_24XX: | |
1927 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1928 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1929 | break; | |
e5c56ed3 | 1930 | #endif |
92105bb7 TL |
1931 | default: |
1932 | continue; | |
1933 | } | |
1934 | ||
a6472533 | 1935 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1936 | __raw_writel(0xffffffff, wake_clear); |
1937 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 1938 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1939 | } |
1940 | ||
1941 | return 0; | |
1942 | } | |
1943 | ||
1944 | static struct sysdev_class omap_gpio_sysclass = { | |
af5ca3f4 | 1945 | .name = "gpio", |
92105bb7 TL |
1946 | .suspend = omap_gpio_suspend, |
1947 | .resume = omap_gpio_resume, | |
1948 | }; | |
1949 | ||
1950 | static struct sys_device omap_gpio_device = { | |
1951 | .id = 0, | |
1952 | .cls = &omap_gpio_sysclass, | |
1953 | }; | |
3ac4fa99 JY |
1954 | |
1955 | #endif | |
1956 | ||
44169075 SS |
1957 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1958 | defined(CONFIG_ARCH_OMAP4) | |
3ac4fa99 JY |
1959 | |
1960 | static int workaround_enabled; | |
1961 | ||
1962 | void omap2_gpio_prepare_for_retention(void) | |
1963 | { | |
1964 | int i, c = 0; | |
1965 | ||
1966 | /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious | |
1967 | * IRQs will be generated. See OMAP2420 Errata item 1.101. */ | |
1968 | for (i = 0; i < gpio_bank_count; i++) { | |
1969 | struct gpio_bank *bank = &gpio_bank[i]; | |
1970 | u32 l1, l2; | |
1971 | ||
1972 | if (!(bank->enabled_non_wakeup_gpios)) | |
1973 | continue; | |
78a1a6d3 | 1974 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1975 | bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
1976 | l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1977 | l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
78a1a6d3 SR |
1978 | #endif |
1979 | #ifdef CONFIG_ARCH_OMAP4 | |
1980 | bank->saved_datain = __raw_readl(bank->base + | |
1981 | OMAP4_GPIO_DATAIN); | |
1982 | l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT); | |
1983 | l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT); | |
5492fb1a | 1984 | #endif |
3ac4fa99 JY |
1985 | bank->saved_fallingdetect = l1; |
1986 | bank->saved_risingdetect = l2; | |
1987 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1988 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
78a1a6d3 | 1989 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1990 | __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
1991 | __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
78a1a6d3 SR |
1992 | #endif |
1993 | #ifdef CONFIG_ARCH_OMAP4 | |
1994 | __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); | |
1995 | __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); | |
5492fb1a | 1996 | #endif |
3ac4fa99 JY |
1997 | c++; |
1998 | } | |
1999 | if (!c) { | |
2000 | workaround_enabled = 0; | |
2001 | return; | |
2002 | } | |
2003 | workaround_enabled = 1; | |
2004 | } | |
2005 | ||
2006 | void omap2_gpio_resume_after_retention(void) | |
2007 | { | |
2008 | int i; | |
2009 | ||
2010 | if (!workaround_enabled) | |
2011 | return; | |
2012 | for (i = 0; i < gpio_bank_count; i++) { | |
2013 | struct gpio_bank *bank = &gpio_bank[i]; | |
82dbb9d3 | 2014 | u32 l, gen, gen0, gen1; |
3ac4fa99 JY |
2015 | |
2016 | if (!(bank->enabled_non_wakeup_gpios)) | |
2017 | continue; | |
78a1a6d3 | 2018 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
2019 | __raw_writel(bank->saved_fallingdetect, |
2020 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
2021 | __raw_writel(bank->saved_risingdetect, | |
2022 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
78a1a6d3 SR |
2023 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
2024 | #endif | |
2025 | #ifdef CONFIG_ARCH_OMAP4 | |
2026 | __raw_writel(bank->saved_fallingdetect, | |
2027 | bank->base + OMAP4_GPIO_FALLINGDETECT); | |
2028 | __raw_writel(bank->saved_risingdetect, | |
2029 | bank->base + OMAP4_GPIO_RISINGDETECT); | |
2030 | l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); | |
5492fb1a | 2031 | #endif |
3ac4fa99 JY |
2032 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
2033 | * state. If so, generate an IRQ by software. This is | |
2034 | * horribly racy, but it's the best we can do to work around | |
2035 | * this silicon bug. */ | |
3ac4fa99 JY |
2036 | l ^= bank->saved_datain; |
2037 | l &= bank->non_wakeup_gpios; | |
82dbb9d3 EN |
2038 | |
2039 | /* | |
2040 | * No need to generate IRQs for the rising edge for gpio IRQs | |
2041 | * configured with falling edge only; and vice versa. | |
2042 | */ | |
2043 | gen0 = l & bank->saved_fallingdetect; | |
2044 | gen0 &= bank->saved_datain; | |
2045 | ||
2046 | gen1 = l & bank->saved_risingdetect; | |
2047 | gen1 &= ~(bank->saved_datain); | |
2048 | ||
2049 | /* FIXME: Consider GPIO IRQs with level detections properly! */ | |
2050 | gen = l & (~(bank->saved_fallingdetect) & | |
2051 | ~(bank->saved_risingdetect)); | |
2052 | /* Consider all GPIO IRQs needed to be updated */ | |
2053 | gen |= gen0 | gen1; | |
2054 | ||
2055 | if (gen) { | |
3ac4fa99 | 2056 | u32 old0, old1; |
78a1a6d3 | 2057 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
2058 | old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); |
2059 | old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
82dbb9d3 EN |
2060 | __raw_writel(old0 | gen, bank->base + |
2061 | OMAP24XX_GPIO_LEVELDETECT0); | |
2062 | __raw_writel(old1 | gen, bank->base + | |
2063 | OMAP24XX_GPIO_LEVELDETECT1); | |
3ac4fa99 JY |
2064 | __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); |
2065 | __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
78a1a6d3 SR |
2066 | #endif |
2067 | #ifdef CONFIG_ARCH_OMAP4 | |
2068 | old0 = __raw_readl(bank->base + | |
2069 | OMAP4_GPIO_LEVELDETECT0); | |
2070 | old1 = __raw_readl(bank->base + | |
2071 | OMAP4_GPIO_LEVELDETECT1); | |
2072 | __raw_writel(old0 | l, bank->base + | |
2073 | OMAP4_GPIO_LEVELDETECT0); | |
2074 | __raw_writel(old1 | l, bank->base + | |
2075 | OMAP4_GPIO_LEVELDETECT1); | |
2076 | __raw_writel(old0, bank->base + | |
2077 | OMAP4_GPIO_LEVELDETECT0); | |
2078 | __raw_writel(old1, bank->base + | |
2079 | OMAP4_GPIO_LEVELDETECT1); | |
5492fb1a | 2080 | #endif |
3ac4fa99 JY |
2081 | } |
2082 | } | |
2083 | ||
2084 | } | |
2085 | ||
92105bb7 TL |
2086 | #endif |
2087 | ||
40c670f0 RN |
2088 | #ifdef CONFIG_ARCH_OMAP34XX |
2089 | /* save the registers of bank 2-6 */ | |
2090 | void omap_gpio_save_context(void) | |
2091 | { | |
2092 | int i; | |
2093 | ||
2094 | /* saving banks from 2-6 only since GPIO1 is in WKUP */ | |
2095 | for (i = 1; i < gpio_bank_count; i++) { | |
2096 | struct gpio_bank *bank = &gpio_bank[i]; | |
2097 | gpio_context[i].sysconfig = | |
2098 | __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG); | |
2099 | gpio_context[i].irqenable1 = | |
2100 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
2101 | gpio_context[i].irqenable2 = | |
2102 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
2103 | gpio_context[i].wake_en = | |
2104 | __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); | |
2105 | gpio_context[i].ctrl = | |
2106 | __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
2107 | gpio_context[i].oe = | |
2108 | __raw_readl(bank->base + OMAP24XX_GPIO_OE); | |
2109 | gpio_context[i].leveldetect0 = | |
2110 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
2111 | gpio_context[i].leveldetect1 = | |
2112 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
2113 | gpio_context[i].risingdetect = | |
2114 | __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
2115 | gpio_context[i].fallingdetect = | |
2116 | __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
2117 | gpio_context[i].dataout = | |
2118 | __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); | |
2119 | gpio_context[i].setwkuena = | |
2120 | __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA); | |
2121 | gpio_context[i].setdataout = | |
2122 | __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT); | |
2123 | } | |
2124 | } | |
2125 | ||
2126 | /* restore the required registers of bank 2-6 */ | |
2127 | void omap_gpio_restore_context(void) | |
2128 | { | |
2129 | int i; | |
2130 | ||
2131 | for (i = 1; i < gpio_bank_count; i++) { | |
2132 | struct gpio_bank *bank = &gpio_bank[i]; | |
2133 | __raw_writel(gpio_context[i].sysconfig, | |
2134 | bank->base + OMAP24XX_GPIO_SYSCONFIG); | |
2135 | __raw_writel(gpio_context[i].irqenable1, | |
2136 | bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
2137 | __raw_writel(gpio_context[i].irqenable2, | |
2138 | bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
2139 | __raw_writel(gpio_context[i].wake_en, | |
2140 | bank->base + OMAP24XX_GPIO_WAKE_EN); | |
2141 | __raw_writel(gpio_context[i].ctrl, | |
2142 | bank->base + OMAP24XX_GPIO_CTRL); | |
2143 | __raw_writel(gpio_context[i].oe, | |
2144 | bank->base + OMAP24XX_GPIO_OE); | |
2145 | __raw_writel(gpio_context[i].leveldetect0, | |
2146 | bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
2147 | __raw_writel(gpio_context[i].leveldetect1, | |
2148 | bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
2149 | __raw_writel(gpio_context[i].risingdetect, | |
2150 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
2151 | __raw_writel(gpio_context[i].fallingdetect, | |
2152 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
2153 | __raw_writel(gpio_context[i].dataout, | |
2154 | bank->base + OMAP24XX_GPIO_DATAOUT); | |
2155 | __raw_writel(gpio_context[i].setwkuena, | |
2156 | bank->base + OMAP24XX_GPIO_SETWKUENA); | |
2157 | __raw_writel(gpio_context[i].setdataout, | |
2158 | bank->base + OMAP24XX_GPIO_SETDATAOUT); | |
2159 | } | |
2160 | } | |
2161 | #endif | |
2162 | ||
5e1c5ff4 TL |
2163 | /* |
2164 | * This may get called early from board specific init | |
1a8bfa1e | 2165 | * for boards that have interrupts routed via FPGA. |
5e1c5ff4 | 2166 | */ |
277d58ef | 2167 | int __init omap_gpio_init(void) |
5e1c5ff4 TL |
2168 | { |
2169 | if (!initialized) | |
2170 | return _omap_gpio_init(); | |
2171 | else | |
2172 | return 0; | |
2173 | } | |
2174 | ||
92105bb7 TL |
2175 | static int __init omap_gpio_sysinit(void) |
2176 | { | |
2177 | int ret = 0; | |
2178 | ||
2179 | if (!initialized) | |
2180 | ret = _omap_gpio_init(); | |
2181 | ||
11a78b79 DB |
2182 | mpuio_init(); |
2183 | ||
44169075 SS |
2184 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ |
2185 | defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) | |
5492fb1a | 2186 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { |
92105bb7 TL |
2187 | if (ret == 0) { |
2188 | ret = sysdev_class_register(&omap_gpio_sysclass); | |
2189 | if (ret == 0) | |
2190 | ret = sysdev_register(&omap_gpio_device); | |
2191 | } | |
2192 | } | |
2193 | #endif | |
2194 | ||
2195 | return ret; | |
2196 | } | |
2197 | ||
92105bb7 | 2198 | arch_initcall(omap_gpio_sysinit); |
b9772a22 DB |
2199 | |
2200 | ||
2201 | #ifdef CONFIG_DEBUG_FS | |
2202 | ||
2203 | #include <linux/debugfs.h> | |
2204 | #include <linux/seq_file.h> | |
2205 | ||
b9772a22 DB |
2206 | static int dbg_gpio_show(struct seq_file *s, void *unused) |
2207 | { | |
2208 | unsigned i, j, gpio; | |
2209 | ||
2210 | for (i = 0, gpio = 0; i < gpio_bank_count; i++) { | |
2211 | struct gpio_bank *bank = gpio_bank + i; | |
2212 | unsigned bankwidth = 16; | |
2213 | u32 mask = 1; | |
2214 | ||
e5c56ed3 | 2215 | if (bank_is_mpuio(bank)) |
b9772a22 | 2216 | gpio = OMAP_MPUIO(0); |
b718aa81 | 2217 | else if (cpu_class_is_omap2() || cpu_is_omap7xx()) |
b9772a22 DB |
2218 | bankwidth = 32; |
2219 | ||
2220 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | |
2221 | unsigned irq, value, is_in, irqstat; | |
52e31344 | 2222 | const char *label; |
b9772a22 | 2223 | |
52e31344 DB |
2224 | label = gpiochip_is_requested(&bank->chip, j); |
2225 | if (!label) | |
b9772a22 DB |
2226 | continue; |
2227 | ||
2228 | irq = bank->virtual_irq_start + j; | |
0b84b5ca | 2229 | value = gpio_get_value(gpio); |
b9772a22 DB |
2230 | is_in = gpio_is_input(bank, mask); |
2231 | ||
e5c56ed3 | 2232 | if (bank_is_mpuio(bank)) |
52e31344 | 2233 | seq_printf(s, "MPUIO %2d ", j); |
b9772a22 | 2234 | else |
52e31344 | 2235 | seq_printf(s, "GPIO %3d ", gpio); |
21c867f1 | 2236 | seq_printf(s, "(%-20.20s): %s %s", |
52e31344 | 2237 | label, |
b9772a22 DB |
2238 | is_in ? "in " : "out", |
2239 | value ? "hi" : "lo"); | |
2240 | ||
52e31344 DB |
2241 | /* FIXME for at least omap2, show pullup/pulldown state */ |
2242 | ||
b9772a22 | 2243 | irqstat = irq_desc[irq].status; |
3a26e331 | 2244 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ |
44169075 | 2245 | defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) |
b9772a22 DB |
2246 | if (is_in && ((bank->suspend_wakeup & mask) |
2247 | || irqstat & IRQ_TYPE_SENSE_MASK)) { | |
2248 | char *trigger = NULL; | |
2249 | ||
2250 | switch (irqstat & IRQ_TYPE_SENSE_MASK) { | |
2251 | case IRQ_TYPE_EDGE_FALLING: | |
2252 | trigger = "falling"; | |
2253 | break; | |
2254 | case IRQ_TYPE_EDGE_RISING: | |
2255 | trigger = "rising"; | |
2256 | break; | |
2257 | case IRQ_TYPE_EDGE_BOTH: | |
2258 | trigger = "bothedge"; | |
2259 | break; | |
2260 | case IRQ_TYPE_LEVEL_LOW: | |
2261 | trigger = "low"; | |
2262 | break; | |
2263 | case IRQ_TYPE_LEVEL_HIGH: | |
2264 | trigger = "high"; | |
2265 | break; | |
2266 | case IRQ_TYPE_NONE: | |
52e31344 | 2267 | trigger = "(?)"; |
b9772a22 DB |
2268 | break; |
2269 | } | |
52e31344 | 2270 | seq_printf(s, ", irq-%d %-8s%s", |
b9772a22 DB |
2271 | irq, trigger, |
2272 | (bank->suspend_wakeup & mask) | |
2273 | ? " wakeup" : ""); | |
2274 | } | |
3a26e331 | 2275 | #endif |
b9772a22 DB |
2276 | seq_printf(s, "\n"); |
2277 | } | |
2278 | ||
e5c56ed3 | 2279 | if (bank_is_mpuio(bank)) { |
b9772a22 DB |
2280 | seq_printf(s, "\n"); |
2281 | gpio = 0; | |
2282 | } | |
2283 | } | |
2284 | return 0; | |
2285 | } | |
2286 | ||
2287 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
2288 | { | |
e5c56ed3 | 2289 | return single_open(file, dbg_gpio_show, &inode->i_private); |
b9772a22 DB |
2290 | } |
2291 | ||
2292 | static const struct file_operations debug_fops = { | |
2293 | .open = dbg_gpio_open, | |
2294 | .read = seq_read, | |
2295 | .llseek = seq_lseek, | |
2296 | .release = single_release, | |
2297 | }; | |
2298 | ||
2299 | static int __init omap_gpio_debuginit(void) | |
2300 | { | |
e5c56ed3 DB |
2301 | (void) debugfs_create_file("omap_gpio", S_IRUGO, |
2302 | NULL, NULL, &debug_fops); | |
b9772a22 DB |
2303 | return 0; |
2304 | } | |
2305 | late_initcall(omap_gpio_debuginit); | |
2306 | #endif |