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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/gpio.c | |
3 | * | |
4 | * Support functions for OMAP GPIO | |
5 | * | |
92105bb7 | 6 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 TL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
5e1c5ff4 TL |
14 | #include <linux/init.h> |
15 | #include <linux/module.h> | |
5e1c5ff4 | 16 | #include <linux/interrupt.h> |
92105bb7 TL |
17 | #include <linux/sysdev.h> |
18 | #include <linux/err.h> | |
f8ce2547 | 19 | #include <linux/clk.h> |
fced80c7 | 20 | #include <linux/io.h> |
5e1c5ff4 | 21 | |
a09e64fb | 22 | #include <mach/hardware.h> |
5e1c5ff4 | 23 | #include <asm/irq.h> |
a09e64fb RK |
24 | #include <mach/irqs.h> |
25 | #include <mach/gpio.h> | |
5e1c5ff4 TL |
26 | #include <asm/mach/irq.h> |
27 | ||
5e1c5ff4 TL |
28 | /* |
29 | * OMAP1510 GPIO registers | |
30 | */ | |
7c7095aa | 31 | #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000) |
5e1c5ff4 TL |
32 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
33 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | |
34 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | |
35 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | |
36 | #define OMAP1510_GPIO_INT_MASK 0x10 | |
37 | #define OMAP1510_GPIO_INT_STATUS 0x14 | |
38 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | |
39 | ||
40 | #define OMAP1510_IH_GPIO_BASE 64 | |
41 | ||
42 | /* | |
43 | * OMAP1610 specific GPIO registers | |
44 | */ | |
7c7095aa RK |
45 | #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400) |
46 | #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00) | |
47 | #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400) | |
48 | #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00) | |
5e1c5ff4 TL |
49 | #define OMAP1610_GPIO_REVISION 0x0000 |
50 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | |
51 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | |
52 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | |
53 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | |
92105bb7 | 54 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 |
5e1c5ff4 TL |
55 | #define OMAP1610_GPIO_DATAIN 0x002c |
56 | #define OMAP1610_GPIO_DATAOUT 0x0030 | |
57 | #define OMAP1610_GPIO_DIRECTION 0x0034 | |
58 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | |
59 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | |
60 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | |
92105bb7 | 61 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 |
5e1c5ff4 TL |
62 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 |
63 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | |
92105bb7 | 64 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 |
5e1c5ff4 TL |
65 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
66 | ||
67 | /* | |
68 | * OMAP730 specific GPIO registers | |
69 | */ | |
7c7095aa RK |
70 | #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000) |
71 | #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800) | |
72 | #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000) | |
73 | #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800) | |
74 | #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000) | |
75 | #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800) | |
5e1c5ff4 TL |
76 | #define OMAP730_GPIO_DATA_INPUT 0x00 |
77 | #define OMAP730_GPIO_DATA_OUTPUT 0x04 | |
78 | #define OMAP730_GPIO_DIR_CONTROL 0x08 | |
79 | #define OMAP730_GPIO_INT_CONTROL 0x0c | |
80 | #define OMAP730_GPIO_INT_MASK 0x10 | |
81 | #define OMAP730_GPIO_INT_STATUS 0x14 | |
82 | ||
92105bb7 TL |
83 | /* |
84 | * omap24xx specific GPIO registers | |
85 | */ | |
7c7095aa RK |
86 | #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000) |
87 | #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000) | |
88 | #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000) | |
89 | #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000) | |
56a25641 | 90 | |
7c7095aa RK |
91 | #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000) |
92 | #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000) | |
93 | #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000) | |
94 | #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000) | |
95 | #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000) | |
56a25641 | 96 | |
92105bb7 TL |
97 | #define OMAP24XX_GPIO_REVISION 0x0000 |
98 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | |
99 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | |
100 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | |
bee7930f HD |
101 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
102 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | |
92105bb7 | 103 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c |
723fdb78 | 104 | #define OMAP24XX_GPIO_WAKE_EN 0x0020 |
92105bb7 TL |
105 | #define OMAP24XX_GPIO_CTRL 0x0030 |
106 | #define OMAP24XX_GPIO_OE 0x0034 | |
107 | #define OMAP24XX_GPIO_DATAIN 0x0038 | |
108 | #define OMAP24XX_GPIO_DATAOUT 0x003c | |
109 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | |
110 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | |
111 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | |
112 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | |
5eb3bb9c KH |
113 | #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 |
114 | #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 | |
92105bb7 TL |
115 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 |
116 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | |
117 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | |
118 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | |
119 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | |
120 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | |
121 | ||
5492fb1a SMK |
122 | /* |
123 | * omap34xx specific GPIO registers | |
124 | */ | |
125 | ||
7c7095aa RK |
126 | #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000) |
127 | #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000) | |
128 | #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000) | |
129 | #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000) | |
130 | #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000) | |
131 | #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000) | |
5492fb1a | 132 | |
7c7095aa | 133 | #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE) |
5492fb1a | 134 | |
5e1c5ff4 | 135 | struct gpio_bank { |
92105bb7 | 136 | void __iomem *base; |
5e1c5ff4 TL |
137 | u16 irq; |
138 | u16 virtual_irq_start; | |
92105bb7 | 139 | int method; |
5492fb1a | 140 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
141 | u32 suspend_wakeup; |
142 | u32 saved_wakeup; | |
3ac4fa99 | 143 | #endif |
5492fb1a | 144 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
145 | u32 non_wakeup_gpios; |
146 | u32 enabled_non_wakeup_gpios; | |
147 | ||
148 | u32 saved_datain; | |
149 | u32 saved_fallingdetect; | |
150 | u32 saved_risingdetect; | |
151 | #endif | |
b144ff6f | 152 | u32 level_mask; |
5e1c5ff4 | 153 | spinlock_t lock; |
52e31344 | 154 | struct gpio_chip chip; |
89db9482 | 155 | struct clk *dbck; |
5e1c5ff4 TL |
156 | }; |
157 | ||
158 | #define METHOD_MPUIO 0 | |
159 | #define METHOD_GPIO_1510 1 | |
160 | #define METHOD_GPIO_1610 2 | |
161 | #define METHOD_GPIO_730 3 | |
92105bb7 | 162 | #define METHOD_GPIO_24XX 4 |
5e1c5ff4 | 163 | |
92105bb7 | 164 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 165 | static struct gpio_bank gpio_bank_1610[5] = { |
7c7095aa | 166 | { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, |
5e1c5ff4 TL |
167 | { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, |
168 | { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, | |
169 | { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, | |
170 | { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, | |
171 | }; | |
172 | #endif | |
173 | ||
1a8bfa1e | 174 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 175 | static struct gpio_bank gpio_bank_1510[2] = { |
7c7095aa | 176 | { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, |
5e1c5ff4 TL |
177 | { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } |
178 | }; | |
179 | #endif | |
180 | ||
181 | #ifdef CONFIG_ARCH_OMAP730 | |
182 | static struct gpio_bank gpio_bank_730[7] = { | |
7c7095aa | 183 | { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, |
5e1c5ff4 TL |
184 | { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, |
185 | { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, | |
186 | { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, | |
187 | { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, | |
188 | { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, | |
189 | { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, | |
190 | }; | |
191 | #endif | |
192 | ||
92105bb7 | 193 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 SMK |
194 | |
195 | static struct gpio_bank gpio_bank_242x[4] = { | |
196 | { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
197 | { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
198 | { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
199 | { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
92105bb7 | 200 | }; |
56a25641 SMK |
201 | |
202 | static struct gpio_bank gpio_bank_243x[5] = { | |
203 | { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
204 | { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
205 | { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
206 | { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
207 | { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
208 | }; | |
209 | ||
92105bb7 TL |
210 | #endif |
211 | ||
5492fb1a SMK |
212 | #ifdef CONFIG_ARCH_OMAP34XX |
213 | static struct gpio_bank gpio_bank_34xx[6] = { | |
214 | { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
215 | { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
216 | { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
217 | { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
218 | { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
219 | { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX }, | |
220 | }; | |
221 | ||
222 | #endif | |
223 | ||
5e1c5ff4 TL |
224 | static struct gpio_bank *gpio_bank; |
225 | static int gpio_bank_count; | |
226 | ||
227 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
228 | { | |
6e60e79a | 229 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
230 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
231 | return &gpio_bank[0]; | |
232 | return &gpio_bank[1]; | |
233 | } | |
5e1c5ff4 TL |
234 | if (cpu_is_omap16xx()) { |
235 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
236 | return &gpio_bank[0]; | |
237 | return &gpio_bank[1 + (gpio >> 4)]; | |
238 | } | |
5e1c5ff4 TL |
239 | if (cpu_is_omap730()) { |
240 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
241 | return &gpio_bank[0]; | |
242 | return &gpio_bank[1 + (gpio >> 5)]; | |
243 | } | |
92105bb7 TL |
244 | if (cpu_is_omap24xx()) |
245 | return &gpio_bank[gpio >> 5]; | |
5492fb1a SMK |
246 | if (cpu_is_omap34xx()) |
247 | return &gpio_bank[gpio >> 5]; | |
5e1c5ff4 TL |
248 | } |
249 | ||
250 | static inline int get_gpio_index(int gpio) | |
251 | { | |
252 | if (cpu_is_omap730()) | |
253 | return gpio & 0x1f; | |
92105bb7 TL |
254 | if (cpu_is_omap24xx()) |
255 | return gpio & 0x1f; | |
5492fb1a SMK |
256 | if (cpu_is_omap34xx()) |
257 | return gpio & 0x1f; | |
92105bb7 | 258 | return gpio & 0x0f; |
5e1c5ff4 TL |
259 | } |
260 | ||
261 | static inline int gpio_valid(int gpio) | |
262 | { | |
263 | if (gpio < 0) | |
264 | return -1; | |
d11ac979 | 265 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 266 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
267 | return -1; |
268 | return 0; | |
269 | } | |
6e60e79a | 270 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 271 | return 0; |
5e1c5ff4 TL |
272 | if ((cpu_is_omap16xx()) && gpio < 64) |
273 | return 0; | |
5e1c5ff4 TL |
274 | if (cpu_is_omap730() && gpio < 192) |
275 | return 0; | |
92105bb7 TL |
276 | if (cpu_is_omap24xx() && gpio < 128) |
277 | return 0; | |
5492fb1a SMK |
278 | if (cpu_is_omap34xx() && gpio < 160) |
279 | return 0; | |
5e1c5ff4 TL |
280 | return -1; |
281 | } | |
282 | ||
283 | static int check_gpio(int gpio) | |
284 | { | |
285 | if (unlikely(gpio_valid(gpio)) < 0) { | |
286 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); | |
287 | dump_stack(); | |
288 | return -1; | |
289 | } | |
290 | return 0; | |
291 | } | |
292 | ||
293 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
294 | { | |
92105bb7 | 295 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
296 | u32 l; |
297 | ||
298 | switch (bank->method) { | |
e5c56ed3 | 299 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
300 | case METHOD_MPUIO: |
301 | reg += OMAP_MPUIO_IO_CNTL; | |
302 | break; | |
e5c56ed3 DB |
303 | #endif |
304 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
305 | case METHOD_GPIO_1510: |
306 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
307 | break; | |
e5c56ed3 DB |
308 | #endif |
309 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
310 | case METHOD_GPIO_1610: |
311 | reg += OMAP1610_GPIO_DIRECTION; | |
312 | break; | |
e5c56ed3 DB |
313 | #endif |
314 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
315 | case METHOD_GPIO_730: |
316 | reg += OMAP730_GPIO_DIR_CONTROL; | |
317 | break; | |
e5c56ed3 | 318 | #endif |
5492fb1a | 319 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
320 | case METHOD_GPIO_24XX: |
321 | reg += OMAP24XX_GPIO_OE; | |
322 | break; | |
e5c56ed3 DB |
323 | #endif |
324 | default: | |
325 | WARN_ON(1); | |
326 | return; | |
5e1c5ff4 TL |
327 | } |
328 | l = __raw_readl(reg); | |
329 | if (is_input) | |
330 | l |= 1 << gpio; | |
331 | else | |
332 | l &= ~(1 << gpio); | |
333 | __raw_writel(l, reg); | |
334 | } | |
335 | ||
336 | void omap_set_gpio_direction(int gpio, int is_input) | |
337 | { | |
338 | struct gpio_bank *bank; | |
a6472533 | 339 | unsigned long flags; |
5e1c5ff4 TL |
340 | |
341 | if (check_gpio(gpio) < 0) | |
342 | return; | |
343 | bank = get_gpio_bank(gpio); | |
a6472533 | 344 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 345 | _set_gpio_direction(bank, get_gpio_index(gpio), is_input); |
a6472533 | 346 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
347 | } |
348 | ||
349 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) | |
350 | { | |
92105bb7 | 351 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
352 | u32 l = 0; |
353 | ||
354 | switch (bank->method) { | |
e5c56ed3 | 355 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
356 | case METHOD_MPUIO: |
357 | reg += OMAP_MPUIO_OUTPUT; | |
358 | l = __raw_readl(reg); | |
359 | if (enable) | |
360 | l |= 1 << gpio; | |
361 | else | |
362 | l &= ~(1 << gpio); | |
363 | break; | |
e5c56ed3 DB |
364 | #endif |
365 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
366 | case METHOD_GPIO_1510: |
367 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
368 | l = __raw_readl(reg); | |
369 | if (enable) | |
370 | l |= 1 << gpio; | |
371 | else | |
372 | l &= ~(1 << gpio); | |
373 | break; | |
e5c56ed3 DB |
374 | #endif |
375 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
376 | case METHOD_GPIO_1610: |
377 | if (enable) | |
378 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
379 | else | |
380 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
381 | l = 1 << gpio; | |
382 | break; | |
e5c56ed3 DB |
383 | #endif |
384 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
385 | case METHOD_GPIO_730: |
386 | reg += OMAP730_GPIO_DATA_OUTPUT; | |
387 | l = __raw_readl(reg); | |
388 | if (enable) | |
389 | l |= 1 << gpio; | |
390 | else | |
391 | l &= ~(1 << gpio); | |
392 | break; | |
e5c56ed3 | 393 | #endif |
5492fb1a | 394 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
395 | case METHOD_GPIO_24XX: |
396 | if (enable) | |
397 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
398 | else | |
399 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
400 | l = 1 << gpio; | |
401 | break; | |
e5c56ed3 | 402 | #endif |
5e1c5ff4 | 403 | default: |
e5c56ed3 | 404 | WARN_ON(1); |
5e1c5ff4 TL |
405 | return; |
406 | } | |
407 | __raw_writel(l, reg); | |
408 | } | |
409 | ||
410 | void omap_set_gpio_dataout(int gpio, int enable) | |
411 | { | |
412 | struct gpio_bank *bank; | |
a6472533 | 413 | unsigned long flags; |
5e1c5ff4 TL |
414 | |
415 | if (check_gpio(gpio) < 0) | |
416 | return; | |
417 | bank = get_gpio_bank(gpio); | |
a6472533 | 418 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 419 | _set_gpio_dataout(bank, get_gpio_index(gpio), enable); |
a6472533 | 420 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
421 | } |
422 | ||
423 | int omap_get_gpio_datain(int gpio) | |
424 | { | |
425 | struct gpio_bank *bank; | |
92105bb7 | 426 | void __iomem *reg; |
5e1c5ff4 TL |
427 | |
428 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 429 | return -EINVAL; |
5e1c5ff4 TL |
430 | bank = get_gpio_bank(gpio); |
431 | reg = bank->base; | |
432 | switch (bank->method) { | |
e5c56ed3 | 433 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
434 | case METHOD_MPUIO: |
435 | reg += OMAP_MPUIO_INPUT_LATCH; | |
436 | break; | |
e5c56ed3 DB |
437 | #endif |
438 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
439 | case METHOD_GPIO_1510: |
440 | reg += OMAP1510_GPIO_DATA_INPUT; | |
441 | break; | |
e5c56ed3 DB |
442 | #endif |
443 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
444 | case METHOD_GPIO_1610: |
445 | reg += OMAP1610_GPIO_DATAIN; | |
446 | break; | |
e5c56ed3 DB |
447 | #endif |
448 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
449 | case METHOD_GPIO_730: |
450 | reg += OMAP730_GPIO_DATA_INPUT; | |
451 | break; | |
e5c56ed3 | 452 | #endif |
5492fb1a | 453 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
454 | case METHOD_GPIO_24XX: |
455 | reg += OMAP24XX_GPIO_DATAIN; | |
456 | break; | |
e5c56ed3 | 457 | #endif |
5e1c5ff4 | 458 | default: |
e5c56ed3 | 459 | return -EINVAL; |
5e1c5ff4 | 460 | } |
92105bb7 TL |
461 | return (__raw_readl(reg) |
462 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
463 | } |
464 | ||
92105bb7 TL |
465 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
466 | do { \ | |
467 | int l = __raw_readl(base + reg); \ | |
468 | if (set) l |= bit_mask; \ | |
469 | else l &= ~bit_mask; \ | |
470 | __raw_writel(l, base + reg); \ | |
471 | } while(0) | |
472 | ||
5eb3bb9c KH |
473 | void omap_set_gpio_debounce(int gpio, int enable) |
474 | { | |
475 | struct gpio_bank *bank; | |
476 | void __iomem *reg; | |
477 | u32 val, l = 1 << get_gpio_index(gpio); | |
478 | ||
479 | if (cpu_class_is_omap1()) | |
480 | return; | |
481 | ||
482 | bank = get_gpio_bank(gpio); | |
483 | reg = bank->base; | |
484 | ||
485 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | |
486 | val = __raw_readl(reg); | |
487 | ||
89db9482 | 488 | if (enable && !(val & l)) |
5eb3bb9c | 489 | val |= l; |
89db9482 | 490 | else if (!enable && val & l) |
5eb3bb9c | 491 | val &= ~l; |
89db9482 JH |
492 | else |
493 | return; | |
494 | ||
495 | if (cpu_is_omap34xx()) | |
496 | enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck); | |
5eb3bb9c KH |
497 | |
498 | __raw_writel(val, reg); | |
499 | } | |
500 | EXPORT_SYMBOL(omap_set_gpio_debounce); | |
501 | ||
502 | void omap_set_gpio_debounce_time(int gpio, int enc_time) | |
503 | { | |
504 | struct gpio_bank *bank; | |
505 | void __iomem *reg; | |
506 | ||
507 | if (cpu_class_is_omap1()) | |
508 | return; | |
509 | ||
510 | bank = get_gpio_bank(gpio); | |
511 | reg = bank->base; | |
512 | ||
513 | enc_time &= 0xff; | |
514 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
515 | __raw_writel(enc_time, reg); | |
516 | } | |
517 | EXPORT_SYMBOL(omap_set_gpio_debounce_time); | |
518 | ||
5492fb1a | 519 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
5eb3bb9c KH |
520 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
521 | int trigger) | |
5e1c5ff4 | 522 | { |
3ac4fa99 | 523 | void __iomem *base = bank->base; |
92105bb7 TL |
524 | u32 gpio_bit = 1 << gpio; |
525 | ||
526 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
6cab4860 | 527 | trigger & IRQ_TYPE_LEVEL_LOW); |
92105bb7 | 528 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, |
6cab4860 | 529 | trigger & IRQ_TYPE_LEVEL_HIGH); |
92105bb7 | 530 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, |
6cab4860 | 531 | trigger & IRQ_TYPE_EDGE_RISING); |
92105bb7 | 532 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, |
6cab4860 | 533 | trigger & IRQ_TYPE_EDGE_FALLING); |
5eb3bb9c | 534 | |
3ac4fa99 JY |
535 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
536 | if (trigger != 0) | |
5eb3bb9c KH |
537 | __raw_writel(1 << gpio, bank->base |
538 | + OMAP24XX_GPIO_SETWKUENA); | |
3ac4fa99 | 539 | else |
5eb3bb9c KH |
540 | __raw_writel(1 << gpio, bank->base |
541 | + OMAP24XX_GPIO_CLEARWKUENA); | |
3ac4fa99 JY |
542 | } else { |
543 | if (trigger != 0) | |
544 | bank->enabled_non_wakeup_gpios |= gpio_bit; | |
545 | else | |
546 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
547 | } | |
5eb3bb9c | 548 | |
b144ff6f KH |
549 | bank->level_mask = |
550 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
551 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
92105bb7 | 552 | } |
3ac4fa99 | 553 | #endif |
92105bb7 TL |
554 | |
555 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |
556 | { | |
557 | void __iomem *reg = bank->base; | |
558 | u32 l = 0; | |
5e1c5ff4 TL |
559 | |
560 | switch (bank->method) { | |
e5c56ed3 | 561 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
562 | case METHOD_MPUIO: |
563 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
564 | l = __raw_readl(reg); | |
6cab4860 | 565 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 566 | l |= 1 << gpio; |
6cab4860 | 567 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 568 | l &= ~(1 << gpio); |
92105bb7 TL |
569 | else |
570 | goto bad; | |
5e1c5ff4 | 571 | break; |
e5c56ed3 DB |
572 | #endif |
573 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
574 | case METHOD_GPIO_1510: |
575 | reg += OMAP1510_GPIO_INT_CONTROL; | |
576 | l = __raw_readl(reg); | |
6cab4860 | 577 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 578 | l |= 1 << gpio; |
6cab4860 | 579 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 580 | l &= ~(1 << gpio); |
92105bb7 TL |
581 | else |
582 | goto bad; | |
5e1c5ff4 | 583 | break; |
e5c56ed3 | 584 | #endif |
3ac4fa99 | 585 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 586 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
587 | if (gpio & 0x08) |
588 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
589 | else | |
590 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
591 | gpio &= 0x07; | |
592 | l = __raw_readl(reg); | |
593 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 594 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 595 | l |= 2 << (gpio << 1); |
6cab4860 | 596 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 597 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
598 | if (trigger) |
599 | /* Enable wake-up during idle for dynamic tick */ | |
600 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
601 | else | |
602 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 603 | break; |
3ac4fa99 JY |
604 | #endif |
605 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
606 | case METHOD_GPIO_730: |
607 | reg += OMAP730_GPIO_INT_CONTROL; | |
608 | l = __raw_readl(reg); | |
6cab4860 | 609 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 610 | l |= 1 << gpio; |
6cab4860 | 611 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 612 | l &= ~(1 << gpio); |
92105bb7 TL |
613 | else |
614 | goto bad; | |
615 | break; | |
3ac4fa99 | 616 | #endif |
5492fb1a | 617 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 618 | case METHOD_GPIO_24XX: |
3ac4fa99 | 619 | set_24xx_gpio_triggering(bank, gpio, trigger); |
5e1c5ff4 | 620 | break; |
3ac4fa99 | 621 | #endif |
5e1c5ff4 | 622 | default: |
92105bb7 | 623 | goto bad; |
5e1c5ff4 | 624 | } |
92105bb7 TL |
625 | __raw_writel(l, reg); |
626 | return 0; | |
627 | bad: | |
628 | return -EINVAL; | |
5e1c5ff4 TL |
629 | } |
630 | ||
92105bb7 | 631 | static int gpio_irq_type(unsigned irq, unsigned type) |
5e1c5ff4 TL |
632 | { |
633 | struct gpio_bank *bank; | |
92105bb7 TL |
634 | unsigned gpio; |
635 | int retval; | |
a6472533 | 636 | unsigned long flags; |
92105bb7 | 637 | |
5492fb1a | 638 | if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) |
92105bb7 TL |
639 | gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); |
640 | else | |
641 | gpio = irq - IH_GPIO_BASE; | |
5e1c5ff4 TL |
642 | |
643 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
644 | return -EINVAL; |
645 | ||
e5c56ed3 | 646 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 647 | return -EINVAL; |
e5c56ed3 DB |
648 | |
649 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 650 | if (!cpu_class_is_omap2() |
e5c56ed3 | 651 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
652 | return -EINVAL; |
653 | ||
58781016 | 654 | bank = get_irq_chip_data(irq); |
a6472533 | 655 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 656 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
b9772a22 DB |
657 | if (retval == 0) { |
658 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
659 | irq_desc[irq].status |= type; | |
660 | } | |
a6472533 | 661 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
662 | |
663 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
664 | __set_irq_handler_unlocked(irq, handle_level_irq); | |
665 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
666 | __set_irq_handler_unlocked(irq, handle_edge_irq); | |
667 | ||
92105bb7 | 668 | return retval; |
5e1c5ff4 TL |
669 | } |
670 | ||
671 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
672 | { | |
92105bb7 | 673 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
674 | |
675 | switch (bank->method) { | |
e5c56ed3 | 676 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
677 | case METHOD_MPUIO: |
678 | /* MPUIO irqstatus is reset by reading the status register, | |
679 | * so do nothing here */ | |
680 | return; | |
e5c56ed3 DB |
681 | #endif |
682 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
683 | case METHOD_GPIO_1510: |
684 | reg += OMAP1510_GPIO_INT_STATUS; | |
685 | break; | |
e5c56ed3 DB |
686 | #endif |
687 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
688 | case METHOD_GPIO_1610: |
689 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
690 | break; | |
e5c56ed3 DB |
691 | #endif |
692 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
693 | case METHOD_GPIO_730: |
694 | reg += OMAP730_GPIO_INT_STATUS; | |
695 | break; | |
e5c56ed3 | 696 | #endif |
5492fb1a | 697 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
698 | case METHOD_GPIO_24XX: |
699 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
700 | break; | |
e5c56ed3 | 701 | #endif |
5e1c5ff4 | 702 | default: |
e5c56ed3 | 703 | WARN_ON(1); |
5e1c5ff4 TL |
704 | return; |
705 | } | |
706 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
707 | |
708 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
5492fb1a SMK |
709 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
710 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
bee7930f | 711 | __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); |
5492fb1a | 712 | #endif |
5e1c5ff4 TL |
713 | } |
714 | ||
715 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
716 | { | |
717 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
718 | } | |
719 | ||
ea6dedd7 ID |
720 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
721 | { | |
722 | void __iomem *reg = bank->base; | |
99c47707 ID |
723 | int inv = 0; |
724 | u32 l; | |
725 | u32 mask; | |
ea6dedd7 ID |
726 | |
727 | switch (bank->method) { | |
e5c56ed3 | 728 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 ID |
729 | case METHOD_MPUIO: |
730 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
99c47707 ID |
731 | mask = 0xffff; |
732 | inv = 1; | |
ea6dedd7 | 733 | break; |
e5c56ed3 DB |
734 | #endif |
735 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
736 | case METHOD_GPIO_1510: |
737 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
738 | mask = 0xffff; |
739 | inv = 1; | |
ea6dedd7 | 740 | break; |
e5c56ed3 DB |
741 | #endif |
742 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
743 | case METHOD_GPIO_1610: |
744 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 745 | mask = 0xffff; |
ea6dedd7 | 746 | break; |
e5c56ed3 DB |
747 | #endif |
748 | #ifdef CONFIG_ARCH_OMAP730 | |
ea6dedd7 ID |
749 | case METHOD_GPIO_730: |
750 | reg += OMAP730_GPIO_INT_MASK; | |
99c47707 ID |
751 | mask = 0xffffffff; |
752 | inv = 1; | |
ea6dedd7 | 753 | break; |
e5c56ed3 | 754 | #endif |
5492fb1a | 755 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
ea6dedd7 ID |
756 | case METHOD_GPIO_24XX: |
757 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 758 | mask = 0xffffffff; |
ea6dedd7 | 759 | break; |
e5c56ed3 | 760 | #endif |
ea6dedd7 | 761 | default: |
e5c56ed3 | 762 | WARN_ON(1); |
ea6dedd7 ID |
763 | return 0; |
764 | } | |
765 | ||
99c47707 ID |
766 | l = __raw_readl(reg); |
767 | if (inv) | |
768 | l = ~l; | |
769 | l &= mask; | |
770 | return l; | |
ea6dedd7 ID |
771 | } |
772 | ||
5e1c5ff4 TL |
773 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
774 | { | |
92105bb7 | 775 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
776 | u32 l; |
777 | ||
778 | switch (bank->method) { | |
e5c56ed3 | 779 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
780 | case METHOD_MPUIO: |
781 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
782 | l = __raw_readl(reg); | |
783 | if (enable) | |
784 | l &= ~(gpio_mask); | |
785 | else | |
786 | l |= gpio_mask; | |
787 | break; | |
e5c56ed3 DB |
788 | #endif |
789 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
790 | case METHOD_GPIO_1510: |
791 | reg += OMAP1510_GPIO_INT_MASK; | |
792 | l = __raw_readl(reg); | |
793 | if (enable) | |
794 | l &= ~(gpio_mask); | |
795 | else | |
796 | l |= gpio_mask; | |
797 | break; | |
e5c56ed3 DB |
798 | #endif |
799 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
800 | case METHOD_GPIO_1610: |
801 | if (enable) | |
802 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
803 | else | |
804 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
805 | l = gpio_mask; | |
806 | break; | |
e5c56ed3 DB |
807 | #endif |
808 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
809 | case METHOD_GPIO_730: |
810 | reg += OMAP730_GPIO_INT_MASK; | |
811 | l = __raw_readl(reg); | |
812 | if (enable) | |
813 | l &= ~(gpio_mask); | |
814 | else | |
815 | l |= gpio_mask; | |
816 | break; | |
e5c56ed3 | 817 | #endif |
5492fb1a | 818 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
819 | case METHOD_GPIO_24XX: |
820 | if (enable) | |
821 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
822 | else | |
823 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
824 | l = gpio_mask; | |
825 | break; | |
e5c56ed3 | 826 | #endif |
5e1c5ff4 | 827 | default: |
e5c56ed3 | 828 | WARN_ON(1); |
5e1c5ff4 TL |
829 | return; |
830 | } | |
831 | __raw_writel(l, reg); | |
832 | } | |
833 | ||
834 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
835 | { | |
836 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
837 | } | |
838 | ||
92105bb7 TL |
839 | /* |
840 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
841 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
842 | * to the target, system will wake up always on GPIO events. While | |
843 | * system is running all registered GPIO interrupts need to have wake-up | |
844 | * enabled. When system is suspended, only selected GPIO interrupts need | |
845 | * to have wake-up enabled. | |
846 | */ | |
847 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
848 | { | |
a6472533 DB |
849 | unsigned long flags; |
850 | ||
92105bb7 | 851 | switch (bank->method) { |
3ac4fa99 | 852 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 853 | case METHOD_MPUIO: |
92105bb7 | 854 | case METHOD_GPIO_1610: |
a6472533 | 855 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 856 | if (enable) { |
92105bb7 | 857 | bank->suspend_wakeup |= (1 << gpio); |
11a78b79 DB |
858 | enable_irq_wake(bank->irq); |
859 | } else { | |
860 | disable_irq_wake(bank->irq); | |
92105bb7 | 861 | bank->suspend_wakeup &= ~(1 << gpio); |
11a78b79 | 862 | } |
a6472533 | 863 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 864 | return 0; |
3ac4fa99 | 865 | #endif |
5492fb1a | 866 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 | 867 | case METHOD_GPIO_24XX: |
11a78b79 DB |
868 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
869 | printk(KERN_ERR "Unable to modify wakeup on " | |
870 | "non-wakeup GPIO%d\n", | |
871 | (bank - gpio_bank) * 32 + gpio); | |
872 | return -EINVAL; | |
873 | } | |
a6472533 | 874 | spin_lock_irqsave(&bank->lock, flags); |
3ac4fa99 | 875 | if (enable) { |
3ac4fa99 | 876 | bank->suspend_wakeup |= (1 << gpio); |
11a78b79 DB |
877 | enable_irq_wake(bank->irq); |
878 | } else { | |
879 | disable_irq_wake(bank->irq); | |
3ac4fa99 | 880 | bank->suspend_wakeup &= ~(1 << gpio); |
11a78b79 | 881 | } |
a6472533 | 882 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
883 | return 0; |
884 | #endif | |
92105bb7 TL |
885 | default: |
886 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
887 | bank->method); | |
888 | return -EINVAL; | |
889 | } | |
890 | } | |
891 | ||
4196dd6b TL |
892 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
893 | { | |
894 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
895 | _set_gpio_irqenable(bank, gpio, 0); | |
896 | _clear_gpio_irqstatus(bank, gpio); | |
6cab4860 | 897 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
898 | } |
899 | ||
92105bb7 TL |
900 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
901 | static int gpio_wake_enable(unsigned int irq, unsigned int enable) | |
902 | { | |
903 | unsigned int gpio = irq - IH_GPIO_BASE; | |
904 | struct gpio_bank *bank; | |
905 | int retval; | |
906 | ||
907 | if (check_gpio(gpio) < 0) | |
908 | return -ENODEV; | |
58781016 | 909 | bank = get_irq_chip_data(irq); |
92105bb7 | 910 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
911 | |
912 | return retval; | |
913 | } | |
914 | ||
5e1c5ff4 TL |
915 | int omap_request_gpio(int gpio) |
916 | { | |
917 | struct gpio_bank *bank; | |
a6472533 | 918 | unsigned long flags; |
52e31344 | 919 | int status; |
5e1c5ff4 TL |
920 | |
921 | if (check_gpio(gpio) < 0) | |
922 | return -EINVAL; | |
923 | ||
52e31344 DB |
924 | status = gpio_request(gpio, NULL); |
925 | if (status < 0) | |
926 | return status; | |
927 | ||
5e1c5ff4 | 928 | bank = get_gpio_bank(gpio); |
a6472533 | 929 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 930 | |
4196dd6b TL |
931 | /* Set trigger to none. You need to enable the desired trigger with |
932 | * request_irq() or set_irq_type(). | |
933 | */ | |
6cab4860 | 934 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
92105bb7 | 935 | |
1a8bfa1e | 936 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 937 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 938 | void __iomem *reg; |
5e1c5ff4 | 939 | |
92105bb7 | 940 | /* Claim the pin for MPU */ |
5e1c5ff4 TL |
941 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
942 | __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); | |
943 | } | |
944 | #endif | |
a6472533 | 945 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
946 | |
947 | return 0; | |
948 | } | |
949 | ||
950 | void omap_free_gpio(int gpio) | |
951 | { | |
952 | struct gpio_bank *bank; | |
a6472533 | 953 | unsigned long flags; |
5e1c5ff4 TL |
954 | |
955 | if (check_gpio(gpio) < 0) | |
956 | return; | |
957 | bank = get_gpio_bank(gpio); | |
a6472533 | 958 | spin_lock_irqsave(&bank->lock, flags); |
52e31344 DB |
959 | if (unlikely(!gpiochip_is_requested(&bank->chip, |
960 | get_gpio_index(gpio)))) { | |
961 | spin_unlock_irqrestore(&bank->lock, flags); | |
5e1c5ff4 TL |
962 | printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); |
963 | dump_stack(); | |
5e1c5ff4 TL |
964 | return; |
965 | } | |
92105bb7 TL |
966 | #ifdef CONFIG_ARCH_OMAP16XX |
967 | if (bank->method == METHOD_GPIO_1610) { | |
968 | /* Disable wake-up during idle for dynamic tick */ | |
969 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
970 | __raw_writel(1 << get_gpio_index(gpio), reg); | |
971 | } | |
972 | #endif | |
5492fb1a | 973 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
974 | if (bank->method == METHOD_GPIO_24XX) { |
975 | /* Disable wake-up during idle for dynamic tick */ | |
976 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
977 | __raw_writel(1 << get_gpio_index(gpio), reg); | |
978 | } | |
979 | #endif | |
4196dd6b | 980 | _reset_gpio(bank, gpio); |
a6472533 | 981 | spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 | 982 | gpio_free(gpio); |
5e1c5ff4 TL |
983 | } |
984 | ||
985 | /* | |
986 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
987 | * avoid missing GPIO interrupts for other lines in the bank. | |
988 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
989 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
990 | * If we wait to unmask individual GPIO lines in the bank after the | |
991 | * line's interrupt handler has been run, we may miss some nested | |
992 | * interrupts. | |
993 | */ | |
10dd5ce2 | 994 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 995 | { |
92105bb7 | 996 | void __iomem *isr_reg = NULL; |
5e1c5ff4 TL |
997 | u32 isr; |
998 | unsigned int gpio_irq; | |
999 | struct gpio_bank *bank; | |
ea6dedd7 ID |
1000 | u32 retrigger = 0; |
1001 | int unmasked = 0; | |
5e1c5ff4 TL |
1002 | |
1003 | desc->chip->ack(irq); | |
1004 | ||
418ca1f0 | 1005 | bank = get_irq_data(irq); |
e5c56ed3 | 1006 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
1007 | if (bank->method == METHOD_MPUIO) |
1008 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | |
e5c56ed3 | 1009 | #endif |
1a8bfa1e | 1010 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
1011 | if (bank->method == METHOD_GPIO_1510) |
1012 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
1013 | #endif | |
1014 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1015 | if (bank->method == METHOD_GPIO_1610) | |
1016 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
1017 | #endif | |
1018 | #ifdef CONFIG_ARCH_OMAP730 | |
1019 | if (bank->method == METHOD_GPIO_730) | |
1020 | isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; | |
1021 | #endif | |
5492fb1a | 1022 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1023 | if (bank->method == METHOD_GPIO_24XX) |
1024 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
1025 | #endif | |
92105bb7 | 1026 | while(1) { |
6e60e79a | 1027 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 1028 | u32 enabled; |
6e60e79a | 1029 | |
ea6dedd7 ID |
1030 | enabled = _get_gpio_irqbank_mask(bank); |
1031 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
1032 | |
1033 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
1034 | isr &= 0x0000ffff; | |
1035 | ||
5492fb1a | 1036 | if (cpu_class_is_omap2()) { |
b144ff6f | 1037 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 1038 | } |
6e60e79a TL |
1039 | |
1040 | /* clear edge sensitive interrupts before handler(s) are | |
1041 | called so that we don't miss any interrupt occurred while | |
1042 | executing them */ | |
1043 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1044 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1045 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1046 | ||
1047 | /* if there is only edge sensitive GPIO pin interrupts | |
1048 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1049 | if (!level_mask && !unmasked) { |
1050 | unmasked = 1; | |
6e60e79a | 1051 | desc->chip->unmask(irq); |
ea6dedd7 | 1052 | } |
92105bb7 | 1053 | |
ea6dedd7 ID |
1054 | isr |= retrigger; |
1055 | retrigger = 0; | |
92105bb7 TL |
1056 | if (!isr) |
1057 | break; | |
1058 | ||
1059 | gpio_irq = bank->virtual_irq_start; | |
1060 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
92105bb7 TL |
1061 | if (!(isr & 1)) |
1062 | continue; | |
29454dde | 1063 | |
d8aa0251 | 1064 | generic_handle_irq(gpio_irq); |
92105bb7 | 1065 | } |
1a8bfa1e | 1066 | } |
ea6dedd7 ID |
1067 | /* if bank has any level sensitive GPIO pin interrupt |
1068 | configured, we must unmask the bank interrupt only after | |
1069 | handler(s) are executed in order to avoid spurious bank | |
1070 | interrupt */ | |
1071 | if (!unmasked) | |
1072 | desc->chip->unmask(irq); | |
1073 | ||
5e1c5ff4 TL |
1074 | } |
1075 | ||
4196dd6b TL |
1076 | static void gpio_irq_shutdown(unsigned int irq) |
1077 | { | |
1078 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1079 | struct gpio_bank *bank = get_irq_chip_data(irq); |
4196dd6b TL |
1080 | |
1081 | _reset_gpio(bank, gpio); | |
1082 | } | |
1083 | ||
5e1c5ff4 TL |
1084 | static void gpio_ack_irq(unsigned int irq) |
1085 | { | |
1086 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1087 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1088 | |
1089 | _clear_gpio_irqstatus(bank, gpio); | |
1090 | } | |
1091 | ||
1092 | static void gpio_mask_irq(unsigned int irq) | |
1093 | { | |
1094 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1095 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1096 | |
1097 | _set_gpio_irqenable(bank, gpio, 0); | |
1098 | } | |
1099 | ||
1100 | static void gpio_unmask_irq(unsigned int irq) | |
1101 | { | |
1102 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1103 | struct gpio_bank *bank = get_irq_chip_data(irq); |
b144ff6f KH |
1104 | unsigned int irq_mask = 1 << get_gpio_index(gpio); |
1105 | ||
1106 | /* For level-triggered GPIOs, the clearing must be done after | |
1107 | * the HW source is cleared, thus after the handler has run */ | |
1108 | if (bank->level_mask & irq_mask) { | |
1109 | _set_gpio_irqenable(bank, gpio, 0); | |
1110 | _clear_gpio_irqstatus(bank, gpio); | |
1111 | } | |
5e1c5ff4 | 1112 | |
4de8c75b | 1113 | _set_gpio_irqenable(bank, gpio, 1); |
5e1c5ff4 TL |
1114 | } |
1115 | ||
e5c56ed3 DB |
1116 | static struct irq_chip gpio_irq_chip = { |
1117 | .name = "GPIO", | |
1118 | .shutdown = gpio_irq_shutdown, | |
1119 | .ack = gpio_ack_irq, | |
1120 | .mask = gpio_mask_irq, | |
1121 | .unmask = gpio_unmask_irq, | |
1122 | .set_type = gpio_irq_type, | |
1123 | .set_wake = gpio_wake_enable, | |
1124 | }; | |
1125 | ||
1126 | /*---------------------------------------------------------------------*/ | |
1127 | ||
1128 | #ifdef CONFIG_ARCH_OMAP1 | |
1129 | ||
1130 | /* MPUIO uses the always-on 32k clock */ | |
1131 | ||
5e1c5ff4 TL |
1132 | static void mpuio_ack_irq(unsigned int irq) |
1133 | { | |
1134 | /* The ISR is reset automatically, so do nothing here. */ | |
1135 | } | |
1136 | ||
1137 | static void mpuio_mask_irq(unsigned int irq) | |
1138 | { | |
1139 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1140 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1141 | |
1142 | _set_gpio_irqenable(bank, gpio, 0); | |
1143 | } | |
1144 | ||
1145 | static void mpuio_unmask_irq(unsigned int irq) | |
1146 | { | |
1147 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1148 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1149 | |
1150 | _set_gpio_irqenable(bank, gpio, 1); | |
1151 | } | |
1152 | ||
e5c56ed3 DB |
1153 | static struct irq_chip mpuio_irq_chip = { |
1154 | .name = "MPUIO", | |
1155 | .ack = mpuio_ack_irq, | |
1156 | .mask = mpuio_mask_irq, | |
1157 | .unmask = mpuio_unmask_irq, | |
92105bb7 | 1158 | .set_type = gpio_irq_type, |
11a78b79 DB |
1159 | #ifdef CONFIG_ARCH_OMAP16XX |
1160 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1161 | .set_wake = gpio_wake_enable, | |
1162 | #endif | |
5e1c5ff4 TL |
1163 | }; |
1164 | ||
e5c56ed3 DB |
1165 | |
1166 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1167 | ||
11a78b79 DB |
1168 | |
1169 | #ifdef CONFIG_ARCH_OMAP16XX | |
1170 | ||
1171 | #include <linux/platform_device.h> | |
1172 | ||
1173 | static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg) | |
1174 | { | |
1175 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1176 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1177 | unsigned long flags; |
11a78b79 | 1178 | |
a6472533 | 1179 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1180 | bank->saved_wakeup = __raw_readl(mask_reg); |
1181 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1182 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1183 | |
1184 | return 0; | |
1185 | } | |
1186 | ||
1187 | static int omap_mpuio_resume_early(struct platform_device *pdev) | |
1188 | { | |
1189 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1190 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1191 | unsigned long flags; |
11a78b79 | 1192 | |
a6472533 | 1193 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1194 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1195 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1196 | |
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | /* use platform_driver for this, now that there's no longer any | |
1201 | * point to sys_device (other than not disturbing old code). | |
1202 | */ | |
1203 | static struct platform_driver omap_mpuio_driver = { | |
1204 | .suspend_late = omap_mpuio_suspend_late, | |
1205 | .resume_early = omap_mpuio_resume_early, | |
1206 | .driver = { | |
1207 | .name = "mpuio", | |
1208 | }, | |
1209 | }; | |
1210 | ||
1211 | static struct platform_device omap_mpuio_device = { | |
1212 | .name = "mpuio", | |
1213 | .id = -1, | |
1214 | .dev = { | |
1215 | .driver = &omap_mpuio_driver.driver, | |
1216 | } | |
1217 | /* could list the /proc/iomem resources */ | |
1218 | }; | |
1219 | ||
1220 | static inline void mpuio_init(void) | |
1221 | { | |
fcf126d8 DB |
1222 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); |
1223 | ||
11a78b79 DB |
1224 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1225 | (void) platform_device_register(&omap_mpuio_device); | |
1226 | } | |
1227 | ||
1228 | #else | |
1229 | static inline void mpuio_init(void) {} | |
1230 | #endif /* 16xx */ | |
1231 | ||
e5c56ed3 DB |
1232 | #else |
1233 | ||
1234 | extern struct irq_chip mpuio_irq_chip; | |
1235 | ||
1236 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1237 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1238 | |
1239 | #endif | |
1240 | ||
1241 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1242 | |
52e31344 DB |
1243 | /* REVISIT these are stupid implementations! replace by ones that |
1244 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1245 | */ | |
1246 | ||
1247 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1248 | { | |
1249 | struct gpio_bank *bank; | |
1250 | unsigned long flags; | |
1251 | ||
1252 | bank = container_of(chip, struct gpio_bank, chip); | |
1253 | spin_lock_irqsave(&bank->lock, flags); | |
1254 | _set_gpio_direction(bank, offset, 1); | |
1255 | spin_unlock_irqrestore(&bank->lock, flags); | |
1256 | return 0; | |
1257 | } | |
1258 | ||
1259 | static int gpio_get(struct gpio_chip *chip, unsigned offset) | |
1260 | { | |
1261 | return omap_get_gpio_datain(chip->base + offset); | |
1262 | } | |
1263 | ||
1264 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1265 | { | |
1266 | struct gpio_bank *bank; | |
1267 | unsigned long flags; | |
1268 | ||
1269 | bank = container_of(chip, struct gpio_bank, chip); | |
1270 | spin_lock_irqsave(&bank->lock, flags); | |
1271 | _set_gpio_dataout(bank, offset, value); | |
1272 | _set_gpio_direction(bank, offset, 0); | |
1273 | spin_unlock_irqrestore(&bank->lock, flags); | |
1274 | return 0; | |
1275 | } | |
1276 | ||
1277 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
1278 | { | |
1279 | struct gpio_bank *bank; | |
1280 | unsigned long flags; | |
1281 | ||
1282 | bank = container_of(chip, struct gpio_bank, chip); | |
1283 | spin_lock_irqsave(&bank->lock, flags); | |
1284 | _set_gpio_dataout(bank, offset, value); | |
1285 | spin_unlock_irqrestore(&bank->lock, flags); | |
1286 | } | |
1287 | ||
1288 | /*---------------------------------------------------------------------*/ | |
1289 | ||
1a8bfa1e | 1290 | static int initialized; |
5492fb1a | 1291 | #if !defined(CONFIG_ARCH_OMAP3) |
1a8bfa1e | 1292 | static struct clk * gpio_ick; |
5492fb1a SMK |
1293 | #endif |
1294 | ||
1295 | #if defined(CONFIG_ARCH_OMAP2) | |
1a8bfa1e | 1296 | static struct clk * gpio_fck; |
5492fb1a | 1297 | #endif |
5e1c5ff4 | 1298 | |
5492fb1a | 1299 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1300 | static struct clk * gpio5_ick; |
1301 | static struct clk * gpio5_fck; | |
1302 | #endif | |
1303 | ||
5492fb1a | 1304 | #if defined(CONFIG_ARCH_OMAP3) |
5492fb1a SMK |
1305 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; |
1306 | #endif | |
1307 | ||
8ba55c5c DB |
1308 | /* This lock class tells lockdep that GPIO irqs are in a different |
1309 | * category than their parents, so it won't report false recursion. | |
1310 | */ | |
1311 | static struct lock_class_key gpio_lock_class; | |
1312 | ||
5e1c5ff4 TL |
1313 | static int __init _omap_gpio_init(void) |
1314 | { | |
1315 | int i; | |
52e31344 | 1316 | int gpio = 0; |
5e1c5ff4 | 1317 | struct gpio_bank *bank; |
5492fb1a | 1318 | char clk_name[11]; |
5e1c5ff4 TL |
1319 | |
1320 | initialized = 1; | |
1321 | ||
5492fb1a | 1322 | #if defined(CONFIG_ARCH_OMAP1) |
6e60e79a | 1323 | if (cpu_is_omap15xx()) { |
1a8bfa1e TL |
1324 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); |
1325 | if (IS_ERR(gpio_ick)) | |
92105bb7 TL |
1326 | printk("Could not get arm_gpio_ck\n"); |
1327 | else | |
30ff720b | 1328 | clk_enable(gpio_ick); |
1a8bfa1e | 1329 | } |
5492fb1a SMK |
1330 | #endif |
1331 | #if defined(CONFIG_ARCH_OMAP2) | |
1332 | if (cpu_class_is_omap2()) { | |
1a8bfa1e TL |
1333 | gpio_ick = clk_get(NULL, "gpios_ick"); |
1334 | if (IS_ERR(gpio_ick)) | |
1335 | printk("Could not get gpios_ick\n"); | |
1336 | else | |
30ff720b | 1337 | clk_enable(gpio_ick); |
1a8bfa1e | 1338 | gpio_fck = clk_get(NULL, "gpios_fck"); |
1630b52d | 1339 | if (IS_ERR(gpio_fck)) |
1a8bfa1e TL |
1340 | printk("Could not get gpios_fck\n"); |
1341 | else | |
30ff720b | 1342 | clk_enable(gpio_fck); |
56a25641 SMK |
1343 | |
1344 | /* | |
5492fb1a | 1345 | * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK |
56a25641 | 1346 | */ |
5492fb1a | 1347 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1348 | if (cpu_is_omap2430()) { |
1349 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | |
1350 | if (IS_ERR(gpio5_ick)) | |
1351 | printk("Could not get gpio5_ick\n"); | |
1352 | else | |
1353 | clk_enable(gpio5_ick); | |
1354 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | |
1355 | if (IS_ERR(gpio5_fck)) | |
1356 | printk("Could not get gpio5_fck\n"); | |
1357 | else | |
1358 | clk_enable(gpio5_fck); | |
1359 | } | |
1360 | #endif | |
5492fb1a SMK |
1361 | } |
1362 | #endif | |
1363 | ||
1364 | #if defined(CONFIG_ARCH_OMAP3) | |
1365 | if (cpu_is_omap34xx()) { | |
1366 | for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { | |
1367 | sprintf(clk_name, "gpio%d_ick", i + 1); | |
1368 | gpio_iclks[i] = clk_get(NULL, clk_name); | |
1369 | if (IS_ERR(gpio_iclks[i])) | |
1370 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1371 | else | |
1372 | clk_enable(gpio_iclks[i]); | |
5492fb1a SMK |
1373 | } |
1374 | } | |
1375 | #endif | |
1376 | ||
92105bb7 | 1377 | |
1a8bfa1e | 1378 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 1379 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
1380 | printk(KERN_INFO "OMAP1510 GPIO hardware\n"); |
1381 | gpio_bank_count = 2; | |
1382 | gpio_bank = gpio_bank_1510; | |
1383 | } | |
1384 | #endif | |
1385 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1386 | if (cpu_is_omap16xx()) { | |
92105bb7 | 1387 | u32 rev; |
5e1c5ff4 TL |
1388 | |
1389 | gpio_bank_count = 5; | |
1390 | gpio_bank = gpio_bank_1610; | |
7c7095aa | 1391 | rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); |
5e1c5ff4 TL |
1392 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", |
1393 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1394 | } | |
1395 | #endif | |
1396 | #ifdef CONFIG_ARCH_OMAP730 | |
1397 | if (cpu_is_omap730()) { | |
1398 | printk(KERN_INFO "OMAP730 GPIO hardware\n"); | |
1399 | gpio_bank_count = 7; | |
1400 | gpio_bank = gpio_bank_730; | |
1401 | } | |
92105bb7 | 1402 | #endif |
56a25641 | 1403 | |
92105bb7 | 1404 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 | 1405 | if (cpu_is_omap242x()) { |
92105bb7 TL |
1406 | int rev; |
1407 | ||
1408 | gpio_bank_count = 4; | |
56a25641 | 1409 | gpio_bank = gpio_bank_242x; |
7c7095aa | 1410 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
56a25641 SMK |
1411 | printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", |
1412 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1413 | } | |
1414 | if (cpu_is_omap243x()) { | |
1415 | int rev; | |
1416 | ||
1417 | gpio_bank_count = 5; | |
1418 | gpio_bank = gpio_bank_243x; | |
7c7095aa | 1419 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
56a25641 | 1420 | printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", |
92105bb7 TL |
1421 | (rev >> 4) & 0x0f, rev & 0x0f); |
1422 | } | |
5492fb1a SMK |
1423 | #endif |
1424 | #ifdef CONFIG_ARCH_OMAP34XX | |
1425 | if (cpu_is_omap34xx()) { | |
1426 | int rev; | |
1427 | ||
1428 | gpio_bank_count = OMAP34XX_NR_GPIOS; | |
1429 | gpio_bank = gpio_bank_34xx; | |
7c7095aa | 1430 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
5492fb1a SMK |
1431 | printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n", |
1432 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1433 | } | |
5e1c5ff4 TL |
1434 | #endif |
1435 | for (i = 0; i < gpio_bank_count; i++) { | |
1436 | int j, gpio_count = 16; | |
1437 | ||
1438 | bank = &gpio_bank[i]; | |
5e1c5ff4 | 1439 | spin_lock_init(&bank->lock); |
e5c56ed3 | 1440 | if (bank_is_mpuio(bank)) |
7c7095aa | 1441 | __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); |
d11ac979 | 1442 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
5e1c5ff4 TL |
1443 | __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); |
1444 | __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); | |
1445 | } | |
d11ac979 | 1446 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { |
5e1c5ff4 TL |
1447 | __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); |
1448 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | |
92105bb7 | 1449 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
5e1c5ff4 | 1450 | } |
d11ac979 | 1451 | if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) { |
5e1c5ff4 TL |
1452 | __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); |
1453 | __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); | |
1454 | ||
1455 | gpio_count = 32; /* 730 has 32-bit GPIOs */ | |
1456 | } | |
d11ac979 | 1457 | |
5492fb1a | 1458 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1459 | if (bank->method == METHOD_GPIO_24XX) { |
3ac4fa99 JY |
1460 | static const u32 non_wakeup_gpios[] = { |
1461 | 0xe203ffc0, 0x08700040 | |
1462 | }; | |
1463 | ||
92105bb7 TL |
1464 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); |
1465 | __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); | |
14f1c3bf JY |
1466 | __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); |
1467 | ||
1468 | /* Initialize interface clock ungated, module enabled */ | |
1469 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
3ac4fa99 JY |
1470 | if (i < ARRAY_SIZE(non_wakeup_gpios)) |
1471 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; | |
92105bb7 TL |
1472 | gpio_count = 32; |
1473 | } | |
5e1c5ff4 | 1474 | #endif |
52e31344 DB |
1475 | |
1476 | /* REVISIT eventually switch from OMAP-specific gpio structs | |
1477 | * over to the generic ones | |
1478 | */ | |
1479 | bank->chip.direction_input = gpio_input; | |
1480 | bank->chip.get = gpio_get; | |
1481 | bank->chip.direction_output = gpio_output; | |
1482 | bank->chip.set = gpio_set; | |
1483 | if (bank_is_mpuio(bank)) { | |
1484 | bank->chip.label = "mpuio"; | |
69114a47 | 1485 | #ifdef CONFIG_ARCH_OMAP16XX |
d8f388d8 DB |
1486 | bank->chip.dev = &omap_mpuio_device.dev; |
1487 | #endif | |
52e31344 DB |
1488 | bank->chip.base = OMAP_MPUIO(0); |
1489 | } else { | |
1490 | bank->chip.label = "gpio"; | |
1491 | bank->chip.base = gpio; | |
1492 | gpio += gpio_count; | |
1493 | } | |
1494 | bank->chip.ngpio = gpio_count; | |
1495 | ||
1496 | gpiochip_add(&bank->chip); | |
1497 | ||
5e1c5ff4 TL |
1498 | for (j = bank->virtual_irq_start; |
1499 | j < bank->virtual_irq_start + gpio_count; j++) { | |
8ba55c5c | 1500 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); |
58781016 | 1501 | set_irq_chip_data(j, bank); |
e5c56ed3 | 1502 | if (bank_is_mpuio(bank)) |
5e1c5ff4 TL |
1503 | set_irq_chip(j, &mpuio_irq_chip); |
1504 | else | |
1505 | set_irq_chip(j, &gpio_irq_chip); | |
10dd5ce2 | 1506 | set_irq_handler(j, handle_simple_irq); |
5e1c5ff4 TL |
1507 | set_irq_flags(j, IRQF_VALID); |
1508 | } | |
1509 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | |
1510 | set_irq_data(bank->irq, bank); | |
89db9482 JH |
1511 | |
1512 | if (cpu_is_omap34xx()) { | |
1513 | sprintf(clk_name, "gpio%d_dbck", i + 1); | |
1514 | bank->dbck = clk_get(NULL, clk_name); | |
1515 | if (IS_ERR(bank->dbck)) | |
1516 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1517 | } | |
5e1c5ff4 TL |
1518 | } |
1519 | ||
1520 | /* Enable system clock for GPIO module. | |
1521 | * The CAM_CLK_CTRL *is* really the right place. */ | |
92105bb7 | 1522 | if (cpu_is_omap16xx()) |
5e1c5ff4 TL |
1523 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); |
1524 | ||
14f1c3bf JY |
1525 | /* Enable autoidle for the OCP interface */ |
1526 | if (cpu_is_omap24xx()) | |
1527 | omap_writel(1 << 0, 0x48019010); | |
5492fb1a SMK |
1528 | if (cpu_is_omap34xx()) |
1529 | omap_writel(1 << 0, 0x48306814); | |
d11ac979 | 1530 | |
5e1c5ff4 TL |
1531 | return 0; |
1532 | } | |
1533 | ||
5492fb1a | 1534 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1535 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) |
1536 | { | |
1537 | int i; | |
1538 | ||
5492fb1a | 1539 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1540 | return 0; |
1541 | ||
1542 | for (i = 0; i < gpio_bank_count; i++) { | |
1543 | struct gpio_bank *bank = &gpio_bank[i]; | |
1544 | void __iomem *wake_status; | |
1545 | void __iomem *wake_clear; | |
1546 | void __iomem *wake_set; | |
a6472533 | 1547 | unsigned long flags; |
92105bb7 TL |
1548 | |
1549 | switch (bank->method) { | |
e5c56ed3 | 1550 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1551 | case METHOD_GPIO_1610: |
1552 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1553 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1554 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1555 | break; | |
e5c56ed3 | 1556 | #endif |
5492fb1a | 1557 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1558 | case METHOD_GPIO_24XX: |
723fdb78 | 1559 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1560 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1561 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1562 | break; | |
e5c56ed3 | 1563 | #endif |
92105bb7 TL |
1564 | default: |
1565 | continue; | |
1566 | } | |
1567 | ||
a6472533 | 1568 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1569 | bank->saved_wakeup = __raw_readl(wake_status); |
1570 | __raw_writel(0xffffffff, wake_clear); | |
1571 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1572 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1573 | } |
1574 | ||
1575 | return 0; | |
1576 | } | |
1577 | ||
1578 | static int omap_gpio_resume(struct sys_device *dev) | |
1579 | { | |
1580 | int i; | |
1581 | ||
723fdb78 | 1582 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1583 | return 0; |
1584 | ||
1585 | for (i = 0; i < gpio_bank_count; i++) { | |
1586 | struct gpio_bank *bank = &gpio_bank[i]; | |
1587 | void __iomem *wake_clear; | |
1588 | void __iomem *wake_set; | |
a6472533 | 1589 | unsigned long flags; |
92105bb7 TL |
1590 | |
1591 | switch (bank->method) { | |
e5c56ed3 | 1592 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1593 | case METHOD_GPIO_1610: |
1594 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1595 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1596 | break; | |
e5c56ed3 | 1597 | #endif |
5492fb1a | 1598 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1599 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1600 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1601 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1602 | break; |
e5c56ed3 | 1603 | #endif |
92105bb7 TL |
1604 | default: |
1605 | continue; | |
1606 | } | |
1607 | ||
a6472533 | 1608 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1609 | __raw_writel(0xffffffff, wake_clear); |
1610 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 1611 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1612 | } |
1613 | ||
1614 | return 0; | |
1615 | } | |
1616 | ||
1617 | static struct sysdev_class omap_gpio_sysclass = { | |
af5ca3f4 | 1618 | .name = "gpio", |
92105bb7 TL |
1619 | .suspend = omap_gpio_suspend, |
1620 | .resume = omap_gpio_resume, | |
1621 | }; | |
1622 | ||
1623 | static struct sys_device omap_gpio_device = { | |
1624 | .id = 0, | |
1625 | .cls = &omap_gpio_sysclass, | |
1626 | }; | |
3ac4fa99 JY |
1627 | |
1628 | #endif | |
1629 | ||
5492fb1a | 1630 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1631 | |
1632 | static int workaround_enabled; | |
1633 | ||
1634 | void omap2_gpio_prepare_for_retention(void) | |
1635 | { | |
1636 | int i, c = 0; | |
1637 | ||
1638 | /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious | |
1639 | * IRQs will be generated. See OMAP2420 Errata item 1.101. */ | |
1640 | for (i = 0; i < gpio_bank_count; i++) { | |
1641 | struct gpio_bank *bank = &gpio_bank[i]; | |
1642 | u32 l1, l2; | |
1643 | ||
1644 | if (!(bank->enabled_non_wakeup_gpios)) | |
1645 | continue; | |
5492fb1a | 1646 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1647 | bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
1648 | l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1649 | l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1650 | #endif |
3ac4fa99 JY |
1651 | bank->saved_fallingdetect = l1; |
1652 | bank->saved_risingdetect = l2; | |
1653 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1654 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
5492fb1a | 1655 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1656 | __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
1657 | __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1658 | #endif |
3ac4fa99 JY |
1659 | c++; |
1660 | } | |
1661 | if (!c) { | |
1662 | workaround_enabled = 0; | |
1663 | return; | |
1664 | } | |
1665 | workaround_enabled = 1; | |
1666 | } | |
1667 | ||
1668 | void omap2_gpio_resume_after_retention(void) | |
1669 | { | |
1670 | int i; | |
1671 | ||
1672 | if (!workaround_enabled) | |
1673 | return; | |
1674 | for (i = 0; i < gpio_bank_count; i++) { | |
1675 | struct gpio_bank *bank = &gpio_bank[i]; | |
1676 | u32 l; | |
1677 | ||
1678 | if (!(bank->enabled_non_wakeup_gpios)) | |
1679 | continue; | |
5492fb1a | 1680 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1681 | __raw_writel(bank->saved_fallingdetect, |
1682 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1683 | __raw_writel(bank->saved_risingdetect, | |
1684 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1685 | #endif |
3ac4fa99 JY |
1686 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1687 | * state. If so, generate an IRQ by software. This is | |
1688 | * horribly racy, but it's the best we can do to work around | |
1689 | * this silicon bug. */ | |
5492fb1a | 1690 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 | 1691 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
5492fb1a | 1692 | #endif |
3ac4fa99 JY |
1693 | l ^= bank->saved_datain; |
1694 | l &= bank->non_wakeup_gpios; | |
1695 | if (l) { | |
1696 | u32 old0, old1; | |
5492fb1a | 1697 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1698 | old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); |
1699 | old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1700 | __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1701 | __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1702 | __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1703 | __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
5492fb1a | 1704 | #endif |
3ac4fa99 JY |
1705 | } |
1706 | } | |
1707 | ||
1708 | } | |
1709 | ||
92105bb7 TL |
1710 | #endif |
1711 | ||
5e1c5ff4 TL |
1712 | /* |
1713 | * This may get called early from board specific init | |
1a8bfa1e | 1714 | * for boards that have interrupts routed via FPGA. |
5e1c5ff4 | 1715 | */ |
277d58ef | 1716 | int __init omap_gpio_init(void) |
5e1c5ff4 TL |
1717 | { |
1718 | if (!initialized) | |
1719 | return _omap_gpio_init(); | |
1720 | else | |
1721 | return 0; | |
1722 | } | |
1723 | ||
92105bb7 TL |
1724 | static int __init omap_gpio_sysinit(void) |
1725 | { | |
1726 | int ret = 0; | |
1727 | ||
1728 | if (!initialized) | |
1729 | ret = _omap_gpio_init(); | |
1730 | ||
11a78b79 DB |
1731 | mpuio_init(); |
1732 | ||
5492fb1a SMK |
1733 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
1734 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { | |
92105bb7 TL |
1735 | if (ret == 0) { |
1736 | ret = sysdev_class_register(&omap_gpio_sysclass); | |
1737 | if (ret == 0) | |
1738 | ret = sysdev_register(&omap_gpio_device); | |
1739 | } | |
1740 | } | |
1741 | #endif | |
1742 | ||
1743 | return ret; | |
1744 | } | |
1745 | ||
5e1c5ff4 TL |
1746 | EXPORT_SYMBOL(omap_request_gpio); |
1747 | EXPORT_SYMBOL(omap_free_gpio); | |
1748 | EXPORT_SYMBOL(omap_set_gpio_direction); | |
1749 | EXPORT_SYMBOL(omap_set_gpio_dataout); | |
1750 | EXPORT_SYMBOL(omap_get_gpio_datain); | |
5e1c5ff4 | 1751 | |
92105bb7 | 1752 | arch_initcall(omap_gpio_sysinit); |
b9772a22 DB |
1753 | |
1754 | ||
1755 | #ifdef CONFIG_DEBUG_FS | |
1756 | ||
1757 | #include <linux/debugfs.h> | |
1758 | #include <linux/seq_file.h> | |
1759 | ||
1760 | static int gpio_is_input(struct gpio_bank *bank, int mask) | |
1761 | { | |
1762 | void __iomem *reg = bank->base; | |
1763 | ||
1764 | switch (bank->method) { | |
1765 | case METHOD_MPUIO: | |
1766 | reg += OMAP_MPUIO_IO_CNTL; | |
1767 | break; | |
1768 | case METHOD_GPIO_1510: | |
1769 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1770 | break; | |
1771 | case METHOD_GPIO_1610: | |
1772 | reg += OMAP1610_GPIO_DIRECTION; | |
1773 | break; | |
1774 | case METHOD_GPIO_730: | |
1775 | reg += OMAP730_GPIO_DIR_CONTROL; | |
1776 | break; | |
1777 | case METHOD_GPIO_24XX: | |
1778 | reg += OMAP24XX_GPIO_OE; | |
1779 | break; | |
1780 | } | |
1781 | return __raw_readl(reg) & mask; | |
1782 | } | |
1783 | ||
1784 | ||
1785 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
1786 | { | |
1787 | unsigned i, j, gpio; | |
1788 | ||
1789 | for (i = 0, gpio = 0; i < gpio_bank_count; i++) { | |
1790 | struct gpio_bank *bank = gpio_bank + i; | |
1791 | unsigned bankwidth = 16; | |
1792 | u32 mask = 1; | |
1793 | ||
e5c56ed3 | 1794 | if (bank_is_mpuio(bank)) |
b9772a22 | 1795 | gpio = OMAP_MPUIO(0); |
5492fb1a | 1796 | else if (cpu_class_is_omap2() || cpu_is_omap730()) |
b9772a22 DB |
1797 | bankwidth = 32; |
1798 | ||
1799 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | |
1800 | unsigned irq, value, is_in, irqstat; | |
52e31344 | 1801 | const char *label; |
b9772a22 | 1802 | |
52e31344 DB |
1803 | label = gpiochip_is_requested(&bank->chip, j); |
1804 | if (!label) | |
b9772a22 DB |
1805 | continue; |
1806 | ||
1807 | irq = bank->virtual_irq_start + j; | |
1808 | value = omap_get_gpio_datain(gpio); | |
1809 | is_in = gpio_is_input(bank, mask); | |
1810 | ||
e5c56ed3 | 1811 | if (bank_is_mpuio(bank)) |
52e31344 | 1812 | seq_printf(s, "MPUIO %2d ", j); |
b9772a22 | 1813 | else |
52e31344 DB |
1814 | seq_printf(s, "GPIO %3d ", gpio); |
1815 | seq_printf(s, "(%10s): %s %s", | |
1816 | label, | |
b9772a22 DB |
1817 | is_in ? "in " : "out", |
1818 | value ? "hi" : "lo"); | |
1819 | ||
52e31344 DB |
1820 | /* FIXME for at least omap2, show pullup/pulldown state */ |
1821 | ||
b9772a22 DB |
1822 | irqstat = irq_desc[irq].status; |
1823 | if (is_in && ((bank->suspend_wakeup & mask) | |
1824 | || irqstat & IRQ_TYPE_SENSE_MASK)) { | |
1825 | char *trigger = NULL; | |
1826 | ||
1827 | switch (irqstat & IRQ_TYPE_SENSE_MASK) { | |
1828 | case IRQ_TYPE_EDGE_FALLING: | |
1829 | trigger = "falling"; | |
1830 | break; | |
1831 | case IRQ_TYPE_EDGE_RISING: | |
1832 | trigger = "rising"; | |
1833 | break; | |
1834 | case IRQ_TYPE_EDGE_BOTH: | |
1835 | trigger = "bothedge"; | |
1836 | break; | |
1837 | case IRQ_TYPE_LEVEL_LOW: | |
1838 | trigger = "low"; | |
1839 | break; | |
1840 | case IRQ_TYPE_LEVEL_HIGH: | |
1841 | trigger = "high"; | |
1842 | break; | |
1843 | case IRQ_TYPE_NONE: | |
52e31344 | 1844 | trigger = "(?)"; |
b9772a22 DB |
1845 | break; |
1846 | } | |
52e31344 | 1847 | seq_printf(s, ", irq-%d %-8s%s", |
b9772a22 DB |
1848 | irq, trigger, |
1849 | (bank->suspend_wakeup & mask) | |
1850 | ? " wakeup" : ""); | |
1851 | } | |
1852 | seq_printf(s, "\n"); | |
1853 | } | |
1854 | ||
e5c56ed3 | 1855 | if (bank_is_mpuio(bank)) { |
b9772a22 DB |
1856 | seq_printf(s, "\n"); |
1857 | gpio = 0; | |
1858 | } | |
1859 | } | |
1860 | return 0; | |
1861 | } | |
1862 | ||
1863 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
1864 | { | |
e5c56ed3 | 1865 | return single_open(file, dbg_gpio_show, &inode->i_private); |
b9772a22 DB |
1866 | } |
1867 | ||
1868 | static const struct file_operations debug_fops = { | |
1869 | .open = dbg_gpio_open, | |
1870 | .read = seq_read, | |
1871 | .llseek = seq_lseek, | |
1872 | .release = single_release, | |
1873 | }; | |
1874 | ||
1875 | static int __init omap_gpio_debuginit(void) | |
1876 | { | |
e5c56ed3 DB |
1877 | (void) debugfs_create_file("omap_gpio", S_IRUGO, |
1878 | NULL, NULL, &debug_fops); | |
b9772a22 DB |
1879 | return 0; |
1880 | } | |
1881 | late_initcall(omap_gpio_debuginit); | |
1882 | #endif |