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ARM: OMAP: Clear level-triggered GPIO interrupts in unmask hook
[mirror_ubuntu-bionic-kernel.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
5e1c5ff4
TL		 14#include <linux/init.h>
15#include <linux/module.h>
5e1c5ff4 16#include <linux/interrupt.h>
92105bb7
TL		 17#include <linux/sysdev.h>
18#include <linux/err.h>
f8ce2547 19#include <linux/clk.h>
5e1c5ff4
TL		 20
21#include <asm/hardware.h>
22#include <asm/irq.h>
23#include <asm/arch/irqs.h>
24#include <asm/arch/gpio.h>
25#include <asm/mach/irq.h>
26
27#include <asm/io.h>
28
29/*
30 * OMAP1510 GPIO registers
31 */
92105bb7 32#define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
5e1c5ff4
TL		 33#define OMAP1510_GPIO_DATA_INPUT 0x00
34#define OMAP1510_GPIO_DATA_OUTPUT 0x04
35#define OMAP1510_GPIO_DIR_CONTROL 0x08
36#define OMAP1510_GPIO_INT_CONTROL 0x0c
37#define OMAP1510_GPIO_INT_MASK 0x10
38#define OMAP1510_GPIO_INT_STATUS 0x14
39#define OMAP1510_GPIO_PIN_CONTROL 0x18
40
41#define OMAP1510_IH_GPIO_BASE 64
42
43/*
44 * OMAP1610 specific GPIO registers
45 */
92105bb7
TL		 46#define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47#define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48#define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49#define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
5e1c5ff4
TL		 50#define OMAP1610_GPIO_REVISION 0x0000
51#define OMAP1610_GPIO_SYSCONFIG 0x0010
52#define OMAP1610_GPIO_SYSSTATUS 0x0014
53#define OMAP1610_GPIO_IRQSTATUS1 0x0018
54#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 55#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 56#define OMAP1610_GPIO_DATAIN 0x002c
57#define OMAP1610_GPIO_DATAOUT 0x0030
58#define OMAP1610_GPIO_DIRECTION 0x0034
59#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 62#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 63#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 65#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 66#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
67
68/*
69 * OMAP730 specific GPIO registers
70 */
92105bb7
TL		 71#define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72#define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73#define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74#define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75#define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76#define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
5e1c5ff4
TL		 77#define OMAP730_GPIO_DATA_INPUT 0x00
78#define OMAP730_GPIO_DATA_OUTPUT 0x04
79#define OMAP730_GPIO_DIR_CONTROL 0x08
80#define OMAP730_GPIO_INT_CONTROL 0x0c
81#define OMAP730_GPIO_INT_MASK 0x10
82#define OMAP730_GPIO_INT_STATUS 0x14
83
92105bb7
TL		 84/*
85 * omap24xx specific GPIO registers
86 */
56a25641
SMK		 87#define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88#define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89#define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90#define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
91
92#define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93#define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94#define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95#define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96#define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
97
92105bb7
TL		 98#define OMAP24XX_GPIO_REVISION 0x0000
99#define OMAP24XX_GPIO_SYSCONFIG 0x0010
100#define OMAP24XX_GPIO_SYSSTATUS 0x0014
101#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 102#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7
TL		 104#define OMAP24XX_GPIO_IRQENABLE1 0x001c
105#define OMAP24XX_GPIO_CTRL 0x0030
106#define OMAP24XX_GPIO_OE 0x0034
107#define OMAP24XX_GPIO_DATAIN 0x0038
108#define OMAP24XX_GPIO_DATAOUT 0x003c
109#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111#define OMAP24XX_GPIO_RISINGDETECT 0x0048
112#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 113#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 115#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118#define OMAP24XX_GPIO_SETWKUENA 0x0084
119#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120#define OMAP24XX_GPIO_SETDATAOUT 0x0094
121
5492fb1a
SMK		 122/*
123 * omap34xx specific GPIO registers
124 */
125
126#define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127#define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128#define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129#define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130#define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131#define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
132
133
5e1c5ff4 134struct gpio_bank {
92105bb7 135 void __iomem *base;
5e1c5ff4
TL		 136 u16 irq;
137 u16 virtual_irq_start;
92105bb7 138 int method;
5492fb1a 139#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 140 u32 suspend_wakeup;
141 u32 saved_wakeup;
3ac4fa99 142#endif
5492fb1a 143#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 144 u32 non_wakeup_gpios;
145 u32 enabled_non_wakeup_gpios;
146
147 u32 saved_datain;
148 u32 saved_fallingdetect;
149 u32 saved_risingdetect;
150#endif
b144ff6f 151 u32 level_mask;
5e1c5ff4 152 spinlock_t lock;
52e31344 153 struct gpio_chip chip;
5e1c5ff4
TL		 154};
155
156#define METHOD_MPUIO 0
157#define METHOD_GPIO_1510 1
158#define METHOD_GPIO_1610 2
159#define METHOD_GPIO_730 3
92105bb7 160#define METHOD_GPIO_24XX 4
5e1c5ff4 161
92105bb7 162#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 163static struct gpio_bank gpio_bank_1610[5] = {
164 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
165 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
169};
170#endif
171
1a8bfa1e 172#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 173static struct gpio_bank gpio_bank_1510[2] = {
174 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
175 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
176};
177#endif
178
179#ifdef CONFIG_ARCH_OMAP730
180static struct gpio_bank gpio_bank_730[7] = {
181 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
182 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
183 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
184 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
185 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
186 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
187 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
188};
189#endif
190
92105bb7 191#ifdef CONFIG_ARCH_OMAP24XX
56a25641
SMK		 192
193static struct gpio_bank gpio_bank_242x[4] = {
194 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
92105bb7 198};
56a25641
SMK		 199
200static struct gpio_bank gpio_bank_243x[5] = {
201 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
206};
207
92105bb7
TL		 208#endif
209
5492fb1a
SMK		 210#ifdef CONFIG_ARCH_OMAP34XX
211static struct gpio_bank gpio_bank_34xx[6] = {
212 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
218};
219
220#endif
221
5e1c5ff4
TL		 222static struct gpio_bank *gpio_bank;
223static int gpio_bank_count;
224
225static inline struct gpio_bank *get_gpio_bank(int gpio)
226{
6e60e79a 227 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 228 if (OMAP_GPIO_IS_MPUIO(gpio))
229 return &gpio_bank[0];
230 return &gpio_bank[1];
231 }
5e1c5ff4
TL		 232 if (cpu_is_omap16xx()) {
233 if (OMAP_GPIO_IS_MPUIO(gpio))
234 return &gpio_bank[0];
235 return &gpio_bank[1 + (gpio >> 4)];
236 }
5e1c5ff4
TL		 237 if (cpu_is_omap730()) {
238 if (OMAP_GPIO_IS_MPUIO(gpio))
239 return &gpio_bank[0];
240 return &gpio_bank[1 + (gpio >> 5)];
241 }
92105bb7
TL		 242 if (cpu_is_omap24xx())
243 return &gpio_bank[gpio >> 5];
5492fb1a
SMK		 244 if (cpu_is_omap34xx())
245 return &gpio_bank[gpio >> 5];
5e1c5ff4
TL		 246}
247
248static inline int get_gpio_index(int gpio)
249{
250 if (cpu_is_omap730())
251 return gpio & 0x1f;
92105bb7
TL		 252 if (cpu_is_omap24xx())
253 return gpio & 0x1f;
5492fb1a
SMK		 254 if (cpu_is_omap34xx())
255 return gpio & 0x1f;
92105bb7 256 return gpio & 0x0f;
5e1c5ff4
TL		 257}
258
259static inline int gpio_valid(int gpio)
260{
261 if (gpio < 0)
262 return -1;
d11ac979 263 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 264 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 265 return -1;
266 return 0;
267 }
6e60e79a 268 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 269 return 0;
5e1c5ff4
TL		 270 if ((cpu_is_omap16xx()) && gpio < 64)
271 return 0;
5e1c5ff4
TL		 272 if (cpu_is_omap730() && gpio < 192)
273 return 0;
92105bb7
TL		 274 if (cpu_is_omap24xx() && gpio < 128)
275 return 0;
5492fb1a
SMK		 276 if (cpu_is_omap34xx() && gpio < 160)
277 return 0;
5e1c5ff4
TL		 278 return -1;
279}
280
281static int check_gpio(int gpio)
282{
283 if (unlikely(gpio_valid(gpio)) < 0) {
284 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
285 dump_stack();
286 return -1;
287 }
288 return 0;
289}
290
291static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
292{
92105bb7 293 void __iomem *reg = bank->base;
5e1c5ff4
TL		 294 u32 l;
295
296 switch (bank->method) {
e5c56ed3 297#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 298 case METHOD_MPUIO:
299 reg += OMAP_MPUIO_IO_CNTL;
300 break;
e5c56ed3
DB		 301#endif
302#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 303 case METHOD_GPIO_1510:
304 reg += OMAP1510_GPIO_DIR_CONTROL;
305 break;
e5c56ed3
DB		 306#endif
307#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 308 case METHOD_GPIO_1610:
309 reg += OMAP1610_GPIO_DIRECTION;
310 break;
e5c56ed3
DB		 311#endif
312#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 313 case METHOD_GPIO_730:
314 reg += OMAP730_GPIO_DIR_CONTROL;
315 break;
e5c56ed3 316#endif
5492fb1a 317#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 318 case METHOD_GPIO_24XX:
319 reg += OMAP24XX_GPIO_OE;
320 break;
e5c56ed3
DB		 321#endif
322 default:
323 WARN_ON(1);
324 return;
5e1c5ff4
TL		 325 }
326 l = __raw_readl(reg);
327 if (is_input)
328 l |= 1 << gpio;
329 else
330 l &= ~(1 << gpio);
331 __raw_writel(l, reg);
332}
333
334void omap_set_gpio_direction(int gpio, int is_input)
335{
336 struct gpio_bank *bank;
a6472533 337 unsigned long flags;
5e1c5ff4
TL		 338
339 if (check_gpio(gpio) < 0)
340 return;
341 bank = get_gpio_bank(gpio);
a6472533 342 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 343 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
a6472533 344 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 345}
346
347static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
348{
92105bb7 349 void __iomem *reg = bank->base;
5e1c5ff4
TL		 350 u32 l = 0;
351
352 switch (bank->method) {
e5c56ed3 353#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 354 case METHOD_MPUIO:
355 reg += OMAP_MPUIO_OUTPUT;
356 l = __raw_readl(reg);
357 if (enable)
358 l |= 1 << gpio;
359 else
360 l &= ~(1 << gpio);
361 break;
e5c56ed3
DB		 362#endif
363#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 364 case METHOD_GPIO_1510:
365 reg += OMAP1510_GPIO_DATA_OUTPUT;
366 l = __raw_readl(reg);
367 if (enable)
368 l |= 1 << gpio;
369 else
370 l &= ~(1 << gpio);
371 break;
e5c56ed3
DB		 372#endif
373#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 374 case METHOD_GPIO_1610:
375 if (enable)
376 reg += OMAP1610_GPIO_SET_DATAOUT;
377 else
378 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
379 l = 1 << gpio;
380 break;
e5c56ed3
DB		 381#endif
382#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 383 case METHOD_GPIO_730:
384 reg += OMAP730_GPIO_DATA_OUTPUT;
385 l = __raw_readl(reg);
386 if (enable)
387 l |= 1 << gpio;
388 else
389 l &= ~(1 << gpio);
390 break;
e5c56ed3 391#endif
5492fb1a 392#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 393 case METHOD_GPIO_24XX:
394 if (enable)
395 reg += OMAP24XX_GPIO_SETDATAOUT;
396 else
397 reg += OMAP24XX_GPIO_CLEARDATAOUT;
398 l = 1 << gpio;
399 break;
e5c56ed3 400#endif
5e1c5ff4 401 default:
e5c56ed3 402 WARN_ON(1);
5e1c5ff4
TL		 403 return;
404 }
405 __raw_writel(l, reg);
406}
407
408void omap_set_gpio_dataout(int gpio, int enable)
409{
410 struct gpio_bank *bank;
a6472533 411 unsigned long flags;
5e1c5ff4
TL		 412
413 if (check_gpio(gpio) < 0)
414 return;
415 bank = get_gpio_bank(gpio);
a6472533 416 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 417 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
a6472533 418 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 419}
420
421int omap_get_gpio_datain(int gpio)
422{
423 struct gpio_bank *bank;
92105bb7 424 void __iomem *reg;
5e1c5ff4
TL		 425
426 if (check_gpio(gpio) < 0)
e5c56ed3 427 return -EINVAL;
5e1c5ff4
TL		 428 bank = get_gpio_bank(gpio);
429 reg = bank->base;
430 switch (bank->method) {
e5c56ed3 431#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 432 case METHOD_MPUIO:
433 reg += OMAP_MPUIO_INPUT_LATCH;
434 break;
e5c56ed3
DB		 435#endif
436#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 437 case METHOD_GPIO_1510:
438 reg += OMAP1510_GPIO_DATA_INPUT;
439 break;
e5c56ed3
DB		 440#endif
441#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 442 case METHOD_GPIO_1610:
443 reg += OMAP1610_GPIO_DATAIN;
444 break;
e5c56ed3
DB		 445#endif
446#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 447 case METHOD_GPIO_730:
448 reg += OMAP730_GPIO_DATA_INPUT;
449 break;
e5c56ed3 450#endif
5492fb1a 451#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 452 case METHOD_GPIO_24XX:
453 reg += OMAP24XX_GPIO_DATAIN;
454 break;
e5c56ed3 455#endif
5e1c5ff4 456 default:
e5c56ed3 457 return -EINVAL;
5e1c5ff4 458 }
92105bb7
TL		 459 return (__raw_readl(reg)
460 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 461}
462
92105bb7
TL		 463#define MOD_REG_BIT(reg, bit_mask, set) \
464do { \
465 int l = __raw_readl(base + reg); \
466 if (set) l |= bit_mask; \
467 else l &= ~bit_mask; \
468 __raw_writel(l, base + reg); \
469} while(0)
470
5eb3bb9c
KH		 471void omap_set_gpio_debounce(int gpio, int enable)
472{
473 struct gpio_bank *bank;
474 void __iomem *reg;
475 u32 val, l = 1 << get_gpio_index(gpio);
476
477 if (cpu_class_is_omap1())
478 return;
479
480 bank = get_gpio_bank(gpio);
481 reg = bank->base;
482
483 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
484 val = __raw_readl(reg);
485
486 if (enable)
487 val |= l;
488 else
489 val &= ~l;
490
491 __raw_writel(val, reg);
492}
493EXPORT_SYMBOL(omap_set_gpio_debounce);
494
495void omap_set_gpio_debounce_time(int gpio, int enc_time)
496{
497 struct gpio_bank *bank;
498 void __iomem *reg;
499
500 if (cpu_class_is_omap1())
501 return;
502
503 bank = get_gpio_bank(gpio);
504 reg = bank->base;
505
506 enc_time &= 0xff;
507 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
508 __raw_writel(enc_time, reg);
509}
510EXPORT_SYMBOL(omap_set_gpio_debounce_time);
511
5492fb1a 512#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
5eb3bb9c
KH		 513static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
514 int trigger)
5e1c5ff4 515{
3ac4fa99 516 void __iomem *base = bank->base;
92105bb7
TL		 517 u32 gpio_bit = 1 << gpio;
518
519 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
6e60e79a 520 trigger & __IRQT_LOWLVL);
92105bb7 521 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
6e60e79a 522 trigger & __IRQT_HIGHLVL);
92105bb7 523 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
6e60e79a 524 trigger & __IRQT_RISEDGE);
92105bb7 525 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
6e60e79a 526 trigger & __IRQT_FALEDGE);
5eb3bb9c 527
3ac4fa99
JY		 528 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
529 if (trigger != 0)
5eb3bb9c
KH		 530 __raw_writel(1 << gpio, bank->base
531 + OMAP24XX_GPIO_SETWKUENA);
3ac4fa99 532 else
5eb3bb9c
KH		 533 __raw_writel(1 << gpio, bank->base
534 + OMAP24XX_GPIO_CLEARWKUENA);
3ac4fa99
JY		 535 } else {
536 if (trigger != 0)
537 bank->enabled_non_wakeup_gpios |= gpio_bit;
538 else
539 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
540 }
5eb3bb9c 541
b144ff6f
KH		 542 bank->level_mask =
543 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
544 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
5eb3bb9c
KH		 545 /*
546 * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
547 * level triggering requested.
548 */
92105bb7 549}
3ac4fa99 550#endif
92105bb7
TL		 551
552static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
553{
554 void __iomem *reg = bank->base;
555 u32 l = 0;
5e1c5ff4
TL		 556
557 switch (bank->method) {
e5c56ed3 558#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 559 case METHOD_MPUIO:
560 reg += OMAP_MPUIO_GPIO_INT_EDGE;
561 l = __raw_readl(reg);
6e60e79a 562 if (trigger & __IRQT_RISEDGE)
5e1c5ff4 563 l |= 1 << gpio;
6e60e79a 564 else if (trigger & __IRQT_FALEDGE)
5e1c5ff4 565 l &= ~(1 << gpio);
92105bb7
TL		 566 else
567 goto bad;
5e1c5ff4 568 break;
e5c56ed3
DB		 569#endif
570#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 571 case METHOD_GPIO_1510:
572 reg += OMAP1510_GPIO_INT_CONTROL;
573 l = __raw_readl(reg);
6e60e79a 574 if (trigger & __IRQT_RISEDGE)
5e1c5ff4 575 l |= 1 << gpio;
6e60e79a 576 else if (trigger & __IRQT_FALEDGE)
5e1c5ff4 577 l &= ~(1 << gpio);
92105bb7
TL		 578 else
579 goto bad;
5e1c5ff4 580 break;
e5c56ed3 581#endif
3ac4fa99 582#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 583 case METHOD_GPIO_1610:
5e1c5ff4
TL		 584 if (gpio & 0x08)
585 reg += OMAP1610_GPIO_EDGE_CTRL2;
586 else
587 reg += OMAP1610_GPIO_EDGE_CTRL1;
588 gpio &= 0x07;
589 l = __raw_readl(reg);
590 l &= ~(3 << (gpio << 1));
6e60e79a
TL		 591 if (trigger & __IRQT_RISEDGE)
592 l |= 2 << (gpio << 1);
593 if (trigger & __IRQT_FALEDGE)
594 l |= 1 << (gpio << 1);
3ac4fa99
JY		 595 if (trigger)
596 /* Enable wake-up during idle for dynamic tick */
597 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
598 else
599 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 600 break;
3ac4fa99
JY		 601#endif
602#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 603 case METHOD_GPIO_730:
604 reg += OMAP730_GPIO_INT_CONTROL;
605 l = __raw_readl(reg);
6e60e79a 606 if (trigger & __IRQT_RISEDGE)
5e1c5ff4 607 l |= 1 << gpio;
6e60e79a 608 else if (trigger & __IRQT_FALEDGE)
5e1c5ff4 609 l &= ~(1 << gpio);
92105bb7
TL		 610 else
611 goto bad;
612 break;
3ac4fa99 613#endif
5492fb1a 614#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 615 case METHOD_GPIO_24XX:
3ac4fa99 616 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 617 break;
3ac4fa99 618#endif
5e1c5ff4 619 default:
92105bb7 620 goto bad;
5e1c5ff4 621 }
92105bb7
TL		 622 __raw_writel(l, reg);
623 return 0;
624bad:
625 return -EINVAL;
5e1c5ff4
TL		 626}
627
92105bb7 628static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 629{
630 struct gpio_bank *bank;
92105bb7
TL		 631 unsigned gpio;
632 int retval;
a6472533 633 unsigned long flags;
92105bb7 634
5492fb1a 635 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 636 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
637 else
638 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 639
640 if (check_gpio(gpio) < 0)
92105bb7
TL		 641 return -EINVAL;
642
e5c56ed3 643 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 644 return -EINVAL;
e5c56ed3
DB		 645
646 /* OMAP1 allows only only edge triggering */
5492fb1a 647 if (!cpu_class_is_omap2()
e5c56ed3 648 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 649 return -EINVAL;
650
58781016 651 bank = get_irq_chip_data(irq);
a6472533 652 spin_lock_irqsave(&bank->lock, flags);
92105bb7 653 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 654 if (retval == 0) {
655 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
656 irq_desc[irq].status |= type;
657 }
a6472533 658 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 659 return retval;
5e1c5ff4
TL		 660}
661
662static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
663{
92105bb7 664 void __iomem *reg = bank->base;
5e1c5ff4
TL		 665
666 switch (bank->method) {
e5c56ed3 667#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 668 case METHOD_MPUIO:
669 /* MPUIO irqstatus is reset by reading the status register,
670 * so do nothing here */
671 return;
e5c56ed3
DB		 672#endif
673#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 674 case METHOD_GPIO_1510:
675 reg += OMAP1510_GPIO_INT_STATUS;
676 break;
e5c56ed3
DB		 677#endif
678#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 679 case METHOD_GPIO_1610:
680 reg += OMAP1610_GPIO_IRQSTATUS1;
681 break;
e5c56ed3
DB		 682#endif
683#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 684 case METHOD_GPIO_730:
685 reg += OMAP730_GPIO_INT_STATUS;
686 break;
e5c56ed3 687#endif
5492fb1a 688#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 689 case METHOD_GPIO_24XX:
690 reg += OMAP24XX_GPIO_IRQSTATUS1;
691 break;
e5c56ed3 692#endif
5e1c5ff4 693 default:
e5c56ed3 694 WARN_ON(1);
5e1c5ff4
TL		 695 return;
696 }
697 __raw_writel(gpio_mask, reg);
bee7930f
HD		 698
699 /* Workaround for clearing DSP GPIO interrupts to allow retention */
5492fb1a
SMK		 700#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
701 if (cpu_is_omap24xx() || cpu_is_omap34xx())
bee7930f 702 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
5492fb1a 703#endif
5e1c5ff4
TL		 704}
705
706static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
707{
708 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
709}
710
ea6dedd7
ID		 711static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
712{
713 void __iomem *reg = bank->base;
99c47707
ID		 714 int inv = 0;
715 u32 l;
716 u32 mask;
ea6dedd7
ID		 717
718 switch (bank->method) {
e5c56ed3 719#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 720 case METHOD_MPUIO:
721 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 722 mask = 0xffff;
723 inv = 1;
ea6dedd7 724 break;
e5c56ed3
DB		 725#endif
726#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 727 case METHOD_GPIO_1510:
728 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 729 mask = 0xffff;
730 inv = 1;
ea6dedd7 731 break;
e5c56ed3
DB		 732#endif
733#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 734 case METHOD_GPIO_1610:
735 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 736 mask = 0xffff;
ea6dedd7 737 break;
e5c56ed3
DB		 738#endif
739#ifdef CONFIG_ARCH_OMAP730
ea6dedd7
ID		 740 case METHOD_GPIO_730:
741 reg += OMAP730_GPIO_INT_MASK;
99c47707
ID		 742 mask = 0xffffffff;
743 inv = 1;
ea6dedd7 744 break;
e5c56ed3 745#endif
5492fb1a 746#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
ea6dedd7
ID		 747 case METHOD_GPIO_24XX:
748 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 749 mask = 0xffffffff;
ea6dedd7 750 break;
e5c56ed3 751#endif
ea6dedd7 752 default:
e5c56ed3 753 WARN_ON(1);
ea6dedd7
ID		 754 return 0;
755 }
756
99c47707
ID		 757 l = __raw_readl(reg);
758 if (inv)
759 l = ~l;
760 l &= mask;
761 return l;
ea6dedd7
ID		 762}
763
5e1c5ff4
TL		 764static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
765{
92105bb7 766 void __iomem *reg = bank->base;
5e1c5ff4
TL		 767 u32 l;
768
769 switch (bank->method) {
e5c56ed3 770#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 771 case METHOD_MPUIO:
772 reg += OMAP_MPUIO_GPIO_MASKIT;
773 l = __raw_readl(reg);
774 if (enable)
775 l &= ~(gpio_mask);
776 else
777 l |= gpio_mask;
778 break;
e5c56ed3
DB		 779#endif
780#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 781 case METHOD_GPIO_1510:
782 reg += OMAP1510_GPIO_INT_MASK;
783 l = __raw_readl(reg);
784 if (enable)
785 l &= ~(gpio_mask);
786 else
787 l |= gpio_mask;
788 break;
e5c56ed3
DB		 789#endif
790#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 791 case METHOD_GPIO_1610:
792 if (enable)
793 reg += OMAP1610_GPIO_SET_IRQENABLE1;
794 else
795 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
796 l = gpio_mask;
797 break;
e5c56ed3
DB		 798#endif
799#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 800 case METHOD_GPIO_730:
801 reg += OMAP730_GPIO_INT_MASK;
802 l = __raw_readl(reg);
803 if (enable)
804 l &= ~(gpio_mask);
805 else
806 l |= gpio_mask;
807 break;
e5c56ed3 808#endif
5492fb1a 809#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 810 case METHOD_GPIO_24XX:
811 if (enable)
812 reg += OMAP24XX_GPIO_SETIRQENABLE1;
813 else
814 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
815 l = gpio_mask;
816 break;
e5c56ed3 817#endif
5e1c5ff4 818 default:
e5c56ed3 819 WARN_ON(1);
5e1c5ff4
TL		 820 return;
821 }
822 __raw_writel(l, reg);
823}
824
825static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
826{
827 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
828}
829
92105bb7
TL		 830/*
831 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
832 * 1510 does not seem to have a wake-up register. If JTAG is connected
833 * to the target, system will wake up always on GPIO events. While
834 * system is running all registered GPIO interrupts need to have wake-up
835 * enabled. When system is suspended, only selected GPIO interrupts need
836 * to have wake-up enabled.
837 */
838static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
839{
a6472533
DB		 840 unsigned long flags;
841
92105bb7 842 switch (bank->method) {
3ac4fa99 843#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 844 case METHOD_MPUIO:
92105bb7 845 case METHOD_GPIO_1610:
a6472533 846 spin_lock_irqsave(&bank->lock, flags);
11a78b79 847 if (enable) {
92105bb7 848 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 849 enable_irq_wake(bank->irq);
850 } else {
851 disable_irq_wake(bank->irq);
92105bb7 852 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 853 }
a6472533 854 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 855 return 0;
3ac4fa99 856#endif
5492fb1a 857#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 858 case METHOD_GPIO_24XX:
11a78b79
DB		 859 if (bank->non_wakeup_gpios & (1 << gpio)) {
860 printk(KERN_ERR "Unable to modify wakeup on "
861 "non-wakeup GPIO%d\n",
862 (bank - gpio_bank) * 32 + gpio);
863 return -EINVAL;
864 }
a6472533 865 spin_lock_irqsave(&bank->lock, flags);
3ac4fa99 866 if (enable) {
3ac4fa99 867 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 868 enable_irq_wake(bank->irq);
869 } else {
870 disable_irq_wake(bank->irq);
3ac4fa99 871 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 872 }
a6472533 873 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 874 return 0;
875#endif
92105bb7
TL		 876 default:
877 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
878 bank->method);
879 return -EINVAL;
880 }
881}
882
4196dd6b
TL		 883static void _reset_gpio(struct gpio_bank *bank, int gpio)
884{
885 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
886 _set_gpio_irqenable(bank, gpio, 0);
887 _clear_gpio_irqstatus(bank, gpio);
888 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
889}
890
92105bb7
TL		 891/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
892static int gpio_wake_enable(unsigned int irq, unsigned int enable)
893{
894 unsigned int gpio = irq - IH_GPIO_BASE;
895 struct gpio_bank *bank;
896 int retval;
897
898 if (check_gpio(gpio) < 0)
899 return -ENODEV;
58781016 900 bank = get_irq_chip_data(irq);
92105bb7 901 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 902
903 return retval;
904}
905
5e1c5ff4
TL		 906int omap_request_gpio(int gpio)
907{
908 struct gpio_bank *bank;
a6472533 909 unsigned long flags;
52e31344 910 int status;
5e1c5ff4
TL		 911
912 if (check_gpio(gpio) < 0)
913 return -EINVAL;
914
52e31344
DB		 915 status = gpio_request(gpio, NULL);
916 if (status < 0)
917 return status;
918
5e1c5ff4 919 bank = get_gpio_bank(gpio);
a6472533 920 spin_lock_irqsave(&bank->lock, flags);
92105bb7 921
4196dd6b
TL		 922 /* Set trigger to none. You need to enable the desired trigger with
923 * request_irq() or set_irq_type().
924 */
92105bb7
TL		 925 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
926
1a8bfa1e 927#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 928 if (bank->method == METHOD_GPIO_1510) {
92105bb7 929 void __iomem *reg;
5e1c5ff4 930
92105bb7 931 /* Claim the pin for MPU */
5e1c5ff4
TL		 932 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
933 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
934 }
935#endif
a6472533 936 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 937
938 return 0;
939}
940
941void omap_free_gpio(int gpio)
942{
943 struct gpio_bank *bank;
a6472533 944 unsigned long flags;
5e1c5ff4
TL		 945
946 if (check_gpio(gpio) < 0)
947 return;
948 bank = get_gpio_bank(gpio);
a6472533 949 spin_lock_irqsave(&bank->lock, flags);
52e31344
DB		 950 if (unlikely(!gpiochip_is_requested(&bank->chip,
951 get_gpio_index(gpio)))) {
952 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 953 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
954 dump_stack();
5e1c5ff4
TL		 955 return;
956 }
92105bb7
TL		 957#ifdef CONFIG_ARCH_OMAP16XX
958 if (bank->method == METHOD_GPIO_1610) {
959 /* Disable wake-up during idle for dynamic tick */
960 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
961 __raw_writel(1 << get_gpio_index(gpio), reg);
962 }
963#endif
5492fb1a 964#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 965 if (bank->method == METHOD_GPIO_24XX) {
966 /* Disable wake-up during idle for dynamic tick */
967 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
968 __raw_writel(1 << get_gpio_index(gpio), reg);
969 }
970#endif
4196dd6b 971 _reset_gpio(bank, gpio);
a6472533 972 spin_unlock_irqrestore(&bank->lock, flags);
52e31344 973 gpio_free(gpio);
5e1c5ff4
TL		 974}
975
976/*
977 * We need to unmask the GPIO bank interrupt as soon as possible to
978 * avoid missing GPIO interrupts for other lines in the bank.
979 * Then we need to mask-read-clear-unmask the triggered GPIO lines
980 * in the bank to avoid missing nested interrupts for a GPIO line.
981 * If we wait to unmask individual GPIO lines in the bank after the
982 * line's interrupt handler has been run, we may miss some nested
983 * interrupts.
984 */
10dd5ce2 985static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 986{
92105bb7 987 void __iomem *isr_reg = NULL;
5e1c5ff4
TL		 988 u32 isr;
989 unsigned int gpio_irq;
990 struct gpio_bank *bank;
ea6dedd7
ID		 991 u32 retrigger = 0;
992 int unmasked = 0;
5e1c5ff4
TL		 993
994 desc->chip->ack(irq);
995
418ca1f0 996 bank = get_irq_data(irq);
e5c56ed3 997#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 998 if (bank->method == METHOD_MPUIO)
999 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 1000#endif
1a8bfa1e 1001#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1002 if (bank->method == METHOD_GPIO_1510)
1003 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1004#endif
1005#if defined(CONFIG_ARCH_OMAP16XX)
1006 if (bank->method == METHOD_GPIO_1610)
1007 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1008#endif
1009#ifdef CONFIG_ARCH_OMAP730
1010 if (bank->method == METHOD_GPIO_730)
1011 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1012#endif
5492fb1a 1013#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1014 if (bank->method == METHOD_GPIO_24XX)
1015 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1016#endif
92105bb7 1017 while(1) {
6e60e79a 1018 u32 isr_saved, level_mask = 0;
ea6dedd7 1019 u32 enabled;
6e60e79a 1020
ea6dedd7
ID		 1021 enabled = _get_gpio_irqbank_mask(bank);
1022 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1023
1024 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1025 isr &= 0x0000ffff;
1026
5492fb1a 1027 if (cpu_class_is_omap2()) {
b144ff6f 1028 level_mask = bank->level_mask & enabled;
ea6dedd7 1029 }
6e60e79a
TL		 1030
1031 /* clear edge sensitive interrupts before handler(s) are
1032 called so that we don't miss any interrupt occurred while
1033 executing them */
1034 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1035 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1036 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1037
1038 /* if there is only edge sensitive GPIO pin interrupts
1039 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1040 if (!level_mask && !unmasked) {
1041 unmasked = 1;
6e60e79a 1042 desc->chip->unmask(irq);
ea6dedd7 1043 }
92105bb7 1044
ea6dedd7
ID		 1045 isr |= retrigger;
1046 retrigger = 0;
92105bb7
TL		 1047 if (!isr)
1048 break;
1049
1050 gpio_irq = bank->virtual_irq_start;
1051 for (; isr != 0; isr >>= 1, gpio_irq++) {
10dd5ce2 1052 struct irq_desc *d;
ea6dedd7 1053 int irq_mask;
92105bb7
TL		 1054 if (!(isr & 1))
1055 continue;
1056 d = irq_desc + gpio_irq;
ea6dedd7
ID		 1057 /* Don't run the handler if it's already running
1058 * or was disabled lazely.
1059 */
29454dde
TG		 1060 if (unlikely((d->depth ||
1061 (d->status & IRQ_INPROGRESS)))) {
ea6dedd7
ID		 1062 irq_mask = 1 <<
1063 (gpio_irq - bank->virtual_irq_start);
1064 /* The unmasking will be done by
1065 * enable_irq in case it is disabled or
1066 * after returning from the handler if
1067 * it's already running.
1068 */
1069 _enable_gpio_irqbank(bank, irq_mask, 0);
29454dde 1070 if (!d->depth) {
ea6dedd7
ID		 1071 /* Level triggered interrupts
1072 * won't ever be reentered
1073 */
1074 BUG_ON(level_mask & irq_mask);
29454dde 1075 d->status |= IRQ_PENDING;
ea6dedd7
ID		 1076 }
1077 continue;
1078 }
29454dde 1079
0cd61b68 1080 desc_handle_irq(gpio_irq, d);
29454dde
TG		 1081
1082 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
ea6dedd7
ID		 1083 irq_mask = 1 <<
1084 (gpio_irq - bank->virtual_irq_start);
29454dde 1085 d->status &= ~IRQ_PENDING;
ea6dedd7
ID		 1086 _enable_gpio_irqbank(bank, irq_mask, 1);
1087 retrigger |= irq_mask;
1088 }
92105bb7 1089 }
1a8bfa1e 1090 }
ea6dedd7
ID		 1091 /* if bank has any level sensitive GPIO pin interrupt
1092 configured, we must unmask the bank interrupt only after
1093 handler(s) are executed in order to avoid spurious bank
1094 interrupt */
1095 if (!unmasked)
1096 desc->chip->unmask(irq);
1097
5e1c5ff4
TL		 1098}
1099
4196dd6b
TL		 1100static void gpio_irq_shutdown(unsigned int irq)
1101{
1102 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1103 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1104
1105 _reset_gpio(bank, gpio);
1106}
1107
5e1c5ff4
TL		 1108static void gpio_ack_irq(unsigned int irq)
1109{
1110 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1111 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1112
1113 _clear_gpio_irqstatus(bank, gpio);
1114}
1115
1116static void gpio_mask_irq(unsigned int irq)
1117{
1118 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1119 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1120
1121 _set_gpio_irqenable(bank, gpio, 0);
1122}
1123
1124static void gpio_unmask_irq(unsigned int irq)
1125{
1126 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1127 struct gpio_bank *bank = get_irq_chip_data(irq);
b144ff6f
KH		 1128 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1129
1130 /* For level-triggered GPIOs, the clearing must be done after
1131 * the HW source is cleared, thus after the handler has run */
1132 if (bank->level_mask & irq_mask) {
1133 _set_gpio_irqenable(bank, gpio, 0);
1134 _clear_gpio_irqstatus(bank, gpio);
1135 }
5e1c5ff4 1136
4de8c75b 1137 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1138}
1139
e5c56ed3
DB		 1140static struct irq_chip gpio_irq_chip = {
1141 .name = "GPIO",
1142 .shutdown = gpio_irq_shutdown,
1143 .ack = gpio_ack_irq,
1144 .mask = gpio_mask_irq,
1145 .unmask = gpio_unmask_irq,
1146 .set_type = gpio_irq_type,
1147 .set_wake = gpio_wake_enable,
1148};
1149
1150/*---------------------------------------------------------------------*/
1151
1152#ifdef CONFIG_ARCH_OMAP1
1153
1154/* MPUIO uses the always-on 32k clock */
1155
5e1c5ff4
TL		 1156static void mpuio_ack_irq(unsigned int irq)
1157{
1158 /* The ISR is reset automatically, so do nothing here. */
1159}
1160
1161static void mpuio_mask_irq(unsigned int irq)
1162{
1163 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1164 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1165
1166 _set_gpio_irqenable(bank, gpio, 0);
1167}
1168
1169static void mpuio_unmask_irq(unsigned int irq)
1170{
1171 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1172 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1173
1174 _set_gpio_irqenable(bank, gpio, 1);
1175}
1176
e5c56ed3
DB		 1177static struct irq_chip mpuio_irq_chip = {
1178 .name = "MPUIO",
1179 .ack = mpuio_ack_irq,
1180 .mask = mpuio_mask_irq,
1181 .unmask = mpuio_unmask_irq,
92105bb7 1182 .set_type = gpio_irq_type,
11a78b79
DB		 1183#ifdef CONFIG_ARCH_OMAP16XX
1184 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1185 .set_wake = gpio_wake_enable,
1186#endif
5e1c5ff4
TL		 1187};
1188
e5c56ed3
DB		 1189
1190#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1191
11a78b79
DB		 1192
1193#ifdef CONFIG_ARCH_OMAP16XX
1194
1195#include <linux/platform_device.h>
1196
1197static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1198{
1199 struct gpio_bank *bank = platform_get_drvdata(pdev);
1200 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1201 unsigned long flags;
11a78b79 1202
a6472533 1203 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1204 bank->saved_wakeup = __raw_readl(mask_reg);
1205 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1206 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1207
1208 return 0;
1209}
1210
1211static int omap_mpuio_resume_early(struct platform_device *pdev)
1212{
1213 struct gpio_bank *bank = platform_get_drvdata(pdev);
1214 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1215 unsigned long flags;
11a78b79 1216
a6472533 1217 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1218 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1219 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1220
1221 return 0;
1222}
1223
1224/* use platform_driver for this, now that there's no longer any
1225 * point to sys_device (other than not disturbing old code).
1226 */
1227static struct platform_driver omap_mpuio_driver = {
1228 .suspend_late = omap_mpuio_suspend_late,
1229 .resume_early = omap_mpuio_resume_early,
1230 .driver = {
1231 .name = "mpuio",
1232 },
1233};
1234
1235static struct platform_device omap_mpuio_device = {
1236 .name = "mpuio",
1237 .id = -1,
1238 .dev = {
1239 .driver = &omap_mpuio_driver.driver,
1240 }
1241 /* could list the /proc/iomem resources */
1242};
1243
1244static inline void mpuio_init(void)
1245{
fcf126d8
DB		 1246 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1247
11a78b79
DB		 1248 if (platform_driver_register(&omap_mpuio_driver) == 0)
1249 (void) platform_device_register(&omap_mpuio_device);
1250}
1251
1252#else
1253static inline void mpuio_init(void) {}
1254#endif /* 16xx */
1255
e5c56ed3
DB		 1256#else
1257
1258extern struct irq_chip mpuio_irq_chip;
1259
1260#define bank_is_mpuio(bank) 0
11a78b79 1261static inline void mpuio_init(void) {}
e5c56ed3
DB		 1262
1263#endif
1264
1265/*---------------------------------------------------------------------*/
5e1c5ff4 1266
52e31344
DB		 1267/* REVISIT these are stupid implementations! replace by ones that
1268 * don't switch on METHOD_* and which mostly avoid spinlocks
1269 */
1270
1271static int gpio_input(struct gpio_chip *chip, unsigned offset)
1272{
1273 struct gpio_bank *bank;
1274 unsigned long flags;
1275
1276 bank = container_of(chip, struct gpio_bank, chip);
1277 spin_lock_irqsave(&bank->lock, flags);
1278 _set_gpio_direction(bank, offset, 1);
1279 spin_unlock_irqrestore(&bank->lock, flags);
1280 return 0;
1281}
1282
1283static int gpio_get(struct gpio_chip *chip, unsigned offset)
1284{
1285 return omap_get_gpio_datain(chip->base + offset);
1286}
1287
1288static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1289{
1290 struct gpio_bank *bank;
1291 unsigned long flags;
1292
1293 bank = container_of(chip, struct gpio_bank, chip);
1294 spin_lock_irqsave(&bank->lock, flags);
1295 _set_gpio_dataout(bank, offset, value);
1296 _set_gpio_direction(bank, offset, 0);
1297 spin_unlock_irqrestore(&bank->lock, flags);
1298 return 0;
1299}
1300
1301static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1302{
1303 struct gpio_bank *bank;
1304 unsigned long flags;
1305
1306 bank = container_of(chip, struct gpio_bank, chip);
1307 spin_lock_irqsave(&bank->lock, flags);
1308 _set_gpio_dataout(bank, offset, value);
1309 spin_unlock_irqrestore(&bank->lock, flags);
1310}
1311
1312/*---------------------------------------------------------------------*/
1313
1a8bfa1e 1314static int initialized;
5492fb1a 1315#if !defined(CONFIG_ARCH_OMAP3)
1a8bfa1e 1316static struct clk * gpio_ick;
5492fb1a
SMK		 1317#endif
1318
1319#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1320static struct clk * gpio_fck;
5492fb1a 1321#endif
5e1c5ff4 1322
5492fb1a 1323#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1324static struct clk * gpio5_ick;
1325static struct clk * gpio5_fck;
1326#endif
1327
5492fb1a
SMK		 1328#if defined(CONFIG_ARCH_OMAP3)
1329static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1330static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1331#endif
1332
8ba55c5c
DB		 1333/* This lock class tells lockdep that GPIO irqs are in a different
1334 * category than their parents, so it won't report false recursion.
1335 */
1336static struct lock_class_key gpio_lock_class;
1337
5e1c5ff4
TL		 1338static int __init _omap_gpio_init(void)
1339{
1340 int i;
52e31344 1341 int gpio = 0;
5e1c5ff4 1342 struct gpio_bank *bank;
5492fb1a
SMK		 1343#if defined(CONFIG_ARCH_OMAP3)
1344 char clk_name[11];
1345#endif
5e1c5ff4
TL		 1346
1347 initialized = 1;
1348
5492fb1a 1349#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1350 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1351 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1352 if (IS_ERR(gpio_ick))
92105bb7
TL		 1353 printk("Could not get arm_gpio_ck\n");
1354 else
30ff720b 1355 clk_enable(gpio_ick);
1a8bfa1e 1356 }
5492fb1a
SMK		 1357#endif
1358#if defined(CONFIG_ARCH_OMAP2)
1359 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1360 gpio_ick = clk_get(NULL, "gpios_ick");
1361 if (IS_ERR(gpio_ick))
1362 printk("Could not get gpios_ick\n");
1363 else
30ff720b 1364 clk_enable(gpio_ick);
1a8bfa1e 1365 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1366 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1367 printk("Could not get gpios_fck\n");
1368 else
30ff720b 1369 clk_enable(gpio_fck);
56a25641
SMK		 1370
1371 /*
5492fb1a 1372 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1373 */
5492fb1a 1374#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1375 if (cpu_is_omap2430()) {
1376 gpio5_ick = clk_get(NULL, "gpio5_ick");
1377 if (IS_ERR(gpio5_ick))
1378 printk("Could not get gpio5_ick\n");
1379 else
1380 clk_enable(gpio5_ick);
1381 gpio5_fck = clk_get(NULL, "gpio5_fck");
1382 if (IS_ERR(gpio5_fck))
1383 printk("Could not get gpio5_fck\n");
1384 else
1385 clk_enable(gpio5_fck);
1386 }
1387#endif
5492fb1a
SMK		 1388 }
1389#endif
1390
1391#if defined(CONFIG_ARCH_OMAP3)
1392 if (cpu_is_omap34xx()) {
1393 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1394 sprintf(clk_name, "gpio%d_ick", i + 1);
1395 gpio_iclks[i] = clk_get(NULL, clk_name);
1396 if (IS_ERR(gpio_iclks[i]))
1397 printk(KERN_ERR "Could not get %s\n", clk_name);
1398 else
1399 clk_enable(gpio_iclks[i]);
1400 sprintf(clk_name, "gpio%d_fck", i + 1);
1401 gpio_fclks[i] = clk_get(NULL, clk_name);
1402 if (IS_ERR(gpio_fclks[i]))
1403 printk(KERN_ERR "Could not get %s\n", clk_name);
1404 else
1405 clk_enable(gpio_fclks[i]);
1406 }
1407 }
1408#endif
1409
92105bb7 1410
1a8bfa1e 1411#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1412 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1413 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1414 gpio_bank_count = 2;
1415 gpio_bank = gpio_bank_1510;
1416 }
1417#endif
1418#if defined(CONFIG_ARCH_OMAP16XX)
1419 if (cpu_is_omap16xx()) {
92105bb7 1420 u32 rev;
5e1c5ff4
TL		 1421
1422 gpio_bank_count = 5;
1423 gpio_bank = gpio_bank_1610;
1424 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1425 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1426 (rev >> 4) & 0x0f, rev & 0x0f);
1427 }
1428#endif
1429#ifdef CONFIG_ARCH_OMAP730
1430 if (cpu_is_omap730()) {
1431 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1432 gpio_bank_count = 7;
1433 gpio_bank = gpio_bank_730;
1434 }
92105bb7 1435#endif
56a25641 1436
92105bb7 1437#ifdef CONFIG_ARCH_OMAP24XX
56a25641 1438 if (cpu_is_omap242x()) {
92105bb7
TL		 1439 int rev;
1440
1441 gpio_bank_count = 4;
56a25641
SMK		 1442 gpio_bank = gpio_bank_242x;
1443 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1444 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1445 (rev >> 4) & 0x0f, rev & 0x0f);
1446 }
1447 if (cpu_is_omap243x()) {
1448 int rev;
1449
1450 gpio_bank_count = 5;
1451 gpio_bank = gpio_bank_243x;
92105bb7 1452 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641 1453 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
92105bb7
TL		 1454 (rev >> 4) & 0x0f, rev & 0x0f);
1455 }
5492fb1a
SMK		 1456#endif
1457#ifdef CONFIG_ARCH_OMAP34XX
1458 if (cpu_is_omap34xx()) {
1459 int rev;
1460
1461 gpio_bank_count = OMAP34XX_NR_GPIOS;
1462 gpio_bank = gpio_bank_34xx;
1463 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1464 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1465 (rev >> 4) & 0x0f, rev & 0x0f);
1466 }
5e1c5ff4
TL		 1467#endif
1468 for (i = 0; i < gpio_bank_count; i++) {
1469 int j, gpio_count = 16;
1470
1471 bank = &gpio_bank[i];
5e1c5ff4
TL		 1472 bank->base = IO_ADDRESS(bank->base);
1473 spin_lock_init(&bank->lock);
e5c56ed3 1474 if (bank_is_mpuio(bank))
5e1c5ff4 1475 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
d11ac979 1476 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
5e1c5ff4
TL		 1477 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1478 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1479 }
d11ac979 1480 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
5e1c5ff4
TL		 1481 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1482 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1483 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4 1484 }
d11ac979 1485 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
5e1c5ff4
TL		 1486 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1487 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1488
1489 gpio_count = 32; /* 730 has 32-bit GPIOs */
1490 }
d11ac979 1491
5492fb1a 1492#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1493 if (bank->method == METHOD_GPIO_24XX) {
3ac4fa99
JY		 1494 static const u32 non_wakeup_gpios[] = {
1495 0xe203ffc0, 0x08700040
1496 };
1497
92105bb7
TL		 1498 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1499 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
14f1c3bf
JY		 1500 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1501
1502 /* Initialize interface clock ungated, module enabled */
1503 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
3ac4fa99
JY		 1504 if (i < ARRAY_SIZE(non_wakeup_gpios))
1505 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1506 gpio_count = 32;
1507 }
5e1c5ff4 1508#endif
52e31344
DB		 1509
1510 /* REVISIT eventually switch from OMAP-specific gpio structs
1511 * over to the generic ones
1512 */
1513 bank->chip.direction_input = gpio_input;
1514 bank->chip.get = gpio_get;
1515 bank->chip.direction_output = gpio_output;
1516 bank->chip.set = gpio_set;
1517 if (bank_is_mpuio(bank)) {
1518 bank->chip.label = "mpuio";
1519 bank->chip.base = OMAP_MPUIO(0);
1520 } else {
1521 bank->chip.label = "gpio";
1522 bank->chip.base = gpio;
1523 gpio += gpio_count;
1524 }
1525 bank->chip.ngpio = gpio_count;
1526
1527 gpiochip_add(&bank->chip);
1528
5e1c5ff4
TL		 1529 for (j = bank->virtual_irq_start;
1530 j < bank->virtual_irq_start + gpio_count; j++) {
8ba55c5c 1531 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
58781016 1532 set_irq_chip_data(j, bank);
e5c56ed3 1533 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1534 set_irq_chip(j, &mpuio_irq_chip);
1535 else
1536 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1537 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1538 set_irq_flags(j, IRQF_VALID);
1539 }
1540 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1541 set_irq_data(bank->irq, bank);
1542 }
1543
1544 /* Enable system clock for GPIO module.
1545 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1546 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1547 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1548
14f1c3bf
JY		 1549 /* Enable autoidle for the OCP interface */
1550 if (cpu_is_omap24xx())
1551 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1552 if (cpu_is_omap34xx())
1553 omap_writel(1 << 0, 0x48306814);
d11ac979 1554
5e1c5ff4
TL		 1555 return 0;
1556}
1557
5492fb1a 1558#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1559static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1560{
1561 int i;
1562
5492fb1a 1563 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1564 return 0;
1565
1566 for (i = 0; i < gpio_bank_count; i++) {
1567 struct gpio_bank *bank = &gpio_bank[i];
1568 void __iomem *wake_status;
1569 void __iomem *wake_clear;
1570 void __iomem *wake_set;
a6472533 1571 unsigned long flags;
92105bb7
TL		 1572
1573 switch (bank->method) {
e5c56ed3 1574#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1575 case METHOD_GPIO_1610:
1576 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1577 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1578 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1579 break;
e5c56ed3 1580#endif
5492fb1a 1581#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1582 case METHOD_GPIO_24XX:
1583 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1584 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1585 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1586 break;
e5c56ed3 1587#endif
92105bb7
TL		 1588 default:
1589 continue;
1590 }
1591
a6472533 1592 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1593 bank->saved_wakeup = __raw_readl(wake_status);
1594 __raw_writel(0xffffffff, wake_clear);
1595 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1596 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1597 }
1598
1599 return 0;
1600}
1601
1602static int omap_gpio_resume(struct sys_device *dev)
1603{
1604 int i;
1605
1606 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1607 return 0;
1608
1609 for (i = 0; i < gpio_bank_count; i++) {
1610 struct gpio_bank *bank = &gpio_bank[i];
1611 void __iomem *wake_clear;
1612 void __iomem *wake_set;
a6472533 1613 unsigned long flags;
92105bb7
TL		 1614
1615 switch (bank->method) {
e5c56ed3 1616#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1617 case METHOD_GPIO_1610:
1618 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1619 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1620 break;
e5c56ed3 1621#endif
5492fb1a 1622#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1623 case METHOD_GPIO_24XX:
0d9356cb
TL		 1624 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1625 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1626 break;
e5c56ed3 1627#endif
92105bb7
TL		 1628 default:
1629 continue;
1630 }
1631
a6472533 1632 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1633 __raw_writel(0xffffffff, wake_clear);
1634 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1635 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1636 }
1637
1638 return 0;
1639}
1640
1641static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1642 .name = "gpio",
92105bb7
TL		 1643 .suspend = omap_gpio_suspend,
1644 .resume = omap_gpio_resume,
1645};
1646
1647static struct sys_device omap_gpio_device = {
1648 .id = 0,
1649 .cls = &omap_gpio_sysclass,
1650};
3ac4fa99
JY		 1651
1652#endif
1653
5492fb1a 1654#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1655
1656static int workaround_enabled;
1657
1658void omap2_gpio_prepare_for_retention(void)
1659{
1660 int i, c = 0;
1661
1662 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1663 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1664 for (i = 0; i < gpio_bank_count; i++) {
1665 struct gpio_bank *bank = &gpio_bank[i];
1666 u32 l1, l2;
1667
1668 if (!(bank->enabled_non_wakeup_gpios))
1669 continue;
5492fb1a 1670#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1671 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1672 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1673 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1674#endif
3ac4fa99
JY		 1675 bank->saved_fallingdetect = l1;
1676 bank->saved_risingdetect = l2;
1677 l1 &= ~bank->enabled_non_wakeup_gpios;
1678 l2 &= ~bank->enabled_non_wakeup_gpios;
5492fb1a 1679#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1680 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1681 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1682#endif
3ac4fa99
JY		 1683 c++;
1684 }
1685 if (!c) {
1686 workaround_enabled = 0;
1687 return;
1688 }
1689 workaround_enabled = 1;
1690}
1691
1692void omap2_gpio_resume_after_retention(void)
1693{
1694 int i;
1695
1696 if (!workaround_enabled)
1697 return;
1698 for (i = 0; i < gpio_bank_count; i++) {
1699 struct gpio_bank *bank = &gpio_bank[i];
1700 u32 l;
1701
1702 if (!(bank->enabled_non_wakeup_gpios))
1703 continue;
5492fb1a 1704#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1705 __raw_writel(bank->saved_fallingdetect,
1706 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1707 __raw_writel(bank->saved_risingdetect,
1708 bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1709#endif
3ac4fa99
JY		 1710 /* Check if any of the non-wakeup interrupt GPIOs have changed
1711 * state. If so, generate an IRQ by software. This is
1712 * horribly racy, but it's the best we can do to work around
1713 * this silicon bug. */
5492fb1a 1714#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 1715 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
5492fb1a 1716#endif
3ac4fa99
JY		 1717 l ^= bank->saved_datain;
1718 l &= bank->non_wakeup_gpios;
1719 if (l) {
1720 u32 old0, old1;
5492fb1a 1721#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1722 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1723 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1724 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1725 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1726 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1727 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
5492fb1a 1728#endif
3ac4fa99
JY		 1729 }
1730 }
1731
1732}
1733
92105bb7
TL		 1734#endif
1735
5e1c5ff4
TL		 1736/*
1737 * This may get called early from board specific init
1a8bfa1e 1738 * for boards that have interrupts routed via FPGA.
5e1c5ff4 1739 */
277d58ef 1740int __init omap_gpio_init(void)
5e1c5ff4
TL		 1741{
1742 if (!initialized)
1743 return _omap_gpio_init();
1744 else
1745 return 0;
1746}
1747
92105bb7
TL		 1748static int __init omap_gpio_sysinit(void)
1749{
1750 int ret = 0;
1751
1752 if (!initialized)
1753 ret = _omap_gpio_init();
1754
11a78b79
DB		 1755 mpuio_init();
1756
5492fb1a
SMK		 1757#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1758 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 1759 if (ret == 0) {
1760 ret = sysdev_class_register(&omap_gpio_sysclass);
1761 if (ret == 0)
1762 ret = sysdev_register(&omap_gpio_device);
1763 }
1764 }
1765#endif
1766
1767 return ret;
1768}
1769
5e1c5ff4
TL		 1770EXPORT_SYMBOL(omap_request_gpio);
1771EXPORT_SYMBOL(omap_free_gpio);
1772EXPORT_SYMBOL(omap_set_gpio_direction);
1773EXPORT_SYMBOL(omap_set_gpio_dataout);
1774EXPORT_SYMBOL(omap_get_gpio_datain);
5e1c5ff4 1775
92105bb7 1776arch_initcall(omap_gpio_sysinit);
b9772a22
DB		 1777
1778
1779#ifdef CONFIG_DEBUG_FS
1780
1781#include <linux/debugfs.h>
1782#include <linux/seq_file.h>
1783
1784static int gpio_is_input(struct gpio_bank *bank, int mask)
1785{
1786 void __iomem *reg = bank->base;
1787
1788 switch (bank->method) {
1789 case METHOD_MPUIO:
1790 reg += OMAP_MPUIO_IO_CNTL;
1791 break;
1792 case METHOD_GPIO_1510:
1793 reg += OMAP1510_GPIO_DIR_CONTROL;
1794 break;
1795 case METHOD_GPIO_1610:
1796 reg += OMAP1610_GPIO_DIRECTION;
1797 break;
1798 case METHOD_GPIO_730:
1799 reg += OMAP730_GPIO_DIR_CONTROL;
1800 break;
1801 case METHOD_GPIO_24XX:
1802 reg += OMAP24XX_GPIO_OE;
1803 break;
1804 }
1805 return __raw_readl(reg) & mask;
1806}
1807
1808
1809static int dbg_gpio_show(struct seq_file *s, void *unused)
1810{
1811 unsigned i, j, gpio;
1812
1813 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1814 struct gpio_bank *bank = gpio_bank + i;
1815 unsigned bankwidth = 16;
1816 u32 mask = 1;
1817
e5c56ed3 1818 if (bank_is_mpuio(bank))
b9772a22 1819 gpio = OMAP_MPUIO(0);
5492fb1a 1820 else if (cpu_class_is_omap2() || cpu_is_omap730())
b9772a22
DB		 1821 bankwidth = 32;
1822
1823 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1824 unsigned irq, value, is_in, irqstat;
52e31344 1825 const char *label;
b9772a22 1826
52e31344
DB		 1827 label = gpiochip_is_requested(&bank->chip, j);
1828 if (!label)
b9772a22
DB		 1829 continue;
1830
1831 irq = bank->virtual_irq_start + j;
1832 value = omap_get_gpio_datain(gpio);
1833 is_in = gpio_is_input(bank, mask);
1834
e5c56ed3 1835 if (bank_is_mpuio(bank))
52e31344 1836 seq_printf(s, "MPUIO %2d ", j);
b9772a22 1837 else
52e31344
DB		 1838 seq_printf(s, "GPIO %3d ", gpio);
1839 seq_printf(s, "(%10s): %s %s",
1840 label,
b9772a22
DB		 1841 is_in ? "in " : "out",
1842 value ? "hi" : "lo");
1843
52e31344
DB		 1844/* FIXME for at least omap2, show pullup/pulldown state */
1845
b9772a22
DB		 1846 irqstat = irq_desc[irq].status;
1847 if (is_in && ((bank->suspend_wakeup & mask)
1848 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1849 char *trigger = NULL;
1850
1851 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1852 case IRQ_TYPE_EDGE_FALLING:
1853 trigger = "falling";
1854 break;
1855 case IRQ_TYPE_EDGE_RISING:
1856 trigger = "rising";
1857 break;
1858 case IRQ_TYPE_EDGE_BOTH:
1859 trigger = "bothedge";
1860 break;
1861 case IRQ_TYPE_LEVEL_LOW:
1862 trigger = "low";
1863 break;
1864 case IRQ_TYPE_LEVEL_HIGH:
1865 trigger = "high";
1866 break;
1867 case IRQ_TYPE_NONE:
52e31344 1868 trigger = "(?)";
b9772a22
DB		 1869 break;
1870 }
52e31344 1871 seq_printf(s, ", irq-%d %-8s%s",
b9772a22
DB		 1872 irq, trigger,
1873 (bank->suspend_wakeup & mask)
1874 ? " wakeup" : "");
1875 }
1876 seq_printf(s, "\n");
1877 }
1878
e5c56ed3 1879 if (bank_is_mpuio(bank)) {
b9772a22
DB		 1880 seq_printf(s, "\n");
1881 gpio = 0;
1882 }
1883 }
1884 return 0;
1885}
1886
1887static int dbg_gpio_open(struct inode *inode, struct file *file)
1888{
e5c56ed3 1889 return single_open(file, dbg_gpio_show, &inode->i_private);
b9772a22
DB		 1890}
1891
1892static const struct file_operations debug_fops = {
1893 .open = dbg_gpio_open,
1894 .read = seq_read,
1895 .llseek = seq_lseek,
1896 .release = single_release,
1897};
1898
1899static int __init omap_gpio_debuginit(void)
1900{
e5c56ed3
DB		 1901 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1902 NULL, NULL, &debug_fops);
b9772a22
DB		 1903 return 0;
1904}
1905late_initcall(omap_gpio_debuginit);
1906#endif
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