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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/gpio.c | |
3 | * | |
4 | * Support functions for OMAP GPIO | |
5 | * | |
92105bb7 | 6 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 8 | * |
44169075 SS |
9 | * Copyright (C) 2009 Texas Instruments |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
11 | * | |
5e1c5ff4 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
5e1c5ff4 TL |
17 | #include <linux/init.h> |
18 | #include <linux/module.h> | |
5e1c5ff4 | 19 | #include <linux/interrupt.h> |
92105bb7 TL |
20 | #include <linux/sysdev.h> |
21 | #include <linux/err.h> | |
f8ce2547 | 22 | #include <linux/clk.h> |
fced80c7 | 23 | #include <linux/io.h> |
5e1c5ff4 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e1c5ff4 | 26 | #include <asm/irq.h> |
a09e64fb RK |
27 | #include <mach/irqs.h> |
28 | #include <mach/gpio.h> | |
5e1c5ff4 | 29 | #include <asm/mach/irq.h> |
43ffcd9a | 30 | #include <plat/powerdomain.h> |
5e1c5ff4 | 31 | |
5e1c5ff4 TL |
32 | /* |
33 | * OMAP1510 GPIO registers | |
34 | */ | |
9f7065da | 35 | #define OMAP1510_GPIO_BASE 0xfffce000 |
5e1c5ff4 TL |
36 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
37 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | |
38 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | |
39 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | |
40 | #define OMAP1510_GPIO_INT_MASK 0x10 | |
41 | #define OMAP1510_GPIO_INT_STATUS 0x14 | |
42 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | |
43 | ||
44 | #define OMAP1510_IH_GPIO_BASE 64 | |
45 | ||
46 | /* | |
47 | * OMAP1610 specific GPIO registers | |
48 | */ | |
9f7065da TL |
49 | #define OMAP1610_GPIO1_BASE 0xfffbe400 |
50 | #define OMAP1610_GPIO2_BASE 0xfffbec00 | |
51 | #define OMAP1610_GPIO3_BASE 0xfffbb400 | |
52 | #define OMAP1610_GPIO4_BASE 0xfffbbc00 | |
5e1c5ff4 TL |
53 | #define OMAP1610_GPIO_REVISION 0x0000 |
54 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | |
55 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | |
56 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | |
57 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | |
92105bb7 | 58 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 |
5e1c5ff4 TL |
59 | #define OMAP1610_GPIO_DATAIN 0x002c |
60 | #define OMAP1610_GPIO_DATAOUT 0x0030 | |
61 | #define OMAP1610_GPIO_DIRECTION 0x0034 | |
62 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | |
63 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | |
64 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | |
92105bb7 | 65 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 |
5e1c5ff4 TL |
66 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 |
67 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | |
92105bb7 | 68 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 |
5e1c5ff4 TL |
69 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
70 | ||
71 | /* | |
7c006926 | 72 | * OMAP7XX specific GPIO registers |
5e1c5ff4 | 73 | */ |
9f7065da TL |
74 | #define OMAP7XX_GPIO1_BASE 0xfffbc000 |
75 | #define OMAP7XX_GPIO2_BASE 0xfffbc800 | |
76 | #define OMAP7XX_GPIO3_BASE 0xfffbd000 | |
77 | #define OMAP7XX_GPIO4_BASE 0xfffbd800 | |
78 | #define OMAP7XX_GPIO5_BASE 0xfffbe000 | |
79 | #define OMAP7XX_GPIO6_BASE 0xfffbe800 | |
7c006926 AB |
80 | #define OMAP7XX_GPIO_DATA_INPUT 0x00 |
81 | #define OMAP7XX_GPIO_DATA_OUTPUT 0x04 | |
82 | #define OMAP7XX_GPIO_DIR_CONTROL 0x08 | |
83 | #define OMAP7XX_GPIO_INT_CONTROL 0x0c | |
84 | #define OMAP7XX_GPIO_INT_MASK 0x10 | |
85 | #define OMAP7XX_GPIO_INT_STATUS 0x14 | |
5e1c5ff4 | 86 | |
9f7065da | 87 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE |
94113260 | 88 | |
92105bb7 TL |
89 | /* |
90 | * omap24xx specific GPIO registers | |
91 | */ | |
9f7065da TL |
92 | #define OMAP242X_GPIO1_BASE 0x48018000 |
93 | #define OMAP242X_GPIO2_BASE 0x4801a000 | |
94 | #define OMAP242X_GPIO3_BASE 0x4801c000 | |
95 | #define OMAP242X_GPIO4_BASE 0x4801e000 | |
56a25641 | 96 | |
9f7065da TL |
97 | #define OMAP243X_GPIO1_BASE 0x4900C000 |
98 | #define OMAP243X_GPIO2_BASE 0x4900E000 | |
99 | #define OMAP243X_GPIO3_BASE 0x49010000 | |
100 | #define OMAP243X_GPIO4_BASE 0x49012000 | |
101 | #define OMAP243X_GPIO5_BASE 0x480B6000 | |
56a25641 | 102 | |
92105bb7 TL |
103 | #define OMAP24XX_GPIO_REVISION 0x0000 |
104 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | |
105 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | |
106 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | |
bee7930f HD |
107 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
108 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | |
92105bb7 | 109 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c |
723fdb78 | 110 | #define OMAP24XX_GPIO_WAKE_EN 0x0020 |
92105bb7 TL |
111 | #define OMAP24XX_GPIO_CTRL 0x0030 |
112 | #define OMAP24XX_GPIO_OE 0x0034 | |
113 | #define OMAP24XX_GPIO_DATAIN 0x0038 | |
114 | #define OMAP24XX_GPIO_DATAOUT 0x003c | |
115 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | |
116 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | |
117 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | |
118 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | |
5eb3bb9c KH |
119 | #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 |
120 | #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 | |
92105bb7 TL |
121 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 |
122 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | |
123 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | |
124 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | |
125 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | |
126 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | |
127 | ||
78a1a6d3 SR |
128 | #define OMAP4_GPIO_REVISION 0x0000 |
129 | #define OMAP4_GPIO_SYSCONFIG 0x0010 | |
130 | #define OMAP4_GPIO_EOI 0x0020 | |
131 | #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 | |
132 | #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 | |
133 | #define OMAP4_GPIO_IRQSTATUS0 0x002c | |
134 | #define OMAP4_GPIO_IRQSTATUS1 0x0030 | |
135 | #define OMAP4_GPIO_IRQSTATUSSET0 0x0034 | |
136 | #define OMAP4_GPIO_IRQSTATUSSET1 0x0038 | |
137 | #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c | |
138 | #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 | |
139 | #define OMAP4_GPIO_IRQWAKEN0 0x0044 | |
140 | #define OMAP4_GPIO_IRQWAKEN1 0x0048 | |
9f096868 C |
141 | #define OMAP4_GPIO_SYSSTATUS 0x0114 |
142 | #define OMAP4_GPIO_IRQENABLE1 0x011c | |
143 | #define OMAP4_GPIO_WAKE_EN 0x0120 | |
144 | #define OMAP4_GPIO_IRQSTATUS2 0x0128 | |
145 | #define OMAP4_GPIO_IRQENABLE2 0x012c | |
78a1a6d3 SR |
146 | #define OMAP4_GPIO_CTRL 0x0130 |
147 | #define OMAP4_GPIO_OE 0x0134 | |
148 | #define OMAP4_GPIO_DATAIN 0x0138 | |
149 | #define OMAP4_GPIO_DATAOUT 0x013c | |
150 | #define OMAP4_GPIO_LEVELDETECT0 0x0140 | |
151 | #define OMAP4_GPIO_LEVELDETECT1 0x0144 | |
152 | #define OMAP4_GPIO_RISINGDETECT 0x0148 | |
153 | #define OMAP4_GPIO_FALLINGDETECT 0x014c | |
154 | #define OMAP4_GPIO_DEBOUNCENABLE 0x0150 | |
155 | #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 | |
9f096868 C |
156 | #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160 |
157 | #define OMAP4_GPIO_SETIRQENABLE1 0x0164 | |
158 | #define OMAP4_GPIO_CLEARWKUENA 0x0180 | |
159 | #define OMAP4_GPIO_SETWKUENA 0x0184 | |
78a1a6d3 SR |
160 | #define OMAP4_GPIO_CLEARDATAOUT 0x0190 |
161 | #define OMAP4_GPIO_SETDATAOUT 0x0194 | |
5492fb1a SMK |
162 | /* |
163 | * omap34xx specific GPIO registers | |
164 | */ | |
165 | ||
9f7065da TL |
166 | #define OMAP34XX_GPIO1_BASE 0x48310000 |
167 | #define OMAP34XX_GPIO2_BASE 0x49050000 | |
168 | #define OMAP34XX_GPIO3_BASE 0x49052000 | |
169 | #define OMAP34XX_GPIO4_BASE 0x49054000 | |
170 | #define OMAP34XX_GPIO5_BASE 0x49056000 | |
171 | #define OMAP34XX_GPIO6_BASE 0x49058000 | |
5492fb1a | 172 | |
44169075 SS |
173 | /* |
174 | * OMAP44XX specific GPIO registers | |
175 | */ | |
9f7065da TL |
176 | #define OMAP44XX_GPIO1_BASE 0x4a310000 |
177 | #define OMAP44XX_GPIO2_BASE 0x48055000 | |
178 | #define OMAP44XX_GPIO3_BASE 0x48057000 | |
179 | #define OMAP44XX_GPIO4_BASE 0x48059000 | |
180 | #define OMAP44XX_GPIO5_BASE 0x4805B000 | |
181 | #define OMAP44XX_GPIO6_BASE 0x4805D000 | |
5492fb1a | 182 | |
5e1c5ff4 | 183 | struct gpio_bank { |
9f7065da | 184 | unsigned long pbase; |
92105bb7 | 185 | void __iomem *base; |
5e1c5ff4 TL |
186 | u16 irq; |
187 | u16 virtual_irq_start; | |
92105bb7 | 188 | int method; |
140455fa | 189 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 TL |
190 | u32 suspend_wakeup; |
191 | u32 saved_wakeup; | |
3ac4fa99 | 192 | #endif |
140455fa | 193 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 JY |
194 | u32 non_wakeup_gpios; |
195 | u32 enabled_non_wakeup_gpios; | |
196 | ||
197 | u32 saved_datain; | |
198 | u32 saved_fallingdetect; | |
199 | u32 saved_risingdetect; | |
200 | #endif | |
b144ff6f | 201 | u32 level_mask; |
4318f36b | 202 | u32 toggle_mask; |
5e1c5ff4 | 203 | spinlock_t lock; |
52e31344 | 204 | struct gpio_chip chip; |
89db9482 | 205 | struct clk *dbck; |
058af1ea | 206 | u32 mod_usage; |
8865b9b6 | 207 | u32 dbck_enable_mask; |
5e1c5ff4 TL |
208 | }; |
209 | ||
210 | #define METHOD_MPUIO 0 | |
211 | #define METHOD_GPIO_1510 1 | |
212 | #define METHOD_GPIO_1610 2 | |
7c006926 | 213 | #define METHOD_GPIO_7XX 3 |
56739a69 | 214 | #define METHOD_GPIO_24XX 5 |
3f1686a9 | 215 | #define METHOD_GPIO_44XX 6 |
5e1c5ff4 | 216 | |
92105bb7 | 217 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 218 | static struct gpio_bank gpio_bank_1610[5] = { |
9f7065da TL |
219 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, |
220 | METHOD_MPUIO }, | |
221 | { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | |
222 | METHOD_GPIO_1610 }, | |
223 | { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, | |
224 | METHOD_GPIO_1610 }, | |
225 | { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, | |
226 | METHOD_GPIO_1610 }, | |
227 | { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, | |
228 | METHOD_GPIO_1610 }, | |
5e1c5ff4 TL |
229 | }; |
230 | #endif | |
231 | ||
1a8bfa1e | 232 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 233 | static struct gpio_bank gpio_bank_1510[2] = { |
9f7065da TL |
234 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, |
235 | METHOD_MPUIO }, | |
236 | { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | |
237 | METHOD_GPIO_1510 } | |
5e1c5ff4 TL |
238 | }; |
239 | #endif | |
240 | ||
b718aa81 | 241 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 | 242 | static struct gpio_bank gpio_bank_7xx[7] = { |
9f7065da TL |
243 | { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE, |
244 | METHOD_MPUIO }, | |
245 | { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, | |
246 | METHOD_GPIO_7XX }, | |
247 | { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
248 | METHOD_GPIO_7XX }, | |
249 | { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
250 | METHOD_GPIO_7XX }, | |
251 | { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
252 | METHOD_GPIO_7XX }, | |
253 | { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
254 | METHOD_GPIO_7XX }, | |
255 | { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, | |
256 | METHOD_GPIO_7XX }, | |
5e1c5ff4 TL |
257 | }; |
258 | #endif | |
259 | ||
088ef950 | 260 | #ifdef CONFIG_ARCH_OMAP2 |
56a25641 SMK |
261 | |
262 | static struct gpio_bank gpio_bank_242x[4] = { | |
9f7065da TL |
263 | { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
264 | METHOD_GPIO_24XX }, | |
265 | { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
266 | METHOD_GPIO_24XX }, | |
267 | { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
268 | METHOD_GPIO_24XX }, | |
269 | { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
270 | METHOD_GPIO_24XX }, | |
92105bb7 | 271 | }; |
56a25641 SMK |
272 | |
273 | static struct gpio_bank gpio_bank_243x[5] = { | |
9f7065da TL |
274 | { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
275 | METHOD_GPIO_24XX }, | |
276 | { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
277 | METHOD_GPIO_24XX }, | |
278 | { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
279 | METHOD_GPIO_24XX }, | |
280 | { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
281 | METHOD_GPIO_24XX }, | |
282 | { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
283 | METHOD_GPIO_24XX }, | |
56a25641 SMK |
284 | }; |
285 | ||
92105bb7 TL |
286 | #endif |
287 | ||
a8eb7ca0 | 288 | #ifdef CONFIG_ARCH_OMAP3 |
5492fb1a | 289 | static struct gpio_bank gpio_bank_34xx[6] = { |
9f7065da TL |
290 | { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, |
291 | METHOD_GPIO_24XX }, | |
292 | { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
293 | METHOD_GPIO_24XX }, | |
294 | { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
295 | METHOD_GPIO_24XX }, | |
296 | { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
297 | METHOD_GPIO_24XX }, | |
298 | { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
299 | METHOD_GPIO_24XX }, | |
300 | { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, | |
301 | METHOD_GPIO_24XX }, | |
5492fb1a SMK |
302 | }; |
303 | ||
40c670f0 RN |
304 | struct omap3_gpio_regs { |
305 | u32 sysconfig; | |
306 | u32 irqenable1; | |
307 | u32 irqenable2; | |
308 | u32 wake_en; | |
309 | u32 ctrl; | |
310 | u32 oe; | |
311 | u32 leveldetect0; | |
312 | u32 leveldetect1; | |
313 | u32 risingdetect; | |
314 | u32 fallingdetect; | |
315 | u32 dataout; | |
5492fb1a SMK |
316 | }; |
317 | ||
40c670f0 | 318 | static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; |
5492fb1a SMK |
319 | #endif |
320 | ||
44169075 SS |
321 | #ifdef CONFIG_ARCH_OMAP4 |
322 | static struct gpio_bank gpio_bank_44xx[6] = { | |
5772ca7d | 323 | { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE, |
3f1686a9 | 324 | METHOD_GPIO_44XX }, |
5772ca7d | 325 | { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32, |
3f1686a9 | 326 | METHOD_GPIO_44XX }, |
5772ca7d | 327 | { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64, |
3f1686a9 | 328 | METHOD_GPIO_44XX }, |
5772ca7d | 329 | { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96, |
3f1686a9 | 330 | METHOD_GPIO_44XX }, |
5772ca7d | 331 | { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128, |
3f1686a9 | 332 | METHOD_GPIO_44XX }, |
5772ca7d | 333 | { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160, |
3f1686a9 | 334 | METHOD_GPIO_44XX }, |
44169075 SS |
335 | }; |
336 | ||
337 | #endif | |
338 | ||
5e1c5ff4 TL |
339 | static struct gpio_bank *gpio_bank; |
340 | static int gpio_bank_count; | |
341 | ||
342 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
343 | { | |
6e60e79a | 344 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
345 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
346 | return &gpio_bank[0]; | |
347 | return &gpio_bank[1]; | |
348 | } | |
5e1c5ff4 TL |
349 | if (cpu_is_omap16xx()) { |
350 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
351 | return &gpio_bank[0]; | |
352 | return &gpio_bank[1 + (gpio >> 4)]; | |
353 | } | |
56739a69 | 354 | if (cpu_is_omap7xx()) { |
5e1c5ff4 TL |
355 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
356 | return &gpio_bank[0]; | |
357 | return &gpio_bank[1 + (gpio >> 5)]; | |
358 | } | |
92105bb7 TL |
359 | if (cpu_is_omap24xx()) |
360 | return &gpio_bank[gpio >> 5]; | |
44169075 | 361 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 362 | return &gpio_bank[gpio >> 5]; |
e031ab23 DB |
363 | BUG(); |
364 | return NULL; | |
5e1c5ff4 TL |
365 | } |
366 | ||
367 | static inline int get_gpio_index(int gpio) | |
368 | { | |
56739a69 | 369 | if (cpu_is_omap7xx()) |
5e1c5ff4 | 370 | return gpio & 0x1f; |
92105bb7 TL |
371 | if (cpu_is_omap24xx()) |
372 | return gpio & 0x1f; | |
44169075 | 373 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 374 | return gpio & 0x1f; |
92105bb7 | 375 | return gpio & 0x0f; |
5e1c5ff4 TL |
376 | } |
377 | ||
378 | static inline int gpio_valid(int gpio) | |
379 | { | |
380 | if (gpio < 0) | |
381 | return -1; | |
d11ac979 | 382 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 383 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
384 | return -1; |
385 | return 0; | |
386 | } | |
6e60e79a | 387 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 388 | return 0; |
5e1c5ff4 TL |
389 | if ((cpu_is_omap16xx()) && gpio < 64) |
390 | return 0; | |
56739a69 | 391 | if (cpu_is_omap7xx() && gpio < 192) |
5e1c5ff4 | 392 | return 0; |
25d6f630 TL |
393 | if (cpu_is_omap2420() && gpio < 128) |
394 | return 0; | |
395 | if (cpu_is_omap2430() && gpio < 160) | |
92105bb7 | 396 | return 0; |
44169075 | 397 | if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) |
5492fb1a | 398 | return 0; |
5e1c5ff4 TL |
399 | return -1; |
400 | } | |
401 | ||
402 | static int check_gpio(int gpio) | |
403 | { | |
d32b20fc | 404 | if (unlikely(gpio_valid(gpio) < 0)) { |
5e1c5ff4 TL |
405 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); |
406 | dump_stack(); | |
407 | return -1; | |
408 | } | |
409 | return 0; | |
410 | } | |
411 | ||
412 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
413 | { | |
92105bb7 | 414 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
415 | u32 l; |
416 | ||
417 | switch (bank->method) { | |
e5c56ed3 | 418 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
419 | case METHOD_MPUIO: |
420 | reg += OMAP_MPUIO_IO_CNTL; | |
421 | break; | |
e5c56ed3 DB |
422 | #endif |
423 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
424 | case METHOD_GPIO_1510: |
425 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
426 | break; | |
e5c56ed3 DB |
427 | #endif |
428 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
429 | case METHOD_GPIO_1610: |
430 | reg += OMAP1610_GPIO_DIRECTION; | |
431 | break; | |
e5c56ed3 | 432 | #endif |
b718aa81 | 433 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
434 | case METHOD_GPIO_7XX: |
435 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
56739a69 ZM |
436 | break; |
437 | #endif | |
a8eb7ca0 | 438 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
439 | case METHOD_GPIO_24XX: |
440 | reg += OMAP24XX_GPIO_OE; | |
441 | break; | |
78a1a6d3 SR |
442 | #endif |
443 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 444 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
445 | reg += OMAP4_GPIO_OE; |
446 | break; | |
e5c56ed3 DB |
447 | #endif |
448 | default: | |
449 | WARN_ON(1); | |
450 | return; | |
5e1c5ff4 TL |
451 | } |
452 | l = __raw_readl(reg); | |
453 | if (is_input) | |
454 | l |= 1 << gpio; | |
455 | else | |
456 | l &= ~(1 << gpio); | |
457 | __raw_writel(l, reg); | |
458 | } | |
459 | ||
5e1c5ff4 TL |
460 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) |
461 | { | |
92105bb7 | 462 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
463 | u32 l = 0; |
464 | ||
465 | switch (bank->method) { | |
e5c56ed3 | 466 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
467 | case METHOD_MPUIO: |
468 | reg += OMAP_MPUIO_OUTPUT; | |
469 | l = __raw_readl(reg); | |
470 | if (enable) | |
471 | l |= 1 << gpio; | |
472 | else | |
473 | l &= ~(1 << gpio); | |
474 | break; | |
e5c56ed3 DB |
475 | #endif |
476 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
477 | case METHOD_GPIO_1510: |
478 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
479 | l = __raw_readl(reg); | |
480 | if (enable) | |
481 | l |= 1 << gpio; | |
482 | else | |
483 | l &= ~(1 << gpio); | |
484 | break; | |
e5c56ed3 DB |
485 | #endif |
486 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
487 | case METHOD_GPIO_1610: |
488 | if (enable) | |
489 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
490 | else | |
491 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
492 | l = 1 << gpio; | |
493 | break; | |
e5c56ed3 | 494 | #endif |
b718aa81 | 495 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
496 | case METHOD_GPIO_7XX: |
497 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
56739a69 ZM |
498 | l = __raw_readl(reg); |
499 | if (enable) | |
500 | l |= 1 << gpio; | |
501 | else | |
502 | l &= ~(1 << gpio); | |
503 | break; | |
504 | #endif | |
a8eb7ca0 | 505 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
506 | case METHOD_GPIO_24XX: |
507 | if (enable) | |
508 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
509 | else | |
510 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
511 | l = 1 << gpio; | |
512 | break; | |
78a1a6d3 SR |
513 | #endif |
514 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 515 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
516 | if (enable) |
517 | reg += OMAP4_GPIO_SETDATAOUT; | |
518 | else | |
519 | reg += OMAP4_GPIO_CLEARDATAOUT; | |
520 | l = 1 << gpio; | |
521 | break; | |
e5c56ed3 | 522 | #endif |
5e1c5ff4 | 523 | default: |
e5c56ed3 | 524 | WARN_ON(1); |
5e1c5ff4 TL |
525 | return; |
526 | } | |
527 | __raw_writel(l, reg); | |
528 | } | |
529 | ||
b37c45b8 | 530 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
5e1c5ff4 | 531 | { |
92105bb7 | 532 | void __iomem *reg; |
5e1c5ff4 TL |
533 | |
534 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 535 | return -EINVAL; |
5e1c5ff4 TL |
536 | reg = bank->base; |
537 | switch (bank->method) { | |
e5c56ed3 | 538 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
539 | case METHOD_MPUIO: |
540 | reg += OMAP_MPUIO_INPUT_LATCH; | |
541 | break; | |
e5c56ed3 DB |
542 | #endif |
543 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
544 | case METHOD_GPIO_1510: |
545 | reg += OMAP1510_GPIO_DATA_INPUT; | |
546 | break; | |
e5c56ed3 DB |
547 | #endif |
548 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
549 | case METHOD_GPIO_1610: |
550 | reg += OMAP1610_GPIO_DATAIN; | |
551 | break; | |
e5c56ed3 | 552 | #endif |
b718aa81 | 553 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
554 | case METHOD_GPIO_7XX: |
555 | reg += OMAP7XX_GPIO_DATA_INPUT; | |
56739a69 ZM |
556 | break; |
557 | #endif | |
a8eb7ca0 | 558 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
559 | case METHOD_GPIO_24XX: |
560 | reg += OMAP24XX_GPIO_DATAIN; | |
561 | break; | |
78a1a6d3 SR |
562 | #endif |
563 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 564 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
565 | reg += OMAP4_GPIO_DATAIN; |
566 | break; | |
e5c56ed3 | 567 | #endif |
5e1c5ff4 | 568 | default: |
e5c56ed3 | 569 | return -EINVAL; |
5e1c5ff4 | 570 | } |
92105bb7 TL |
571 | return (__raw_readl(reg) |
572 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
573 | } |
574 | ||
b37c45b8 RQ |
575 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
576 | { | |
577 | void __iomem *reg; | |
578 | ||
579 | if (check_gpio(gpio) < 0) | |
580 | return -EINVAL; | |
581 | reg = bank->base; | |
582 | ||
583 | switch (bank->method) { | |
584 | #ifdef CONFIG_ARCH_OMAP1 | |
585 | case METHOD_MPUIO: | |
586 | reg += OMAP_MPUIO_OUTPUT; | |
587 | break; | |
588 | #endif | |
589 | #ifdef CONFIG_ARCH_OMAP15XX | |
590 | case METHOD_GPIO_1510: | |
591 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
592 | break; | |
593 | #endif | |
594 | #ifdef CONFIG_ARCH_OMAP16XX | |
595 | case METHOD_GPIO_1610: | |
596 | reg += OMAP1610_GPIO_DATAOUT; | |
597 | break; | |
598 | #endif | |
b718aa81 | 599 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
600 | case METHOD_GPIO_7XX: |
601 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
b37c45b8 RQ |
602 | break; |
603 | #endif | |
9f096868 | 604 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
b37c45b8 RQ |
605 | case METHOD_GPIO_24XX: |
606 | reg += OMAP24XX_GPIO_DATAOUT; | |
607 | break; | |
9f096868 C |
608 | #endif |
609 | #ifdef CONFIG_ARCH_OMAP4 | |
610 | case METHOD_GPIO_44XX: | |
611 | reg += OMAP4_GPIO_DATAOUT; | |
612 | break; | |
b37c45b8 RQ |
613 | #endif |
614 | default: | |
615 | return -EINVAL; | |
616 | } | |
617 | ||
618 | return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; | |
619 | } | |
620 | ||
92105bb7 TL |
621 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
622 | do { \ | |
623 | int l = __raw_readl(base + reg); \ | |
624 | if (set) l |= bit_mask; \ | |
625 | else l &= ~bit_mask; \ | |
626 | __raw_writel(l, base + reg); \ | |
627 | } while(0) | |
628 | ||
168ef3d9 FB |
629 | /** |
630 | * _set_gpio_debounce - low level gpio debounce time | |
631 | * @bank: the gpio bank we're acting upon | |
632 | * @gpio: the gpio number on this @gpio | |
633 | * @debounce: debounce time to use | |
634 | * | |
635 | * OMAP's debounce time is in 31us steps so we need | |
636 | * to convert and round up to the closest unit. | |
637 | */ | |
638 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
639 | unsigned debounce) | |
640 | { | |
641 | void __iomem *reg = bank->base; | |
642 | u32 val; | |
643 | u32 l; | |
644 | ||
645 | if (debounce < 32) | |
646 | debounce = 0x01; | |
647 | else if (debounce > 7936) | |
648 | debounce = 0xff; | |
649 | else | |
650 | debounce = (debounce / 0x1f) - 1; | |
651 | ||
652 | l = 1 << get_gpio_index(gpio); | |
653 | ||
654 | if (cpu_is_omap44xx()) | |
655 | reg += OMAP4_GPIO_DEBOUNCINGTIME; | |
656 | else | |
657 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
658 | ||
659 | __raw_writel(debounce, reg); | |
660 | ||
661 | reg = bank->base; | |
662 | if (cpu_is_omap44xx()) | |
663 | reg += OMAP4_GPIO_DEBOUNCENABLE; | |
664 | else | |
665 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | |
666 | ||
667 | val = __raw_readl(reg); | |
668 | ||
669 | if (debounce) { | |
670 | val |= l; | |
671 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) | |
672 | clk_enable(bank->dbck); | |
673 | } else { | |
674 | val &= ~l; | |
675 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) | |
676 | clk_disable(bank->dbck); | |
677 | } | |
f7ec0b0b | 678 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
679 | |
680 | __raw_writel(val, reg); | |
681 | } | |
682 | ||
140455fa | 683 | #ifdef CONFIG_ARCH_OMAP2PLUS |
5eb3bb9c KH |
684 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
685 | int trigger) | |
5e1c5ff4 | 686 | { |
3ac4fa99 | 687 | void __iomem *base = bank->base; |
92105bb7 | 688 | u32 gpio_bit = 1 << gpio; |
78a1a6d3 | 689 | u32 val; |
92105bb7 | 690 | |
78a1a6d3 SR |
691 | if (cpu_is_omap44xx()) { |
692 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit, | |
693 | trigger & IRQ_TYPE_LEVEL_LOW); | |
694 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit, | |
695 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
696 | MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit, | |
697 | trigger & IRQ_TYPE_EDGE_RISING); | |
698 | MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit, | |
699 | trigger & IRQ_TYPE_EDGE_FALLING); | |
700 | } else { | |
701 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
702 | trigger & IRQ_TYPE_LEVEL_LOW); | |
703 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, | |
704 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
705 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, | |
706 | trigger & IRQ_TYPE_EDGE_RISING); | |
707 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, | |
708 | trigger & IRQ_TYPE_EDGE_FALLING); | |
709 | } | |
3ac4fa99 | 710 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
78a1a6d3 SR |
711 | if (cpu_is_omap44xx()) { |
712 | if (trigger != 0) | |
713 | __raw_writel(1 << gpio, bank->base+ | |
714 | OMAP4_GPIO_IRQWAKEN0); | |
715 | else { | |
716 | val = __raw_readl(bank->base + | |
717 | OMAP4_GPIO_IRQWAKEN0); | |
718 | __raw_writel(val & (~(1 << gpio)), bank->base + | |
719 | OMAP4_GPIO_IRQWAKEN0); | |
720 | } | |
721 | } else { | |
699117a6 CW |
722 | /* |
723 | * GPIO wakeup request can only be generated on edge | |
724 | * transitions | |
725 | */ | |
726 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
78a1a6d3 | 727 | __raw_writel(1 << gpio, bank->base |
5eb3bb9c | 728 | + OMAP24XX_GPIO_SETWKUENA); |
78a1a6d3 SR |
729 | else |
730 | __raw_writel(1 << gpio, bank->base | |
5eb3bb9c | 731 | + OMAP24XX_GPIO_CLEARWKUENA); |
78a1a6d3 | 732 | } |
a118b5f3 TK |
733 | } |
734 | /* This part needs to be executed always for OMAP34xx */ | |
735 | if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) { | |
699117a6 CW |
736 | /* |
737 | * Log the edge gpio and manually trigger the IRQ | |
738 | * after resume if the input level changes | |
739 | * to avoid irq lost during PER RET/OFF mode | |
740 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
741 | */ | |
742 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
743 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
744 | else | |
745 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
746 | } | |
5eb3bb9c | 747 | |
78a1a6d3 SR |
748 | if (cpu_is_omap44xx()) { |
749 | bank->level_mask = | |
750 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | | |
751 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); | |
752 | } else { | |
753 | bank->level_mask = | |
754 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
755 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
756 | } | |
92105bb7 | 757 | } |
3ac4fa99 | 758 | #endif |
92105bb7 | 759 | |
9198bcd3 | 760 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
761 | /* |
762 | * This only applies to chips that can't do both rising and falling edge | |
763 | * detection at once. For all other chips, this function is a noop. | |
764 | */ | |
765 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
766 | { | |
767 | void __iomem *reg = bank->base; | |
768 | u32 l = 0; | |
769 | ||
770 | switch (bank->method) { | |
4318f36b CM |
771 | case METHOD_MPUIO: |
772 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
773 | break; | |
4318f36b CM |
774 | #ifdef CONFIG_ARCH_OMAP15XX |
775 | case METHOD_GPIO_1510: | |
776 | reg += OMAP1510_GPIO_INT_CONTROL; | |
777 | break; | |
778 | #endif | |
779 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | |
780 | case METHOD_GPIO_7XX: | |
781 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
782 | break; | |
783 | #endif | |
784 | default: | |
785 | return; | |
786 | } | |
787 | ||
788 | l = __raw_readl(reg); | |
789 | if ((l >> gpio) & 1) | |
790 | l &= ~(1 << gpio); | |
791 | else | |
792 | l |= 1 << gpio; | |
793 | ||
794 | __raw_writel(l, reg); | |
795 | } | |
9198bcd3 | 796 | #endif |
4318f36b | 797 | |
92105bb7 TL |
798 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
799 | { | |
800 | void __iomem *reg = bank->base; | |
801 | u32 l = 0; | |
5e1c5ff4 TL |
802 | |
803 | switch (bank->method) { | |
e5c56ed3 | 804 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
805 | case METHOD_MPUIO: |
806 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
807 | l = __raw_readl(reg); | |
29501577 | 808 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 809 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 810 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 811 | l |= 1 << gpio; |
6cab4860 | 812 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 813 | l &= ~(1 << gpio); |
92105bb7 TL |
814 | else |
815 | goto bad; | |
5e1c5ff4 | 816 | break; |
e5c56ed3 DB |
817 | #endif |
818 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
819 | case METHOD_GPIO_1510: |
820 | reg += OMAP1510_GPIO_INT_CONTROL; | |
821 | l = __raw_readl(reg); | |
29501577 | 822 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 823 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 824 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 825 | l |= 1 << gpio; |
6cab4860 | 826 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 827 | l &= ~(1 << gpio); |
92105bb7 TL |
828 | else |
829 | goto bad; | |
5e1c5ff4 | 830 | break; |
e5c56ed3 | 831 | #endif |
3ac4fa99 | 832 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 833 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
834 | if (gpio & 0x08) |
835 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
836 | else | |
837 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
838 | gpio &= 0x07; | |
839 | l = __raw_readl(reg); | |
840 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 841 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 842 | l |= 2 << (gpio << 1); |
6cab4860 | 843 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 844 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
845 | if (trigger) |
846 | /* Enable wake-up during idle for dynamic tick */ | |
847 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
848 | else | |
849 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 850 | break; |
3ac4fa99 | 851 | #endif |
b718aa81 | 852 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
853 | case METHOD_GPIO_7XX: |
854 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
56739a69 | 855 | l = __raw_readl(reg); |
29501577 | 856 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 857 | bank->toggle_mask |= 1 << gpio; |
56739a69 ZM |
858 | if (trigger & IRQ_TYPE_EDGE_RISING) |
859 | l |= 1 << gpio; | |
860 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | |
861 | l &= ~(1 << gpio); | |
862 | else | |
863 | goto bad; | |
864 | break; | |
865 | #endif | |
140455fa | 866 | #ifdef CONFIG_ARCH_OMAP2PLUS |
92105bb7 | 867 | case METHOD_GPIO_24XX: |
3f1686a9 | 868 | case METHOD_GPIO_44XX: |
3ac4fa99 | 869 | set_24xx_gpio_triggering(bank, gpio, trigger); |
5e1c5ff4 | 870 | break; |
3ac4fa99 | 871 | #endif |
5e1c5ff4 | 872 | default: |
92105bb7 | 873 | goto bad; |
5e1c5ff4 | 874 | } |
92105bb7 TL |
875 | __raw_writel(l, reg); |
876 | return 0; | |
877 | bad: | |
878 | return -EINVAL; | |
5e1c5ff4 TL |
879 | } |
880 | ||
92105bb7 | 881 | static int gpio_irq_type(unsigned irq, unsigned type) |
5e1c5ff4 TL |
882 | { |
883 | struct gpio_bank *bank; | |
92105bb7 TL |
884 | unsigned gpio; |
885 | int retval; | |
a6472533 | 886 | unsigned long flags; |
92105bb7 | 887 | |
5492fb1a | 888 | if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) |
92105bb7 TL |
889 | gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); |
890 | else | |
891 | gpio = irq - IH_GPIO_BASE; | |
5e1c5ff4 TL |
892 | |
893 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
894 | return -EINVAL; |
895 | ||
e5c56ed3 | 896 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 897 | return -EINVAL; |
e5c56ed3 DB |
898 | |
899 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 900 | if (!cpu_class_is_omap2() |
e5c56ed3 | 901 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
902 | return -EINVAL; |
903 | ||
58781016 | 904 | bank = get_irq_chip_data(irq); |
a6472533 | 905 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 906 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
b9772a22 DB |
907 | if (retval == 0) { |
908 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
909 | irq_desc[irq].status |= type; | |
910 | } | |
a6472533 | 911 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
912 | |
913 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
914 | __set_irq_handler_unlocked(irq, handle_level_irq); | |
915 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
916 | __set_irq_handler_unlocked(irq, handle_edge_irq); | |
917 | ||
92105bb7 | 918 | return retval; |
5e1c5ff4 TL |
919 | } |
920 | ||
921 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
922 | { | |
92105bb7 | 923 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
924 | |
925 | switch (bank->method) { | |
e5c56ed3 | 926 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
927 | case METHOD_MPUIO: |
928 | /* MPUIO irqstatus is reset by reading the status register, | |
929 | * so do nothing here */ | |
930 | return; | |
e5c56ed3 DB |
931 | #endif |
932 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
933 | case METHOD_GPIO_1510: |
934 | reg += OMAP1510_GPIO_INT_STATUS; | |
935 | break; | |
e5c56ed3 DB |
936 | #endif |
937 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
938 | case METHOD_GPIO_1610: |
939 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
940 | break; | |
e5c56ed3 | 941 | #endif |
b718aa81 | 942 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
943 | case METHOD_GPIO_7XX: |
944 | reg += OMAP7XX_GPIO_INT_STATUS; | |
56739a69 ZM |
945 | break; |
946 | #endif | |
a8eb7ca0 | 947 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
948 | case METHOD_GPIO_24XX: |
949 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
950 | break; | |
78a1a6d3 SR |
951 | #endif |
952 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 953 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
954 | reg += OMAP4_GPIO_IRQSTATUS0; |
955 | break; | |
e5c56ed3 | 956 | #endif |
5e1c5ff4 | 957 | default: |
e5c56ed3 | 958 | WARN_ON(1); |
5e1c5ff4 TL |
959 | return; |
960 | } | |
961 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
962 | |
963 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
3f1686a9 TL |
964 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
965 | reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; | |
966 | else if (cpu_is_omap44xx()) | |
967 | reg = bank->base + OMAP4_GPIO_IRQSTATUS1; | |
968 | ||
78a1a6d3 | 969 | if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
bedfd154 RQ |
970 | __raw_writel(gpio_mask, reg); |
971 | ||
972 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
973 | __raw_readl(reg); | |
78a1a6d3 | 974 | } |
5e1c5ff4 TL |
975 | } |
976 | ||
977 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
978 | { | |
979 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
980 | } | |
981 | ||
ea6dedd7 ID |
982 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
983 | { | |
984 | void __iomem *reg = bank->base; | |
99c47707 ID |
985 | int inv = 0; |
986 | u32 l; | |
987 | u32 mask; | |
ea6dedd7 ID |
988 | |
989 | switch (bank->method) { | |
e5c56ed3 | 990 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 ID |
991 | case METHOD_MPUIO: |
992 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
99c47707 ID |
993 | mask = 0xffff; |
994 | inv = 1; | |
ea6dedd7 | 995 | break; |
e5c56ed3 DB |
996 | #endif |
997 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
998 | case METHOD_GPIO_1510: |
999 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
1000 | mask = 0xffff; |
1001 | inv = 1; | |
ea6dedd7 | 1002 | break; |
e5c56ed3 DB |
1003 | #endif |
1004 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
1005 | case METHOD_GPIO_1610: |
1006 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 1007 | mask = 0xffff; |
ea6dedd7 | 1008 | break; |
e5c56ed3 | 1009 | #endif |
b718aa81 | 1010 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1011 | case METHOD_GPIO_7XX: |
1012 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
1013 | mask = 0xffffffff; |
1014 | inv = 1; | |
1015 | break; | |
1016 | #endif | |
a8eb7ca0 | 1017 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
ea6dedd7 ID |
1018 | case METHOD_GPIO_24XX: |
1019 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 1020 | mask = 0xffffffff; |
ea6dedd7 | 1021 | break; |
78a1a6d3 SR |
1022 | #endif |
1023 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 1024 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1025 | reg += OMAP4_GPIO_IRQSTATUSSET0; |
1026 | mask = 0xffffffff; | |
1027 | break; | |
e5c56ed3 | 1028 | #endif |
ea6dedd7 | 1029 | default: |
e5c56ed3 | 1030 | WARN_ON(1); |
ea6dedd7 ID |
1031 | return 0; |
1032 | } | |
1033 | ||
99c47707 ID |
1034 | l = __raw_readl(reg); |
1035 | if (inv) | |
1036 | l = ~l; | |
1037 | l &= mask; | |
1038 | return l; | |
ea6dedd7 ID |
1039 | } |
1040 | ||
5e1c5ff4 TL |
1041 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
1042 | { | |
92105bb7 | 1043 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
1044 | u32 l; |
1045 | ||
1046 | switch (bank->method) { | |
e5c56ed3 | 1047 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
1048 | case METHOD_MPUIO: |
1049 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
1050 | l = __raw_readl(reg); | |
1051 | if (enable) | |
1052 | l &= ~(gpio_mask); | |
1053 | else | |
1054 | l |= gpio_mask; | |
1055 | break; | |
e5c56ed3 DB |
1056 | #endif |
1057 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
1058 | case METHOD_GPIO_1510: |
1059 | reg += OMAP1510_GPIO_INT_MASK; | |
1060 | l = __raw_readl(reg); | |
1061 | if (enable) | |
1062 | l &= ~(gpio_mask); | |
1063 | else | |
1064 | l |= gpio_mask; | |
1065 | break; | |
e5c56ed3 DB |
1066 | #endif |
1067 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
1068 | case METHOD_GPIO_1610: |
1069 | if (enable) | |
1070 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
1071 | else | |
1072 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
1073 | l = gpio_mask; | |
1074 | break; | |
e5c56ed3 | 1075 | #endif |
b718aa81 | 1076 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1077 | case METHOD_GPIO_7XX: |
1078 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
1079 | l = __raw_readl(reg); |
1080 | if (enable) | |
1081 | l &= ~(gpio_mask); | |
1082 | else | |
1083 | l |= gpio_mask; | |
1084 | break; | |
1085 | #endif | |
a8eb7ca0 | 1086 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
1087 | case METHOD_GPIO_24XX: |
1088 | if (enable) | |
1089 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
1090 | else | |
1091 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
1092 | l = gpio_mask; | |
1093 | break; | |
78a1a6d3 SR |
1094 | #endif |
1095 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1096 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1097 | if (enable) |
1098 | reg += OMAP4_GPIO_IRQSTATUSSET0; | |
1099 | else | |
1100 | reg += OMAP4_GPIO_IRQSTATUSCLR0; | |
1101 | l = gpio_mask; | |
1102 | break; | |
e5c56ed3 | 1103 | #endif |
5e1c5ff4 | 1104 | default: |
e5c56ed3 | 1105 | WARN_ON(1); |
5e1c5ff4 TL |
1106 | return; |
1107 | } | |
1108 | __raw_writel(l, reg); | |
1109 | } | |
1110 | ||
1111 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
1112 | { | |
1113 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
1114 | } | |
1115 | ||
92105bb7 TL |
1116 | /* |
1117 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
1118 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
1119 | * to the target, system will wake up always on GPIO events. While | |
1120 | * system is running all registered GPIO interrupts need to have wake-up | |
1121 | * enabled. When system is suspended, only selected GPIO interrupts need | |
1122 | * to have wake-up enabled. | |
1123 | */ | |
1124 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
1125 | { | |
4cc6420c | 1126 | unsigned long uninitialized_var(flags); |
a6472533 | 1127 | |
92105bb7 | 1128 | switch (bank->method) { |
3ac4fa99 | 1129 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 1130 | case METHOD_MPUIO: |
92105bb7 | 1131 | case METHOD_GPIO_1610: |
a6472533 | 1132 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 1133 | if (enable) |
92105bb7 | 1134 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 1135 | else |
92105bb7 | 1136 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 1137 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1138 | return 0; |
3ac4fa99 | 1139 | #endif |
140455fa | 1140 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 | 1141 | case METHOD_GPIO_24XX: |
3f1686a9 | 1142 | case METHOD_GPIO_44XX: |
11a78b79 DB |
1143 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
1144 | printk(KERN_ERR "Unable to modify wakeup on " | |
1145 | "non-wakeup GPIO%d\n", | |
1146 | (bank - gpio_bank) * 32 + gpio); | |
1147 | return -EINVAL; | |
1148 | } | |
a6472533 | 1149 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 1150 | if (enable) |
3ac4fa99 | 1151 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 1152 | else |
3ac4fa99 | 1153 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 1154 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
1155 | return 0; |
1156 | #endif | |
92105bb7 TL |
1157 | default: |
1158 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
1159 | bank->method); | |
1160 | return -EINVAL; | |
1161 | } | |
1162 | } | |
1163 | ||
4196dd6b TL |
1164 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
1165 | { | |
1166 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
1167 | _set_gpio_irqenable(bank, gpio, 0); | |
1168 | _clear_gpio_irqstatus(bank, gpio); | |
6cab4860 | 1169 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
1170 | } |
1171 | ||
92105bb7 TL |
1172 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
1173 | static int gpio_wake_enable(unsigned int irq, unsigned int enable) | |
1174 | { | |
1175 | unsigned int gpio = irq - IH_GPIO_BASE; | |
1176 | struct gpio_bank *bank; | |
1177 | int retval; | |
1178 | ||
1179 | if (check_gpio(gpio) < 0) | |
1180 | return -ENODEV; | |
58781016 | 1181 | bank = get_irq_chip_data(irq); |
92105bb7 | 1182 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
1183 | |
1184 | return retval; | |
1185 | } | |
1186 | ||
3ff164e1 | 1187 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1188 | { |
3ff164e1 | 1189 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1190 | unsigned long flags; |
52e31344 | 1191 | |
a6472533 | 1192 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 1193 | |
4196dd6b TL |
1194 | /* Set trigger to none. You need to enable the desired trigger with |
1195 | * request_irq() or set_irq_type(). | |
1196 | */ | |
3ff164e1 | 1197 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 1198 | |
1a8bfa1e | 1199 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 1200 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 1201 | void __iomem *reg; |
5e1c5ff4 | 1202 | |
92105bb7 | 1203 | /* Claim the pin for MPU */ |
5e1c5ff4 | 1204 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 1205 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
1206 | } |
1207 | #endif | |
058af1ea C |
1208 | if (!cpu_class_is_omap1()) { |
1209 | if (!bank->mod_usage) { | |
9f096868 | 1210 | void __iomem *reg = bank->base; |
058af1ea | 1211 | u32 ctrl; |
9f096868 C |
1212 | |
1213 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1214 | reg += OMAP24XX_GPIO_CTRL; | |
1215 | else if (cpu_is_omap44xx()) | |
1216 | reg += OMAP4_GPIO_CTRL; | |
1217 | ctrl = __raw_readl(reg); | |
058af1ea | 1218 | /* Module is enabled, clocks are not gated */ |
9f096868 C |
1219 | ctrl &= 0xFFFFFFFE; |
1220 | __raw_writel(ctrl, reg); | |
058af1ea C |
1221 | } |
1222 | bank->mod_usage |= 1 << offset; | |
1223 | } | |
a6472533 | 1224 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1225 | |
1226 | return 0; | |
1227 | } | |
1228 | ||
3ff164e1 | 1229 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1230 | { |
3ff164e1 | 1231 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1232 | unsigned long flags; |
5e1c5ff4 | 1233 | |
a6472533 | 1234 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1235 | #ifdef CONFIG_ARCH_OMAP16XX |
1236 | if (bank->method == METHOD_GPIO_1610) { | |
1237 | /* Disable wake-up during idle for dynamic tick */ | |
1238 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 1239 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
1240 | } |
1241 | #endif | |
9f096868 C |
1242 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
1243 | if (bank->method == METHOD_GPIO_24XX) { | |
92105bb7 TL |
1244 | /* Disable wake-up during idle for dynamic tick */ |
1245 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 1246 | __raw_writel(1 << offset, reg); |
92105bb7 | 1247 | } |
9f096868 C |
1248 | #endif |
1249 | #ifdef CONFIG_ARCH_OMAP4 | |
1250 | if (bank->method == METHOD_GPIO_44XX) { | |
1251 | /* Disable wake-up during idle for dynamic tick */ | |
1252 | void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1253 | __raw_writel(1 << offset, reg); | |
1254 | } | |
92105bb7 | 1255 | #endif |
058af1ea C |
1256 | if (!cpu_class_is_omap1()) { |
1257 | bank->mod_usage &= ~(1 << offset); | |
1258 | if (!bank->mod_usage) { | |
9f096868 | 1259 | void __iomem *reg = bank->base; |
058af1ea | 1260 | u32 ctrl; |
9f096868 C |
1261 | |
1262 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1263 | reg += OMAP24XX_GPIO_CTRL; | |
1264 | else if (cpu_is_omap44xx()) | |
1265 | reg += OMAP4_GPIO_CTRL; | |
1266 | ctrl = __raw_readl(reg); | |
058af1ea C |
1267 | /* Module is disabled, clocks are gated */ |
1268 | ctrl |= 1; | |
9f096868 | 1269 | __raw_writel(ctrl, reg); |
058af1ea C |
1270 | } |
1271 | } | |
3ff164e1 | 1272 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 1273 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1274 | } |
1275 | ||
1276 | /* | |
1277 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
1278 | * avoid missing GPIO interrupts for other lines in the bank. | |
1279 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
1280 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
1281 | * If we wait to unmask individual GPIO lines in the bank after the | |
1282 | * line's interrupt handler has been run, we may miss some nested | |
1283 | * interrupts. | |
1284 | */ | |
10dd5ce2 | 1285 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 1286 | { |
92105bb7 | 1287 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 1288 | u32 isr; |
4318f36b | 1289 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 1290 | struct gpio_bank *bank; |
ea6dedd7 ID |
1291 | u32 retrigger = 0; |
1292 | int unmasked = 0; | |
5e1c5ff4 TL |
1293 | |
1294 | desc->chip->ack(irq); | |
1295 | ||
418ca1f0 | 1296 | bank = get_irq_data(irq); |
e5c56ed3 | 1297 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
1298 | if (bank->method == METHOD_MPUIO) |
1299 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | |
e5c56ed3 | 1300 | #endif |
1a8bfa1e | 1301 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
1302 | if (bank->method == METHOD_GPIO_1510) |
1303 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
1304 | #endif | |
1305 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1306 | if (bank->method == METHOD_GPIO_1610) | |
1307 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
1308 | #endif | |
b718aa81 | 1309 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1310 | if (bank->method == METHOD_GPIO_7XX) |
1311 | isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; | |
56739a69 | 1312 | #endif |
a8eb7ca0 | 1313 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
1314 | if (bank->method == METHOD_GPIO_24XX) |
1315 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
78a1a6d3 SR |
1316 | #endif |
1317 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 1318 | if (bank->method == METHOD_GPIO_44XX) |
78a1a6d3 | 1319 | isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; |
92105bb7 | 1320 | #endif |
b1cc4c55 EK |
1321 | |
1322 | if (WARN_ON(!isr_reg)) | |
1323 | goto exit; | |
1324 | ||
92105bb7 | 1325 | while(1) { |
6e60e79a | 1326 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 1327 | u32 enabled; |
6e60e79a | 1328 | |
ea6dedd7 ID |
1329 | enabled = _get_gpio_irqbank_mask(bank); |
1330 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
1331 | |
1332 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
1333 | isr &= 0x0000ffff; | |
1334 | ||
5492fb1a | 1335 | if (cpu_class_is_omap2()) { |
b144ff6f | 1336 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 1337 | } |
6e60e79a TL |
1338 | |
1339 | /* clear edge sensitive interrupts before handler(s) are | |
1340 | called so that we don't miss any interrupt occurred while | |
1341 | executing them */ | |
1342 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1343 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1344 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1345 | ||
1346 | /* if there is only edge sensitive GPIO pin interrupts | |
1347 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1348 | if (!level_mask && !unmasked) { |
1349 | unmasked = 1; | |
6e60e79a | 1350 | desc->chip->unmask(irq); |
ea6dedd7 | 1351 | } |
92105bb7 | 1352 | |
ea6dedd7 ID |
1353 | isr |= retrigger; |
1354 | retrigger = 0; | |
92105bb7 TL |
1355 | if (!isr) |
1356 | break; | |
1357 | ||
1358 | gpio_irq = bank->virtual_irq_start; | |
1359 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
4318f36b CM |
1360 | gpio_index = get_gpio_index(irq_to_gpio(gpio_irq)); |
1361 | ||
92105bb7 TL |
1362 | if (!(isr & 1)) |
1363 | continue; | |
29454dde | 1364 | |
4318f36b CM |
1365 | #ifdef CONFIG_ARCH_OMAP1 |
1366 | /* | |
1367 | * Some chips can't respond to both rising and falling | |
1368 | * at the same time. If this irq was requested with | |
1369 | * both flags, we need to flip the ICR data for the IRQ | |
1370 | * to respond to the IRQ for the opposite direction. | |
1371 | * This will be indicated in the bank toggle_mask. | |
1372 | */ | |
1373 | if (bank->toggle_mask & (1 << gpio_index)) | |
1374 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
1375 | #endif | |
1376 | ||
d8aa0251 | 1377 | generic_handle_irq(gpio_irq); |
92105bb7 | 1378 | } |
1a8bfa1e | 1379 | } |
ea6dedd7 ID |
1380 | /* if bank has any level sensitive GPIO pin interrupt |
1381 | configured, we must unmask the bank interrupt only after | |
1382 | handler(s) are executed in order to avoid spurious bank | |
1383 | interrupt */ | |
b1cc4c55 | 1384 | exit: |
ea6dedd7 ID |
1385 | if (!unmasked) |
1386 | desc->chip->unmask(irq); | |
1387 | ||
5e1c5ff4 TL |
1388 | } |
1389 | ||
4196dd6b TL |
1390 | static void gpio_irq_shutdown(unsigned int irq) |
1391 | { | |
1392 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1393 | struct gpio_bank *bank = get_irq_chip_data(irq); |
4196dd6b TL |
1394 | |
1395 | _reset_gpio(bank, gpio); | |
1396 | } | |
1397 | ||
5e1c5ff4 TL |
1398 | static void gpio_ack_irq(unsigned int irq) |
1399 | { | |
1400 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1401 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1402 | |
1403 | _clear_gpio_irqstatus(bank, gpio); | |
1404 | } | |
1405 | ||
1406 | static void gpio_mask_irq(unsigned int irq) | |
1407 | { | |
1408 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1409 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1410 | |
1411 | _set_gpio_irqenable(bank, gpio, 0); | |
55b6019a | 1412 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
5e1c5ff4 TL |
1413 | } |
1414 | ||
1415 | static void gpio_unmask_irq(unsigned int irq) | |
1416 | { | |
1417 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1418 | struct gpio_bank *bank = get_irq_chip_data(irq); |
b144ff6f | 1419 | unsigned int irq_mask = 1 << get_gpio_index(gpio); |
55b6019a KH |
1420 | struct irq_desc *desc = irq_to_desc(irq); |
1421 | u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; | |
1422 | ||
1423 | if (trigger) | |
1424 | _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); | |
b144ff6f KH |
1425 | |
1426 | /* For level-triggered GPIOs, the clearing must be done after | |
1427 | * the HW source is cleared, thus after the handler has run */ | |
1428 | if (bank->level_mask & irq_mask) { | |
1429 | _set_gpio_irqenable(bank, gpio, 0); | |
1430 | _clear_gpio_irqstatus(bank, gpio); | |
1431 | } | |
5e1c5ff4 | 1432 | |
4de8c75b | 1433 | _set_gpio_irqenable(bank, gpio, 1); |
5e1c5ff4 TL |
1434 | } |
1435 | ||
e5c56ed3 DB |
1436 | static struct irq_chip gpio_irq_chip = { |
1437 | .name = "GPIO", | |
1438 | .shutdown = gpio_irq_shutdown, | |
1439 | .ack = gpio_ack_irq, | |
1440 | .mask = gpio_mask_irq, | |
1441 | .unmask = gpio_unmask_irq, | |
1442 | .set_type = gpio_irq_type, | |
1443 | .set_wake = gpio_wake_enable, | |
1444 | }; | |
1445 | ||
1446 | /*---------------------------------------------------------------------*/ | |
1447 | ||
1448 | #ifdef CONFIG_ARCH_OMAP1 | |
1449 | ||
1450 | /* MPUIO uses the always-on 32k clock */ | |
1451 | ||
5e1c5ff4 TL |
1452 | static void mpuio_ack_irq(unsigned int irq) |
1453 | { | |
1454 | /* The ISR is reset automatically, so do nothing here. */ | |
1455 | } | |
1456 | ||
1457 | static void mpuio_mask_irq(unsigned int irq) | |
1458 | { | |
1459 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1460 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1461 | |
1462 | _set_gpio_irqenable(bank, gpio, 0); | |
1463 | } | |
1464 | ||
1465 | static void mpuio_unmask_irq(unsigned int irq) | |
1466 | { | |
1467 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1468 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1469 | |
1470 | _set_gpio_irqenable(bank, gpio, 1); | |
1471 | } | |
1472 | ||
e5c56ed3 DB |
1473 | static struct irq_chip mpuio_irq_chip = { |
1474 | .name = "MPUIO", | |
1475 | .ack = mpuio_ack_irq, | |
1476 | .mask = mpuio_mask_irq, | |
1477 | .unmask = mpuio_unmask_irq, | |
92105bb7 | 1478 | .set_type = gpio_irq_type, |
11a78b79 DB |
1479 | #ifdef CONFIG_ARCH_OMAP16XX |
1480 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1481 | .set_wake = gpio_wake_enable, | |
1482 | #endif | |
5e1c5ff4 TL |
1483 | }; |
1484 | ||
e5c56ed3 DB |
1485 | |
1486 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1487 | ||
11a78b79 DB |
1488 | |
1489 | #ifdef CONFIG_ARCH_OMAP16XX | |
1490 | ||
1491 | #include <linux/platform_device.h> | |
1492 | ||
79ee031f | 1493 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 1494 | { |
79ee031f | 1495 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 DB |
1496 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
1497 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1498 | unsigned long flags; |
11a78b79 | 1499 | |
a6472533 | 1500 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1501 | bank->saved_wakeup = __raw_readl(mask_reg); |
1502 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1503 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1504 | |
1505 | return 0; | |
1506 | } | |
1507 | ||
79ee031f | 1508 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 1509 | { |
79ee031f | 1510 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 DB |
1511 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
1512 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1513 | unsigned long flags; |
11a78b79 | 1514 | |
a6472533 | 1515 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1516 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1517 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1518 | |
1519 | return 0; | |
1520 | } | |
1521 | ||
47145210 | 1522 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
1523 | .suspend_noirq = omap_mpuio_suspend_noirq, |
1524 | .resume_noirq = omap_mpuio_resume_noirq, | |
1525 | }; | |
1526 | ||
11a78b79 DB |
1527 | /* use platform_driver for this, now that there's no longer any |
1528 | * point to sys_device (other than not disturbing old code). | |
1529 | */ | |
1530 | static struct platform_driver omap_mpuio_driver = { | |
11a78b79 DB |
1531 | .driver = { |
1532 | .name = "mpuio", | |
79ee031f | 1533 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
1534 | }, |
1535 | }; | |
1536 | ||
1537 | static struct platform_device omap_mpuio_device = { | |
1538 | .name = "mpuio", | |
1539 | .id = -1, | |
1540 | .dev = { | |
1541 | .driver = &omap_mpuio_driver.driver, | |
1542 | } | |
1543 | /* could list the /proc/iomem resources */ | |
1544 | }; | |
1545 | ||
1546 | static inline void mpuio_init(void) | |
1547 | { | |
fcf126d8 DB |
1548 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); |
1549 | ||
11a78b79 DB |
1550 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1551 | (void) platform_device_register(&omap_mpuio_device); | |
1552 | } | |
1553 | ||
1554 | #else | |
1555 | static inline void mpuio_init(void) {} | |
1556 | #endif /* 16xx */ | |
1557 | ||
e5c56ed3 DB |
1558 | #else |
1559 | ||
1560 | extern struct irq_chip mpuio_irq_chip; | |
1561 | ||
1562 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1563 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1564 | |
1565 | #endif | |
1566 | ||
1567 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1568 | |
52e31344 DB |
1569 | /* REVISIT these are stupid implementations! replace by ones that |
1570 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1571 | */ | |
1572 | ||
1573 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1574 | { | |
1575 | struct gpio_bank *bank; | |
1576 | unsigned long flags; | |
1577 | ||
1578 | bank = container_of(chip, struct gpio_bank, chip); | |
1579 | spin_lock_irqsave(&bank->lock, flags); | |
1580 | _set_gpio_direction(bank, offset, 1); | |
1581 | spin_unlock_irqrestore(&bank->lock, flags); | |
1582 | return 0; | |
1583 | } | |
1584 | ||
b37c45b8 RQ |
1585 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
1586 | { | |
1587 | void __iomem *reg = bank->base; | |
1588 | ||
1589 | switch (bank->method) { | |
1590 | case METHOD_MPUIO: | |
1591 | reg += OMAP_MPUIO_IO_CNTL; | |
1592 | break; | |
1593 | case METHOD_GPIO_1510: | |
1594 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1595 | break; | |
1596 | case METHOD_GPIO_1610: | |
1597 | reg += OMAP1610_GPIO_DIRECTION; | |
1598 | break; | |
7c006926 AB |
1599 | case METHOD_GPIO_7XX: |
1600 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
b37c45b8 RQ |
1601 | break; |
1602 | case METHOD_GPIO_24XX: | |
1603 | reg += OMAP24XX_GPIO_OE; | |
1604 | break; | |
9f096868 C |
1605 | case METHOD_GPIO_44XX: |
1606 | reg += OMAP4_GPIO_OE; | |
1607 | break; | |
1608 | default: | |
1609 | WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method"); | |
1610 | return -EINVAL; | |
b37c45b8 RQ |
1611 | } |
1612 | return __raw_readl(reg) & mask; | |
1613 | } | |
1614 | ||
52e31344 DB |
1615 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
1616 | { | |
b37c45b8 RQ |
1617 | struct gpio_bank *bank; |
1618 | void __iomem *reg; | |
1619 | int gpio; | |
1620 | u32 mask; | |
1621 | ||
1622 | gpio = chip->base + offset; | |
1623 | bank = get_gpio_bank(gpio); | |
1624 | reg = bank->base; | |
1625 | mask = 1 << get_gpio_index(gpio); | |
1626 | ||
1627 | if (gpio_is_input(bank, mask)) | |
1628 | return _get_gpio_datain(bank, gpio); | |
1629 | else | |
1630 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
1631 | } |
1632 | ||
1633 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1634 | { | |
1635 | struct gpio_bank *bank; | |
1636 | unsigned long flags; | |
1637 | ||
1638 | bank = container_of(chip, struct gpio_bank, chip); | |
1639 | spin_lock_irqsave(&bank->lock, flags); | |
1640 | _set_gpio_dataout(bank, offset, value); | |
1641 | _set_gpio_direction(bank, offset, 0); | |
1642 | spin_unlock_irqrestore(&bank->lock, flags); | |
1643 | return 0; | |
1644 | } | |
1645 | ||
168ef3d9 FB |
1646 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1647 | unsigned debounce) | |
1648 | { | |
1649 | struct gpio_bank *bank; | |
1650 | unsigned long flags; | |
1651 | ||
1652 | bank = container_of(chip, struct gpio_bank, chip); | |
1653 | spin_lock_irqsave(&bank->lock, flags); | |
1654 | _set_gpio_debounce(bank, offset, debounce); | |
1655 | spin_unlock_irqrestore(&bank->lock, flags); | |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
52e31344 DB |
1660 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
1661 | { | |
1662 | struct gpio_bank *bank; | |
1663 | unsigned long flags; | |
1664 | ||
1665 | bank = container_of(chip, struct gpio_bank, chip); | |
1666 | spin_lock_irqsave(&bank->lock, flags); | |
1667 | _set_gpio_dataout(bank, offset, value); | |
1668 | spin_unlock_irqrestore(&bank->lock, flags); | |
1669 | } | |
1670 | ||
a007b709 DB |
1671 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
1672 | { | |
1673 | struct gpio_bank *bank; | |
1674 | ||
1675 | bank = container_of(chip, struct gpio_bank, chip); | |
1676 | return bank->virtual_irq_start + offset; | |
1677 | } | |
1678 | ||
52e31344 DB |
1679 | /*---------------------------------------------------------------------*/ |
1680 | ||
1a8bfa1e | 1681 | static int initialized; |
56213ca4 | 1682 | #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) |
1a8bfa1e | 1683 | static struct clk * gpio_ick; |
5492fb1a SMK |
1684 | #endif |
1685 | ||
1686 | #if defined(CONFIG_ARCH_OMAP2) | |
1a8bfa1e | 1687 | static struct clk * gpio_fck; |
5492fb1a | 1688 | #endif |
5e1c5ff4 | 1689 | |
5492fb1a | 1690 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1691 | static struct clk * gpio5_ick; |
1692 | static struct clk * gpio5_fck; | |
1693 | #endif | |
1694 | ||
44169075 | 1695 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
5492fb1a SMK |
1696 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; |
1697 | #endif | |
1698 | ||
9f7065da TL |
1699 | static void __init omap_gpio_show_rev(void) |
1700 | { | |
1701 | u32 rev; | |
1702 | ||
1703 | if (cpu_is_omap16xx()) | |
1704 | rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); | |
1705 | else if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1706 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | |
1707 | else if (cpu_is_omap44xx()) | |
1708 | rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION); | |
1709 | else | |
1710 | return; | |
1711 | ||
1712 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | |
1713 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1714 | } | |
1715 | ||
8ba55c5c DB |
1716 | /* This lock class tells lockdep that GPIO irqs are in a different |
1717 | * category than their parents, so it won't report false recursion. | |
1718 | */ | |
1719 | static struct lock_class_key gpio_lock_class; | |
1720 | ||
5e1c5ff4 TL |
1721 | static int __init _omap_gpio_init(void) |
1722 | { | |
1723 | int i; | |
52e31344 | 1724 | int gpio = 0; |
5e1c5ff4 | 1725 | struct gpio_bank *bank; |
9f7065da | 1726 | int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ |
5492fb1a | 1727 | char clk_name[11]; |
5e1c5ff4 TL |
1728 | |
1729 | initialized = 1; | |
1730 | ||
5492fb1a | 1731 | #if defined(CONFIG_ARCH_OMAP1) |
6e60e79a | 1732 | if (cpu_is_omap15xx()) { |
1a8bfa1e TL |
1733 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); |
1734 | if (IS_ERR(gpio_ick)) | |
92105bb7 TL |
1735 | printk("Could not get arm_gpio_ck\n"); |
1736 | else | |
30ff720b | 1737 | clk_enable(gpio_ick); |
1a8bfa1e | 1738 | } |
5492fb1a SMK |
1739 | #endif |
1740 | #if defined(CONFIG_ARCH_OMAP2) | |
1741 | if (cpu_class_is_omap2()) { | |
1a8bfa1e TL |
1742 | gpio_ick = clk_get(NULL, "gpios_ick"); |
1743 | if (IS_ERR(gpio_ick)) | |
1744 | printk("Could not get gpios_ick\n"); | |
1745 | else | |
30ff720b | 1746 | clk_enable(gpio_ick); |
1a8bfa1e | 1747 | gpio_fck = clk_get(NULL, "gpios_fck"); |
1630b52d | 1748 | if (IS_ERR(gpio_fck)) |
1a8bfa1e TL |
1749 | printk("Could not get gpios_fck\n"); |
1750 | else | |
30ff720b | 1751 | clk_enable(gpio_fck); |
56a25641 SMK |
1752 | |
1753 | /* | |
5492fb1a | 1754 | * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK |
56a25641 | 1755 | */ |
5492fb1a | 1756 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1757 | if (cpu_is_omap2430()) { |
1758 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | |
1759 | if (IS_ERR(gpio5_ick)) | |
1760 | printk("Could not get gpio5_ick\n"); | |
1761 | else | |
1762 | clk_enable(gpio5_ick); | |
1763 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | |
1764 | if (IS_ERR(gpio5_fck)) | |
1765 | printk("Could not get gpio5_fck\n"); | |
1766 | else | |
1767 | clk_enable(gpio5_fck); | |
1768 | } | |
1769 | #endif | |
5492fb1a SMK |
1770 | } |
1771 | #endif | |
1772 | ||
44169075 SS |
1773 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
1774 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
5492fb1a SMK |
1775 | for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { |
1776 | sprintf(clk_name, "gpio%d_ick", i + 1); | |
1777 | gpio_iclks[i] = clk_get(NULL, clk_name); | |
1778 | if (IS_ERR(gpio_iclks[i])) | |
1779 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1780 | else | |
1781 | clk_enable(gpio_iclks[i]); | |
5492fb1a SMK |
1782 | } |
1783 | } | |
1784 | #endif | |
1785 | ||
92105bb7 | 1786 | |
1a8bfa1e | 1787 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 1788 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
1789 | gpio_bank_count = 2; |
1790 | gpio_bank = gpio_bank_1510; | |
9f7065da | 1791 | bank_size = SZ_2K; |
5e1c5ff4 TL |
1792 | } |
1793 | #endif | |
1794 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1795 | if (cpu_is_omap16xx()) { | |
5e1c5ff4 TL |
1796 | gpio_bank_count = 5; |
1797 | gpio_bank = gpio_bank_1610; | |
9f7065da | 1798 | bank_size = SZ_2K; |
5e1c5ff4 TL |
1799 | } |
1800 | #endif | |
b718aa81 AB |
1801 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
1802 | if (cpu_is_omap7xx()) { | |
56739a69 | 1803 | gpio_bank_count = 7; |
7c006926 | 1804 | gpio_bank = gpio_bank_7xx; |
9f7065da | 1805 | bank_size = SZ_2K; |
56739a69 ZM |
1806 | } |
1807 | #endif | |
088ef950 | 1808 | #ifdef CONFIG_ARCH_OMAP2 |
56a25641 | 1809 | if (cpu_is_omap242x()) { |
92105bb7 | 1810 | gpio_bank_count = 4; |
56a25641 | 1811 | gpio_bank = gpio_bank_242x; |
56a25641 SMK |
1812 | } |
1813 | if (cpu_is_omap243x()) { | |
56a25641 SMK |
1814 | gpio_bank_count = 5; |
1815 | gpio_bank = gpio_bank_243x; | |
92105bb7 | 1816 | } |
5492fb1a | 1817 | #endif |
a8eb7ca0 | 1818 | #ifdef CONFIG_ARCH_OMAP3 |
5492fb1a | 1819 | if (cpu_is_omap34xx()) { |
5492fb1a SMK |
1820 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
1821 | gpio_bank = gpio_bank_34xx; | |
5492fb1a | 1822 | } |
44169075 SS |
1823 | #endif |
1824 | #ifdef CONFIG_ARCH_OMAP4 | |
1825 | if (cpu_is_omap44xx()) { | |
44169075 SS |
1826 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
1827 | gpio_bank = gpio_bank_44xx; | |
44169075 | 1828 | } |
5e1c5ff4 TL |
1829 | #endif |
1830 | for (i = 0; i < gpio_bank_count; i++) { | |
1831 | int j, gpio_count = 16; | |
1832 | ||
1833 | bank = &gpio_bank[i]; | |
5e1c5ff4 | 1834 | spin_lock_init(&bank->lock); |
9f7065da TL |
1835 | |
1836 | /* Static mapping, never released */ | |
1837 | bank->base = ioremap(bank->pbase, bank_size); | |
1838 | if (!bank->base) { | |
1839 | printk(KERN_ERR "Could not ioremap gpio bank%i\n", i); | |
1840 | continue; | |
1841 | } | |
1842 | ||
e5c56ed3 | 1843 | if (bank_is_mpuio(bank)) |
7c7095aa | 1844 | __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); |
d11ac979 | 1845 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
5e1c5ff4 TL |
1846 | __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); |
1847 | __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); | |
1848 | } | |
d11ac979 | 1849 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { |
5e1c5ff4 TL |
1850 | __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); |
1851 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | |
92105bb7 | 1852 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
5e1c5ff4 | 1853 | } |
7c006926 AB |
1854 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { |
1855 | __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK); | |
1856 | __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS); | |
5e1c5ff4 | 1857 | |
7c006926 | 1858 | gpio_count = 32; /* 7xx has 32-bit GPIOs */ |
5e1c5ff4 | 1859 | } |
d11ac979 | 1860 | |
140455fa | 1861 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3f1686a9 TL |
1862 | if ((bank->method == METHOD_GPIO_24XX) || |
1863 | (bank->method == METHOD_GPIO_44XX)) { | |
3ac4fa99 JY |
1864 | static const u32 non_wakeup_gpios[] = { |
1865 | 0xe203ffc0, 0x08700040 | |
1866 | }; | |
3f1686a9 TL |
1867 | |
1868 | if (cpu_is_omap44xx()) { | |
1869 | __raw_writel(0xffffffff, bank->base + | |
78a1a6d3 | 1870 | OMAP4_GPIO_IRQSTATUSCLR0); |
3f1686a9 | 1871 | __raw_writew(0x0015, bank->base + |
78a1a6d3 | 1872 | OMAP4_GPIO_SYSCONFIG); |
3f1686a9 | 1873 | __raw_writel(0x00000000, bank->base + |
78a1a6d3 | 1874 | OMAP4_GPIO_DEBOUNCENABLE); |
3f1686a9 TL |
1875 | /* |
1876 | * Initialize interface clock ungated, | |
1877 | * module enabled | |
1878 | */ | |
1879 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); | |
1880 | } else { | |
1881 | __raw_writel(0x00000000, bank->base + | |
1882 | OMAP24XX_GPIO_IRQENABLE1); | |
1883 | __raw_writel(0xffffffff, bank->base + | |
1884 | OMAP24XX_GPIO_IRQSTATUS1); | |
1885 | __raw_writew(0x0015, bank->base + | |
1886 | OMAP24XX_GPIO_SYSCONFIG); | |
1887 | __raw_writel(0x00000000, bank->base + | |
1888 | OMAP24XX_GPIO_DEBOUNCE_EN); | |
1889 | ||
1890 | /* | |
1891 | * Initialize interface clock ungated, | |
1892 | * module enabled | |
1893 | */ | |
1894 | __raw_writel(0, bank->base + | |
1895 | OMAP24XX_GPIO_CTRL); | |
1896 | } | |
a118b5f3 TK |
1897 | if (cpu_is_omap24xx() && |
1898 | i < ARRAY_SIZE(non_wakeup_gpios)) | |
3ac4fa99 | 1899 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; |
92105bb7 TL |
1900 | gpio_count = 32; |
1901 | } | |
5e1c5ff4 | 1902 | #endif |
058af1ea C |
1903 | |
1904 | bank->mod_usage = 0; | |
52e31344 DB |
1905 | /* REVISIT eventually switch from OMAP-specific gpio structs |
1906 | * over to the generic ones | |
1907 | */ | |
3ff164e1 JN |
1908 | bank->chip.request = omap_gpio_request; |
1909 | bank->chip.free = omap_gpio_free; | |
52e31344 DB |
1910 | bank->chip.direction_input = gpio_input; |
1911 | bank->chip.get = gpio_get; | |
1912 | bank->chip.direction_output = gpio_output; | |
168ef3d9 | 1913 | bank->chip.set_debounce = gpio_debounce; |
52e31344 | 1914 | bank->chip.set = gpio_set; |
a007b709 | 1915 | bank->chip.to_irq = gpio_2irq; |
52e31344 DB |
1916 | if (bank_is_mpuio(bank)) { |
1917 | bank->chip.label = "mpuio"; | |
69114a47 | 1918 | #ifdef CONFIG_ARCH_OMAP16XX |
d8f388d8 DB |
1919 | bank->chip.dev = &omap_mpuio_device.dev; |
1920 | #endif | |
52e31344 DB |
1921 | bank->chip.base = OMAP_MPUIO(0); |
1922 | } else { | |
1923 | bank->chip.label = "gpio"; | |
1924 | bank->chip.base = gpio; | |
1925 | gpio += gpio_count; | |
1926 | } | |
1927 | bank->chip.ngpio = gpio_count; | |
1928 | ||
1929 | gpiochip_add(&bank->chip); | |
1930 | ||
5e1c5ff4 TL |
1931 | for (j = bank->virtual_irq_start; |
1932 | j < bank->virtual_irq_start + gpio_count; j++) { | |
8ba55c5c | 1933 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); |
58781016 | 1934 | set_irq_chip_data(j, bank); |
e5c56ed3 | 1935 | if (bank_is_mpuio(bank)) |
5e1c5ff4 TL |
1936 | set_irq_chip(j, &mpuio_irq_chip); |
1937 | else | |
1938 | set_irq_chip(j, &gpio_irq_chip); | |
10dd5ce2 | 1939 | set_irq_handler(j, handle_simple_irq); |
5e1c5ff4 TL |
1940 | set_irq_flags(j, IRQF_VALID); |
1941 | } | |
1942 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | |
1943 | set_irq_data(bank->irq, bank); | |
89db9482 | 1944 | |
44169075 | 1945 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
89db9482 JH |
1946 | sprintf(clk_name, "gpio%d_dbck", i + 1); |
1947 | bank->dbck = clk_get(NULL, clk_name); | |
1948 | if (IS_ERR(bank->dbck)) | |
1949 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1950 | } | |
5e1c5ff4 TL |
1951 | } |
1952 | ||
1953 | /* Enable system clock for GPIO module. | |
1954 | * The CAM_CLK_CTRL *is* really the right place. */ | |
92105bb7 | 1955 | if (cpu_is_omap16xx()) |
5e1c5ff4 TL |
1956 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); |
1957 | ||
14f1c3bf JY |
1958 | /* Enable autoidle for the OCP interface */ |
1959 | if (cpu_is_omap24xx()) | |
1960 | omap_writel(1 << 0, 0x48019010); | |
5492fb1a SMK |
1961 | if (cpu_is_omap34xx()) |
1962 | omap_writel(1 << 0, 0x48306814); | |
d11ac979 | 1963 | |
9f7065da TL |
1964 | omap_gpio_show_rev(); |
1965 | ||
5e1c5ff4 TL |
1966 | return 0; |
1967 | } | |
1968 | ||
140455fa | 1969 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 TL |
1970 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) |
1971 | { | |
1972 | int i; | |
1973 | ||
5492fb1a | 1974 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1975 | return 0; |
1976 | ||
1977 | for (i = 0; i < gpio_bank_count; i++) { | |
1978 | struct gpio_bank *bank = &gpio_bank[i]; | |
1979 | void __iomem *wake_status; | |
1980 | void __iomem *wake_clear; | |
1981 | void __iomem *wake_set; | |
a6472533 | 1982 | unsigned long flags; |
92105bb7 TL |
1983 | |
1984 | switch (bank->method) { | |
e5c56ed3 | 1985 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1986 | case METHOD_GPIO_1610: |
1987 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1988 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1989 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1990 | break; | |
e5c56ed3 | 1991 | #endif |
a8eb7ca0 | 1992 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1993 | case METHOD_GPIO_24XX: |
723fdb78 | 1994 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1995 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1996 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1997 | break; | |
78a1a6d3 SR |
1998 | #endif |
1999 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 2000 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
2001 | wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; |
2002 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
2003 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
2004 | break; | |
e5c56ed3 | 2005 | #endif |
92105bb7 TL |
2006 | default: |
2007 | continue; | |
2008 | } | |
2009 | ||
a6472533 | 2010 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
2011 | bank->saved_wakeup = __raw_readl(wake_status); |
2012 | __raw_writel(0xffffffff, wake_clear); | |
2013 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 2014 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
2015 | } |
2016 | ||
2017 | return 0; | |
2018 | } | |
2019 | ||
2020 | static int omap_gpio_resume(struct sys_device *dev) | |
2021 | { | |
2022 | int i; | |
2023 | ||
723fdb78 | 2024 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
2025 | return 0; |
2026 | ||
2027 | for (i = 0; i < gpio_bank_count; i++) { | |
2028 | struct gpio_bank *bank = &gpio_bank[i]; | |
2029 | void __iomem *wake_clear; | |
2030 | void __iomem *wake_set; | |
a6472533 | 2031 | unsigned long flags; |
92105bb7 TL |
2032 | |
2033 | switch (bank->method) { | |
e5c56ed3 | 2034 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
2035 | case METHOD_GPIO_1610: |
2036 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
2037 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
2038 | break; | |
e5c56ed3 | 2039 | #endif |
a8eb7ca0 | 2040 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 2041 | case METHOD_GPIO_24XX: |
0d9356cb TL |
2042 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
2043 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 2044 | break; |
78a1a6d3 SR |
2045 | #endif |
2046 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 2047 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
2048 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; |
2049 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
2050 | break; | |
e5c56ed3 | 2051 | #endif |
92105bb7 TL |
2052 | default: |
2053 | continue; | |
2054 | } | |
2055 | ||
a6472533 | 2056 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
2057 | __raw_writel(0xffffffff, wake_clear); |
2058 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 2059 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
2060 | } |
2061 | ||
2062 | return 0; | |
2063 | } | |
2064 | ||
2065 | static struct sysdev_class omap_gpio_sysclass = { | |
af5ca3f4 | 2066 | .name = "gpio", |
92105bb7 TL |
2067 | .suspend = omap_gpio_suspend, |
2068 | .resume = omap_gpio_resume, | |
2069 | }; | |
2070 | ||
2071 | static struct sys_device omap_gpio_device = { | |
2072 | .id = 0, | |
2073 | .cls = &omap_gpio_sysclass, | |
2074 | }; | |
3ac4fa99 JY |
2075 | |
2076 | #endif | |
2077 | ||
140455fa | 2078 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 JY |
2079 | |
2080 | static int workaround_enabled; | |
2081 | ||
43ffcd9a | 2082 | void omap2_gpio_prepare_for_idle(int power_state) |
3ac4fa99 JY |
2083 | { |
2084 | int i, c = 0; | |
a118b5f3 | 2085 | int min = 0; |
3ac4fa99 | 2086 | |
a118b5f3 TK |
2087 | if (cpu_is_omap34xx()) |
2088 | min = 1; | |
43ffcd9a | 2089 | |
a118b5f3 | 2090 | for (i = min; i < gpio_bank_count; i++) { |
3ac4fa99 | 2091 | struct gpio_bank *bank = &gpio_bank[i]; |
ca828760 | 2092 | u32 l1 = 0, l2 = 0; |
0aed0435 | 2093 | int j; |
3ac4fa99 | 2094 | |
0aed0435 | 2095 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
2096 | clk_disable(bank->dbck); |
2097 | ||
43ffcd9a KH |
2098 | if (power_state > PWRDM_POWER_OFF) |
2099 | continue; | |
2100 | ||
2101 | /* If going to OFF, remove triggering for all | |
2102 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
2103 | * generated. See OMAP2420 Errata item 1.101. */ | |
3ac4fa99 JY |
2104 | if (!(bank->enabled_non_wakeup_gpios)) |
2105 | continue; | |
3f1686a9 TL |
2106 | |
2107 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
2108 | bank->saved_datain = __raw_readl(bank->base + | |
2109 | OMAP24XX_GPIO_DATAIN); | |
2110 | l1 = __raw_readl(bank->base + | |
2111 | OMAP24XX_GPIO_FALLINGDETECT); | |
2112 | l2 = __raw_readl(bank->base + | |
2113 | OMAP24XX_GPIO_RISINGDETECT); | |
2114 | } | |
2115 | ||
2116 | if (cpu_is_omap44xx()) { | |
2117 | bank->saved_datain = __raw_readl(bank->base + | |
2118 | OMAP4_GPIO_DATAIN); | |
2119 | l1 = __raw_readl(bank->base + | |
2120 | OMAP4_GPIO_FALLINGDETECT); | |
2121 | l2 = __raw_readl(bank->base + | |
2122 | OMAP4_GPIO_RISINGDETECT); | |
2123 | } | |
2124 | ||
3ac4fa99 JY |
2125 | bank->saved_fallingdetect = l1; |
2126 | bank->saved_risingdetect = l2; | |
2127 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
2128 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 TL |
2129 | |
2130 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
2131 | __raw_writel(l1, bank->base + | |
2132 | OMAP24XX_GPIO_FALLINGDETECT); | |
2133 | __raw_writel(l2, bank->base + | |
2134 | OMAP24XX_GPIO_RISINGDETECT); | |
2135 | } | |
2136 | ||
2137 | if (cpu_is_omap44xx()) { | |
2138 | __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); | |
2139 | __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); | |
2140 | } | |
2141 | ||
3ac4fa99 JY |
2142 | c++; |
2143 | } | |
2144 | if (!c) { | |
2145 | workaround_enabled = 0; | |
2146 | return; | |
2147 | } | |
2148 | workaround_enabled = 1; | |
2149 | } | |
2150 | ||
43ffcd9a | 2151 | void omap2_gpio_resume_after_idle(void) |
3ac4fa99 JY |
2152 | { |
2153 | int i; | |
a118b5f3 | 2154 | int min = 0; |
3ac4fa99 | 2155 | |
a118b5f3 TK |
2156 | if (cpu_is_omap34xx()) |
2157 | min = 1; | |
2158 | for (i = min; i < gpio_bank_count; i++) { | |
3ac4fa99 | 2159 | struct gpio_bank *bank = &gpio_bank[i]; |
ca828760 | 2160 | u32 l = 0, gen, gen0, gen1; |
0aed0435 | 2161 | int j; |
3ac4fa99 | 2162 | |
0aed0435 | 2163 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
2164 | clk_enable(bank->dbck); |
2165 | ||
43ffcd9a KH |
2166 | if (!workaround_enabled) |
2167 | continue; | |
2168 | ||
3ac4fa99 JY |
2169 | if (!(bank->enabled_non_wakeup_gpios)) |
2170 | continue; | |
3f1686a9 TL |
2171 | |
2172 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
2173 | __raw_writel(bank->saved_fallingdetect, | |
3ac4fa99 | 2174 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
3f1686a9 | 2175 | __raw_writel(bank->saved_risingdetect, |
3ac4fa99 | 2176 | bank->base + OMAP24XX_GPIO_RISINGDETECT); |
3f1686a9 TL |
2177 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
2178 | } | |
2179 | ||
2180 | if (cpu_is_omap44xx()) { | |
2181 | __raw_writel(bank->saved_fallingdetect, | |
78a1a6d3 | 2182 | bank->base + OMAP4_GPIO_FALLINGDETECT); |
3f1686a9 | 2183 | __raw_writel(bank->saved_risingdetect, |
78a1a6d3 | 2184 | bank->base + OMAP4_GPIO_RISINGDETECT); |
3f1686a9 TL |
2185 | l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); |
2186 | } | |
2187 | ||
3ac4fa99 JY |
2188 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
2189 | * state. If so, generate an IRQ by software. This is | |
2190 | * horribly racy, but it's the best we can do to work around | |
2191 | * this silicon bug. */ | |
3ac4fa99 | 2192 | l ^= bank->saved_datain; |
a118b5f3 | 2193 | l &= bank->enabled_non_wakeup_gpios; |
82dbb9d3 EN |
2194 | |
2195 | /* | |
2196 | * No need to generate IRQs for the rising edge for gpio IRQs | |
2197 | * configured with falling edge only; and vice versa. | |
2198 | */ | |
2199 | gen0 = l & bank->saved_fallingdetect; | |
2200 | gen0 &= bank->saved_datain; | |
2201 | ||
2202 | gen1 = l & bank->saved_risingdetect; | |
2203 | gen1 &= ~(bank->saved_datain); | |
2204 | ||
2205 | /* FIXME: Consider GPIO IRQs with level detections properly! */ | |
2206 | gen = l & (~(bank->saved_fallingdetect) & | |
2207 | ~(bank->saved_risingdetect)); | |
2208 | /* Consider all GPIO IRQs needed to be updated */ | |
2209 | gen |= gen0 | gen1; | |
2210 | ||
2211 | if (gen) { | |
3ac4fa99 | 2212 | u32 old0, old1; |
3f1686a9 | 2213 | |
f00d6497 | 2214 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
3f1686a9 TL |
2215 | old0 = __raw_readl(bank->base + |
2216 | OMAP24XX_GPIO_LEVELDETECT0); | |
2217 | old1 = __raw_readl(bank->base + | |
2218 | OMAP24XX_GPIO_LEVELDETECT1); | |
f00d6497 | 2219 | __raw_writel(old0 | gen, bank->base + |
82dbb9d3 | 2220 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 2221 | __raw_writel(old1 | gen, bank->base + |
82dbb9d3 | 2222 | OMAP24XX_GPIO_LEVELDETECT1); |
f00d6497 | 2223 | __raw_writel(old0, bank->base + |
3f1686a9 | 2224 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 2225 | __raw_writel(old1, bank->base + |
3f1686a9 TL |
2226 | OMAP24XX_GPIO_LEVELDETECT1); |
2227 | } | |
2228 | ||
2229 | if (cpu_is_omap44xx()) { | |
2230 | old0 = __raw_readl(bank->base + | |
78a1a6d3 | 2231 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 2232 | old1 = __raw_readl(bank->base + |
78a1a6d3 | 2233 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 2234 | __raw_writel(old0 | l, bank->base + |
78a1a6d3 | 2235 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 2236 | __raw_writel(old1 | l, bank->base + |
78a1a6d3 | 2237 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 2238 | __raw_writel(old0, bank->base + |
78a1a6d3 | 2239 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 2240 | __raw_writel(old1, bank->base + |
78a1a6d3 | 2241 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 2242 | } |
3ac4fa99 JY |
2243 | } |
2244 | } | |
2245 | ||
2246 | } | |
2247 | ||
92105bb7 TL |
2248 | #endif |
2249 | ||
a8eb7ca0 | 2250 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 RN |
2251 | /* save the registers of bank 2-6 */ |
2252 | void omap_gpio_save_context(void) | |
2253 | { | |
2254 | int i; | |
2255 | ||
2256 | /* saving banks from 2-6 only since GPIO1 is in WKUP */ | |
2257 | for (i = 1; i < gpio_bank_count; i++) { | |
2258 | struct gpio_bank *bank = &gpio_bank[i]; | |
2259 | gpio_context[i].sysconfig = | |
2260 | __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG); | |
2261 | gpio_context[i].irqenable1 = | |
2262 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
2263 | gpio_context[i].irqenable2 = | |
2264 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
2265 | gpio_context[i].wake_en = | |
2266 | __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); | |
2267 | gpio_context[i].ctrl = | |
2268 | __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
2269 | gpio_context[i].oe = | |
2270 | __raw_readl(bank->base + OMAP24XX_GPIO_OE); | |
2271 | gpio_context[i].leveldetect0 = | |
2272 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
2273 | gpio_context[i].leveldetect1 = | |
2274 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
2275 | gpio_context[i].risingdetect = | |
2276 | __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
2277 | gpio_context[i].fallingdetect = | |
2278 | __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
2279 | gpio_context[i].dataout = | |
2280 | __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
2281 | } |
2282 | } | |
2283 | ||
2284 | /* restore the required registers of bank 2-6 */ | |
2285 | void omap_gpio_restore_context(void) | |
2286 | { | |
2287 | int i; | |
2288 | ||
2289 | for (i = 1; i < gpio_bank_count; i++) { | |
2290 | struct gpio_bank *bank = &gpio_bank[i]; | |
2291 | __raw_writel(gpio_context[i].sysconfig, | |
2292 | bank->base + OMAP24XX_GPIO_SYSCONFIG); | |
2293 | __raw_writel(gpio_context[i].irqenable1, | |
2294 | bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
2295 | __raw_writel(gpio_context[i].irqenable2, | |
2296 | bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
2297 | __raw_writel(gpio_context[i].wake_en, | |
2298 | bank->base + OMAP24XX_GPIO_WAKE_EN); | |
2299 | __raw_writel(gpio_context[i].ctrl, | |
2300 | bank->base + OMAP24XX_GPIO_CTRL); | |
2301 | __raw_writel(gpio_context[i].oe, | |
2302 | bank->base + OMAP24XX_GPIO_OE); | |
2303 | __raw_writel(gpio_context[i].leveldetect0, | |
2304 | bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
2305 | __raw_writel(gpio_context[i].leveldetect1, | |
2306 | bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
2307 | __raw_writel(gpio_context[i].risingdetect, | |
2308 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
2309 | __raw_writel(gpio_context[i].fallingdetect, | |
2310 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
2311 | __raw_writel(gpio_context[i].dataout, | |
2312 | bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
2313 | } |
2314 | } | |
2315 | #endif | |
2316 | ||
5e1c5ff4 TL |
2317 | /* |
2318 | * This may get called early from board specific init | |
1a8bfa1e | 2319 | * for boards that have interrupts routed via FPGA. |
5e1c5ff4 | 2320 | */ |
277d58ef | 2321 | int __init omap_gpio_init(void) |
5e1c5ff4 TL |
2322 | { |
2323 | if (!initialized) | |
2324 | return _omap_gpio_init(); | |
2325 | else | |
2326 | return 0; | |
2327 | } | |
2328 | ||
92105bb7 TL |
2329 | static int __init omap_gpio_sysinit(void) |
2330 | { | |
2331 | int ret = 0; | |
2332 | ||
2333 | if (!initialized) | |
2334 | ret = _omap_gpio_init(); | |
2335 | ||
11a78b79 DB |
2336 | mpuio_init(); |
2337 | ||
140455fa | 2338 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
5492fb1a | 2339 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { |
92105bb7 TL |
2340 | if (ret == 0) { |
2341 | ret = sysdev_class_register(&omap_gpio_sysclass); | |
2342 | if (ret == 0) | |
2343 | ret = sysdev_register(&omap_gpio_device); | |
2344 | } | |
2345 | } | |
2346 | #endif | |
2347 | ||
2348 | return ret; | |
2349 | } | |
2350 | ||
92105bb7 | 2351 | arch_initcall(omap_gpio_sysinit); |