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ARM: OMAP: Get rid of unnecessary ifdefs in GPIO code
[mirror_ubuntu-artful-kernel.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
5e1c5ff4
TL		 14#include <linux/init.h>
15#include <linux/module.h>
5e1c5ff4 16#include <linux/interrupt.h>
92105bb7
TL		 17#include <linux/sysdev.h>
18#include <linux/err.h>
f8ce2547 19#include <linux/clk.h>
5e1c5ff4
TL		 20
21#include <asm/hardware.h>
22#include <asm/irq.h>
23#include <asm/arch/irqs.h>
24#include <asm/arch/gpio.h>
25#include <asm/mach/irq.h>
26
27#include <asm/io.h>
28
29/*
30 * OMAP1510 GPIO registers
31 */
92105bb7 32#define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
5e1c5ff4
TL		 33#define OMAP1510_GPIO_DATA_INPUT 0x00
34#define OMAP1510_GPIO_DATA_OUTPUT 0x04
35#define OMAP1510_GPIO_DIR_CONTROL 0x08
36#define OMAP1510_GPIO_INT_CONTROL 0x0c
37#define OMAP1510_GPIO_INT_MASK 0x10
38#define OMAP1510_GPIO_INT_STATUS 0x14
39#define OMAP1510_GPIO_PIN_CONTROL 0x18
40
41#define OMAP1510_IH_GPIO_BASE 64
42
43/*
44 * OMAP1610 specific GPIO registers
45 */
92105bb7
TL		 46#define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47#define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48#define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49#define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
5e1c5ff4
TL		 50#define OMAP1610_GPIO_REVISION 0x0000
51#define OMAP1610_GPIO_SYSCONFIG 0x0010
52#define OMAP1610_GPIO_SYSSTATUS 0x0014
53#define OMAP1610_GPIO_IRQSTATUS1 0x0018
54#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 55#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 56#define OMAP1610_GPIO_DATAIN 0x002c
57#define OMAP1610_GPIO_DATAOUT 0x0030
58#define OMAP1610_GPIO_DIRECTION 0x0034
59#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 62#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 63#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 65#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 66#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
67
68/*
69 * OMAP730 specific GPIO registers
70 */
92105bb7
TL		 71#define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72#define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73#define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74#define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75#define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76#define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
5e1c5ff4
TL		 77#define OMAP730_GPIO_DATA_INPUT 0x00
78#define OMAP730_GPIO_DATA_OUTPUT 0x04
79#define OMAP730_GPIO_DIR_CONTROL 0x08
80#define OMAP730_GPIO_INT_CONTROL 0x0c
81#define OMAP730_GPIO_INT_MASK 0x10
82#define OMAP730_GPIO_INT_STATUS 0x14
83
92105bb7
TL		 84/*
85 * omap24xx specific GPIO registers
86 */
56a25641
SMK		 87#define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88#define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89#define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90#define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
91
92#define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93#define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94#define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95#define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96#define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
97
92105bb7
TL		 98#define OMAP24XX_GPIO_REVISION 0x0000
99#define OMAP24XX_GPIO_SYSCONFIG 0x0010
100#define OMAP24XX_GPIO_SYSSTATUS 0x0014
101#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 102#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7
TL		 104#define OMAP24XX_GPIO_IRQENABLE1 0x001c
105#define OMAP24XX_GPIO_CTRL 0x0030
106#define OMAP24XX_GPIO_OE 0x0034
107#define OMAP24XX_GPIO_DATAIN 0x0038
108#define OMAP24XX_GPIO_DATAOUT 0x003c
109#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111#define OMAP24XX_GPIO_RISINGDETECT 0x0048
112#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
114#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
115#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
116#define OMAP24XX_GPIO_SETWKUENA 0x0084
117#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
118#define OMAP24XX_GPIO_SETDATAOUT 0x0094
119
5492fb1a
SMK		 120/*
121 * omap34xx specific GPIO registers
122 */
123
124#define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
125#define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
126#define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
127#define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
128#define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
129#define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
130
131
5e1c5ff4 132struct gpio_bank {
92105bb7 133 void __iomem *base;
5e1c5ff4
TL		 134 u16 irq;
135 u16 virtual_irq_start;
92105bb7 136 int method;
5e1c5ff4 137 u32 reserved_map;
5492fb1a 138#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 139 u32 suspend_wakeup;
140 u32 saved_wakeup;
3ac4fa99 141#endif
5492fb1a 142#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 143 u32 non_wakeup_gpios;
144 u32 enabled_non_wakeup_gpios;
145
146 u32 saved_datain;
147 u32 saved_fallingdetect;
148 u32 saved_risingdetect;
149#endif
5e1c5ff4
TL		 150 spinlock_t lock;
151};
152
153#define METHOD_MPUIO 0
154#define METHOD_GPIO_1510 1
155#define METHOD_GPIO_1610 2
156#define METHOD_GPIO_730 3
92105bb7 157#define METHOD_GPIO_24XX 4
5e1c5ff4 158
92105bb7 159#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 160static struct gpio_bank gpio_bank_1610[5] = {
161 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
162 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
163 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
164 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
165 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
166};
167#endif
168
1a8bfa1e 169#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 170static struct gpio_bank gpio_bank_1510[2] = {
171 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
172 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
173};
174#endif
175
176#ifdef CONFIG_ARCH_OMAP730
177static struct gpio_bank gpio_bank_730[7] = {
178 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
179 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
180 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
181 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
182 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
183 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
184 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
185};
186#endif
187
92105bb7 188#ifdef CONFIG_ARCH_OMAP24XX
56a25641
SMK		 189
190static struct gpio_bank gpio_bank_242x[4] = {
191 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
192 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
193 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
194 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
92105bb7 195};
56a25641
SMK		 196
197static struct gpio_bank gpio_bank_243x[5] = {
198 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
199 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
200 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
201 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
203};
204
92105bb7
TL		 205#endif
206
5492fb1a
SMK		 207#ifdef CONFIG_ARCH_OMAP34XX
208static struct gpio_bank gpio_bank_34xx[6] = {
209 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
210 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
211 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
212 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
215};
216
217#endif
218
5e1c5ff4
TL		 219static struct gpio_bank *gpio_bank;
220static int gpio_bank_count;
221
222static inline struct gpio_bank *get_gpio_bank(int gpio)
223{
6e60e79a 224 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 225 if (OMAP_GPIO_IS_MPUIO(gpio))
226 return &gpio_bank[0];
227 return &gpio_bank[1];
228 }
5e1c5ff4
TL		 229 if (cpu_is_omap16xx()) {
230 if (OMAP_GPIO_IS_MPUIO(gpio))
231 return &gpio_bank[0];
232 return &gpio_bank[1 + (gpio >> 4)];
233 }
5e1c5ff4
TL		 234 if (cpu_is_omap730()) {
235 if (OMAP_GPIO_IS_MPUIO(gpio))
236 return &gpio_bank[0];
237 return &gpio_bank[1 + (gpio >> 5)];
238 }
92105bb7
TL		 239 if (cpu_is_omap24xx())
240 return &gpio_bank[gpio >> 5];
5492fb1a
SMK		 241 if (cpu_is_omap34xx())
242 return &gpio_bank[gpio >> 5];
5e1c5ff4
TL		 243}
244
245static inline int get_gpio_index(int gpio)
246{
247 if (cpu_is_omap730())
248 return gpio & 0x1f;
92105bb7
TL		 249 if (cpu_is_omap24xx())
250 return gpio & 0x1f;
5492fb1a
SMK		 251 if (cpu_is_omap34xx())
252 return gpio & 0x1f;
92105bb7 253 return gpio & 0x0f;
5e1c5ff4
TL		 254}
255
256static inline int gpio_valid(int gpio)
257{
258 if (gpio < 0)
259 return -1;
d11ac979 260 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 261 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 262 return -1;
263 return 0;
264 }
6e60e79a 265 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 266 return 0;
5e1c5ff4
TL		 267 if ((cpu_is_omap16xx()) && gpio < 64)
268 return 0;
5e1c5ff4
TL		 269 if (cpu_is_omap730() && gpio < 192)
270 return 0;
92105bb7
TL		 271 if (cpu_is_omap24xx() && gpio < 128)
272 return 0;
5492fb1a
SMK		 273 if (cpu_is_omap34xx() && gpio < 160)
274 return 0;
5e1c5ff4
TL		 275 return -1;
276}
277
278static int check_gpio(int gpio)
279{
280 if (unlikely(gpio_valid(gpio)) < 0) {
281 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
282 dump_stack();
283 return -1;
284 }
285 return 0;
286}
287
288static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
289{
92105bb7 290 void __iomem *reg = bank->base;
5e1c5ff4
TL		 291 u32 l;
292
293 switch (bank->method) {
e5c56ed3 294#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 295 case METHOD_MPUIO:
296 reg += OMAP_MPUIO_IO_CNTL;
297 break;
e5c56ed3
DB		 298#endif
299#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 300 case METHOD_GPIO_1510:
301 reg += OMAP1510_GPIO_DIR_CONTROL;
302 break;
e5c56ed3
DB		 303#endif
304#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 305 case METHOD_GPIO_1610:
306 reg += OMAP1610_GPIO_DIRECTION;
307 break;
e5c56ed3
DB		 308#endif
309#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 310 case METHOD_GPIO_730:
311 reg += OMAP730_GPIO_DIR_CONTROL;
312 break;
e5c56ed3 313#endif
5492fb1a 314#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 315 case METHOD_GPIO_24XX:
316 reg += OMAP24XX_GPIO_OE;
317 break;
e5c56ed3
DB		 318#endif
319 default:
320 WARN_ON(1);
321 return;
5e1c5ff4
TL		 322 }
323 l = __raw_readl(reg);
324 if (is_input)
325 l |= 1 << gpio;
326 else
327 l &= ~(1 << gpio);
328 __raw_writel(l, reg);
329}
330
331void omap_set_gpio_direction(int gpio, int is_input)
332{
333 struct gpio_bank *bank;
334
335 if (check_gpio(gpio) < 0)
336 return;
337 bank = get_gpio_bank(gpio);
338 spin_lock(&bank->lock);
339 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
340 spin_unlock(&bank->lock);
341}
342
343static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
344{
92105bb7 345 void __iomem *reg = bank->base;
5e1c5ff4
TL		 346 u32 l = 0;
347
348 switch (bank->method) {
e5c56ed3 349#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 350 case METHOD_MPUIO:
351 reg += OMAP_MPUIO_OUTPUT;
352 l = __raw_readl(reg);
353 if (enable)
354 l |= 1 << gpio;
355 else
356 l &= ~(1 << gpio);
357 break;
e5c56ed3
DB		 358#endif
359#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 360 case METHOD_GPIO_1510:
361 reg += OMAP1510_GPIO_DATA_OUTPUT;
362 l = __raw_readl(reg);
363 if (enable)
364 l |= 1 << gpio;
365 else
366 l &= ~(1 << gpio);
367 break;
e5c56ed3
DB		 368#endif
369#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 370 case METHOD_GPIO_1610:
371 if (enable)
372 reg += OMAP1610_GPIO_SET_DATAOUT;
373 else
374 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
375 l = 1 << gpio;
376 break;
e5c56ed3
DB		 377#endif
378#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 379 case METHOD_GPIO_730:
380 reg += OMAP730_GPIO_DATA_OUTPUT;
381 l = __raw_readl(reg);
382 if (enable)
383 l |= 1 << gpio;
384 else
385 l &= ~(1 << gpio);
386 break;
e5c56ed3 387#endif
5492fb1a 388#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 389 case METHOD_GPIO_24XX:
390 if (enable)
391 reg += OMAP24XX_GPIO_SETDATAOUT;
392 else
393 reg += OMAP24XX_GPIO_CLEARDATAOUT;
394 l = 1 << gpio;
395 break;
e5c56ed3 396#endif
5e1c5ff4 397 default:
e5c56ed3 398 WARN_ON(1);
5e1c5ff4
TL		 399 return;
400 }
401 __raw_writel(l, reg);
402}
403
404void omap_set_gpio_dataout(int gpio, int enable)
405{
406 struct gpio_bank *bank;
407
408 if (check_gpio(gpio) < 0)
409 return;
410 bank = get_gpio_bank(gpio);
411 spin_lock(&bank->lock);
412 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
413 spin_unlock(&bank->lock);
414}
415
416int omap_get_gpio_datain(int gpio)
417{
418 struct gpio_bank *bank;
92105bb7 419 void __iomem *reg;
5e1c5ff4
TL		 420
421 if (check_gpio(gpio) < 0)
e5c56ed3 422 return -EINVAL;
5e1c5ff4
TL		 423 bank = get_gpio_bank(gpio);
424 reg = bank->base;
425 switch (bank->method) {
e5c56ed3 426#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 427 case METHOD_MPUIO:
428 reg += OMAP_MPUIO_INPUT_LATCH;
429 break;
e5c56ed3
DB		 430#endif
431#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 432 case METHOD_GPIO_1510:
433 reg += OMAP1510_GPIO_DATA_INPUT;
434 break;
e5c56ed3
DB		 435#endif
436#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 437 case METHOD_GPIO_1610:
438 reg += OMAP1610_GPIO_DATAIN;
439 break;
e5c56ed3
DB		 440#endif
441#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 442 case METHOD_GPIO_730:
443 reg += OMAP730_GPIO_DATA_INPUT;
444 break;
e5c56ed3 445#endif
5492fb1a 446#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 447 case METHOD_GPIO_24XX:
448 reg += OMAP24XX_GPIO_DATAIN;
449 break;
e5c56ed3 450#endif
5e1c5ff4 451 default:
e5c56ed3 452 return -EINVAL;
5e1c5ff4 453 }
92105bb7
TL		 454 return (__raw_readl(reg)
455 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 456}
457
92105bb7
TL		 458#define MOD_REG_BIT(reg, bit_mask, set) \
459do { \
460 int l = __raw_readl(base + reg); \
461 if (set) l |= bit_mask; \
462 else l &= ~bit_mask; \
463 __raw_writel(l, base + reg); \
464} while(0)
465
5492fb1a 466#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 467static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
5e1c5ff4 468{
3ac4fa99 469 void __iomem *base = bank->base;
92105bb7
TL		 470 u32 gpio_bit = 1 << gpio;
471
472 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
6e60e79a 473 trigger & __IRQT_LOWLVL);
92105bb7 474 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
6e60e79a 475 trigger & __IRQT_HIGHLVL);
92105bb7 476 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
6e60e79a 477 trigger & __IRQT_RISEDGE);
92105bb7 478 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
6e60e79a 479 trigger & __IRQT_FALEDGE);
3ac4fa99
JY		 480 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
481 if (trigger != 0)
482 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
483 else
484 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
485 } else {
486 if (trigger != 0)
487 bank->enabled_non_wakeup_gpios |= gpio_bit;
488 else
489 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
490 }
10dd5ce2 491 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
92105bb7
TL		 492 * triggering requested. */
493}
3ac4fa99 494#endif
92105bb7
TL		 495
496static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
497{
498 void __iomem *reg = bank->base;
499 u32 l = 0;
5e1c5ff4
TL		 500
501 switch (bank->method) {
e5c56ed3 502#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 503 case METHOD_MPUIO:
504 reg += OMAP_MPUIO_GPIO_INT_EDGE;
505 l = __raw_readl(reg);
6e60e79a 506 if (trigger & __IRQT_RISEDGE)
5e1c5ff4 507 l |= 1 << gpio;
6e60e79a 508 else if (trigger & __IRQT_FALEDGE)
5e1c5ff4 509 l &= ~(1 << gpio);
92105bb7
TL		 510 else
511 goto bad;
5e1c5ff4 512 break;
e5c56ed3
DB		 513#endif
514#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 515 case METHOD_GPIO_1510:
516 reg += OMAP1510_GPIO_INT_CONTROL;
517 l = __raw_readl(reg);
6e60e79a 518 if (trigger & __IRQT_RISEDGE)
5e1c5ff4 519 l |= 1 << gpio;
6e60e79a 520 else if (trigger & __IRQT_FALEDGE)
5e1c5ff4 521 l &= ~(1 << gpio);
92105bb7
TL		 522 else
523 goto bad;
5e1c5ff4 524 break;
e5c56ed3 525#endif
3ac4fa99 526#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 527 case METHOD_GPIO_1610:
5e1c5ff4
TL		 528 if (gpio & 0x08)
529 reg += OMAP1610_GPIO_EDGE_CTRL2;
530 else
531 reg += OMAP1610_GPIO_EDGE_CTRL1;
532 gpio &= 0x07;
533 l = __raw_readl(reg);
534 l &= ~(3 << (gpio << 1));
6e60e79a
TL		 535 if (trigger & __IRQT_RISEDGE)
536 l |= 2 << (gpio << 1);
537 if (trigger & __IRQT_FALEDGE)
538 l |= 1 << (gpio << 1);
3ac4fa99
JY		 539 if (trigger)
540 /* Enable wake-up during idle for dynamic tick */
541 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
542 else
543 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 544 break;
3ac4fa99
JY		 545#endif
546#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 547 case METHOD_GPIO_730:
548 reg += OMAP730_GPIO_INT_CONTROL;
549 l = __raw_readl(reg);
6e60e79a 550 if (trigger & __IRQT_RISEDGE)
5e1c5ff4 551 l |= 1 << gpio;
6e60e79a 552 else if (trigger & __IRQT_FALEDGE)
5e1c5ff4 553 l &= ~(1 << gpio);
92105bb7
TL		 554 else
555 goto bad;
556 break;
3ac4fa99 557#endif
5492fb1a 558#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 559 case METHOD_GPIO_24XX:
3ac4fa99 560 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 561 break;
3ac4fa99 562#endif
5e1c5ff4 563 default:
92105bb7 564 goto bad;
5e1c5ff4 565 }
92105bb7
TL		 566 __raw_writel(l, reg);
567 return 0;
568bad:
569 return -EINVAL;
5e1c5ff4
TL		 570}
571
92105bb7 572static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 573{
574 struct gpio_bank *bank;
92105bb7
TL		 575 unsigned gpio;
576 int retval;
577
5492fb1a 578 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 579 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
580 else
581 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 582
583 if (check_gpio(gpio) < 0)
92105bb7
TL		 584 return -EINVAL;
585
e5c56ed3 586 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 587 return -EINVAL;
e5c56ed3
DB		 588
589 /* OMAP1 allows only only edge triggering */
5492fb1a 590 if (!cpu_class_is_omap2()
e5c56ed3 591 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 592 return -EINVAL;
593
58781016 594 bank = get_irq_chip_data(irq);
5e1c5ff4 595 spin_lock(&bank->lock);
92105bb7 596 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 597 if (retval == 0) {
598 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
599 irq_desc[irq].status |= type;
600 }
5e1c5ff4 601 spin_unlock(&bank->lock);
92105bb7 602 return retval;
5e1c5ff4
TL		 603}
604
605static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
606{
92105bb7 607 void __iomem *reg = bank->base;
5e1c5ff4
TL		 608
609 switch (bank->method) {
e5c56ed3 610#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 611 case METHOD_MPUIO:
612 /* MPUIO irqstatus is reset by reading the status register,
613 * so do nothing here */
614 return;
e5c56ed3
DB		 615#endif
616#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 617 case METHOD_GPIO_1510:
618 reg += OMAP1510_GPIO_INT_STATUS;
619 break;
e5c56ed3
DB		 620#endif
621#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 622 case METHOD_GPIO_1610:
623 reg += OMAP1610_GPIO_IRQSTATUS1;
624 break;
e5c56ed3
DB		 625#endif
626#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 627 case METHOD_GPIO_730:
628 reg += OMAP730_GPIO_INT_STATUS;
629 break;
e5c56ed3 630#endif
5492fb1a 631#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 632 case METHOD_GPIO_24XX:
633 reg += OMAP24XX_GPIO_IRQSTATUS1;
634 break;
e5c56ed3 635#endif
5e1c5ff4 636 default:
e5c56ed3 637 WARN_ON(1);
5e1c5ff4
TL		 638 return;
639 }
640 __raw_writel(gpio_mask, reg);
bee7930f
HD		 641
642 /* Workaround for clearing DSP GPIO interrupts to allow retention */
5492fb1a
SMK		 643#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
644 if (cpu_is_omap24xx() || cpu_is_omap34xx())
bee7930f 645 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
5492fb1a 646#endif
5e1c5ff4
TL		 647}
648
649static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
650{
651 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
652}
653
ea6dedd7
ID		 654static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
655{
656 void __iomem *reg = bank->base;
99c47707
ID		 657 int inv = 0;
658 u32 l;
659 u32 mask;
ea6dedd7
ID		 660
661 switch (bank->method) {
e5c56ed3 662#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 663 case METHOD_MPUIO:
664 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 665 mask = 0xffff;
666 inv = 1;
ea6dedd7 667 break;
e5c56ed3
DB		 668#endif
669#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 670 case METHOD_GPIO_1510:
671 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 672 mask = 0xffff;
673 inv = 1;
ea6dedd7 674 break;
e5c56ed3
DB		 675#endif
676#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 677 case METHOD_GPIO_1610:
678 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 679 mask = 0xffff;
ea6dedd7 680 break;
e5c56ed3
DB		 681#endif
682#ifdef CONFIG_ARCH_OMAP730
ea6dedd7
ID		 683 case METHOD_GPIO_730:
684 reg += OMAP730_GPIO_INT_MASK;
99c47707
ID		 685 mask = 0xffffffff;
686 inv = 1;
ea6dedd7 687 break;
e5c56ed3 688#endif
5492fb1a 689#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
ea6dedd7
ID		 690 case METHOD_GPIO_24XX:
691 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 692 mask = 0xffffffff;
ea6dedd7 693 break;
e5c56ed3 694#endif
ea6dedd7 695 default:
e5c56ed3 696 WARN_ON(1);
ea6dedd7
ID		 697 return 0;
698 }
699
99c47707
ID		 700 l = __raw_readl(reg);
701 if (inv)
702 l = ~l;
703 l &= mask;
704 return l;
ea6dedd7
ID		 705}
706
5e1c5ff4
TL		 707static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
708{
92105bb7 709 void __iomem *reg = bank->base;
5e1c5ff4
TL		 710 u32 l;
711
712 switch (bank->method) {
e5c56ed3 713#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 714 case METHOD_MPUIO:
715 reg += OMAP_MPUIO_GPIO_MASKIT;
716 l = __raw_readl(reg);
717 if (enable)
718 l &= ~(gpio_mask);
719 else
720 l |= gpio_mask;
721 break;
e5c56ed3
DB		 722#endif
723#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 724 case METHOD_GPIO_1510:
725 reg += OMAP1510_GPIO_INT_MASK;
726 l = __raw_readl(reg);
727 if (enable)
728 l &= ~(gpio_mask);
729 else
730 l |= gpio_mask;
731 break;
e5c56ed3
DB		 732#endif
733#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 734 case METHOD_GPIO_1610:
735 if (enable)
736 reg += OMAP1610_GPIO_SET_IRQENABLE1;
737 else
738 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
739 l = gpio_mask;
740 break;
e5c56ed3
DB		 741#endif
742#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 743 case METHOD_GPIO_730:
744 reg += OMAP730_GPIO_INT_MASK;
745 l = __raw_readl(reg);
746 if (enable)
747 l &= ~(gpio_mask);
748 else
749 l |= gpio_mask;
750 break;
e5c56ed3 751#endif
5492fb1a 752#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 753 case METHOD_GPIO_24XX:
754 if (enable)
755 reg += OMAP24XX_GPIO_SETIRQENABLE1;
756 else
757 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
758 l = gpio_mask;
759 break;
e5c56ed3 760#endif
5e1c5ff4 761 default:
e5c56ed3 762 WARN_ON(1);
5e1c5ff4
TL		 763 return;
764 }
765 __raw_writel(l, reg);
766}
767
768static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
769{
770 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
771}
772
92105bb7
TL		 773/*
774 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
775 * 1510 does not seem to have a wake-up register. If JTAG is connected
776 * to the target, system will wake up always on GPIO events. While
777 * system is running all registered GPIO interrupts need to have wake-up
778 * enabled. When system is suspended, only selected GPIO interrupts need
779 * to have wake-up enabled.
780 */
781static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
782{
783 switch (bank->method) {
3ac4fa99 784#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 785 case METHOD_MPUIO:
92105bb7 786 case METHOD_GPIO_1610:
92105bb7 787 spin_lock(&bank->lock);
11a78b79 788 if (enable) {
92105bb7 789 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 790 enable_irq_wake(bank->irq);
791 } else {
792 disable_irq_wake(bank->irq);
92105bb7 793 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 794 }
92105bb7
TL		 795 spin_unlock(&bank->lock);
796 return 0;
3ac4fa99 797#endif
5492fb1a 798#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 799 case METHOD_GPIO_24XX:
11a78b79
DB		 800 if (bank->non_wakeup_gpios & (1 << gpio)) {
801 printk(KERN_ERR "Unable to modify wakeup on "
802 "non-wakeup GPIO%d\n",
803 (bank - gpio_bank) * 32 + gpio);
804 return -EINVAL;
805 }
3ac4fa99
JY		 806 spin_lock(&bank->lock);
807 if (enable) {
3ac4fa99 808 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 809 enable_irq_wake(bank->irq);
810 } else {
811 disable_irq_wake(bank->irq);
3ac4fa99 812 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 813 }
3ac4fa99
JY		 814 spin_unlock(&bank->lock);
815 return 0;
816#endif
92105bb7
TL		 817 default:
818 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
819 bank->method);
820 return -EINVAL;
821 }
822}
823
4196dd6b
TL		 824static void _reset_gpio(struct gpio_bank *bank, int gpio)
825{
826 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
827 _set_gpio_irqenable(bank, gpio, 0);
828 _clear_gpio_irqstatus(bank, gpio);
829 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
830}
831
92105bb7
TL		 832/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
833static int gpio_wake_enable(unsigned int irq, unsigned int enable)
834{
835 unsigned int gpio = irq - IH_GPIO_BASE;
836 struct gpio_bank *bank;
837 int retval;
838
839 if (check_gpio(gpio) < 0)
840 return -ENODEV;
58781016 841 bank = get_irq_chip_data(irq);
92105bb7 842 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 843
844 return retval;
845}
846
5e1c5ff4
TL		 847int omap_request_gpio(int gpio)
848{
849 struct gpio_bank *bank;
850
851 if (check_gpio(gpio) < 0)
852 return -EINVAL;
853
854 bank = get_gpio_bank(gpio);
855 spin_lock(&bank->lock);
856 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
857 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
858 dump_stack();
859 spin_unlock(&bank->lock);
860 return -1;
861 }
862 bank->reserved_map |= (1 << get_gpio_index(gpio));
92105bb7 863
4196dd6b
TL		 864 /* Set trigger to none. You need to enable the desired trigger with
865 * request_irq() or set_irq_type().
866 */
92105bb7
TL		 867 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
868
1a8bfa1e 869#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 870 if (bank->method == METHOD_GPIO_1510) {
92105bb7 871 void __iomem *reg;
5e1c5ff4 872
92105bb7 873 /* Claim the pin for MPU */
5e1c5ff4
TL		 874 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
875 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
876 }
877#endif
878 spin_unlock(&bank->lock);
879
880 return 0;
881}
882
883void omap_free_gpio(int gpio)
884{
885 struct gpio_bank *bank;
886
887 if (check_gpio(gpio) < 0)
888 return;
889 bank = get_gpio_bank(gpio);
890 spin_lock(&bank->lock);
891 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
892 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
893 dump_stack();
894 spin_unlock(&bank->lock);
895 return;
896 }
92105bb7
TL		 897#ifdef CONFIG_ARCH_OMAP16XX
898 if (bank->method == METHOD_GPIO_1610) {
899 /* Disable wake-up during idle for dynamic tick */
900 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
901 __raw_writel(1 << get_gpio_index(gpio), reg);
902 }
903#endif
5492fb1a 904#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 905 if (bank->method == METHOD_GPIO_24XX) {
906 /* Disable wake-up during idle for dynamic tick */
907 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
908 __raw_writel(1 << get_gpio_index(gpio), reg);
909 }
910#endif
5e1c5ff4 911 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
4196dd6b 912 _reset_gpio(bank, gpio);
5e1c5ff4
TL		 913 spin_unlock(&bank->lock);
914}
915
916/*
917 * We need to unmask the GPIO bank interrupt as soon as possible to
918 * avoid missing GPIO interrupts for other lines in the bank.
919 * Then we need to mask-read-clear-unmask the triggered GPIO lines
920 * in the bank to avoid missing nested interrupts for a GPIO line.
921 * If we wait to unmask individual GPIO lines in the bank after the
922 * line's interrupt handler has been run, we may miss some nested
923 * interrupts.
924 */
10dd5ce2 925static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 926{
92105bb7 927 void __iomem *isr_reg = NULL;
5e1c5ff4
TL		 928 u32 isr;
929 unsigned int gpio_irq;
930 struct gpio_bank *bank;
ea6dedd7
ID		 931 u32 retrigger = 0;
932 int unmasked = 0;
5e1c5ff4
TL		 933
934 desc->chip->ack(irq);
935
418ca1f0 936 bank = get_irq_data(irq);
e5c56ed3 937#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 938 if (bank->method == METHOD_MPUIO)
939 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 940#endif
1a8bfa1e 941#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 942 if (bank->method == METHOD_GPIO_1510)
943 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
944#endif
945#if defined(CONFIG_ARCH_OMAP16XX)
946 if (bank->method == METHOD_GPIO_1610)
947 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
948#endif
949#ifdef CONFIG_ARCH_OMAP730
950 if (bank->method == METHOD_GPIO_730)
951 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
952#endif
5492fb1a 953#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 954 if (bank->method == METHOD_GPIO_24XX)
955 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
956#endif
92105bb7 957 while(1) {
6e60e79a 958 u32 isr_saved, level_mask = 0;
ea6dedd7 959 u32 enabled;
6e60e79a 960
ea6dedd7
ID		 961 enabled = _get_gpio_irqbank_mask(bank);
962 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 963
964 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
965 isr &= 0x0000ffff;
966
5492fb1a 967 if (cpu_class_is_omap2()) {
6e60e79a
TL		 968 level_mask =
969 __raw_readl(bank->base +
970 OMAP24XX_GPIO_LEVELDETECT0) |
971 __raw_readl(bank->base +
972 OMAP24XX_GPIO_LEVELDETECT1);
ea6dedd7
ID		 973 level_mask &= enabled;
974 }
6e60e79a
TL		 975
976 /* clear edge sensitive interrupts before handler(s) are
977 called so that we don't miss any interrupt occurred while
978 executing them */
979 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
980 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
981 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
982
983 /* if there is only edge sensitive GPIO pin interrupts
984 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 985 if (!level_mask && !unmasked) {
986 unmasked = 1;
6e60e79a 987 desc->chip->unmask(irq);
ea6dedd7 988 }
92105bb7 989
ea6dedd7
ID		 990 isr |= retrigger;
991 retrigger = 0;
92105bb7
TL		 992 if (!isr)
993 break;
994
995 gpio_irq = bank->virtual_irq_start;
996 for (; isr != 0; isr >>= 1, gpio_irq++) {
10dd5ce2 997 struct irq_desc *d;
ea6dedd7 998 int irq_mask;
92105bb7
TL		 999 if (!(isr & 1))
1000 continue;
1001 d = irq_desc + gpio_irq;
ea6dedd7
ID		 1002 /* Don't run the handler if it's already running
1003 * or was disabled lazely.
1004 */
29454dde
TG		 1005 if (unlikely((d->depth ||
1006 (d->status & IRQ_INPROGRESS)))) {
ea6dedd7
ID		 1007 irq_mask = 1 <<
1008 (gpio_irq - bank->virtual_irq_start);
1009 /* The unmasking will be done by
1010 * enable_irq in case it is disabled or
1011 * after returning from the handler if
1012 * it's already running.
1013 */
1014 _enable_gpio_irqbank(bank, irq_mask, 0);
29454dde 1015 if (!d->depth) {
ea6dedd7
ID		 1016 /* Level triggered interrupts
1017 * won't ever be reentered
1018 */
1019 BUG_ON(level_mask & irq_mask);
29454dde 1020 d->status |= IRQ_PENDING;
ea6dedd7
ID		 1021 }
1022 continue;
1023 }
29454dde 1024
0cd61b68 1025 desc_handle_irq(gpio_irq, d);
29454dde
TG		 1026
1027 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
ea6dedd7
ID		 1028 irq_mask = 1 <<
1029 (gpio_irq - bank->virtual_irq_start);
29454dde 1030 d->status &= ~IRQ_PENDING;
ea6dedd7
ID		 1031 _enable_gpio_irqbank(bank, irq_mask, 1);
1032 retrigger |= irq_mask;
1033 }
92105bb7 1034 }
6e60e79a 1035
5492fb1a 1036 if (cpu_class_is_omap2()) {
6e60e79a
TL		 1037 /* clear level sensitive interrupts after handler(s) */
1038 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1039 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1040 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1041 }
1042
1a8bfa1e 1043 }
ea6dedd7
ID		 1044 /* if bank has any level sensitive GPIO pin interrupt
1045 configured, we must unmask the bank interrupt only after
1046 handler(s) are executed in order to avoid spurious bank
1047 interrupt */
1048 if (!unmasked)
1049 desc->chip->unmask(irq);
1050
5e1c5ff4
TL		 1051}
1052
4196dd6b
TL		 1053static void gpio_irq_shutdown(unsigned int irq)
1054{
1055 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1056 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1057
1058 _reset_gpio(bank, gpio);
1059}
1060
5e1c5ff4
TL		 1061static void gpio_ack_irq(unsigned int irq)
1062{
1063 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1064 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1065
1066 _clear_gpio_irqstatus(bank, gpio);
1067}
1068
1069static void gpio_mask_irq(unsigned int irq)
1070{
1071 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1072 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1073
1074 _set_gpio_irqenable(bank, gpio, 0);
1075}
1076
1077static void gpio_unmask_irq(unsigned int irq)
1078{
1079 unsigned int gpio = irq - IH_GPIO_BASE;
92105bb7 1080 unsigned int gpio_idx = get_gpio_index(gpio);
58781016 1081 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4 1082
92105bb7 1083 _set_gpio_irqenable(bank, gpio_idx, 1);
5e1c5ff4
TL		 1084}
1085
e5c56ed3
DB		 1086static struct irq_chip gpio_irq_chip = {
1087 .name = "GPIO",
1088 .shutdown = gpio_irq_shutdown,
1089 .ack = gpio_ack_irq,
1090 .mask = gpio_mask_irq,
1091 .unmask = gpio_unmask_irq,
1092 .set_type = gpio_irq_type,
1093 .set_wake = gpio_wake_enable,
1094};
1095
1096/*---------------------------------------------------------------------*/
1097
1098#ifdef CONFIG_ARCH_OMAP1
1099
1100/* MPUIO uses the always-on 32k clock */
1101
5e1c5ff4
TL		 1102static void mpuio_ack_irq(unsigned int irq)
1103{
1104 /* The ISR is reset automatically, so do nothing here. */
1105}
1106
1107static void mpuio_mask_irq(unsigned int irq)
1108{
1109 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1110 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1111
1112 _set_gpio_irqenable(bank, gpio, 0);
1113}
1114
1115static void mpuio_unmask_irq(unsigned int irq)
1116{
1117 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1118 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1119
1120 _set_gpio_irqenable(bank, gpio, 1);
1121}
1122
e5c56ed3
DB		 1123static struct irq_chip mpuio_irq_chip = {
1124 .name = "MPUIO",
1125 .ack = mpuio_ack_irq,
1126 .mask = mpuio_mask_irq,
1127 .unmask = mpuio_unmask_irq,
92105bb7 1128 .set_type = gpio_irq_type,
11a78b79
DB		 1129#ifdef CONFIG_ARCH_OMAP16XX
1130 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1131 .set_wake = gpio_wake_enable,
1132#endif
5e1c5ff4
TL		 1133};
1134
e5c56ed3
DB		 1135
1136#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1137
11a78b79
DB		 1138
1139#ifdef CONFIG_ARCH_OMAP16XX
1140
1141#include <linux/platform_device.h>
1142
1143static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1144{
1145 struct gpio_bank *bank = platform_get_drvdata(pdev);
1146 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1147
1148 spin_lock(&bank->lock);
1149 bank->saved_wakeup = __raw_readl(mask_reg);
1150 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1151 spin_unlock(&bank->lock);
1152
1153 return 0;
1154}
1155
1156static int omap_mpuio_resume_early(struct platform_device *pdev)
1157{
1158 struct gpio_bank *bank = platform_get_drvdata(pdev);
1159 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1160
1161 spin_lock(&bank->lock);
1162 __raw_writel(bank->saved_wakeup, mask_reg);
1163 spin_unlock(&bank->lock);
1164
1165 return 0;
1166}
1167
1168/* use platform_driver for this, now that there's no longer any
1169 * point to sys_device (other than not disturbing old code).
1170 */
1171static struct platform_driver omap_mpuio_driver = {
1172 .suspend_late = omap_mpuio_suspend_late,
1173 .resume_early = omap_mpuio_resume_early,
1174 .driver = {
1175 .name = "mpuio",
1176 },
1177};
1178
1179static struct platform_device omap_mpuio_device = {
1180 .name = "mpuio",
1181 .id = -1,
1182 .dev = {
1183 .driver = &omap_mpuio_driver.driver,
1184 }
1185 /* could list the /proc/iomem resources */
1186};
1187
1188static inline void mpuio_init(void)
1189{
fcf126d8
DB		 1190 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1191
11a78b79
DB		 1192 if (platform_driver_register(&omap_mpuio_driver) == 0)
1193 (void) platform_device_register(&omap_mpuio_device);
1194}
1195
1196#else
1197static inline void mpuio_init(void) {}
1198#endif /* 16xx */
1199
e5c56ed3
DB		 1200#else
1201
1202extern struct irq_chip mpuio_irq_chip;
1203
1204#define bank_is_mpuio(bank) 0
11a78b79 1205static inline void mpuio_init(void) {}
e5c56ed3
DB		 1206
1207#endif
1208
1209/*---------------------------------------------------------------------*/
5e1c5ff4 1210
1a8bfa1e 1211static int initialized;
5492fb1a 1212#if !defined(CONFIG_ARCH_OMAP3)
1a8bfa1e 1213static struct clk * gpio_ick;
5492fb1a
SMK		 1214#endif
1215
1216#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1217static struct clk * gpio_fck;
5492fb1a 1218#endif
5e1c5ff4 1219
5492fb1a 1220#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1221static struct clk * gpio5_ick;
1222static struct clk * gpio5_fck;
1223#endif
1224
5492fb1a
SMK		 1225#if defined(CONFIG_ARCH_OMAP3)
1226static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1227static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1228#endif
1229
5e1c5ff4
TL		 1230static int __init _omap_gpio_init(void)
1231{
1232 int i;
1233 struct gpio_bank *bank;
5492fb1a
SMK		 1234#if defined(CONFIG_ARCH_OMAP3)
1235 char clk_name[11];
1236#endif
5e1c5ff4
TL		 1237
1238 initialized = 1;
1239
5492fb1a 1240#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1241 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1242 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1243 if (IS_ERR(gpio_ick))
92105bb7
TL		 1244 printk("Could not get arm_gpio_ck\n");
1245 else
30ff720b 1246 clk_enable(gpio_ick);
1a8bfa1e 1247 }
5492fb1a
SMK		 1248#endif
1249#if defined(CONFIG_ARCH_OMAP2)
1250 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1251 gpio_ick = clk_get(NULL, "gpios_ick");
1252 if (IS_ERR(gpio_ick))
1253 printk("Could not get gpios_ick\n");
1254 else
30ff720b 1255 clk_enable(gpio_ick);
1a8bfa1e 1256 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1257 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1258 printk("Could not get gpios_fck\n");
1259 else
30ff720b 1260 clk_enable(gpio_fck);
56a25641
SMK		 1261
1262 /*
5492fb1a 1263 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1264 */
5492fb1a 1265#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1266 if (cpu_is_omap2430()) {
1267 gpio5_ick = clk_get(NULL, "gpio5_ick");
1268 if (IS_ERR(gpio5_ick))
1269 printk("Could not get gpio5_ick\n");
1270 else
1271 clk_enable(gpio5_ick);
1272 gpio5_fck = clk_get(NULL, "gpio5_fck");
1273 if (IS_ERR(gpio5_fck))
1274 printk("Could not get gpio5_fck\n");
1275 else
1276 clk_enable(gpio5_fck);
1277 }
1278#endif
5492fb1a
SMK		 1279 }
1280#endif
1281
1282#if defined(CONFIG_ARCH_OMAP3)
1283 if (cpu_is_omap34xx()) {
1284 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1285 sprintf(clk_name, "gpio%d_ick", i + 1);
1286 gpio_iclks[i] = clk_get(NULL, clk_name);
1287 if (IS_ERR(gpio_iclks[i]))
1288 printk(KERN_ERR "Could not get %s\n", clk_name);
1289 else
1290 clk_enable(gpio_iclks[i]);
1291 sprintf(clk_name, "gpio%d_fck", i + 1);
1292 gpio_fclks[i] = clk_get(NULL, clk_name);
1293 if (IS_ERR(gpio_fclks[i]))
1294 printk(KERN_ERR "Could not get %s\n", clk_name);
1295 else
1296 clk_enable(gpio_fclks[i]);
1297 }
1298 }
1299#endif
1300
92105bb7 1301
1a8bfa1e 1302#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1303 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1304 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1305 gpio_bank_count = 2;
1306 gpio_bank = gpio_bank_1510;
1307 }
1308#endif
1309#if defined(CONFIG_ARCH_OMAP16XX)
1310 if (cpu_is_omap16xx()) {
92105bb7 1311 u32 rev;
5e1c5ff4
TL		 1312
1313 gpio_bank_count = 5;
1314 gpio_bank = gpio_bank_1610;
1315 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1316 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1317 (rev >> 4) & 0x0f, rev & 0x0f);
1318 }
1319#endif
1320#ifdef CONFIG_ARCH_OMAP730
1321 if (cpu_is_omap730()) {
1322 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1323 gpio_bank_count = 7;
1324 gpio_bank = gpio_bank_730;
1325 }
92105bb7 1326#endif
56a25641 1327
92105bb7 1328#ifdef CONFIG_ARCH_OMAP24XX
56a25641 1329 if (cpu_is_omap242x()) {
92105bb7
TL		 1330 int rev;
1331
1332 gpio_bank_count = 4;
56a25641
SMK		 1333 gpio_bank = gpio_bank_242x;
1334 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1335 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1336 (rev >> 4) & 0x0f, rev & 0x0f);
1337 }
1338 if (cpu_is_omap243x()) {
1339 int rev;
1340
1341 gpio_bank_count = 5;
1342 gpio_bank = gpio_bank_243x;
92105bb7 1343 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641 1344 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
92105bb7
TL		 1345 (rev >> 4) & 0x0f, rev & 0x0f);
1346 }
5492fb1a
SMK		 1347#endif
1348#ifdef CONFIG_ARCH_OMAP34XX
1349 if (cpu_is_omap34xx()) {
1350 int rev;
1351
1352 gpio_bank_count = OMAP34XX_NR_GPIOS;
1353 gpio_bank = gpio_bank_34xx;
1354 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1355 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1356 (rev >> 4) & 0x0f, rev & 0x0f);
1357 }
5e1c5ff4
TL		 1358#endif
1359 for (i = 0; i < gpio_bank_count; i++) {
1360 int j, gpio_count = 16;
1361
1362 bank = &gpio_bank[i];
1363 bank->reserved_map = 0;
1364 bank->base = IO_ADDRESS(bank->base);
1365 spin_lock_init(&bank->lock);
e5c56ed3 1366 if (bank_is_mpuio(bank))
5e1c5ff4 1367 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
d11ac979 1368 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
5e1c5ff4
TL		 1369 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1370 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1371 }
d11ac979 1372 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
5e1c5ff4
TL		 1373 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1374 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1375 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4 1376 }
d11ac979 1377 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
5e1c5ff4
TL		 1378 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1379 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1380
1381 gpio_count = 32; /* 730 has 32-bit GPIOs */
1382 }
d11ac979 1383
5492fb1a 1384#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1385 if (bank->method == METHOD_GPIO_24XX) {
3ac4fa99
JY		 1386 static const u32 non_wakeup_gpios[] = {
1387 0xe203ffc0, 0x08700040
1388 };
1389
92105bb7
TL		 1390 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1391 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
14f1c3bf
JY		 1392 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1393
1394 /* Initialize interface clock ungated, module enabled */
1395 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
3ac4fa99
JY		 1396 if (i < ARRAY_SIZE(non_wakeup_gpios))
1397 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1398 gpio_count = 32;
1399 }
5e1c5ff4
TL		 1400#endif
1401 for (j = bank->virtual_irq_start;
1402 j < bank->virtual_irq_start + gpio_count; j++) {
58781016 1403 set_irq_chip_data(j, bank);
e5c56ed3 1404 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1405 set_irq_chip(j, &mpuio_irq_chip);
1406 else
1407 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1408 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1409 set_irq_flags(j, IRQF_VALID);
1410 }
1411 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1412 set_irq_data(bank->irq, bank);
1413 }
1414
1415 /* Enable system clock for GPIO module.
1416 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1417 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1418 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1419
14f1c3bf
JY		 1420 /* Enable autoidle for the OCP interface */
1421 if (cpu_is_omap24xx())
1422 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1423 if (cpu_is_omap34xx())
1424 omap_writel(1 << 0, 0x48306814);
d11ac979 1425
5e1c5ff4
TL		 1426 return 0;
1427}
1428
5492fb1a 1429#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1430static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1431{
1432 int i;
1433
5492fb1a 1434 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1435 return 0;
1436
1437 for (i = 0; i < gpio_bank_count; i++) {
1438 struct gpio_bank *bank = &gpio_bank[i];
1439 void __iomem *wake_status;
1440 void __iomem *wake_clear;
1441 void __iomem *wake_set;
1442
1443 switch (bank->method) {
e5c56ed3 1444#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1445 case METHOD_GPIO_1610:
1446 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1447 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1448 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1449 break;
e5c56ed3 1450#endif
5492fb1a 1451#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1452 case METHOD_GPIO_24XX:
1453 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1454 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1455 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1456 break;
e5c56ed3 1457#endif
92105bb7
TL		 1458 default:
1459 continue;
1460 }
1461
1462 spin_lock(&bank->lock);
1463 bank->saved_wakeup = __raw_readl(wake_status);
1464 __raw_writel(0xffffffff, wake_clear);
1465 __raw_writel(bank->suspend_wakeup, wake_set);
1466 spin_unlock(&bank->lock);
1467 }
1468
1469 return 0;
1470}
1471
1472static int omap_gpio_resume(struct sys_device *dev)
1473{
1474 int i;
1475
1476 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1477 return 0;
1478
1479 for (i = 0; i < gpio_bank_count; i++) {
1480 struct gpio_bank *bank = &gpio_bank[i];
1481 void __iomem *wake_clear;
1482 void __iomem *wake_set;
1483
1484 switch (bank->method) {
e5c56ed3 1485#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1486 case METHOD_GPIO_1610:
1487 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1488 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1489 break;
e5c56ed3 1490#endif
5492fb1a 1491#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1492 case METHOD_GPIO_24XX:
0d9356cb
TL		 1493 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1494 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1495 break;
e5c56ed3 1496#endif
92105bb7
TL		 1497 default:
1498 continue;
1499 }
1500
1501 spin_lock(&bank->lock);
1502 __raw_writel(0xffffffff, wake_clear);
1503 __raw_writel(bank->saved_wakeup, wake_set);
1504 spin_unlock(&bank->lock);
1505 }
1506
1507 return 0;
1508}
1509
1510static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1511 .name = "gpio",
92105bb7
TL		 1512 .suspend = omap_gpio_suspend,
1513 .resume = omap_gpio_resume,
1514};
1515
1516static struct sys_device omap_gpio_device = {
1517 .id = 0,
1518 .cls = &omap_gpio_sysclass,
1519};
3ac4fa99
JY		 1520
1521#endif
1522
5492fb1a 1523#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1524
1525static int workaround_enabled;
1526
1527void omap2_gpio_prepare_for_retention(void)
1528{
1529 int i, c = 0;
1530
1531 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1532 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1533 for (i = 0; i < gpio_bank_count; i++) {
1534 struct gpio_bank *bank = &gpio_bank[i];
1535 u32 l1, l2;
1536
1537 if (!(bank->enabled_non_wakeup_gpios))
1538 continue;
5492fb1a 1539#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1540 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1541 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1542 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1543#endif
3ac4fa99
JY		 1544 bank->saved_fallingdetect = l1;
1545 bank->saved_risingdetect = l2;
1546 l1 &= ~bank->enabled_non_wakeup_gpios;
1547 l2 &= ~bank->enabled_non_wakeup_gpios;
5492fb1a 1548#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1549 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1550 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1551#endif
3ac4fa99
JY		 1552 c++;
1553 }
1554 if (!c) {
1555 workaround_enabled = 0;
1556 return;
1557 }
1558 workaround_enabled = 1;
1559}
1560
1561void omap2_gpio_resume_after_retention(void)
1562{
1563 int i;
1564
1565 if (!workaround_enabled)
1566 return;
1567 for (i = 0; i < gpio_bank_count; i++) {
1568 struct gpio_bank *bank = &gpio_bank[i];
1569 u32 l;
1570
1571 if (!(bank->enabled_non_wakeup_gpios))
1572 continue;
5492fb1a 1573#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1574 __raw_writel(bank->saved_fallingdetect,
1575 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1576 __raw_writel(bank->saved_risingdetect,
1577 bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1578#endif
3ac4fa99
JY		 1579 /* Check if any of the non-wakeup interrupt GPIOs have changed
1580 * state. If so, generate an IRQ by software. This is
1581 * horribly racy, but it's the best we can do to work around
1582 * this silicon bug. */
5492fb1a 1583#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 1584 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
5492fb1a 1585#endif
3ac4fa99
JY		 1586 l ^= bank->saved_datain;
1587 l &= bank->non_wakeup_gpios;
1588 if (l) {
1589 u32 old0, old1;
5492fb1a 1590#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1591 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1592 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1593 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1594 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1595 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1596 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
5492fb1a 1597#endif
3ac4fa99
JY		 1598 }
1599 }
1600
1601}
1602
92105bb7
TL		 1603#endif
1604
5e1c5ff4
TL		 1605/*
1606 * This may get called early from board specific init
1a8bfa1e 1607 * for boards that have interrupts routed via FPGA.
5e1c5ff4 1608 */
277d58ef 1609int __init omap_gpio_init(void)
5e1c5ff4
TL		 1610{
1611 if (!initialized)
1612 return _omap_gpio_init();
1613 else
1614 return 0;
1615}
1616
92105bb7
TL		 1617static int __init omap_gpio_sysinit(void)
1618{
1619 int ret = 0;
1620
1621 if (!initialized)
1622 ret = _omap_gpio_init();
1623
11a78b79
DB		 1624 mpuio_init();
1625
5492fb1a
SMK		 1626#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1627 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 1628 if (ret == 0) {
1629 ret = sysdev_class_register(&omap_gpio_sysclass);
1630 if (ret == 0)
1631 ret = sysdev_register(&omap_gpio_device);
1632 }
1633 }
1634#endif
1635
1636 return ret;
1637}
1638
5e1c5ff4
TL		 1639EXPORT_SYMBOL(omap_request_gpio);
1640EXPORT_SYMBOL(omap_free_gpio);
1641EXPORT_SYMBOL(omap_set_gpio_direction);
1642EXPORT_SYMBOL(omap_set_gpio_dataout);
1643EXPORT_SYMBOL(omap_get_gpio_datain);
5e1c5ff4 1644
92105bb7 1645arch_initcall(omap_gpio_sysinit);
b9772a22
DB		 1646
1647
1648#ifdef CONFIG_DEBUG_FS
1649
1650#include <linux/debugfs.h>
1651#include <linux/seq_file.h>
1652
1653static int gpio_is_input(struct gpio_bank *bank, int mask)
1654{
1655 void __iomem *reg = bank->base;
1656
1657 switch (bank->method) {
1658 case METHOD_MPUIO:
1659 reg += OMAP_MPUIO_IO_CNTL;
1660 break;
1661 case METHOD_GPIO_1510:
1662 reg += OMAP1510_GPIO_DIR_CONTROL;
1663 break;
1664 case METHOD_GPIO_1610:
1665 reg += OMAP1610_GPIO_DIRECTION;
1666 break;
1667 case METHOD_GPIO_730:
1668 reg += OMAP730_GPIO_DIR_CONTROL;
1669 break;
1670 case METHOD_GPIO_24XX:
1671 reg += OMAP24XX_GPIO_OE;
1672 break;
1673 }
1674 return __raw_readl(reg) & mask;
1675}
1676
1677
1678static int dbg_gpio_show(struct seq_file *s, void *unused)
1679{
1680 unsigned i, j, gpio;
1681
1682 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1683 struct gpio_bank *bank = gpio_bank + i;
1684 unsigned bankwidth = 16;
1685 u32 mask = 1;
1686
e5c56ed3 1687 if (bank_is_mpuio(bank))
b9772a22 1688 gpio = OMAP_MPUIO(0);
5492fb1a 1689 else if (cpu_class_is_omap2() || cpu_is_omap730())
b9772a22
DB		 1690 bankwidth = 32;
1691
1692 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1693 unsigned irq, value, is_in, irqstat;
1694
1695 if (!(bank->reserved_map & mask))
1696 continue;
1697
1698 irq = bank->virtual_irq_start + j;
1699 value = omap_get_gpio_datain(gpio);
1700 is_in = gpio_is_input(bank, mask);
1701
e5c56ed3 1702 if (bank_is_mpuio(bank))
b9772a22
DB		 1703 seq_printf(s, "MPUIO %2d: ", j);
1704 else
1705 seq_printf(s, "GPIO %3d: ", gpio);
1706 seq_printf(s, "%s %s",
1707 is_in ? "in " : "out",
1708 value ? "hi" : "lo");
1709
1710 irqstat = irq_desc[irq].status;
1711 if (is_in && ((bank->suspend_wakeup & mask)
1712 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1713 char *trigger = NULL;
1714
1715 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1716 case IRQ_TYPE_EDGE_FALLING:
1717 trigger = "falling";
1718 break;
1719 case IRQ_TYPE_EDGE_RISING:
1720 trigger = "rising";
1721 break;
1722 case IRQ_TYPE_EDGE_BOTH:
1723 trigger = "bothedge";
1724 break;
1725 case IRQ_TYPE_LEVEL_LOW:
1726 trigger = "low";
1727 break;
1728 case IRQ_TYPE_LEVEL_HIGH:
1729 trigger = "high";
1730 break;
1731 case IRQ_TYPE_NONE:
1732 trigger = "(unspecified)";
1733 break;
1734 }
1735 seq_printf(s, ", irq-%d %s%s",
1736 irq, trigger,
1737 (bank->suspend_wakeup & mask)
1738 ? " wakeup" : "");
1739 }
1740 seq_printf(s, "\n");
1741 }
1742
e5c56ed3 1743 if (bank_is_mpuio(bank)) {
b9772a22
DB		 1744 seq_printf(s, "\n");
1745 gpio = 0;
1746 }
1747 }
1748 return 0;
1749}
1750
1751static int dbg_gpio_open(struct inode *inode, struct file *file)
1752{
e5c56ed3 1753 return single_open(file, dbg_gpio_show, &inode->i_private);
b9772a22
DB		 1754}
1755
1756static const struct file_operations debug_fops = {
1757 .open = dbg_gpio_open,
1758 .read = seq_read,
1759 .llseek = seq_lseek,
1760 .release = single_release,
1761};
1762
1763static int __init omap_gpio_debuginit(void)
1764{
e5c56ed3
DB		 1765 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1766 NULL, NULL, &debug_fops);
b9772a22
DB		 1767 return 0;
1768}
1769late_initcall(omap_gpio_debuginit);
1770#endif
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