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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/gpio.c | |
3 | * | |
4 | * Support functions for OMAP GPIO | |
5 | * | |
92105bb7 | 6 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 8 | * |
44169075 SS |
9 | * Copyright (C) 2009 Texas Instruments |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
11 | * | |
5e1c5ff4 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
5e1c5ff4 TL |
17 | #include <linux/init.h> |
18 | #include <linux/module.h> | |
5e1c5ff4 | 19 | #include <linux/interrupt.h> |
92105bb7 TL |
20 | #include <linux/sysdev.h> |
21 | #include <linux/err.h> | |
f8ce2547 | 22 | #include <linux/clk.h> |
fced80c7 | 23 | #include <linux/io.h> |
5e1c5ff4 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e1c5ff4 | 26 | #include <asm/irq.h> |
a09e64fb RK |
27 | #include <mach/irqs.h> |
28 | #include <mach/gpio.h> | |
5e1c5ff4 | 29 | #include <asm/mach/irq.h> |
43ffcd9a | 30 | #include <plat/powerdomain.h> |
5e1c5ff4 | 31 | |
5e1c5ff4 TL |
32 | /* |
33 | * OMAP1510 GPIO registers | |
34 | */ | |
9f7065da | 35 | #define OMAP1510_GPIO_BASE 0xfffce000 |
5e1c5ff4 TL |
36 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
37 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | |
38 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | |
39 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | |
40 | #define OMAP1510_GPIO_INT_MASK 0x10 | |
41 | #define OMAP1510_GPIO_INT_STATUS 0x14 | |
42 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | |
43 | ||
44 | #define OMAP1510_IH_GPIO_BASE 64 | |
45 | ||
46 | /* | |
47 | * OMAP1610 specific GPIO registers | |
48 | */ | |
9f7065da TL |
49 | #define OMAP1610_GPIO1_BASE 0xfffbe400 |
50 | #define OMAP1610_GPIO2_BASE 0xfffbec00 | |
51 | #define OMAP1610_GPIO3_BASE 0xfffbb400 | |
52 | #define OMAP1610_GPIO4_BASE 0xfffbbc00 | |
5e1c5ff4 TL |
53 | #define OMAP1610_GPIO_REVISION 0x0000 |
54 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | |
55 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | |
56 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | |
57 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | |
92105bb7 | 58 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 |
5e1c5ff4 TL |
59 | #define OMAP1610_GPIO_DATAIN 0x002c |
60 | #define OMAP1610_GPIO_DATAOUT 0x0030 | |
61 | #define OMAP1610_GPIO_DIRECTION 0x0034 | |
62 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | |
63 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | |
64 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | |
92105bb7 | 65 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 |
5e1c5ff4 TL |
66 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 |
67 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | |
92105bb7 | 68 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 |
5e1c5ff4 TL |
69 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
70 | ||
71 | /* | |
7c006926 | 72 | * OMAP7XX specific GPIO registers |
5e1c5ff4 | 73 | */ |
9f7065da TL |
74 | #define OMAP7XX_GPIO1_BASE 0xfffbc000 |
75 | #define OMAP7XX_GPIO2_BASE 0xfffbc800 | |
76 | #define OMAP7XX_GPIO3_BASE 0xfffbd000 | |
77 | #define OMAP7XX_GPIO4_BASE 0xfffbd800 | |
78 | #define OMAP7XX_GPIO5_BASE 0xfffbe000 | |
79 | #define OMAP7XX_GPIO6_BASE 0xfffbe800 | |
7c006926 AB |
80 | #define OMAP7XX_GPIO_DATA_INPUT 0x00 |
81 | #define OMAP7XX_GPIO_DATA_OUTPUT 0x04 | |
82 | #define OMAP7XX_GPIO_DIR_CONTROL 0x08 | |
83 | #define OMAP7XX_GPIO_INT_CONTROL 0x0c | |
84 | #define OMAP7XX_GPIO_INT_MASK 0x10 | |
85 | #define OMAP7XX_GPIO_INT_STATUS 0x14 | |
5e1c5ff4 | 86 | |
9f7065da | 87 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE |
94113260 | 88 | |
92105bb7 TL |
89 | /* |
90 | * omap24xx specific GPIO registers | |
91 | */ | |
9f7065da TL |
92 | #define OMAP242X_GPIO1_BASE 0x48018000 |
93 | #define OMAP242X_GPIO2_BASE 0x4801a000 | |
94 | #define OMAP242X_GPIO3_BASE 0x4801c000 | |
95 | #define OMAP242X_GPIO4_BASE 0x4801e000 | |
56a25641 | 96 | |
9f7065da TL |
97 | #define OMAP243X_GPIO1_BASE 0x4900C000 |
98 | #define OMAP243X_GPIO2_BASE 0x4900E000 | |
99 | #define OMAP243X_GPIO3_BASE 0x49010000 | |
100 | #define OMAP243X_GPIO4_BASE 0x49012000 | |
101 | #define OMAP243X_GPIO5_BASE 0x480B6000 | |
56a25641 | 102 | |
92105bb7 TL |
103 | #define OMAP24XX_GPIO_REVISION 0x0000 |
104 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | |
105 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | |
106 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | |
bee7930f HD |
107 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
108 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | |
92105bb7 | 109 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c |
723fdb78 | 110 | #define OMAP24XX_GPIO_WAKE_EN 0x0020 |
92105bb7 TL |
111 | #define OMAP24XX_GPIO_CTRL 0x0030 |
112 | #define OMAP24XX_GPIO_OE 0x0034 | |
113 | #define OMAP24XX_GPIO_DATAIN 0x0038 | |
114 | #define OMAP24XX_GPIO_DATAOUT 0x003c | |
115 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | |
116 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | |
117 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | |
118 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | |
5eb3bb9c KH |
119 | #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 |
120 | #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 | |
92105bb7 TL |
121 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 |
122 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | |
123 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | |
124 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | |
125 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | |
126 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | |
127 | ||
78a1a6d3 SR |
128 | #define OMAP4_GPIO_REVISION 0x0000 |
129 | #define OMAP4_GPIO_SYSCONFIG 0x0010 | |
130 | #define OMAP4_GPIO_EOI 0x0020 | |
131 | #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 | |
132 | #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 | |
133 | #define OMAP4_GPIO_IRQSTATUS0 0x002c | |
134 | #define OMAP4_GPIO_IRQSTATUS1 0x0030 | |
135 | #define OMAP4_GPIO_IRQSTATUSSET0 0x0034 | |
136 | #define OMAP4_GPIO_IRQSTATUSSET1 0x0038 | |
137 | #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c | |
138 | #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 | |
139 | #define OMAP4_GPIO_IRQWAKEN0 0x0044 | |
140 | #define OMAP4_GPIO_IRQWAKEN1 0x0048 | |
9f096868 C |
141 | #define OMAP4_GPIO_SYSSTATUS 0x0114 |
142 | #define OMAP4_GPIO_IRQENABLE1 0x011c | |
143 | #define OMAP4_GPIO_WAKE_EN 0x0120 | |
144 | #define OMAP4_GPIO_IRQSTATUS2 0x0128 | |
145 | #define OMAP4_GPIO_IRQENABLE2 0x012c | |
78a1a6d3 SR |
146 | #define OMAP4_GPIO_CTRL 0x0130 |
147 | #define OMAP4_GPIO_OE 0x0134 | |
148 | #define OMAP4_GPIO_DATAIN 0x0138 | |
149 | #define OMAP4_GPIO_DATAOUT 0x013c | |
150 | #define OMAP4_GPIO_LEVELDETECT0 0x0140 | |
151 | #define OMAP4_GPIO_LEVELDETECT1 0x0144 | |
152 | #define OMAP4_GPIO_RISINGDETECT 0x0148 | |
153 | #define OMAP4_GPIO_FALLINGDETECT 0x014c | |
154 | #define OMAP4_GPIO_DEBOUNCENABLE 0x0150 | |
155 | #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 | |
9f096868 C |
156 | #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160 |
157 | #define OMAP4_GPIO_SETIRQENABLE1 0x0164 | |
158 | #define OMAP4_GPIO_CLEARWKUENA 0x0180 | |
159 | #define OMAP4_GPIO_SETWKUENA 0x0184 | |
78a1a6d3 SR |
160 | #define OMAP4_GPIO_CLEARDATAOUT 0x0190 |
161 | #define OMAP4_GPIO_SETDATAOUT 0x0194 | |
5492fb1a SMK |
162 | /* |
163 | * omap34xx specific GPIO registers | |
164 | */ | |
165 | ||
9f7065da TL |
166 | #define OMAP34XX_GPIO1_BASE 0x48310000 |
167 | #define OMAP34XX_GPIO2_BASE 0x49050000 | |
168 | #define OMAP34XX_GPIO3_BASE 0x49052000 | |
169 | #define OMAP34XX_GPIO4_BASE 0x49054000 | |
170 | #define OMAP34XX_GPIO5_BASE 0x49056000 | |
171 | #define OMAP34XX_GPIO6_BASE 0x49058000 | |
5492fb1a | 172 | |
44169075 SS |
173 | /* |
174 | * OMAP44XX specific GPIO registers | |
175 | */ | |
9f7065da TL |
176 | #define OMAP44XX_GPIO1_BASE 0x4a310000 |
177 | #define OMAP44XX_GPIO2_BASE 0x48055000 | |
178 | #define OMAP44XX_GPIO3_BASE 0x48057000 | |
179 | #define OMAP44XX_GPIO4_BASE 0x48059000 | |
180 | #define OMAP44XX_GPIO5_BASE 0x4805B000 | |
181 | #define OMAP44XX_GPIO6_BASE 0x4805D000 | |
5492fb1a | 182 | |
5e1c5ff4 | 183 | struct gpio_bank { |
9f7065da | 184 | unsigned long pbase; |
92105bb7 | 185 | void __iomem *base; |
5e1c5ff4 TL |
186 | u16 irq; |
187 | u16 virtual_irq_start; | |
92105bb7 | 188 | int method; |
140455fa | 189 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 TL |
190 | u32 suspend_wakeup; |
191 | u32 saved_wakeup; | |
3ac4fa99 | 192 | #endif |
3ac4fa99 JY |
193 | u32 non_wakeup_gpios; |
194 | u32 enabled_non_wakeup_gpios; | |
195 | ||
196 | u32 saved_datain; | |
197 | u32 saved_fallingdetect; | |
198 | u32 saved_risingdetect; | |
b144ff6f | 199 | u32 level_mask; |
4318f36b | 200 | u32 toggle_mask; |
5e1c5ff4 | 201 | spinlock_t lock; |
52e31344 | 202 | struct gpio_chip chip; |
89db9482 | 203 | struct clk *dbck; |
058af1ea | 204 | u32 mod_usage; |
8865b9b6 | 205 | u32 dbck_enable_mask; |
5e1c5ff4 TL |
206 | }; |
207 | ||
92105bb7 | 208 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 209 | static struct gpio_bank gpio_bank_1610[5] = { |
9f7065da TL |
210 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, |
211 | METHOD_MPUIO }, | |
212 | { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | |
213 | METHOD_GPIO_1610 }, | |
214 | { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, | |
215 | METHOD_GPIO_1610 }, | |
216 | { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, | |
217 | METHOD_GPIO_1610 }, | |
218 | { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, | |
219 | METHOD_GPIO_1610 }, | |
5e1c5ff4 TL |
220 | }; |
221 | #endif | |
222 | ||
1a8bfa1e | 223 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 224 | static struct gpio_bank gpio_bank_1510[2] = { |
9f7065da TL |
225 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, |
226 | METHOD_MPUIO }, | |
227 | { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | |
228 | METHOD_GPIO_1510 } | |
5e1c5ff4 TL |
229 | }; |
230 | #endif | |
231 | ||
b718aa81 | 232 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 | 233 | static struct gpio_bank gpio_bank_7xx[7] = { |
9f7065da TL |
234 | { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE, |
235 | METHOD_MPUIO }, | |
236 | { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, | |
237 | METHOD_GPIO_7XX }, | |
238 | { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
239 | METHOD_GPIO_7XX }, | |
240 | { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
241 | METHOD_GPIO_7XX }, | |
242 | { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
243 | METHOD_GPIO_7XX }, | |
244 | { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
245 | METHOD_GPIO_7XX }, | |
246 | { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, | |
247 | METHOD_GPIO_7XX }, | |
5e1c5ff4 TL |
248 | }; |
249 | #endif | |
250 | ||
088ef950 | 251 | #ifdef CONFIG_ARCH_OMAP2 |
56a25641 SMK |
252 | |
253 | static struct gpio_bank gpio_bank_242x[4] = { | |
9f7065da TL |
254 | { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
255 | METHOD_GPIO_24XX }, | |
256 | { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
257 | METHOD_GPIO_24XX }, | |
258 | { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
259 | METHOD_GPIO_24XX }, | |
260 | { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
261 | METHOD_GPIO_24XX }, | |
92105bb7 | 262 | }; |
56a25641 SMK |
263 | |
264 | static struct gpio_bank gpio_bank_243x[5] = { | |
9f7065da TL |
265 | { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
266 | METHOD_GPIO_24XX }, | |
267 | { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
268 | METHOD_GPIO_24XX }, | |
269 | { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
270 | METHOD_GPIO_24XX }, | |
271 | { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
272 | METHOD_GPIO_24XX }, | |
273 | { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
274 | METHOD_GPIO_24XX }, | |
56a25641 SMK |
275 | }; |
276 | ||
92105bb7 TL |
277 | #endif |
278 | ||
a8eb7ca0 | 279 | #ifdef CONFIG_ARCH_OMAP3 |
5492fb1a | 280 | static struct gpio_bank gpio_bank_34xx[6] = { |
9f7065da TL |
281 | { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, |
282 | METHOD_GPIO_24XX }, | |
283 | { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
284 | METHOD_GPIO_24XX }, | |
285 | { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
286 | METHOD_GPIO_24XX }, | |
287 | { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
288 | METHOD_GPIO_24XX }, | |
289 | { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
290 | METHOD_GPIO_24XX }, | |
291 | { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, | |
292 | METHOD_GPIO_24XX }, | |
5492fb1a SMK |
293 | }; |
294 | ||
40c670f0 RN |
295 | struct omap3_gpio_regs { |
296 | u32 sysconfig; | |
297 | u32 irqenable1; | |
298 | u32 irqenable2; | |
299 | u32 wake_en; | |
300 | u32 ctrl; | |
301 | u32 oe; | |
302 | u32 leveldetect0; | |
303 | u32 leveldetect1; | |
304 | u32 risingdetect; | |
305 | u32 fallingdetect; | |
306 | u32 dataout; | |
5492fb1a SMK |
307 | }; |
308 | ||
40c670f0 | 309 | static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; |
5492fb1a SMK |
310 | #endif |
311 | ||
44169075 SS |
312 | #ifdef CONFIG_ARCH_OMAP4 |
313 | static struct gpio_bank gpio_bank_44xx[6] = { | |
5772ca7d | 314 | { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE, |
3f1686a9 | 315 | METHOD_GPIO_44XX }, |
5772ca7d | 316 | { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32, |
3f1686a9 | 317 | METHOD_GPIO_44XX }, |
5772ca7d | 318 | { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64, |
3f1686a9 | 319 | METHOD_GPIO_44XX }, |
5772ca7d | 320 | { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96, |
3f1686a9 | 321 | METHOD_GPIO_44XX }, |
5772ca7d | 322 | { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128, |
3f1686a9 | 323 | METHOD_GPIO_44XX }, |
5772ca7d | 324 | { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160, |
3f1686a9 | 325 | METHOD_GPIO_44XX }, |
44169075 SS |
326 | }; |
327 | ||
328 | #endif | |
329 | ||
5e1c5ff4 | 330 | static struct gpio_bank *gpio_bank; |
c95d10bc VC |
331 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ |
332 | int gpio_bank_count; | |
5e1c5ff4 TL |
333 | |
334 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
335 | { | |
6e60e79a | 336 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
337 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
338 | return &gpio_bank[0]; | |
339 | return &gpio_bank[1]; | |
340 | } | |
5e1c5ff4 TL |
341 | if (cpu_is_omap16xx()) { |
342 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
343 | return &gpio_bank[0]; | |
344 | return &gpio_bank[1 + (gpio >> 4)]; | |
345 | } | |
56739a69 | 346 | if (cpu_is_omap7xx()) { |
5e1c5ff4 TL |
347 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
348 | return &gpio_bank[0]; | |
349 | return &gpio_bank[1 + (gpio >> 5)]; | |
350 | } | |
92105bb7 TL |
351 | if (cpu_is_omap24xx()) |
352 | return &gpio_bank[gpio >> 5]; | |
44169075 | 353 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 354 | return &gpio_bank[gpio >> 5]; |
e031ab23 DB |
355 | BUG(); |
356 | return NULL; | |
5e1c5ff4 TL |
357 | } |
358 | ||
359 | static inline int get_gpio_index(int gpio) | |
360 | { | |
56739a69 | 361 | if (cpu_is_omap7xx()) |
5e1c5ff4 | 362 | return gpio & 0x1f; |
92105bb7 TL |
363 | if (cpu_is_omap24xx()) |
364 | return gpio & 0x1f; | |
44169075 | 365 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 366 | return gpio & 0x1f; |
92105bb7 | 367 | return gpio & 0x0f; |
5e1c5ff4 TL |
368 | } |
369 | ||
370 | static inline int gpio_valid(int gpio) | |
371 | { | |
372 | if (gpio < 0) | |
373 | return -1; | |
d11ac979 | 374 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 375 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
376 | return -1; |
377 | return 0; | |
378 | } | |
6e60e79a | 379 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 380 | return 0; |
5e1c5ff4 TL |
381 | if ((cpu_is_omap16xx()) && gpio < 64) |
382 | return 0; | |
56739a69 | 383 | if (cpu_is_omap7xx() && gpio < 192) |
5e1c5ff4 | 384 | return 0; |
25d6f630 TL |
385 | if (cpu_is_omap2420() && gpio < 128) |
386 | return 0; | |
387 | if (cpu_is_omap2430() && gpio < 160) | |
92105bb7 | 388 | return 0; |
44169075 | 389 | if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) |
5492fb1a | 390 | return 0; |
5e1c5ff4 TL |
391 | return -1; |
392 | } | |
393 | ||
394 | static int check_gpio(int gpio) | |
395 | { | |
d32b20fc | 396 | if (unlikely(gpio_valid(gpio) < 0)) { |
5e1c5ff4 TL |
397 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); |
398 | dump_stack(); | |
399 | return -1; | |
400 | } | |
401 | return 0; | |
402 | } | |
403 | ||
404 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
405 | { | |
92105bb7 | 406 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
407 | u32 l; |
408 | ||
409 | switch (bank->method) { | |
e5c56ed3 | 410 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
411 | case METHOD_MPUIO: |
412 | reg += OMAP_MPUIO_IO_CNTL; | |
413 | break; | |
e5c56ed3 DB |
414 | #endif |
415 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
416 | case METHOD_GPIO_1510: |
417 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
418 | break; | |
e5c56ed3 DB |
419 | #endif |
420 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
421 | case METHOD_GPIO_1610: |
422 | reg += OMAP1610_GPIO_DIRECTION; | |
423 | break; | |
e5c56ed3 | 424 | #endif |
b718aa81 | 425 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
426 | case METHOD_GPIO_7XX: |
427 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
56739a69 ZM |
428 | break; |
429 | #endif | |
a8eb7ca0 | 430 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
431 | case METHOD_GPIO_24XX: |
432 | reg += OMAP24XX_GPIO_OE; | |
433 | break; | |
78a1a6d3 SR |
434 | #endif |
435 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 436 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
437 | reg += OMAP4_GPIO_OE; |
438 | break; | |
e5c56ed3 DB |
439 | #endif |
440 | default: | |
441 | WARN_ON(1); | |
442 | return; | |
5e1c5ff4 TL |
443 | } |
444 | l = __raw_readl(reg); | |
445 | if (is_input) | |
446 | l |= 1 << gpio; | |
447 | else | |
448 | l &= ~(1 << gpio); | |
449 | __raw_writel(l, reg); | |
450 | } | |
451 | ||
5e1c5ff4 TL |
452 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) |
453 | { | |
92105bb7 | 454 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
455 | u32 l = 0; |
456 | ||
457 | switch (bank->method) { | |
e5c56ed3 | 458 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
459 | case METHOD_MPUIO: |
460 | reg += OMAP_MPUIO_OUTPUT; | |
461 | l = __raw_readl(reg); | |
462 | if (enable) | |
463 | l |= 1 << gpio; | |
464 | else | |
465 | l &= ~(1 << gpio); | |
466 | break; | |
e5c56ed3 DB |
467 | #endif |
468 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
469 | case METHOD_GPIO_1510: |
470 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
471 | l = __raw_readl(reg); | |
472 | if (enable) | |
473 | l |= 1 << gpio; | |
474 | else | |
475 | l &= ~(1 << gpio); | |
476 | break; | |
e5c56ed3 DB |
477 | #endif |
478 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
479 | case METHOD_GPIO_1610: |
480 | if (enable) | |
481 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
482 | else | |
483 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
484 | l = 1 << gpio; | |
485 | break; | |
e5c56ed3 | 486 | #endif |
b718aa81 | 487 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
488 | case METHOD_GPIO_7XX: |
489 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
56739a69 ZM |
490 | l = __raw_readl(reg); |
491 | if (enable) | |
492 | l |= 1 << gpio; | |
493 | else | |
494 | l &= ~(1 << gpio); | |
495 | break; | |
496 | #endif | |
a8eb7ca0 | 497 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
498 | case METHOD_GPIO_24XX: |
499 | if (enable) | |
500 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
501 | else | |
502 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
503 | l = 1 << gpio; | |
504 | break; | |
78a1a6d3 SR |
505 | #endif |
506 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 507 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
508 | if (enable) |
509 | reg += OMAP4_GPIO_SETDATAOUT; | |
510 | else | |
511 | reg += OMAP4_GPIO_CLEARDATAOUT; | |
512 | l = 1 << gpio; | |
513 | break; | |
e5c56ed3 | 514 | #endif |
5e1c5ff4 | 515 | default: |
e5c56ed3 | 516 | WARN_ON(1); |
5e1c5ff4 TL |
517 | return; |
518 | } | |
519 | __raw_writel(l, reg); | |
520 | } | |
521 | ||
b37c45b8 | 522 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
5e1c5ff4 | 523 | { |
92105bb7 | 524 | void __iomem *reg; |
5e1c5ff4 TL |
525 | |
526 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 527 | return -EINVAL; |
5e1c5ff4 TL |
528 | reg = bank->base; |
529 | switch (bank->method) { | |
e5c56ed3 | 530 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
531 | case METHOD_MPUIO: |
532 | reg += OMAP_MPUIO_INPUT_LATCH; | |
533 | break; | |
e5c56ed3 DB |
534 | #endif |
535 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
536 | case METHOD_GPIO_1510: |
537 | reg += OMAP1510_GPIO_DATA_INPUT; | |
538 | break; | |
e5c56ed3 DB |
539 | #endif |
540 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
541 | case METHOD_GPIO_1610: |
542 | reg += OMAP1610_GPIO_DATAIN; | |
543 | break; | |
e5c56ed3 | 544 | #endif |
b718aa81 | 545 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
546 | case METHOD_GPIO_7XX: |
547 | reg += OMAP7XX_GPIO_DATA_INPUT; | |
56739a69 ZM |
548 | break; |
549 | #endif | |
a8eb7ca0 | 550 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
551 | case METHOD_GPIO_24XX: |
552 | reg += OMAP24XX_GPIO_DATAIN; | |
553 | break; | |
78a1a6d3 SR |
554 | #endif |
555 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 556 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
557 | reg += OMAP4_GPIO_DATAIN; |
558 | break; | |
e5c56ed3 | 559 | #endif |
5e1c5ff4 | 560 | default: |
e5c56ed3 | 561 | return -EINVAL; |
5e1c5ff4 | 562 | } |
92105bb7 TL |
563 | return (__raw_readl(reg) |
564 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
565 | } |
566 | ||
b37c45b8 RQ |
567 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
568 | { | |
569 | void __iomem *reg; | |
570 | ||
571 | if (check_gpio(gpio) < 0) | |
572 | return -EINVAL; | |
573 | reg = bank->base; | |
574 | ||
575 | switch (bank->method) { | |
576 | #ifdef CONFIG_ARCH_OMAP1 | |
577 | case METHOD_MPUIO: | |
578 | reg += OMAP_MPUIO_OUTPUT; | |
579 | break; | |
580 | #endif | |
581 | #ifdef CONFIG_ARCH_OMAP15XX | |
582 | case METHOD_GPIO_1510: | |
583 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
584 | break; | |
585 | #endif | |
586 | #ifdef CONFIG_ARCH_OMAP16XX | |
587 | case METHOD_GPIO_1610: | |
588 | reg += OMAP1610_GPIO_DATAOUT; | |
589 | break; | |
590 | #endif | |
b718aa81 | 591 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
592 | case METHOD_GPIO_7XX: |
593 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
b37c45b8 RQ |
594 | break; |
595 | #endif | |
9f096868 | 596 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
b37c45b8 RQ |
597 | case METHOD_GPIO_24XX: |
598 | reg += OMAP24XX_GPIO_DATAOUT; | |
599 | break; | |
9f096868 C |
600 | #endif |
601 | #ifdef CONFIG_ARCH_OMAP4 | |
602 | case METHOD_GPIO_44XX: | |
603 | reg += OMAP4_GPIO_DATAOUT; | |
604 | break; | |
b37c45b8 RQ |
605 | #endif |
606 | default: | |
607 | return -EINVAL; | |
608 | } | |
609 | ||
610 | return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; | |
611 | } | |
612 | ||
92105bb7 TL |
613 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
614 | do { \ | |
615 | int l = __raw_readl(base + reg); \ | |
616 | if (set) l |= bit_mask; \ | |
617 | else l &= ~bit_mask; \ | |
618 | __raw_writel(l, base + reg); \ | |
619 | } while(0) | |
620 | ||
168ef3d9 FB |
621 | /** |
622 | * _set_gpio_debounce - low level gpio debounce time | |
623 | * @bank: the gpio bank we're acting upon | |
624 | * @gpio: the gpio number on this @gpio | |
625 | * @debounce: debounce time to use | |
626 | * | |
627 | * OMAP's debounce time is in 31us steps so we need | |
628 | * to convert and round up to the closest unit. | |
629 | */ | |
630 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
631 | unsigned debounce) | |
632 | { | |
633 | void __iomem *reg = bank->base; | |
634 | u32 val; | |
635 | u32 l; | |
636 | ||
637 | if (debounce < 32) | |
638 | debounce = 0x01; | |
639 | else if (debounce > 7936) | |
640 | debounce = 0xff; | |
641 | else | |
642 | debounce = (debounce / 0x1f) - 1; | |
643 | ||
644 | l = 1 << get_gpio_index(gpio); | |
645 | ||
646 | if (cpu_is_omap44xx()) | |
647 | reg += OMAP4_GPIO_DEBOUNCINGTIME; | |
648 | else | |
649 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
650 | ||
651 | __raw_writel(debounce, reg); | |
652 | ||
653 | reg = bank->base; | |
654 | if (cpu_is_omap44xx()) | |
655 | reg += OMAP4_GPIO_DEBOUNCENABLE; | |
656 | else | |
657 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | |
658 | ||
659 | val = __raw_readl(reg); | |
660 | ||
661 | if (debounce) { | |
662 | val |= l; | |
663 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) | |
664 | clk_enable(bank->dbck); | |
665 | } else { | |
666 | val &= ~l; | |
667 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) | |
668 | clk_disable(bank->dbck); | |
669 | } | |
f7ec0b0b | 670 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
671 | |
672 | __raw_writel(val, reg); | |
673 | } | |
674 | ||
140455fa | 675 | #ifdef CONFIG_ARCH_OMAP2PLUS |
5eb3bb9c KH |
676 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
677 | int trigger) | |
5e1c5ff4 | 678 | { |
3ac4fa99 | 679 | void __iomem *base = bank->base; |
92105bb7 | 680 | u32 gpio_bit = 1 << gpio; |
78a1a6d3 | 681 | u32 val; |
92105bb7 | 682 | |
78a1a6d3 SR |
683 | if (cpu_is_omap44xx()) { |
684 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit, | |
685 | trigger & IRQ_TYPE_LEVEL_LOW); | |
686 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit, | |
687 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
688 | MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit, | |
689 | trigger & IRQ_TYPE_EDGE_RISING); | |
690 | MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit, | |
691 | trigger & IRQ_TYPE_EDGE_FALLING); | |
692 | } else { | |
693 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
694 | trigger & IRQ_TYPE_LEVEL_LOW); | |
695 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, | |
696 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
697 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, | |
698 | trigger & IRQ_TYPE_EDGE_RISING); | |
699 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, | |
700 | trigger & IRQ_TYPE_EDGE_FALLING); | |
701 | } | |
3ac4fa99 | 702 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
78a1a6d3 SR |
703 | if (cpu_is_omap44xx()) { |
704 | if (trigger != 0) | |
705 | __raw_writel(1 << gpio, bank->base+ | |
706 | OMAP4_GPIO_IRQWAKEN0); | |
707 | else { | |
708 | val = __raw_readl(bank->base + | |
709 | OMAP4_GPIO_IRQWAKEN0); | |
710 | __raw_writel(val & (~(1 << gpio)), bank->base + | |
711 | OMAP4_GPIO_IRQWAKEN0); | |
712 | } | |
713 | } else { | |
699117a6 CW |
714 | /* |
715 | * GPIO wakeup request can only be generated on edge | |
716 | * transitions | |
717 | */ | |
718 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
78a1a6d3 | 719 | __raw_writel(1 << gpio, bank->base |
5eb3bb9c | 720 | + OMAP24XX_GPIO_SETWKUENA); |
78a1a6d3 SR |
721 | else |
722 | __raw_writel(1 << gpio, bank->base | |
5eb3bb9c | 723 | + OMAP24XX_GPIO_CLEARWKUENA); |
78a1a6d3 | 724 | } |
a118b5f3 TK |
725 | } |
726 | /* This part needs to be executed always for OMAP34xx */ | |
727 | if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) { | |
699117a6 CW |
728 | /* |
729 | * Log the edge gpio and manually trigger the IRQ | |
730 | * after resume if the input level changes | |
731 | * to avoid irq lost during PER RET/OFF mode | |
732 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
733 | */ | |
734 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
735 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
736 | else | |
737 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
738 | } | |
5eb3bb9c | 739 | |
78a1a6d3 SR |
740 | if (cpu_is_omap44xx()) { |
741 | bank->level_mask = | |
742 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | | |
743 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); | |
744 | } else { | |
745 | bank->level_mask = | |
746 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
747 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
748 | } | |
92105bb7 | 749 | } |
3ac4fa99 | 750 | #endif |
92105bb7 | 751 | |
9198bcd3 | 752 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
753 | /* |
754 | * This only applies to chips that can't do both rising and falling edge | |
755 | * detection at once. For all other chips, this function is a noop. | |
756 | */ | |
757 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
758 | { | |
759 | void __iomem *reg = bank->base; | |
760 | u32 l = 0; | |
761 | ||
762 | switch (bank->method) { | |
4318f36b CM |
763 | case METHOD_MPUIO: |
764 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
765 | break; | |
4318f36b CM |
766 | #ifdef CONFIG_ARCH_OMAP15XX |
767 | case METHOD_GPIO_1510: | |
768 | reg += OMAP1510_GPIO_INT_CONTROL; | |
769 | break; | |
770 | #endif | |
771 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | |
772 | case METHOD_GPIO_7XX: | |
773 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
774 | break; | |
775 | #endif | |
776 | default: | |
777 | return; | |
778 | } | |
779 | ||
780 | l = __raw_readl(reg); | |
781 | if ((l >> gpio) & 1) | |
782 | l &= ~(1 << gpio); | |
783 | else | |
784 | l |= 1 << gpio; | |
785 | ||
786 | __raw_writel(l, reg); | |
787 | } | |
9198bcd3 | 788 | #endif |
4318f36b | 789 | |
92105bb7 TL |
790 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
791 | { | |
792 | void __iomem *reg = bank->base; | |
793 | u32 l = 0; | |
5e1c5ff4 TL |
794 | |
795 | switch (bank->method) { | |
e5c56ed3 | 796 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
797 | case METHOD_MPUIO: |
798 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
799 | l = __raw_readl(reg); | |
29501577 | 800 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 801 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 802 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 803 | l |= 1 << gpio; |
6cab4860 | 804 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 805 | l &= ~(1 << gpio); |
92105bb7 TL |
806 | else |
807 | goto bad; | |
5e1c5ff4 | 808 | break; |
e5c56ed3 DB |
809 | #endif |
810 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
811 | case METHOD_GPIO_1510: |
812 | reg += OMAP1510_GPIO_INT_CONTROL; | |
813 | l = __raw_readl(reg); | |
29501577 | 814 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 815 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 816 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 817 | l |= 1 << gpio; |
6cab4860 | 818 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 819 | l &= ~(1 << gpio); |
92105bb7 TL |
820 | else |
821 | goto bad; | |
5e1c5ff4 | 822 | break; |
e5c56ed3 | 823 | #endif |
3ac4fa99 | 824 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 825 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
826 | if (gpio & 0x08) |
827 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
828 | else | |
829 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
830 | gpio &= 0x07; | |
831 | l = __raw_readl(reg); | |
832 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 833 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 834 | l |= 2 << (gpio << 1); |
6cab4860 | 835 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 836 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
837 | if (trigger) |
838 | /* Enable wake-up during idle for dynamic tick */ | |
839 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
840 | else | |
841 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 842 | break; |
3ac4fa99 | 843 | #endif |
b718aa81 | 844 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
845 | case METHOD_GPIO_7XX: |
846 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
56739a69 | 847 | l = __raw_readl(reg); |
29501577 | 848 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 849 | bank->toggle_mask |= 1 << gpio; |
56739a69 ZM |
850 | if (trigger & IRQ_TYPE_EDGE_RISING) |
851 | l |= 1 << gpio; | |
852 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | |
853 | l &= ~(1 << gpio); | |
854 | else | |
855 | goto bad; | |
856 | break; | |
857 | #endif | |
140455fa | 858 | #ifdef CONFIG_ARCH_OMAP2PLUS |
92105bb7 | 859 | case METHOD_GPIO_24XX: |
3f1686a9 | 860 | case METHOD_GPIO_44XX: |
3ac4fa99 | 861 | set_24xx_gpio_triggering(bank, gpio, trigger); |
5e1c5ff4 | 862 | break; |
3ac4fa99 | 863 | #endif |
5e1c5ff4 | 864 | default: |
92105bb7 | 865 | goto bad; |
5e1c5ff4 | 866 | } |
92105bb7 TL |
867 | __raw_writel(l, reg); |
868 | return 0; | |
869 | bad: | |
870 | return -EINVAL; | |
5e1c5ff4 TL |
871 | } |
872 | ||
92105bb7 | 873 | static int gpio_irq_type(unsigned irq, unsigned type) |
5e1c5ff4 TL |
874 | { |
875 | struct gpio_bank *bank; | |
92105bb7 TL |
876 | unsigned gpio; |
877 | int retval; | |
a6472533 | 878 | unsigned long flags; |
92105bb7 | 879 | |
5492fb1a | 880 | if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) |
92105bb7 TL |
881 | gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); |
882 | else | |
883 | gpio = irq - IH_GPIO_BASE; | |
5e1c5ff4 TL |
884 | |
885 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
886 | return -EINVAL; |
887 | ||
e5c56ed3 | 888 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 889 | return -EINVAL; |
e5c56ed3 DB |
890 | |
891 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 892 | if (!cpu_class_is_omap2() |
e5c56ed3 | 893 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
894 | return -EINVAL; |
895 | ||
58781016 | 896 | bank = get_irq_chip_data(irq); |
a6472533 | 897 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 898 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
b9772a22 DB |
899 | if (retval == 0) { |
900 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
901 | irq_desc[irq].status |= type; | |
902 | } | |
a6472533 | 903 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
904 | |
905 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
906 | __set_irq_handler_unlocked(irq, handle_level_irq); | |
907 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
908 | __set_irq_handler_unlocked(irq, handle_edge_irq); | |
909 | ||
92105bb7 | 910 | return retval; |
5e1c5ff4 TL |
911 | } |
912 | ||
913 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
914 | { | |
92105bb7 | 915 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
916 | |
917 | switch (bank->method) { | |
e5c56ed3 | 918 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
919 | case METHOD_MPUIO: |
920 | /* MPUIO irqstatus is reset by reading the status register, | |
921 | * so do nothing here */ | |
922 | return; | |
e5c56ed3 DB |
923 | #endif |
924 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
925 | case METHOD_GPIO_1510: |
926 | reg += OMAP1510_GPIO_INT_STATUS; | |
927 | break; | |
e5c56ed3 DB |
928 | #endif |
929 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
930 | case METHOD_GPIO_1610: |
931 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
932 | break; | |
e5c56ed3 | 933 | #endif |
b718aa81 | 934 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
935 | case METHOD_GPIO_7XX: |
936 | reg += OMAP7XX_GPIO_INT_STATUS; | |
56739a69 ZM |
937 | break; |
938 | #endif | |
a8eb7ca0 | 939 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
940 | case METHOD_GPIO_24XX: |
941 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
942 | break; | |
78a1a6d3 SR |
943 | #endif |
944 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 945 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
946 | reg += OMAP4_GPIO_IRQSTATUS0; |
947 | break; | |
e5c56ed3 | 948 | #endif |
5e1c5ff4 | 949 | default: |
e5c56ed3 | 950 | WARN_ON(1); |
5e1c5ff4 TL |
951 | return; |
952 | } | |
953 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
954 | |
955 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
3f1686a9 TL |
956 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
957 | reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; | |
958 | else if (cpu_is_omap44xx()) | |
959 | reg = bank->base + OMAP4_GPIO_IRQSTATUS1; | |
960 | ||
78a1a6d3 | 961 | if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
bedfd154 RQ |
962 | __raw_writel(gpio_mask, reg); |
963 | ||
964 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
965 | __raw_readl(reg); | |
78a1a6d3 | 966 | } |
5e1c5ff4 TL |
967 | } |
968 | ||
969 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
970 | { | |
971 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
972 | } | |
973 | ||
ea6dedd7 ID |
974 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
975 | { | |
976 | void __iomem *reg = bank->base; | |
99c47707 ID |
977 | int inv = 0; |
978 | u32 l; | |
979 | u32 mask; | |
ea6dedd7 ID |
980 | |
981 | switch (bank->method) { | |
e5c56ed3 | 982 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 ID |
983 | case METHOD_MPUIO: |
984 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
99c47707 ID |
985 | mask = 0xffff; |
986 | inv = 1; | |
ea6dedd7 | 987 | break; |
e5c56ed3 DB |
988 | #endif |
989 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
990 | case METHOD_GPIO_1510: |
991 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
992 | mask = 0xffff; |
993 | inv = 1; | |
ea6dedd7 | 994 | break; |
e5c56ed3 DB |
995 | #endif |
996 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
997 | case METHOD_GPIO_1610: |
998 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 999 | mask = 0xffff; |
ea6dedd7 | 1000 | break; |
e5c56ed3 | 1001 | #endif |
b718aa81 | 1002 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1003 | case METHOD_GPIO_7XX: |
1004 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
1005 | mask = 0xffffffff; |
1006 | inv = 1; | |
1007 | break; | |
1008 | #endif | |
a8eb7ca0 | 1009 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
ea6dedd7 ID |
1010 | case METHOD_GPIO_24XX: |
1011 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 1012 | mask = 0xffffffff; |
ea6dedd7 | 1013 | break; |
78a1a6d3 SR |
1014 | #endif |
1015 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 1016 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1017 | reg += OMAP4_GPIO_IRQSTATUSSET0; |
1018 | mask = 0xffffffff; | |
1019 | break; | |
e5c56ed3 | 1020 | #endif |
ea6dedd7 | 1021 | default: |
e5c56ed3 | 1022 | WARN_ON(1); |
ea6dedd7 ID |
1023 | return 0; |
1024 | } | |
1025 | ||
99c47707 ID |
1026 | l = __raw_readl(reg); |
1027 | if (inv) | |
1028 | l = ~l; | |
1029 | l &= mask; | |
1030 | return l; | |
ea6dedd7 ID |
1031 | } |
1032 | ||
5e1c5ff4 TL |
1033 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
1034 | { | |
92105bb7 | 1035 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
1036 | u32 l; |
1037 | ||
1038 | switch (bank->method) { | |
e5c56ed3 | 1039 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
1040 | case METHOD_MPUIO: |
1041 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
1042 | l = __raw_readl(reg); | |
1043 | if (enable) | |
1044 | l &= ~(gpio_mask); | |
1045 | else | |
1046 | l |= gpio_mask; | |
1047 | break; | |
e5c56ed3 DB |
1048 | #endif |
1049 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
1050 | case METHOD_GPIO_1510: |
1051 | reg += OMAP1510_GPIO_INT_MASK; | |
1052 | l = __raw_readl(reg); | |
1053 | if (enable) | |
1054 | l &= ~(gpio_mask); | |
1055 | else | |
1056 | l |= gpio_mask; | |
1057 | break; | |
e5c56ed3 DB |
1058 | #endif |
1059 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
1060 | case METHOD_GPIO_1610: |
1061 | if (enable) | |
1062 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
1063 | else | |
1064 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
1065 | l = gpio_mask; | |
1066 | break; | |
e5c56ed3 | 1067 | #endif |
b718aa81 | 1068 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1069 | case METHOD_GPIO_7XX: |
1070 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
1071 | l = __raw_readl(reg); |
1072 | if (enable) | |
1073 | l &= ~(gpio_mask); | |
1074 | else | |
1075 | l |= gpio_mask; | |
1076 | break; | |
1077 | #endif | |
a8eb7ca0 | 1078 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
1079 | case METHOD_GPIO_24XX: |
1080 | if (enable) | |
1081 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
1082 | else | |
1083 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
1084 | l = gpio_mask; | |
1085 | break; | |
78a1a6d3 SR |
1086 | #endif |
1087 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1088 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1089 | if (enable) |
1090 | reg += OMAP4_GPIO_IRQSTATUSSET0; | |
1091 | else | |
1092 | reg += OMAP4_GPIO_IRQSTATUSCLR0; | |
1093 | l = gpio_mask; | |
1094 | break; | |
e5c56ed3 | 1095 | #endif |
5e1c5ff4 | 1096 | default: |
e5c56ed3 | 1097 | WARN_ON(1); |
5e1c5ff4 TL |
1098 | return; |
1099 | } | |
1100 | __raw_writel(l, reg); | |
1101 | } | |
1102 | ||
1103 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
1104 | { | |
1105 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
1106 | } | |
1107 | ||
92105bb7 TL |
1108 | /* |
1109 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
1110 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
1111 | * to the target, system will wake up always on GPIO events. While | |
1112 | * system is running all registered GPIO interrupts need to have wake-up | |
1113 | * enabled. When system is suspended, only selected GPIO interrupts need | |
1114 | * to have wake-up enabled. | |
1115 | */ | |
1116 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
1117 | { | |
4cc6420c | 1118 | unsigned long uninitialized_var(flags); |
a6472533 | 1119 | |
92105bb7 | 1120 | switch (bank->method) { |
3ac4fa99 | 1121 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 1122 | case METHOD_MPUIO: |
92105bb7 | 1123 | case METHOD_GPIO_1610: |
a6472533 | 1124 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 1125 | if (enable) |
92105bb7 | 1126 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 1127 | else |
92105bb7 | 1128 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 1129 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1130 | return 0; |
3ac4fa99 | 1131 | #endif |
140455fa | 1132 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 | 1133 | case METHOD_GPIO_24XX: |
3f1686a9 | 1134 | case METHOD_GPIO_44XX: |
11a78b79 DB |
1135 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
1136 | printk(KERN_ERR "Unable to modify wakeup on " | |
1137 | "non-wakeup GPIO%d\n", | |
1138 | (bank - gpio_bank) * 32 + gpio); | |
1139 | return -EINVAL; | |
1140 | } | |
a6472533 | 1141 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 1142 | if (enable) |
3ac4fa99 | 1143 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 1144 | else |
3ac4fa99 | 1145 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 1146 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
1147 | return 0; |
1148 | #endif | |
92105bb7 TL |
1149 | default: |
1150 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
1151 | bank->method); | |
1152 | return -EINVAL; | |
1153 | } | |
1154 | } | |
1155 | ||
4196dd6b TL |
1156 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
1157 | { | |
1158 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
1159 | _set_gpio_irqenable(bank, gpio, 0); | |
1160 | _clear_gpio_irqstatus(bank, gpio); | |
6cab4860 | 1161 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
1162 | } |
1163 | ||
92105bb7 TL |
1164 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
1165 | static int gpio_wake_enable(unsigned int irq, unsigned int enable) | |
1166 | { | |
1167 | unsigned int gpio = irq - IH_GPIO_BASE; | |
1168 | struct gpio_bank *bank; | |
1169 | int retval; | |
1170 | ||
1171 | if (check_gpio(gpio) < 0) | |
1172 | return -ENODEV; | |
58781016 | 1173 | bank = get_irq_chip_data(irq); |
92105bb7 | 1174 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
1175 | |
1176 | return retval; | |
1177 | } | |
1178 | ||
3ff164e1 | 1179 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1180 | { |
3ff164e1 | 1181 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1182 | unsigned long flags; |
52e31344 | 1183 | |
a6472533 | 1184 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 1185 | |
4196dd6b TL |
1186 | /* Set trigger to none. You need to enable the desired trigger with |
1187 | * request_irq() or set_irq_type(). | |
1188 | */ | |
3ff164e1 | 1189 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 1190 | |
1a8bfa1e | 1191 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 1192 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 1193 | void __iomem *reg; |
5e1c5ff4 | 1194 | |
92105bb7 | 1195 | /* Claim the pin for MPU */ |
5e1c5ff4 | 1196 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 1197 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
1198 | } |
1199 | #endif | |
058af1ea C |
1200 | if (!cpu_class_is_omap1()) { |
1201 | if (!bank->mod_usage) { | |
9f096868 | 1202 | void __iomem *reg = bank->base; |
058af1ea | 1203 | u32 ctrl; |
9f096868 C |
1204 | |
1205 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1206 | reg += OMAP24XX_GPIO_CTRL; | |
1207 | else if (cpu_is_omap44xx()) | |
1208 | reg += OMAP4_GPIO_CTRL; | |
1209 | ctrl = __raw_readl(reg); | |
058af1ea | 1210 | /* Module is enabled, clocks are not gated */ |
9f096868 C |
1211 | ctrl &= 0xFFFFFFFE; |
1212 | __raw_writel(ctrl, reg); | |
058af1ea C |
1213 | } |
1214 | bank->mod_usage |= 1 << offset; | |
1215 | } | |
a6472533 | 1216 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1217 | |
1218 | return 0; | |
1219 | } | |
1220 | ||
3ff164e1 | 1221 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1222 | { |
3ff164e1 | 1223 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1224 | unsigned long flags; |
5e1c5ff4 | 1225 | |
a6472533 | 1226 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1227 | #ifdef CONFIG_ARCH_OMAP16XX |
1228 | if (bank->method == METHOD_GPIO_1610) { | |
1229 | /* Disable wake-up during idle for dynamic tick */ | |
1230 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 1231 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
1232 | } |
1233 | #endif | |
9f096868 C |
1234 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
1235 | if (bank->method == METHOD_GPIO_24XX) { | |
92105bb7 TL |
1236 | /* Disable wake-up during idle for dynamic tick */ |
1237 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 1238 | __raw_writel(1 << offset, reg); |
92105bb7 | 1239 | } |
9f096868 C |
1240 | #endif |
1241 | #ifdef CONFIG_ARCH_OMAP4 | |
1242 | if (bank->method == METHOD_GPIO_44XX) { | |
1243 | /* Disable wake-up during idle for dynamic tick */ | |
1244 | void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1245 | __raw_writel(1 << offset, reg); | |
1246 | } | |
92105bb7 | 1247 | #endif |
058af1ea C |
1248 | if (!cpu_class_is_omap1()) { |
1249 | bank->mod_usage &= ~(1 << offset); | |
1250 | if (!bank->mod_usage) { | |
9f096868 | 1251 | void __iomem *reg = bank->base; |
058af1ea | 1252 | u32 ctrl; |
9f096868 C |
1253 | |
1254 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1255 | reg += OMAP24XX_GPIO_CTRL; | |
1256 | else if (cpu_is_omap44xx()) | |
1257 | reg += OMAP4_GPIO_CTRL; | |
1258 | ctrl = __raw_readl(reg); | |
058af1ea C |
1259 | /* Module is disabled, clocks are gated */ |
1260 | ctrl |= 1; | |
9f096868 | 1261 | __raw_writel(ctrl, reg); |
058af1ea C |
1262 | } |
1263 | } | |
3ff164e1 | 1264 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 1265 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1266 | } |
1267 | ||
1268 | /* | |
1269 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
1270 | * avoid missing GPIO interrupts for other lines in the bank. | |
1271 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
1272 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
1273 | * If we wait to unmask individual GPIO lines in the bank after the | |
1274 | * line's interrupt handler has been run, we may miss some nested | |
1275 | * interrupts. | |
1276 | */ | |
10dd5ce2 | 1277 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 1278 | { |
92105bb7 | 1279 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 1280 | u32 isr; |
4318f36b | 1281 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 1282 | struct gpio_bank *bank; |
ea6dedd7 ID |
1283 | u32 retrigger = 0; |
1284 | int unmasked = 0; | |
5e1c5ff4 TL |
1285 | |
1286 | desc->chip->ack(irq); | |
1287 | ||
418ca1f0 | 1288 | bank = get_irq_data(irq); |
e5c56ed3 | 1289 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
1290 | if (bank->method == METHOD_MPUIO) |
1291 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | |
e5c56ed3 | 1292 | #endif |
1a8bfa1e | 1293 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
1294 | if (bank->method == METHOD_GPIO_1510) |
1295 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
1296 | #endif | |
1297 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1298 | if (bank->method == METHOD_GPIO_1610) | |
1299 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
1300 | #endif | |
b718aa81 | 1301 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1302 | if (bank->method == METHOD_GPIO_7XX) |
1303 | isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; | |
56739a69 | 1304 | #endif |
a8eb7ca0 | 1305 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
1306 | if (bank->method == METHOD_GPIO_24XX) |
1307 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
78a1a6d3 SR |
1308 | #endif |
1309 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 1310 | if (bank->method == METHOD_GPIO_44XX) |
78a1a6d3 | 1311 | isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; |
92105bb7 | 1312 | #endif |
b1cc4c55 EK |
1313 | |
1314 | if (WARN_ON(!isr_reg)) | |
1315 | goto exit; | |
1316 | ||
92105bb7 | 1317 | while(1) { |
6e60e79a | 1318 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 1319 | u32 enabled; |
6e60e79a | 1320 | |
ea6dedd7 ID |
1321 | enabled = _get_gpio_irqbank_mask(bank); |
1322 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
1323 | |
1324 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
1325 | isr &= 0x0000ffff; | |
1326 | ||
5492fb1a | 1327 | if (cpu_class_is_omap2()) { |
b144ff6f | 1328 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 1329 | } |
6e60e79a TL |
1330 | |
1331 | /* clear edge sensitive interrupts before handler(s) are | |
1332 | called so that we don't miss any interrupt occurred while | |
1333 | executing them */ | |
1334 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1335 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1336 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1337 | ||
1338 | /* if there is only edge sensitive GPIO pin interrupts | |
1339 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1340 | if (!level_mask && !unmasked) { |
1341 | unmasked = 1; | |
6e60e79a | 1342 | desc->chip->unmask(irq); |
ea6dedd7 | 1343 | } |
92105bb7 | 1344 | |
ea6dedd7 ID |
1345 | isr |= retrigger; |
1346 | retrigger = 0; | |
92105bb7 TL |
1347 | if (!isr) |
1348 | break; | |
1349 | ||
1350 | gpio_irq = bank->virtual_irq_start; | |
1351 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
4318f36b CM |
1352 | gpio_index = get_gpio_index(irq_to_gpio(gpio_irq)); |
1353 | ||
92105bb7 TL |
1354 | if (!(isr & 1)) |
1355 | continue; | |
29454dde | 1356 | |
4318f36b CM |
1357 | #ifdef CONFIG_ARCH_OMAP1 |
1358 | /* | |
1359 | * Some chips can't respond to both rising and falling | |
1360 | * at the same time. If this irq was requested with | |
1361 | * both flags, we need to flip the ICR data for the IRQ | |
1362 | * to respond to the IRQ for the opposite direction. | |
1363 | * This will be indicated in the bank toggle_mask. | |
1364 | */ | |
1365 | if (bank->toggle_mask & (1 << gpio_index)) | |
1366 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
1367 | #endif | |
1368 | ||
d8aa0251 | 1369 | generic_handle_irq(gpio_irq); |
92105bb7 | 1370 | } |
1a8bfa1e | 1371 | } |
ea6dedd7 ID |
1372 | /* if bank has any level sensitive GPIO pin interrupt |
1373 | configured, we must unmask the bank interrupt only after | |
1374 | handler(s) are executed in order to avoid spurious bank | |
1375 | interrupt */ | |
b1cc4c55 | 1376 | exit: |
ea6dedd7 ID |
1377 | if (!unmasked) |
1378 | desc->chip->unmask(irq); | |
1379 | ||
5e1c5ff4 TL |
1380 | } |
1381 | ||
4196dd6b TL |
1382 | static void gpio_irq_shutdown(unsigned int irq) |
1383 | { | |
1384 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1385 | struct gpio_bank *bank = get_irq_chip_data(irq); |
4196dd6b TL |
1386 | |
1387 | _reset_gpio(bank, gpio); | |
1388 | } | |
1389 | ||
5e1c5ff4 TL |
1390 | static void gpio_ack_irq(unsigned int irq) |
1391 | { | |
1392 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1393 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1394 | |
1395 | _clear_gpio_irqstatus(bank, gpio); | |
1396 | } | |
1397 | ||
1398 | static void gpio_mask_irq(unsigned int irq) | |
1399 | { | |
1400 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1401 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1402 | |
1403 | _set_gpio_irqenable(bank, gpio, 0); | |
55b6019a | 1404 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
5e1c5ff4 TL |
1405 | } |
1406 | ||
1407 | static void gpio_unmask_irq(unsigned int irq) | |
1408 | { | |
1409 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1410 | struct gpio_bank *bank = get_irq_chip_data(irq); |
b144ff6f | 1411 | unsigned int irq_mask = 1 << get_gpio_index(gpio); |
55b6019a KH |
1412 | struct irq_desc *desc = irq_to_desc(irq); |
1413 | u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; | |
1414 | ||
1415 | if (trigger) | |
1416 | _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); | |
b144ff6f KH |
1417 | |
1418 | /* For level-triggered GPIOs, the clearing must be done after | |
1419 | * the HW source is cleared, thus after the handler has run */ | |
1420 | if (bank->level_mask & irq_mask) { | |
1421 | _set_gpio_irqenable(bank, gpio, 0); | |
1422 | _clear_gpio_irqstatus(bank, gpio); | |
1423 | } | |
5e1c5ff4 | 1424 | |
4de8c75b | 1425 | _set_gpio_irqenable(bank, gpio, 1); |
5e1c5ff4 TL |
1426 | } |
1427 | ||
e5c56ed3 DB |
1428 | static struct irq_chip gpio_irq_chip = { |
1429 | .name = "GPIO", | |
1430 | .shutdown = gpio_irq_shutdown, | |
1431 | .ack = gpio_ack_irq, | |
1432 | .mask = gpio_mask_irq, | |
1433 | .unmask = gpio_unmask_irq, | |
1434 | .set_type = gpio_irq_type, | |
1435 | .set_wake = gpio_wake_enable, | |
1436 | }; | |
1437 | ||
1438 | /*---------------------------------------------------------------------*/ | |
1439 | ||
1440 | #ifdef CONFIG_ARCH_OMAP1 | |
1441 | ||
1442 | /* MPUIO uses the always-on 32k clock */ | |
1443 | ||
5e1c5ff4 TL |
1444 | static void mpuio_ack_irq(unsigned int irq) |
1445 | { | |
1446 | /* The ISR is reset automatically, so do nothing here. */ | |
1447 | } | |
1448 | ||
1449 | static void mpuio_mask_irq(unsigned int irq) | |
1450 | { | |
1451 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1452 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1453 | |
1454 | _set_gpio_irqenable(bank, gpio, 0); | |
1455 | } | |
1456 | ||
1457 | static void mpuio_unmask_irq(unsigned int irq) | |
1458 | { | |
1459 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1460 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1461 | |
1462 | _set_gpio_irqenable(bank, gpio, 1); | |
1463 | } | |
1464 | ||
e5c56ed3 DB |
1465 | static struct irq_chip mpuio_irq_chip = { |
1466 | .name = "MPUIO", | |
1467 | .ack = mpuio_ack_irq, | |
1468 | .mask = mpuio_mask_irq, | |
1469 | .unmask = mpuio_unmask_irq, | |
92105bb7 | 1470 | .set_type = gpio_irq_type, |
11a78b79 DB |
1471 | #ifdef CONFIG_ARCH_OMAP16XX |
1472 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1473 | .set_wake = gpio_wake_enable, | |
1474 | #endif | |
5e1c5ff4 TL |
1475 | }; |
1476 | ||
e5c56ed3 DB |
1477 | |
1478 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1479 | ||
11a78b79 DB |
1480 | |
1481 | #ifdef CONFIG_ARCH_OMAP16XX | |
1482 | ||
1483 | #include <linux/platform_device.h> | |
1484 | ||
79ee031f | 1485 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 1486 | { |
79ee031f | 1487 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 DB |
1488 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
1489 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1490 | unsigned long flags; |
11a78b79 | 1491 | |
a6472533 | 1492 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1493 | bank->saved_wakeup = __raw_readl(mask_reg); |
1494 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1495 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1496 | |
1497 | return 0; | |
1498 | } | |
1499 | ||
79ee031f | 1500 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 1501 | { |
79ee031f | 1502 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 DB |
1503 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
1504 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1505 | unsigned long flags; |
11a78b79 | 1506 | |
a6472533 | 1507 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1508 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1509 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1510 | |
1511 | return 0; | |
1512 | } | |
1513 | ||
47145210 | 1514 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
1515 | .suspend_noirq = omap_mpuio_suspend_noirq, |
1516 | .resume_noirq = omap_mpuio_resume_noirq, | |
1517 | }; | |
1518 | ||
11a78b79 DB |
1519 | /* use platform_driver for this, now that there's no longer any |
1520 | * point to sys_device (other than not disturbing old code). | |
1521 | */ | |
1522 | static struct platform_driver omap_mpuio_driver = { | |
11a78b79 DB |
1523 | .driver = { |
1524 | .name = "mpuio", | |
79ee031f | 1525 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
1526 | }, |
1527 | }; | |
1528 | ||
1529 | static struct platform_device omap_mpuio_device = { | |
1530 | .name = "mpuio", | |
1531 | .id = -1, | |
1532 | .dev = { | |
1533 | .driver = &omap_mpuio_driver.driver, | |
1534 | } | |
1535 | /* could list the /proc/iomem resources */ | |
1536 | }; | |
1537 | ||
1538 | static inline void mpuio_init(void) | |
1539 | { | |
fcf126d8 DB |
1540 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); |
1541 | ||
11a78b79 DB |
1542 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1543 | (void) platform_device_register(&omap_mpuio_device); | |
1544 | } | |
1545 | ||
1546 | #else | |
1547 | static inline void mpuio_init(void) {} | |
1548 | #endif /* 16xx */ | |
1549 | ||
e5c56ed3 DB |
1550 | #else |
1551 | ||
1552 | extern struct irq_chip mpuio_irq_chip; | |
1553 | ||
1554 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1555 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1556 | |
1557 | #endif | |
1558 | ||
1559 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1560 | |
52e31344 DB |
1561 | /* REVISIT these are stupid implementations! replace by ones that |
1562 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1563 | */ | |
1564 | ||
1565 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1566 | { | |
1567 | struct gpio_bank *bank; | |
1568 | unsigned long flags; | |
1569 | ||
1570 | bank = container_of(chip, struct gpio_bank, chip); | |
1571 | spin_lock_irqsave(&bank->lock, flags); | |
1572 | _set_gpio_direction(bank, offset, 1); | |
1573 | spin_unlock_irqrestore(&bank->lock, flags); | |
1574 | return 0; | |
1575 | } | |
1576 | ||
b37c45b8 RQ |
1577 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
1578 | { | |
1579 | void __iomem *reg = bank->base; | |
1580 | ||
1581 | switch (bank->method) { | |
1582 | case METHOD_MPUIO: | |
1583 | reg += OMAP_MPUIO_IO_CNTL; | |
1584 | break; | |
1585 | case METHOD_GPIO_1510: | |
1586 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1587 | break; | |
1588 | case METHOD_GPIO_1610: | |
1589 | reg += OMAP1610_GPIO_DIRECTION; | |
1590 | break; | |
7c006926 AB |
1591 | case METHOD_GPIO_7XX: |
1592 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
b37c45b8 RQ |
1593 | break; |
1594 | case METHOD_GPIO_24XX: | |
1595 | reg += OMAP24XX_GPIO_OE; | |
1596 | break; | |
9f096868 C |
1597 | case METHOD_GPIO_44XX: |
1598 | reg += OMAP4_GPIO_OE; | |
1599 | break; | |
1600 | default: | |
1601 | WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method"); | |
1602 | return -EINVAL; | |
b37c45b8 RQ |
1603 | } |
1604 | return __raw_readl(reg) & mask; | |
1605 | } | |
1606 | ||
52e31344 DB |
1607 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
1608 | { | |
b37c45b8 RQ |
1609 | struct gpio_bank *bank; |
1610 | void __iomem *reg; | |
1611 | int gpio; | |
1612 | u32 mask; | |
1613 | ||
1614 | gpio = chip->base + offset; | |
1615 | bank = get_gpio_bank(gpio); | |
1616 | reg = bank->base; | |
1617 | mask = 1 << get_gpio_index(gpio); | |
1618 | ||
1619 | if (gpio_is_input(bank, mask)) | |
1620 | return _get_gpio_datain(bank, gpio); | |
1621 | else | |
1622 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
1623 | } |
1624 | ||
1625 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1626 | { | |
1627 | struct gpio_bank *bank; | |
1628 | unsigned long flags; | |
1629 | ||
1630 | bank = container_of(chip, struct gpio_bank, chip); | |
1631 | spin_lock_irqsave(&bank->lock, flags); | |
1632 | _set_gpio_dataout(bank, offset, value); | |
1633 | _set_gpio_direction(bank, offset, 0); | |
1634 | spin_unlock_irqrestore(&bank->lock, flags); | |
1635 | return 0; | |
1636 | } | |
1637 | ||
168ef3d9 FB |
1638 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1639 | unsigned debounce) | |
1640 | { | |
1641 | struct gpio_bank *bank; | |
1642 | unsigned long flags; | |
1643 | ||
1644 | bank = container_of(chip, struct gpio_bank, chip); | |
1645 | spin_lock_irqsave(&bank->lock, flags); | |
1646 | _set_gpio_debounce(bank, offset, debounce); | |
1647 | spin_unlock_irqrestore(&bank->lock, flags); | |
1648 | ||
1649 | return 0; | |
1650 | } | |
1651 | ||
52e31344 DB |
1652 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
1653 | { | |
1654 | struct gpio_bank *bank; | |
1655 | unsigned long flags; | |
1656 | ||
1657 | bank = container_of(chip, struct gpio_bank, chip); | |
1658 | spin_lock_irqsave(&bank->lock, flags); | |
1659 | _set_gpio_dataout(bank, offset, value); | |
1660 | spin_unlock_irqrestore(&bank->lock, flags); | |
1661 | } | |
1662 | ||
a007b709 DB |
1663 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
1664 | { | |
1665 | struct gpio_bank *bank; | |
1666 | ||
1667 | bank = container_of(chip, struct gpio_bank, chip); | |
1668 | return bank->virtual_irq_start + offset; | |
1669 | } | |
1670 | ||
52e31344 DB |
1671 | /*---------------------------------------------------------------------*/ |
1672 | ||
1a8bfa1e | 1673 | static int initialized; |
56213ca4 | 1674 | #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) |
1a8bfa1e | 1675 | static struct clk * gpio_ick; |
5492fb1a SMK |
1676 | #endif |
1677 | ||
1678 | #if defined(CONFIG_ARCH_OMAP2) | |
1a8bfa1e | 1679 | static struct clk * gpio_fck; |
5492fb1a | 1680 | #endif |
5e1c5ff4 | 1681 | |
5492fb1a | 1682 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1683 | static struct clk * gpio5_ick; |
1684 | static struct clk * gpio5_fck; | |
1685 | #endif | |
1686 | ||
44169075 | 1687 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
5492fb1a SMK |
1688 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; |
1689 | #endif | |
1690 | ||
9a748053 | 1691 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da TL |
1692 | { |
1693 | u32 rev; | |
1694 | ||
9a748053 TL |
1695 | if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO)) |
1696 | rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION); | |
9f7065da | 1697 | else if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
9a748053 | 1698 | rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION); |
9f7065da | 1699 | else if (cpu_is_omap44xx()) |
9a748053 | 1700 | rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION); |
9f7065da TL |
1701 | else |
1702 | return; | |
1703 | ||
1704 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | |
1705 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1706 | } | |
1707 | ||
8ba55c5c DB |
1708 | /* This lock class tells lockdep that GPIO irqs are in a different |
1709 | * category than their parents, so it won't report false recursion. | |
1710 | */ | |
1711 | static struct lock_class_key gpio_lock_class; | |
1712 | ||
2fae7fbe VC |
1713 | static void omap_gpio_mod_init(struct gpio_bank *bank, int id) |
1714 | { | |
1715 | if (cpu_class_is_omap2()) { | |
1716 | if (cpu_is_omap44xx()) { | |
1717 | __raw_writel(0xffffffff, bank->base + | |
1718 | OMAP4_GPIO_IRQSTATUSCLR0); | |
1719 | __raw_writel(0x00000000, bank->base + | |
1720 | OMAP4_GPIO_DEBOUNCENABLE); | |
1721 | /* Initialize interface clk ungated, module enabled */ | |
1722 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); | |
1723 | } else if (cpu_is_omap34xx()) { | |
1724 | __raw_writel(0x00000000, bank->base + | |
1725 | OMAP24XX_GPIO_IRQENABLE1); | |
1726 | __raw_writel(0xffffffff, bank->base + | |
1727 | OMAP24XX_GPIO_IRQSTATUS1); | |
1728 | __raw_writel(0x00000000, bank->base + | |
1729 | OMAP24XX_GPIO_DEBOUNCE_EN); | |
1730 | ||
1731 | /* Initialize interface clk ungated, module enabled */ | |
1732 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
1733 | } else if (cpu_is_omap24xx()) { | |
1734 | static const u32 non_wakeup_gpios[] = { | |
1735 | 0xe203ffc0, 0x08700040 | |
1736 | }; | |
1737 | if (id < ARRAY_SIZE(non_wakeup_gpios)) | |
1738 | bank->non_wakeup_gpios = non_wakeup_gpios[id]; | |
1739 | } | |
1740 | } else if (cpu_class_is_omap1()) { | |
1741 | if (bank_is_mpuio(bank)) | |
1742 | __raw_writew(0xffff, bank->base | |
1743 | + OMAP_MPUIO_GPIO_MASKIT); | |
1744 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { | |
1745 | __raw_writew(0xffff, bank->base | |
1746 | + OMAP1510_GPIO_INT_MASK); | |
1747 | __raw_writew(0x0000, bank->base | |
1748 | + OMAP1510_GPIO_INT_STATUS); | |
1749 | } | |
1750 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { | |
1751 | __raw_writew(0x0000, bank->base | |
1752 | + OMAP1610_GPIO_IRQENABLE1); | |
1753 | __raw_writew(0xffff, bank->base | |
1754 | + OMAP1610_GPIO_IRQSTATUS1); | |
1755 | __raw_writew(0x0014, bank->base | |
1756 | + OMAP1610_GPIO_SYSCONFIG); | |
1757 | ||
1758 | /* | |
1759 | * Enable system clock for GPIO module. | |
1760 | * The CAM_CLK_CTRL *is* really the right place. | |
1761 | */ | |
1762 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, | |
1763 | ULPD_CAM_CLK_CTRL); | |
1764 | } | |
1765 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { | |
1766 | __raw_writel(0xffffffff, bank->base | |
1767 | + OMAP7XX_GPIO_INT_MASK); | |
1768 | __raw_writel(0x00000000, bank->base | |
1769 | + OMAP7XX_GPIO_INT_STATUS); | |
1770 | } | |
1771 | } | |
1772 | } | |
1773 | ||
1774 | static void __init omap_gpio_chip_init(struct gpio_bank *bank) | |
1775 | { | |
1776 | int j, bank_width = 16; | |
1777 | static int gpio; | |
1778 | ||
1779 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) | |
1780 | bank_width = 32; /* 7xx has 32-bit GPIOs */ | |
1781 | ||
1782 | if ((bank->method == METHOD_GPIO_24XX) || | |
1783 | (bank->method == METHOD_GPIO_44XX)) | |
1784 | bank_width = 32; | |
1785 | ||
1786 | bank->mod_usage = 0; | |
1787 | /* | |
1788 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1789 | * over to the generic ones | |
1790 | */ | |
1791 | bank->chip.request = omap_gpio_request; | |
1792 | bank->chip.free = omap_gpio_free; | |
1793 | bank->chip.direction_input = gpio_input; | |
1794 | bank->chip.get = gpio_get; | |
1795 | bank->chip.direction_output = gpio_output; | |
1796 | bank->chip.set_debounce = gpio_debounce; | |
1797 | bank->chip.set = gpio_set; | |
1798 | bank->chip.to_irq = gpio_2irq; | |
1799 | if (bank_is_mpuio(bank)) { | |
1800 | bank->chip.label = "mpuio"; | |
1801 | #ifdef CONFIG_ARCH_OMAP16XX | |
1802 | bank->chip.dev = &omap_mpuio_device.dev; | |
1803 | #endif | |
1804 | bank->chip.base = OMAP_MPUIO(0); | |
1805 | } else { | |
1806 | bank->chip.label = "gpio"; | |
1807 | bank->chip.base = gpio; | |
1808 | gpio += bank_width; | |
1809 | } | |
1810 | bank->chip.ngpio = bank_width; | |
1811 | ||
1812 | gpiochip_add(&bank->chip); | |
1813 | ||
1814 | for (j = bank->virtual_irq_start; | |
1815 | j < bank->virtual_irq_start + bank_width; j++) { | |
1816 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); | |
1817 | set_irq_chip_data(j, bank); | |
1818 | if (bank_is_mpuio(bank)) | |
1819 | set_irq_chip(j, &mpuio_irq_chip); | |
1820 | else | |
1821 | set_irq_chip(j, &gpio_irq_chip); | |
1822 | set_irq_handler(j, handle_simple_irq); | |
1823 | set_irq_flags(j, IRQF_VALID); | |
1824 | } | |
1825 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | |
1826 | set_irq_data(bank->irq, bank); | |
1827 | } | |
1828 | ||
5e1c5ff4 TL |
1829 | static int __init _omap_gpio_init(void) |
1830 | { | |
1831 | int i; | |
1832 | struct gpio_bank *bank; | |
9f7065da | 1833 | int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ |
5492fb1a | 1834 | char clk_name[11]; |
5e1c5ff4 TL |
1835 | |
1836 | initialized = 1; | |
1837 | ||
5492fb1a | 1838 | #if defined(CONFIG_ARCH_OMAP1) |
6e60e79a | 1839 | if (cpu_is_omap15xx()) { |
1a8bfa1e TL |
1840 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); |
1841 | if (IS_ERR(gpio_ick)) | |
92105bb7 TL |
1842 | printk("Could not get arm_gpio_ck\n"); |
1843 | else | |
30ff720b | 1844 | clk_enable(gpio_ick); |
1a8bfa1e | 1845 | } |
5492fb1a SMK |
1846 | #endif |
1847 | #if defined(CONFIG_ARCH_OMAP2) | |
1848 | if (cpu_class_is_omap2()) { | |
1a8bfa1e TL |
1849 | gpio_ick = clk_get(NULL, "gpios_ick"); |
1850 | if (IS_ERR(gpio_ick)) | |
1851 | printk("Could not get gpios_ick\n"); | |
1852 | else | |
30ff720b | 1853 | clk_enable(gpio_ick); |
1a8bfa1e | 1854 | gpio_fck = clk_get(NULL, "gpios_fck"); |
1630b52d | 1855 | if (IS_ERR(gpio_fck)) |
1a8bfa1e TL |
1856 | printk("Could not get gpios_fck\n"); |
1857 | else | |
30ff720b | 1858 | clk_enable(gpio_fck); |
56a25641 SMK |
1859 | |
1860 | /* | |
5492fb1a | 1861 | * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK |
56a25641 | 1862 | */ |
5492fb1a | 1863 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1864 | if (cpu_is_omap2430()) { |
1865 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | |
1866 | if (IS_ERR(gpio5_ick)) | |
1867 | printk("Could not get gpio5_ick\n"); | |
1868 | else | |
1869 | clk_enable(gpio5_ick); | |
1870 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | |
1871 | if (IS_ERR(gpio5_fck)) | |
1872 | printk("Could not get gpio5_fck\n"); | |
1873 | else | |
1874 | clk_enable(gpio5_fck); | |
1875 | } | |
1876 | #endif | |
5492fb1a SMK |
1877 | } |
1878 | #endif | |
1879 | ||
44169075 SS |
1880 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
1881 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
5492fb1a SMK |
1882 | for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { |
1883 | sprintf(clk_name, "gpio%d_ick", i + 1); | |
1884 | gpio_iclks[i] = clk_get(NULL, clk_name); | |
1885 | if (IS_ERR(gpio_iclks[i])) | |
1886 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1887 | else | |
1888 | clk_enable(gpio_iclks[i]); | |
5492fb1a SMK |
1889 | } |
1890 | } | |
1891 | #endif | |
1892 | ||
92105bb7 | 1893 | |
1a8bfa1e | 1894 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 1895 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
1896 | gpio_bank_count = 2; |
1897 | gpio_bank = gpio_bank_1510; | |
9f7065da | 1898 | bank_size = SZ_2K; |
5e1c5ff4 TL |
1899 | } |
1900 | #endif | |
1901 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1902 | if (cpu_is_omap16xx()) { | |
5e1c5ff4 TL |
1903 | gpio_bank_count = 5; |
1904 | gpio_bank = gpio_bank_1610; | |
9f7065da | 1905 | bank_size = SZ_2K; |
5e1c5ff4 TL |
1906 | } |
1907 | #endif | |
b718aa81 AB |
1908 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
1909 | if (cpu_is_omap7xx()) { | |
56739a69 | 1910 | gpio_bank_count = 7; |
7c006926 | 1911 | gpio_bank = gpio_bank_7xx; |
9f7065da | 1912 | bank_size = SZ_2K; |
56739a69 ZM |
1913 | } |
1914 | #endif | |
088ef950 | 1915 | #ifdef CONFIG_ARCH_OMAP2 |
56a25641 | 1916 | if (cpu_is_omap242x()) { |
92105bb7 | 1917 | gpio_bank_count = 4; |
56a25641 | 1918 | gpio_bank = gpio_bank_242x; |
56a25641 SMK |
1919 | } |
1920 | if (cpu_is_omap243x()) { | |
56a25641 SMK |
1921 | gpio_bank_count = 5; |
1922 | gpio_bank = gpio_bank_243x; | |
92105bb7 | 1923 | } |
5492fb1a | 1924 | #endif |
a8eb7ca0 | 1925 | #ifdef CONFIG_ARCH_OMAP3 |
5492fb1a | 1926 | if (cpu_is_omap34xx()) { |
5492fb1a SMK |
1927 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
1928 | gpio_bank = gpio_bank_34xx; | |
5492fb1a | 1929 | } |
44169075 SS |
1930 | #endif |
1931 | #ifdef CONFIG_ARCH_OMAP4 | |
1932 | if (cpu_is_omap44xx()) { | |
44169075 SS |
1933 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
1934 | gpio_bank = gpio_bank_44xx; | |
44169075 | 1935 | } |
5e1c5ff4 TL |
1936 | #endif |
1937 | for (i = 0; i < gpio_bank_count; i++) { | |
5e1c5ff4 TL |
1938 | |
1939 | bank = &gpio_bank[i]; | |
5e1c5ff4 | 1940 | spin_lock_init(&bank->lock); |
9f7065da TL |
1941 | |
1942 | /* Static mapping, never released */ | |
1943 | bank->base = ioremap(bank->pbase, bank_size); | |
1944 | if (!bank->base) { | |
1945 | printk(KERN_ERR "Could not ioremap gpio bank%i\n", i); | |
1946 | continue; | |
1947 | } | |
1948 | ||
2fae7fbe VC |
1949 | omap_gpio_mod_init(bank, i); |
1950 | omap_gpio_chip_init(bank); | |
89db9482 | 1951 | |
44169075 | 1952 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
89db9482 JH |
1953 | sprintf(clk_name, "gpio%d_dbck", i + 1); |
1954 | bank->dbck = clk_get(NULL, clk_name); | |
1955 | if (IS_ERR(bank->dbck)) | |
1956 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1957 | } | |
5e1c5ff4 TL |
1958 | } |
1959 | ||
9a748053 | 1960 | omap_gpio_show_rev(bank); |
9f7065da | 1961 | |
5e1c5ff4 TL |
1962 | return 0; |
1963 | } | |
1964 | ||
140455fa | 1965 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 TL |
1966 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) |
1967 | { | |
1968 | int i; | |
1969 | ||
5492fb1a | 1970 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1971 | return 0; |
1972 | ||
1973 | for (i = 0; i < gpio_bank_count; i++) { | |
1974 | struct gpio_bank *bank = &gpio_bank[i]; | |
1975 | void __iomem *wake_status; | |
1976 | void __iomem *wake_clear; | |
1977 | void __iomem *wake_set; | |
a6472533 | 1978 | unsigned long flags; |
92105bb7 TL |
1979 | |
1980 | switch (bank->method) { | |
e5c56ed3 | 1981 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1982 | case METHOD_GPIO_1610: |
1983 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1984 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1985 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1986 | break; | |
e5c56ed3 | 1987 | #endif |
a8eb7ca0 | 1988 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1989 | case METHOD_GPIO_24XX: |
723fdb78 | 1990 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1991 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1992 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1993 | break; | |
78a1a6d3 SR |
1994 | #endif |
1995 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1996 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1997 | wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1998 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1999 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
2000 | break; | |
e5c56ed3 | 2001 | #endif |
92105bb7 TL |
2002 | default: |
2003 | continue; | |
2004 | } | |
2005 | ||
a6472533 | 2006 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
2007 | bank->saved_wakeup = __raw_readl(wake_status); |
2008 | __raw_writel(0xffffffff, wake_clear); | |
2009 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 2010 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
2011 | } |
2012 | ||
2013 | return 0; | |
2014 | } | |
2015 | ||
2016 | static int omap_gpio_resume(struct sys_device *dev) | |
2017 | { | |
2018 | int i; | |
2019 | ||
723fdb78 | 2020 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
2021 | return 0; |
2022 | ||
2023 | for (i = 0; i < gpio_bank_count; i++) { | |
2024 | struct gpio_bank *bank = &gpio_bank[i]; | |
2025 | void __iomem *wake_clear; | |
2026 | void __iomem *wake_set; | |
a6472533 | 2027 | unsigned long flags; |
92105bb7 TL |
2028 | |
2029 | switch (bank->method) { | |
e5c56ed3 | 2030 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
2031 | case METHOD_GPIO_1610: |
2032 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
2033 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
2034 | break; | |
e5c56ed3 | 2035 | #endif |
a8eb7ca0 | 2036 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 2037 | case METHOD_GPIO_24XX: |
0d9356cb TL |
2038 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
2039 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 2040 | break; |
78a1a6d3 SR |
2041 | #endif |
2042 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 2043 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
2044 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; |
2045 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
2046 | break; | |
e5c56ed3 | 2047 | #endif |
92105bb7 TL |
2048 | default: |
2049 | continue; | |
2050 | } | |
2051 | ||
a6472533 | 2052 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
2053 | __raw_writel(0xffffffff, wake_clear); |
2054 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 2055 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
2056 | } |
2057 | ||
2058 | return 0; | |
2059 | } | |
2060 | ||
2061 | static struct sysdev_class omap_gpio_sysclass = { | |
af5ca3f4 | 2062 | .name = "gpio", |
92105bb7 TL |
2063 | .suspend = omap_gpio_suspend, |
2064 | .resume = omap_gpio_resume, | |
2065 | }; | |
2066 | ||
2067 | static struct sys_device omap_gpio_device = { | |
2068 | .id = 0, | |
2069 | .cls = &omap_gpio_sysclass, | |
2070 | }; | |
3ac4fa99 JY |
2071 | |
2072 | #endif | |
2073 | ||
140455fa | 2074 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 JY |
2075 | |
2076 | static int workaround_enabled; | |
2077 | ||
43ffcd9a | 2078 | void omap2_gpio_prepare_for_idle(int power_state) |
3ac4fa99 JY |
2079 | { |
2080 | int i, c = 0; | |
a118b5f3 | 2081 | int min = 0; |
3ac4fa99 | 2082 | |
a118b5f3 TK |
2083 | if (cpu_is_omap34xx()) |
2084 | min = 1; | |
43ffcd9a | 2085 | |
a118b5f3 | 2086 | for (i = min; i < gpio_bank_count; i++) { |
3ac4fa99 | 2087 | struct gpio_bank *bank = &gpio_bank[i]; |
ca828760 | 2088 | u32 l1 = 0, l2 = 0; |
0aed0435 | 2089 | int j; |
3ac4fa99 | 2090 | |
0aed0435 | 2091 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
2092 | clk_disable(bank->dbck); |
2093 | ||
43ffcd9a KH |
2094 | if (power_state > PWRDM_POWER_OFF) |
2095 | continue; | |
2096 | ||
2097 | /* If going to OFF, remove triggering for all | |
2098 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
2099 | * generated. See OMAP2420 Errata item 1.101. */ | |
3ac4fa99 JY |
2100 | if (!(bank->enabled_non_wakeup_gpios)) |
2101 | continue; | |
3f1686a9 TL |
2102 | |
2103 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
2104 | bank->saved_datain = __raw_readl(bank->base + | |
2105 | OMAP24XX_GPIO_DATAIN); | |
2106 | l1 = __raw_readl(bank->base + | |
2107 | OMAP24XX_GPIO_FALLINGDETECT); | |
2108 | l2 = __raw_readl(bank->base + | |
2109 | OMAP24XX_GPIO_RISINGDETECT); | |
2110 | } | |
2111 | ||
2112 | if (cpu_is_omap44xx()) { | |
2113 | bank->saved_datain = __raw_readl(bank->base + | |
2114 | OMAP4_GPIO_DATAIN); | |
2115 | l1 = __raw_readl(bank->base + | |
2116 | OMAP4_GPIO_FALLINGDETECT); | |
2117 | l2 = __raw_readl(bank->base + | |
2118 | OMAP4_GPIO_RISINGDETECT); | |
2119 | } | |
2120 | ||
3ac4fa99 JY |
2121 | bank->saved_fallingdetect = l1; |
2122 | bank->saved_risingdetect = l2; | |
2123 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
2124 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 TL |
2125 | |
2126 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
2127 | __raw_writel(l1, bank->base + | |
2128 | OMAP24XX_GPIO_FALLINGDETECT); | |
2129 | __raw_writel(l2, bank->base + | |
2130 | OMAP24XX_GPIO_RISINGDETECT); | |
2131 | } | |
2132 | ||
2133 | if (cpu_is_omap44xx()) { | |
2134 | __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); | |
2135 | __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); | |
2136 | } | |
2137 | ||
3ac4fa99 JY |
2138 | c++; |
2139 | } | |
2140 | if (!c) { | |
2141 | workaround_enabled = 0; | |
2142 | return; | |
2143 | } | |
2144 | workaround_enabled = 1; | |
2145 | } | |
2146 | ||
43ffcd9a | 2147 | void omap2_gpio_resume_after_idle(void) |
3ac4fa99 JY |
2148 | { |
2149 | int i; | |
a118b5f3 | 2150 | int min = 0; |
3ac4fa99 | 2151 | |
a118b5f3 TK |
2152 | if (cpu_is_omap34xx()) |
2153 | min = 1; | |
2154 | for (i = min; i < gpio_bank_count; i++) { | |
3ac4fa99 | 2155 | struct gpio_bank *bank = &gpio_bank[i]; |
ca828760 | 2156 | u32 l = 0, gen, gen0, gen1; |
0aed0435 | 2157 | int j; |
3ac4fa99 | 2158 | |
0aed0435 | 2159 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
2160 | clk_enable(bank->dbck); |
2161 | ||
43ffcd9a KH |
2162 | if (!workaround_enabled) |
2163 | continue; | |
2164 | ||
3ac4fa99 JY |
2165 | if (!(bank->enabled_non_wakeup_gpios)) |
2166 | continue; | |
3f1686a9 TL |
2167 | |
2168 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
2169 | __raw_writel(bank->saved_fallingdetect, | |
3ac4fa99 | 2170 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
3f1686a9 | 2171 | __raw_writel(bank->saved_risingdetect, |
3ac4fa99 | 2172 | bank->base + OMAP24XX_GPIO_RISINGDETECT); |
3f1686a9 TL |
2173 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
2174 | } | |
2175 | ||
2176 | if (cpu_is_omap44xx()) { | |
2177 | __raw_writel(bank->saved_fallingdetect, | |
78a1a6d3 | 2178 | bank->base + OMAP4_GPIO_FALLINGDETECT); |
3f1686a9 | 2179 | __raw_writel(bank->saved_risingdetect, |
78a1a6d3 | 2180 | bank->base + OMAP4_GPIO_RISINGDETECT); |
3f1686a9 TL |
2181 | l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); |
2182 | } | |
2183 | ||
3ac4fa99 JY |
2184 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
2185 | * state. If so, generate an IRQ by software. This is | |
2186 | * horribly racy, but it's the best we can do to work around | |
2187 | * this silicon bug. */ | |
3ac4fa99 | 2188 | l ^= bank->saved_datain; |
a118b5f3 | 2189 | l &= bank->enabled_non_wakeup_gpios; |
82dbb9d3 EN |
2190 | |
2191 | /* | |
2192 | * No need to generate IRQs for the rising edge for gpio IRQs | |
2193 | * configured with falling edge only; and vice versa. | |
2194 | */ | |
2195 | gen0 = l & bank->saved_fallingdetect; | |
2196 | gen0 &= bank->saved_datain; | |
2197 | ||
2198 | gen1 = l & bank->saved_risingdetect; | |
2199 | gen1 &= ~(bank->saved_datain); | |
2200 | ||
2201 | /* FIXME: Consider GPIO IRQs with level detections properly! */ | |
2202 | gen = l & (~(bank->saved_fallingdetect) & | |
2203 | ~(bank->saved_risingdetect)); | |
2204 | /* Consider all GPIO IRQs needed to be updated */ | |
2205 | gen |= gen0 | gen1; | |
2206 | ||
2207 | if (gen) { | |
3ac4fa99 | 2208 | u32 old0, old1; |
3f1686a9 | 2209 | |
f00d6497 | 2210 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
3f1686a9 TL |
2211 | old0 = __raw_readl(bank->base + |
2212 | OMAP24XX_GPIO_LEVELDETECT0); | |
2213 | old1 = __raw_readl(bank->base + | |
2214 | OMAP24XX_GPIO_LEVELDETECT1); | |
f00d6497 | 2215 | __raw_writel(old0 | gen, bank->base + |
82dbb9d3 | 2216 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 2217 | __raw_writel(old1 | gen, bank->base + |
82dbb9d3 | 2218 | OMAP24XX_GPIO_LEVELDETECT1); |
f00d6497 | 2219 | __raw_writel(old0, bank->base + |
3f1686a9 | 2220 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 2221 | __raw_writel(old1, bank->base + |
3f1686a9 TL |
2222 | OMAP24XX_GPIO_LEVELDETECT1); |
2223 | } | |
2224 | ||
2225 | if (cpu_is_omap44xx()) { | |
2226 | old0 = __raw_readl(bank->base + | |
78a1a6d3 | 2227 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 2228 | old1 = __raw_readl(bank->base + |
78a1a6d3 | 2229 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 2230 | __raw_writel(old0 | l, bank->base + |
78a1a6d3 | 2231 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 2232 | __raw_writel(old1 | l, bank->base + |
78a1a6d3 | 2233 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 2234 | __raw_writel(old0, bank->base + |
78a1a6d3 | 2235 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 2236 | __raw_writel(old1, bank->base + |
78a1a6d3 | 2237 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 2238 | } |
3ac4fa99 JY |
2239 | } |
2240 | } | |
2241 | ||
2242 | } | |
2243 | ||
92105bb7 TL |
2244 | #endif |
2245 | ||
a8eb7ca0 | 2246 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 RN |
2247 | /* save the registers of bank 2-6 */ |
2248 | void omap_gpio_save_context(void) | |
2249 | { | |
2250 | int i; | |
2251 | ||
2252 | /* saving banks from 2-6 only since GPIO1 is in WKUP */ | |
2253 | for (i = 1; i < gpio_bank_count; i++) { | |
2254 | struct gpio_bank *bank = &gpio_bank[i]; | |
2255 | gpio_context[i].sysconfig = | |
2256 | __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG); | |
2257 | gpio_context[i].irqenable1 = | |
2258 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
2259 | gpio_context[i].irqenable2 = | |
2260 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
2261 | gpio_context[i].wake_en = | |
2262 | __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); | |
2263 | gpio_context[i].ctrl = | |
2264 | __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
2265 | gpio_context[i].oe = | |
2266 | __raw_readl(bank->base + OMAP24XX_GPIO_OE); | |
2267 | gpio_context[i].leveldetect0 = | |
2268 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
2269 | gpio_context[i].leveldetect1 = | |
2270 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
2271 | gpio_context[i].risingdetect = | |
2272 | __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
2273 | gpio_context[i].fallingdetect = | |
2274 | __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
2275 | gpio_context[i].dataout = | |
2276 | __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
2277 | } |
2278 | } | |
2279 | ||
2280 | /* restore the required registers of bank 2-6 */ | |
2281 | void omap_gpio_restore_context(void) | |
2282 | { | |
2283 | int i; | |
2284 | ||
2285 | for (i = 1; i < gpio_bank_count; i++) { | |
2286 | struct gpio_bank *bank = &gpio_bank[i]; | |
2287 | __raw_writel(gpio_context[i].sysconfig, | |
2288 | bank->base + OMAP24XX_GPIO_SYSCONFIG); | |
2289 | __raw_writel(gpio_context[i].irqenable1, | |
2290 | bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
2291 | __raw_writel(gpio_context[i].irqenable2, | |
2292 | bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
2293 | __raw_writel(gpio_context[i].wake_en, | |
2294 | bank->base + OMAP24XX_GPIO_WAKE_EN); | |
2295 | __raw_writel(gpio_context[i].ctrl, | |
2296 | bank->base + OMAP24XX_GPIO_CTRL); | |
2297 | __raw_writel(gpio_context[i].oe, | |
2298 | bank->base + OMAP24XX_GPIO_OE); | |
2299 | __raw_writel(gpio_context[i].leveldetect0, | |
2300 | bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
2301 | __raw_writel(gpio_context[i].leveldetect1, | |
2302 | bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
2303 | __raw_writel(gpio_context[i].risingdetect, | |
2304 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
2305 | __raw_writel(gpio_context[i].fallingdetect, | |
2306 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
2307 | __raw_writel(gpio_context[i].dataout, | |
2308 | bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
2309 | } |
2310 | } | |
2311 | #endif | |
2312 | ||
5e1c5ff4 TL |
2313 | /* |
2314 | * This may get called early from board specific init | |
1a8bfa1e | 2315 | * for boards that have interrupts routed via FPGA. |
5e1c5ff4 | 2316 | */ |
277d58ef | 2317 | int __init omap_gpio_init(void) |
5e1c5ff4 TL |
2318 | { |
2319 | if (!initialized) | |
2320 | return _omap_gpio_init(); | |
2321 | else | |
2322 | return 0; | |
2323 | } | |
2324 | ||
92105bb7 TL |
2325 | static int __init omap_gpio_sysinit(void) |
2326 | { | |
2327 | int ret = 0; | |
2328 | ||
2329 | if (!initialized) | |
2330 | ret = _omap_gpio_init(); | |
2331 | ||
11a78b79 DB |
2332 | mpuio_init(); |
2333 | ||
140455fa | 2334 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
5492fb1a | 2335 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { |
92105bb7 TL |
2336 | if (ret == 0) { |
2337 | ret = sysdev_class_register(&omap_gpio_sysclass); | |
2338 | if (ret == 0) | |
2339 | ret = sysdev_register(&omap_gpio_device); | |
2340 | } | |
2341 | } | |
2342 | #endif | |
2343 | ||
2344 | return ret; | |
2345 | } | |
2346 | ||
92105bb7 | 2347 | arch_initcall(omap_gpio_sysinit); |