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5e1c5ff4 | 1 | /* |
a09e64fb | 2 | * arch/arm/plat-omap/include/mach/common.h |
5e1c5ff4 TL |
3 | * |
4 | * Header for code common to all OMAP machines. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License along | |
23 | * with this program; if not, write to the Free Software Foundation, Inc., | |
24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | */ | |
26 | ||
27 | #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H | |
28 | #define __ARCH_ARM_MACH_OMAP_COMMON_H | |
29 | ||
59fb659b PW |
30 | #include <linux/delay.h> |
31 | ||
b63128e8 | 32 | #include <plat/i2c.h> |
85d05fb3 | 33 | |
5e1c5ff4 TL |
34 | struct sys_timer; |
35 | ||
36 | extern void omap_map_common_io(void); | |
e74984e4 TL |
37 | extern struct sys_timer omap1_timer; |
38 | extern struct sys_timer omap2_timer; | |
39 | extern struct sys_timer omap3_timer; | |
40 | extern struct sys_timer omap3_secure_timer; | |
41 | extern struct sys_timer omap4_timer; | |
05b5ca9b | 42 | extern bool omap_32k_timer_init(void); |
d8328f3b | 43 | extern int __init omap_init_clocksource_32k(void); |
4912cf04 | 44 | extern unsigned long long notrace omap_32k_sched_clock(void); |
5e1c5ff4 | 45 | |
71ee7dad RK |
46 | extern void omap_reserve(void); |
47 | ||
8f5b5a41 TL |
48 | void omap2420_init_early(void); |
49 | void omap2430_init_early(void); | |
50 | void omap3430_init_early(void); | |
51 | void omap35xx_init_early(void); | |
52 | void omap3630_init_early(void); | |
53 | void am35xx_init_early(void); | |
54 | void ti816x_init_early(void); | |
55 | void omap4430_init_early(void); | |
56 | ||
b7ebb10b SS |
57 | /* |
58 | * IO bases for various OMAP processors | |
59 | * Except the tap base, rest all the io bases | |
60 | * listed are physical addresses. | |
61 | */ | |
a58caad1 | 62 | struct omap_globals { |
0e564848 | 63 | u32 class; /* OMAP class to detect */ |
a58caad1 | 64 | void __iomem *tap; /* Control module ID code */ |
b7ebb10b SS |
65 | unsigned long sdrc; /* SDRAM Controller */ |
66 | unsigned long sms; /* SDRAM Memory Scheduler */ | |
67 | unsigned long ctrl; /* System Control Module */ | |
0c349246 | 68 | unsigned long ctrl_pad; /* PAD Control Module */ |
b7ebb10b SS |
69 | unsigned long prm; /* Power and Reset Management */ |
70 | unsigned long cm; /* Clock Management */ | |
71 | unsigned long cm2; | |
a58caad1 TL |
72 | }; |
73 | ||
c8d2eb8e PW |
74 | void omap2_set_globals_242x(void); |
75 | void omap2_set_globals_243x(void); | |
c573bcf9 | 76 | void omap2_set_globals_3xxx(void); |
44169075 | 77 | void omap2_set_globals_443x(void); |
4bd7be22 | 78 | void omap2_set_globals_ti816x(void); |
c8d2eb8e | 79 | |
a58caad1 | 80 | /* These get called from omap2_set_globals_xxxx(), do not call these */ |
0e564848 | 81 | void omap2_set_globals_tap(struct omap_globals *); |
f2ab9977 | 82 | void omap2_set_globals_sdrc(struct omap_globals *); |
a58caad1 TL |
83 | void omap2_set_globals_control(struct omap_globals *); |
84 | void omap2_set_globals_prcm(struct omap_globals *); | |
85 | ||
869fef41 MR |
86 | void omap3_map_io(void); |
87 | ||
6f8b7ff5 PW |
88 | /** |
89 | * omap_test_timeout - busy-loop, testing a condition | |
90 | * @cond: condition to test until it evaluates to true | |
91 | * @timeout: maximum number of microseconds in the timeout | |
92 | * @index: loop index (integer) | |
93 | * | |
94 | * Loop waiting for @cond to become true or until at least @timeout | |
95 | * microseconds have passed. To use, define some integer @index in the | |
96 | * calling code. After running, if @index == @timeout, then the loop has | |
97 | * timed out. | |
98 | */ | |
99 | #define omap_test_timeout(cond, timeout, index) \ | |
100 | ({ \ | |
101 | for (index = 0; index < timeout; index++) { \ | |
102 | if (cond) \ | |
103 | break; \ | |
104 | udelay(1); \ | |
105 | } \ | |
106 | }) | |
107 | ||
6f88e9bc | 108 | extern struct device *omap2_get_mpuss_device(void); |
b3294e23 | 109 | extern struct device *omap2_get_iva_device(void); |
6f88e9bc | 110 | extern struct device *omap2_get_l3_device(void); |
b3294e23 | 111 | extern struct device *omap4_get_dsp_device(void); |
6f88e9bc | 112 | |
5e1c5ff4 | 113 | #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ |