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559d6701 TV |
1 | /* |
2 | * linux/include/asm-arm/arch-omap/display.h | |
3 | * | |
4 | * Copyright (C) 2008 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef __ASM_ARCH_OMAP_DISPLAY_H | |
21 | #define __ASM_ARCH_OMAP_DISPLAY_H | |
22 | ||
23 | #include <linux/list.h> | |
24 | #include <linux/kobject.h> | |
25 | #include <linux/device.h> | |
b7ee79ab | 26 | #include <linux/platform_device.h> |
559d6701 TV |
27 | #include <asm/atomic.h> |
28 | ||
29 | #define DISPC_IRQ_FRAMEDONE (1 << 0) | |
30 | #define DISPC_IRQ_VSYNC (1 << 1) | |
31 | #define DISPC_IRQ_EVSYNC_EVEN (1 << 2) | |
32 | #define DISPC_IRQ_EVSYNC_ODD (1 << 3) | |
33 | #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) | |
34 | #define DISPC_IRQ_PROG_LINE_NUM (1 << 5) | |
35 | #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) | |
36 | #define DISPC_IRQ_GFX_END_WIN (1 << 7) | |
37 | #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) | |
38 | #define DISPC_IRQ_OCP_ERR (1 << 9) | |
39 | #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) | |
40 | #define DISPC_IRQ_VID1_END_WIN (1 << 11) | |
41 | #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) | |
42 | #define DISPC_IRQ_VID2_END_WIN (1 << 13) | |
43 | #define DISPC_IRQ_SYNC_LOST (1 << 14) | |
44 | #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) | |
45 | #define DISPC_IRQ_WAKEUP (1 << 16) | |
2a205f34 SS |
46 | #define DISPC_IRQ_SYNC_LOST2 (1 << 17) |
47 | #define DISPC_IRQ_VSYNC2 (1 << 18) | |
48 | #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) | |
49 | #define DISPC_IRQ_FRAMEDONE2 (1 << 22) | |
559d6701 TV |
50 | |
51 | struct omap_dss_device; | |
52 | struct omap_overlay_manager; | |
53 | ||
54 | enum omap_display_type { | |
55 | OMAP_DISPLAY_TYPE_NONE = 0, | |
56 | OMAP_DISPLAY_TYPE_DPI = 1 << 0, | |
57 | OMAP_DISPLAY_TYPE_DBI = 1 << 1, | |
58 | OMAP_DISPLAY_TYPE_SDI = 1 << 2, | |
59 | OMAP_DISPLAY_TYPE_DSI = 1 << 3, | |
60 | OMAP_DISPLAY_TYPE_VENC = 1 << 4, | |
b119601d | 61 | OMAP_DISPLAY_TYPE_HDMI = 1 << 5, |
559d6701 TV |
62 | }; |
63 | ||
64 | enum omap_plane { | |
65 | OMAP_DSS_GFX = 0, | |
66 | OMAP_DSS_VIDEO1 = 1, | |
67 | OMAP_DSS_VIDEO2 = 2 | |
68 | }; | |
69 | ||
70 | enum omap_channel { | |
71 | OMAP_DSS_CHANNEL_LCD = 0, | |
72 | OMAP_DSS_CHANNEL_DIGIT = 1, | |
8613b000 | 73 | OMAP_DSS_CHANNEL_LCD2 = 2, |
559d6701 TV |
74 | }; |
75 | ||
76 | enum omap_color_mode { | |
77 | OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ | |
78 | OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ | |
79 | OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ | |
80 | OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ | |
81 | OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */ | |
82 | OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */ | |
83 | OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */ | |
84 | OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */ | |
85 | OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */ | |
86 | OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ | |
87 | OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ | |
88 | OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ | |
89 | OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ | |
90 | OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ | |
559d6701 TV |
91 | }; |
92 | ||
93 | enum omap_lcd_display_type { | |
94 | OMAP_DSS_LCD_DISPLAY_STN, | |
95 | OMAP_DSS_LCD_DISPLAY_TFT, | |
96 | }; | |
97 | ||
98 | enum omap_dss_load_mode { | |
99 | OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, | |
100 | OMAP_DSS_LOAD_CLUT_ONLY = 1, | |
101 | OMAP_DSS_LOAD_FRAME_ONLY = 2, | |
102 | OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, | |
103 | }; | |
104 | ||
105 | enum omap_dss_trans_key_type { | |
106 | OMAP_DSS_COLOR_KEY_GFX_DST = 0, | |
107 | OMAP_DSS_COLOR_KEY_VID_SRC = 1, | |
108 | }; | |
109 | ||
110 | enum omap_rfbi_te_mode { | |
111 | OMAP_DSS_RFBI_TE_MODE_1 = 1, | |
112 | OMAP_DSS_RFBI_TE_MODE_2 = 2, | |
113 | }; | |
114 | ||
115 | enum omap_panel_config { | |
116 | OMAP_DSS_LCD_IVS = 1<<0, | |
117 | OMAP_DSS_LCD_IHS = 1<<1, | |
118 | OMAP_DSS_LCD_IPC = 1<<2, | |
119 | OMAP_DSS_LCD_IEO = 1<<3, | |
120 | OMAP_DSS_LCD_RF = 1<<4, | |
121 | OMAP_DSS_LCD_ONOFF = 1<<5, | |
122 | ||
123 | OMAP_DSS_LCD_TFT = 1<<20, | |
124 | }; | |
125 | ||
126 | enum omap_dss_venc_type { | |
127 | OMAP_DSS_VENC_TYPE_COMPOSITE, | |
128 | OMAP_DSS_VENC_TYPE_SVIDEO, | |
129 | }; | |
130 | ||
131 | enum omap_display_caps { | |
132 | OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, | |
133 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, | |
134 | }; | |
135 | ||
136 | enum omap_dss_update_mode { | |
137 | OMAP_DSS_UPDATE_DISABLED = 0, | |
138 | OMAP_DSS_UPDATE_AUTO, | |
139 | OMAP_DSS_UPDATE_MANUAL, | |
140 | }; | |
141 | ||
142 | enum omap_dss_display_state { | |
143 | OMAP_DSS_DISPLAY_DISABLED = 0, | |
144 | OMAP_DSS_DISPLAY_ACTIVE, | |
145 | OMAP_DSS_DISPLAY_SUSPENDED, | |
146 | }; | |
147 | ||
148 | /* XXX perhaps this should be removed */ | |
149 | enum omap_dss_overlay_managers { | |
150 | OMAP_DSS_OVL_MGR_LCD, | |
151 | OMAP_DSS_OVL_MGR_TV, | |
8613b000 | 152 | OMAP_DSS_OVL_MGR_LCD2, |
559d6701 TV |
153 | }; |
154 | ||
155 | enum omap_dss_rotation_type { | |
156 | OMAP_DSS_ROT_DMA = 0, | |
157 | OMAP_DSS_ROT_VRFB = 1, | |
158 | }; | |
159 | ||
160 | /* clockwise rotation angle */ | |
161 | enum omap_dss_rotation_angle { | |
162 | OMAP_DSS_ROT_0 = 0, | |
163 | OMAP_DSS_ROT_90 = 1, | |
164 | OMAP_DSS_ROT_180 = 2, | |
165 | OMAP_DSS_ROT_270 = 3, | |
166 | }; | |
167 | ||
168 | enum omap_overlay_caps { | |
169 | OMAP_DSS_OVL_CAP_SCALE = 1 << 0, | |
170 | OMAP_DSS_OVL_CAP_DISPC = 1 << 1, | |
171 | }; | |
172 | ||
173 | enum omap_overlay_manager_caps { | |
174 | OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0, | |
175 | }; | |
176 | ||
177 | /* RFBI */ | |
178 | ||
179 | struct rfbi_timings { | |
180 | int cs_on_time; | |
181 | int cs_off_time; | |
182 | int we_on_time; | |
183 | int we_off_time; | |
184 | int re_on_time; | |
185 | int re_off_time; | |
186 | int we_cycle_time; | |
187 | int re_cycle_time; | |
188 | int cs_pulse_width; | |
189 | int access_time; | |
190 | ||
191 | int clk_div; | |
192 | ||
193 | u32 tim[5]; /* set by rfbi_convert_timings() */ | |
194 | ||
195 | int converted; | |
196 | }; | |
197 | ||
198 | void omap_rfbi_write_command(const void *buf, u32 len); | |
199 | void omap_rfbi_read_data(void *buf, u32 len); | |
200 | void omap_rfbi_write_data(const void *buf, u32 len); | |
201 | void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, | |
202 | u16 x, u16 y, | |
203 | u16 w, u16 h); | |
204 | int omap_rfbi_enable_te(bool enable, unsigned line); | |
205 | int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, | |
206 | unsigned hs_pulse_time, unsigned vs_pulse_time, | |
207 | int hs_pol_inv, int vs_pol_inv, int extif_div); | |
208 | ||
209 | /* DSI */ | |
210 | void dsi_bus_lock(void); | |
211 | void dsi_bus_unlock(void); | |
212 | int dsi_vc_dcs_write(int channel, u8 *data, int len); | |
828c48f8 TV |
213 | int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd); |
214 | int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param); | |
559d6701 TV |
215 | int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len); |
216 | int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen); | |
828c48f8 | 217 | int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data); |
0c244f77 | 218 | int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2); |
559d6701 TV |
219 | int dsi_vc_set_max_rx_packet_size(int channel, u16 len); |
220 | int dsi_vc_send_null(int channel); | |
221 | int dsi_vc_send_bta_sync(int channel); | |
222 | ||
223 | /* Board specific data */ | |
224 | struct omap_dss_board_info { | |
225 | int (*get_last_off_on_transaction_id)(struct device *dev); | |
226 | int num_devices; | |
227 | struct omap_dss_device **devices; | |
228 | struct omap_dss_device *default_device; | |
229 | }; | |
230 | ||
b7ee79ab SS |
231 | #if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS) |
232 | /* Init with the board info */ | |
233 | extern int omap_display_init(struct omap_dss_board_info *board_data); | |
234 | #else | |
235 | static inline int omap_display_init(struct omap_dss_board_info *board_data) | |
236 | { | |
237 | return 0; | |
238 | } | |
239 | #endif | |
240 | ||
cf07f531 SG |
241 | struct omap_display_platform_data { |
242 | struct omap_dss_board_info *board_data; | |
243 | /* TODO: Additional members to be added when PM is considered */ | |
fd4b34f6 SS |
244 | |
245 | bool (*opt_clock_available)(const char *clk_role); | |
cf07f531 SG |
246 | }; |
247 | ||
559d6701 TV |
248 | struct omap_video_timings { |
249 | /* Unit: pixels */ | |
250 | u16 x_res; | |
251 | /* Unit: pixels */ | |
252 | u16 y_res; | |
253 | /* Unit: KHz */ | |
254 | u32 pixel_clock; | |
255 | /* Unit: pixel clocks */ | |
256 | u16 hsw; /* Horizontal synchronization pulse width */ | |
257 | /* Unit: pixel clocks */ | |
258 | u16 hfp; /* Horizontal front porch */ | |
259 | /* Unit: pixel clocks */ | |
260 | u16 hbp; /* Horizontal back porch */ | |
261 | /* Unit: line clocks */ | |
262 | u16 vsw; /* Vertical synchronization pulse width */ | |
263 | /* Unit: line clocks */ | |
264 | u16 vfp; /* Vertical front porch */ | |
265 | /* Unit: line clocks */ | |
266 | u16 vbp; /* Vertical back porch */ | |
267 | }; | |
268 | ||
269 | #ifdef CONFIG_OMAP2_DSS_VENC | |
270 | /* Hardcoded timings for tv modes. Venc only uses these to | |
271 | * identify the mode, and does not actually use the configs | |
272 | * itself. However, the configs should be something that | |
273 | * a normal monitor can also show */ | |
5a1819e3 TK |
274 | extern const struct omap_video_timings omap_dss_pal_timings; |
275 | extern const struct omap_video_timings omap_dss_ntsc_timings; | |
559d6701 TV |
276 | #endif |
277 | ||
278 | struct omap_overlay_info { | |
279 | bool enabled; | |
280 | ||
281 | u32 paddr; | |
282 | void __iomem *vaddr; | |
283 | u16 screen_width; | |
284 | u16 width; | |
285 | u16 height; | |
286 | enum omap_color_mode color_mode; | |
287 | u8 rotation; | |
288 | enum omap_dss_rotation_type rotation_type; | |
289 | bool mirror; | |
290 | ||
291 | u16 pos_x; | |
292 | u16 pos_y; | |
293 | u16 out_width; /* if 0, out_width == width */ | |
294 | u16 out_height; /* if 0, out_height == height */ | |
295 | u8 global_alpha; | |
fd28a390 | 296 | u8 pre_mult_alpha; |
559d6701 TV |
297 | }; |
298 | ||
299 | struct omap_overlay { | |
300 | struct kobject kobj; | |
301 | struct list_head list; | |
302 | ||
303 | /* static fields */ | |
304 | const char *name; | |
305 | int id; | |
306 | enum omap_color_mode supported_modes; | |
307 | enum omap_overlay_caps caps; | |
308 | ||
309 | /* dynamic fields */ | |
310 | struct omap_overlay_manager *manager; | |
311 | struct omap_overlay_info info; | |
312 | ||
313 | /* if true, info has been changed, but not applied() yet */ | |
314 | bool info_dirty; | |
315 | ||
316 | int (*set_manager)(struct omap_overlay *ovl, | |
317 | struct omap_overlay_manager *mgr); | |
318 | int (*unset_manager)(struct omap_overlay *ovl); | |
319 | ||
320 | int (*set_overlay_info)(struct omap_overlay *ovl, | |
321 | struct omap_overlay_info *info); | |
322 | void (*get_overlay_info)(struct omap_overlay *ovl, | |
323 | struct omap_overlay_info *info); | |
324 | ||
325 | int (*wait_for_go)(struct omap_overlay *ovl); | |
326 | }; | |
327 | ||
328 | struct omap_overlay_manager_info { | |
329 | u32 default_color; | |
330 | ||
331 | enum omap_dss_trans_key_type trans_key_type; | |
332 | u32 trans_key; | |
333 | bool trans_enabled; | |
334 | ||
335 | bool alpha_enabled; | |
336 | }; | |
337 | ||
338 | struct omap_overlay_manager { | |
339 | struct kobject kobj; | |
340 | struct list_head list; | |
341 | ||
342 | /* static fields */ | |
343 | const char *name; | |
344 | int id; | |
345 | enum omap_overlay_manager_caps caps; | |
346 | int num_overlays; | |
347 | struct omap_overlay **overlays; | |
348 | enum omap_display_type supported_displays; | |
349 | ||
350 | /* dynamic fields */ | |
351 | struct omap_dss_device *device; | |
352 | struct omap_overlay_manager_info info; | |
353 | ||
354 | bool device_changed; | |
355 | /* if true, info has been changed but not applied() yet */ | |
356 | bool info_dirty; | |
357 | ||
358 | int (*set_device)(struct omap_overlay_manager *mgr, | |
359 | struct omap_dss_device *dssdev); | |
360 | int (*unset_device)(struct omap_overlay_manager *mgr); | |
361 | ||
362 | int (*set_manager_info)(struct omap_overlay_manager *mgr, | |
363 | struct omap_overlay_manager_info *info); | |
364 | void (*get_manager_info)(struct omap_overlay_manager *mgr, | |
365 | struct omap_overlay_manager_info *info); | |
366 | ||
367 | int (*apply)(struct omap_overlay_manager *mgr); | |
368 | int (*wait_for_go)(struct omap_overlay_manager *mgr); | |
3f71cbe7 | 369 | int (*wait_for_vsync)(struct omap_overlay_manager *mgr); |
a2faee84 TV |
370 | |
371 | int (*enable)(struct omap_overlay_manager *mgr); | |
372 | int (*disable)(struct omap_overlay_manager *mgr); | |
559d6701 TV |
373 | }; |
374 | ||
375 | struct omap_dss_device { | |
376 | struct device dev; | |
377 | ||
378 | enum omap_display_type type; | |
379 | ||
18faa1b6 SS |
380 | enum omap_channel channel; |
381 | ||
559d6701 TV |
382 | union { |
383 | struct { | |
384 | u8 data_lines; | |
385 | } dpi; | |
386 | ||
387 | struct { | |
388 | u8 channel; | |
389 | u8 data_lines; | |
390 | } rfbi; | |
391 | ||
392 | struct { | |
393 | u8 datapairs; | |
394 | } sdi; | |
395 | ||
396 | struct { | |
397 | u8 clk_lane; | |
398 | u8 clk_pol; | |
399 | u8 data1_lane; | |
400 | u8 data1_pol; | |
401 | u8 data2_lane; | |
402 | u8 data2_pol; | |
403 | ||
404 | struct { | |
405 | u16 regn; | |
406 | u16 regm; | |
1bb47835 AT |
407 | u16 regm_dispc; |
408 | u16 regm_dsi; | |
559d6701 TV |
409 | |
410 | u16 lp_clk_div; | |
411 | ||
412 | u16 lck_div; | |
413 | u16 pck_div; | |
414 | } div; | |
415 | ||
416 | bool ext_te; | |
417 | u8 ext_te_gpio; | |
418 | } dsi; | |
419 | ||
420 | struct { | |
421 | enum omap_dss_venc_type type; | |
422 | bool invert_polarity; | |
423 | } venc; | |
424 | } phy; | |
425 | ||
426 | struct { | |
427 | struct omap_video_timings timings; | |
428 | ||
429 | int acbi; /* ac-bias pin transitions per interrupt */ | |
430 | /* Unit: line clocks */ | |
431 | int acb; /* ac-bias pin frequency */ | |
432 | ||
433 | enum omap_panel_config config; | |
559d6701 TV |
434 | } panel; |
435 | ||
436 | struct { | |
437 | u8 pixel_size; | |
438 | struct rfbi_timings rfbi_timings; | |
559d6701 TV |
439 | } ctrl; |
440 | ||
441 | int reset_gpio; | |
442 | ||
443 | int max_backlight_level; | |
444 | ||
445 | const char *name; | |
446 | ||
447 | /* used to match device to driver */ | |
448 | const char *driver_name; | |
449 | ||
450 | void *data; | |
451 | ||
452 | struct omap_dss_driver *driver; | |
453 | ||
454 | /* helper variable for driver suspend/resume */ | |
455 | bool activate_after_resume; | |
456 | ||
457 | enum omap_display_caps caps; | |
458 | ||
459 | struct omap_overlay_manager *manager; | |
460 | ||
461 | enum omap_dss_display_state state; | |
462 | ||
559d6701 TV |
463 | /* platform specific */ |
464 | int (*platform_enable)(struct omap_dss_device *dssdev); | |
465 | void (*platform_disable)(struct omap_dss_device *dssdev); | |
466 | int (*set_backlight)(struct omap_dss_device *dssdev, int level); | |
467 | int (*get_backlight)(struct omap_dss_device *dssdev); | |
468 | }; | |
469 | ||
470 | struct omap_dss_driver { | |
471 | struct device_driver driver; | |
472 | ||
473 | int (*probe)(struct omap_dss_device *); | |
474 | void (*remove)(struct omap_dss_device *); | |
475 | ||
476 | int (*enable)(struct omap_dss_device *display); | |
477 | void (*disable)(struct omap_dss_device *display); | |
478 | int (*suspend)(struct omap_dss_device *display); | |
479 | int (*resume)(struct omap_dss_device *display); | |
480 | int (*run_test)(struct omap_dss_device *display, int test); | |
481 | ||
446f7bff TV |
482 | int (*set_update_mode)(struct omap_dss_device *dssdev, |
483 | enum omap_dss_update_mode); | |
484 | enum omap_dss_update_mode (*get_update_mode)( | |
485 | struct omap_dss_device *dssdev); | |
559d6701 | 486 | |
18946f62 TV |
487 | int (*update)(struct omap_dss_device *dssdev, |
488 | u16 x, u16 y, u16 w, u16 h); | |
489 | int (*sync)(struct omap_dss_device *dssdev); | |
490 | ||
559d6701 | 491 | int (*enable_te)(struct omap_dss_device *dssdev, bool enable); |
225b650d | 492 | int (*get_te)(struct omap_dss_device *dssdev); |
559d6701 TV |
493 | |
494 | u8 (*get_rotate)(struct omap_dss_device *dssdev); | |
495 | int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); | |
496 | ||
497 | bool (*get_mirror)(struct omap_dss_device *dssdev); | |
498 | int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); | |
499 | ||
500 | int (*memory_read)(struct omap_dss_device *dssdev, | |
501 | void *buf, size_t size, | |
502 | u16 x, u16 y, u16 w, u16 h); | |
96adcece TV |
503 | |
504 | void (*get_resolution)(struct omap_dss_device *dssdev, | |
505 | u16 *xres, u16 *yres); | |
a2699504 | 506 | int (*get_recommended_bpp)(struct omap_dss_device *dssdev); |
36511312 | 507 | |
69b2048f TV |
508 | int (*check_timings)(struct omap_dss_device *dssdev, |
509 | struct omap_video_timings *timings); | |
510 | void (*set_timings)(struct omap_dss_device *dssdev, | |
511 | struct omap_video_timings *timings); | |
512 | void (*get_timings)(struct omap_dss_device *dssdev, | |
513 | struct omap_video_timings *timings); | |
514 | ||
36511312 TV |
515 | int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); |
516 | u32 (*get_wss)(struct omap_dss_device *dssdev); | |
559d6701 TV |
517 | }; |
518 | ||
519 | int omap_dss_register_driver(struct omap_dss_driver *); | |
520 | void omap_dss_unregister_driver(struct omap_dss_driver *); | |
521 | ||
522 | int omap_dss_register_device(struct omap_dss_device *); | |
523 | void omap_dss_unregister_device(struct omap_dss_device *); | |
524 | ||
525 | void omap_dss_get_device(struct omap_dss_device *dssdev); | |
526 | void omap_dss_put_device(struct omap_dss_device *dssdev); | |
527 | #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) | |
528 | struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); | |
529 | struct omap_dss_device *omap_dss_find_device(void *data, | |
530 | int (*match)(struct omap_dss_device *dssdev, void *data)); | |
531 | ||
532 | int omap_dss_start_device(struct omap_dss_device *dssdev); | |
533 | void omap_dss_stop_device(struct omap_dss_device *dssdev); | |
534 | ||
535 | int omap_dss_get_num_overlay_managers(void); | |
536 | struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); | |
537 | ||
538 | int omap_dss_get_num_overlays(void); | |
539 | struct omap_overlay *omap_dss_get_overlay(int num); | |
540 | ||
96adcece TV |
541 | void omapdss_default_get_resolution(struct omap_dss_device *dssdev, |
542 | u16 *xres, u16 *yres); | |
a2699504 TV |
543 | int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); |
544 | ||
559d6701 TV |
545 | typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); |
546 | int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); | |
547 | int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); | |
548 | ||
549 | int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout); | |
550 | int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, | |
551 | unsigned long timeout); | |
552 | ||
553 | #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver) | |
554 | #define to_dss_device(x) container_of((x), struct omap_dss_device, dev) | |
555 | ||
61140c9a | 556 | void omapdss_dsi_vc_enable_hs(int channel, bool enable); |
225b650d | 557 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable); |
61140c9a | 558 | |
18946f62 | 559 | int omap_dsi_prepare_update(struct omap_dss_device *dssdev, |
26a8c250 TV |
560 | u16 *x, u16 *y, u16 *w, u16 *h, |
561 | bool enlarge_update_area); | |
18946f62 TV |
562 | int omap_dsi_update(struct omap_dss_device *dssdev, |
563 | int channel, | |
564 | u16 x, u16 y, u16 w, u16 h, | |
565 | void (*callback)(int, void *), void *data); | |
5ee3c144 AT |
566 | int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); |
567 | int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); | |
568 | void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); | |
18946f62 | 569 | |
37ac60e4 TV |
570 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); |
571 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev); | |
572 | ||
573 | int omapdss_dpi_display_enable(struct omap_dss_device *dssdev); | |
574 | void omapdss_dpi_display_disable(struct omap_dss_device *dssdev); | |
69b2048f TV |
575 | void dpi_set_timings(struct omap_dss_device *dssdev, |
576 | struct omap_video_timings *timings); | |
577 | int dpi_check_timings(struct omap_dss_device *dssdev, | |
578 | struct omap_video_timings *timings); | |
37ac60e4 TV |
579 | |
580 | int omapdss_sdi_display_enable(struct omap_dss_device *dssdev); | |
581 | void omapdss_sdi_display_disable(struct omap_dss_device *dssdev); | |
582 | ||
583 | int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev); | |
584 | void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev); | |
18946f62 TV |
585 | int omap_rfbi_prepare_update(struct omap_dss_device *dssdev, |
586 | u16 *x, u16 *y, u16 *w, u16 *h); | |
587 | int omap_rfbi_update(struct omap_dss_device *dssdev, | |
588 | u16 x, u16 y, u16 w, u16 h, | |
589 | void (*callback)(void *), void *data); | |
590 | ||
559d6701 | 591 | #endif |