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ARM: OMAP: mcbsp: Start generalize omap2_mcbsp_set_clks_src
[mirror_ubuntu-bionic-kernel.git] / arch / arm / plat-omap / mcbsp.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/device.h>
bc5d0c89 18#include <linux/platform_device.h>
5e1c5ff4
TL		 19#include <linux/interrupt.h>
20#include <linux/err.h>
f8ce2547 21#include <linux/clk.h>
04fbf6a2 22#include <linux/delay.h>
fb78d808 23#include <linux/io.h>
5a0e3ad6 24#include <linux/slab.h>
5e1c5ff4 25
ce491cf8 26#include <plat/mcbsp.h>
e95496d4 27#include <linux/pm_runtime.h>
5e1c5ff4 28
b4b58f58 29struct omap_mcbsp **mcbsp_ptr;
ac6747ca 30int omap_mcbsp_count;
bc5d0c89 31
09d28d2c
JN		 32#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
33#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
34
b0a330dc 35static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
b4b58f58 36{
cdc71514
JN		 37 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
38
39 if (mcbsp->pdata->reg_size == 2) {
40 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
41 __raw_writew((u16)val, addr);
c8c99699 42 } else {
cdc71514
JN		 43 ((u32 *)mcbsp->reg_cache)[reg] = val;
44 __raw_writel(val, addr);
c8c99699 45 }
b4b58f58
CS		 46}
47
b0a330dc 48static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
b4b58f58 49{
cdc71514
JN		 50 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
51
52 if (mcbsp->pdata->reg_size == 2) {
53 return !from_cache ? __raw_readw(addr) :
54 ((u16 *)mcbsp->reg_cache)[reg];
c8c99699 55 } else {
cdc71514
JN		 56 return !from_cache ? __raw_readl(addr) :
57 ((u32 *)mcbsp->reg_cache)[reg];
c8c99699 58 }
b4b58f58
CS		 59}
60
b0a330dc 61static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
d912fa92
EN		 62{
63 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
64}
65
b0a330dc 66static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
d912fa92
EN		 67{
68 return __raw_readl(mcbsp->st_data->io_base_st + reg);
69}
d912fa92 70
8ea3200f 71#define MCBSP_READ(mcbsp, reg) \
c8c99699 72 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
8ea3200f
JK		 73#define MCBSP_WRITE(mcbsp, reg, val) \
74 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
c8c99699
JK		 75#define MCBSP_READ_CACHE(mcbsp, reg) \
76 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
b4b58f58 77
d912fa92
EN		 78#define MCBSP_ST_READ(mcbsp, reg) \
79 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
80#define MCBSP_ST_WRITE(mcbsp, reg, val) \
81 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
82
5e1c5ff4
TL		 83static void omap_mcbsp_dump_reg(u8 id)
84{
b4b58f58
CS		 85 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
86
87 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
88 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
8ea3200f 89 MCBSP_READ(mcbsp, DRR2));
b4b58f58 90 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
8ea3200f 91 MCBSP_READ(mcbsp, DRR1));
b4b58f58 92 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
8ea3200f 93 MCBSP_READ(mcbsp, DXR2));
b4b58f58 94 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
8ea3200f 95 MCBSP_READ(mcbsp, DXR1));
b4b58f58 96 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
8ea3200f 97 MCBSP_READ(mcbsp, SPCR2));
b4b58f58 98 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
8ea3200f 99 MCBSP_READ(mcbsp, SPCR1));
b4b58f58 100 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
8ea3200f 101 MCBSP_READ(mcbsp, RCR2));
b4b58f58 102 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
8ea3200f 103 MCBSP_READ(mcbsp, RCR1));
b4b58f58 104 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
8ea3200f 105 MCBSP_READ(mcbsp, XCR2));
b4b58f58 106 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
8ea3200f 107 MCBSP_READ(mcbsp, XCR1));
b4b58f58 108 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
8ea3200f 109 MCBSP_READ(mcbsp, SRGR2));
b4b58f58 110 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
8ea3200f 111 MCBSP_READ(mcbsp, SRGR1));
b4b58f58 112 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
8ea3200f 113 MCBSP_READ(mcbsp, PCR0));
b4b58f58 114 dev_dbg(mcbsp->dev, "***********************\n");
5e1c5ff4
TL		 115}
116
0cd61b68 117static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
5e1c5ff4 118{
e8f2af17 119 struct omap_mcbsp *mcbsp_tx = dev_id;
d6d834b0 120 u16 irqst_spcr2;
5e1c5ff4 121
8ea3200f 122 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
d6d834b0 123 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
5e1c5ff4 124
d6d834b0
EN		 125 if (irqst_spcr2 & XSYNC_ERR) {
126 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
127 irqst_spcr2);
128 /* Writing zero to XSYNC_ERR clears the IRQ */
0841cb82 129 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
d6d834b0 130 }
fb78d808 131
5e1c5ff4
TL		 132 return IRQ_HANDLED;
133}
134
0cd61b68 135static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
5e1c5ff4 136{
e8f2af17 137 struct omap_mcbsp *mcbsp_rx = dev_id;
d6d834b0
EN		 138 u16 irqst_spcr1;
139
8ea3200f 140 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
d6d834b0
EN		 141 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
142
143 if (irqst_spcr1 & RSYNC_ERR) {
144 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
145 irqst_spcr1);
146 /* Writing zero to RSYNC_ERR clears the IRQ */
0841cb82 147 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
d6d834b0 148 }
fb78d808 149
5e1c5ff4
TL		 150 return IRQ_HANDLED;
151}
152
5e1c5ff4
TL		 153/*
154 * omap_mcbsp_config simply write a config to the
155 * appropriate McBSP.
156 * You either call this function or set the McBSP registers
157 * by yourself before calling omap_mcbsp_start().
158 */
fb78d808 159void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
5e1c5ff4 160{
b4b58f58 161 struct omap_mcbsp *mcbsp;
5e1c5ff4 162
bc5d0c89
EV		 163 if (!omap_mcbsp_check_valid_id(id)) {
164 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
165 return;
166 }
b4b58f58 167 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 168
b4b58f58
CS		 169 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
170 mcbsp->id, mcbsp->phys_base);
5e1c5ff4
TL		 171
172 /* We write the given config */
8ea3200f
JK		 173 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
174 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
175 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
176 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
177 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
178 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
179 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
180 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
181 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
182 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
183 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
88408230 184 if (mcbsp->pdata->has_ccr) {
8ea3200f
JK		 185 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
186 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
3127f8f8 187 }
5e1c5ff4 188}
fb78d808 189EXPORT_SYMBOL(omap_mcbsp_config);
5e1c5ff4 190
9504ba64
KVA		 191/**
192 * omap_mcbsp_dma_params - returns the dma channel number
193 * @id - mcbsp id
194 * @stream - indicates the direction of data flow (rx or tx)
195 *
196 * Returns the dma channel number for the rx channel or tx channel
197 * based on the value of @stream for the requested mcbsp given by @id
198 */
199int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
200{
201 struct omap_mcbsp *mcbsp;
202
203 if (!omap_mcbsp_check_valid_id(id)) {
204 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
205 return -ENODEV;
206 }
207 mcbsp = id_to_mcbsp_ptr(id);
208
209 if (stream)
210 return mcbsp->dma_rx_sync;
211 else
212 return mcbsp->dma_tx_sync;
213}
214EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
215
216/**
217 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
218 * @id - mcbsp id
219 * @stream - indicates the direction of data flow (rx or tx)
220 *
221 * Returns the address of mcbsp data transmit register or data receive register
222 * to be used by DMA for transferring/receiving data based on the value of
223 * @stream for the requested mcbsp given by @id
224 */
225int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
226{
227 struct omap_mcbsp *mcbsp;
228 int data_reg;
229
230 if (!omap_mcbsp_check_valid_id(id)) {
231 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
232 return -ENODEV;
233 }
234 mcbsp = id_to_mcbsp_ptr(id);
235
cdc71514 236 if (mcbsp->pdata->reg_size == 2) {
9504ba64 237 if (stream)
cdc71514 238 data_reg = OMAP_MCBSP_REG_DRR1;
9504ba64 239 else
cdc71514 240 data_reg = OMAP_MCBSP_REG_DXR1;
9504ba64
KVA		 241 } else {
242 if (stream)
cdc71514 243 data_reg = OMAP_MCBSP_REG_DRR;
9504ba64 244 else
cdc71514 245 data_reg = OMAP_MCBSP_REG_DXR;
9504ba64
KVA		 246 }
247
cdc71514 248 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
9504ba64
KVA		 249}
250EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
251
d912fa92
EN		 252static void omap_st_on(struct omap_mcbsp *mcbsp)
253{
254 unsigned int w;
255
1743d14f
JN		 256 if (mcbsp->pdata->enable_st_clock)
257 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
d912fa92
EN		 258
259 /* Enable McBSP Sidetone */
260 w = MCBSP_READ(mcbsp, SSELCR);
261 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
262
d912fa92
EN		 263 /* Enable Sidetone from Sidetone Core */
264 w = MCBSP_ST_READ(mcbsp, SSELCR);
265 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
266}
267
268static void omap_st_off(struct omap_mcbsp *mcbsp)
269{
270 unsigned int w;
271
272 w = MCBSP_ST_READ(mcbsp, SSELCR);
273 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
274
d912fa92
EN		 275 w = MCBSP_READ(mcbsp, SSELCR);
276 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
277
1743d14f
JN		 278 if (mcbsp->pdata->enable_st_clock)
279 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
d912fa92
EN		 280}
281
282static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
283{
284 u16 val, i;
d912fa92
EN		 285
286 val = MCBSP_ST_READ(mcbsp, SSELCR);
287
288 if (val & ST_COEFFWREN)
289 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
290
291 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
292
293 for (i = 0; i < 128; i++)
294 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
295
296 i = 0;
297
298 val = MCBSP_ST_READ(mcbsp, SSELCR);
299 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
300 val = MCBSP_ST_READ(mcbsp, SSELCR);
301
302 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
303
304 if (i == 1000)
305 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
306}
307
308static void omap_st_chgain(struct omap_mcbsp *mcbsp)
309{
310 u16 w;
311 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 312
313 w = MCBSP_ST_READ(mcbsp, SSELCR);
314
315 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
316 ST_CH1GAIN(st_data->ch1gain));
317}
318
319int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
320{
321 struct omap_mcbsp *mcbsp;
322 struct omap_mcbsp_st_data *st_data;
323 int ret = 0;
324
325 if (!omap_mcbsp_check_valid_id(id)) {
326 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
327 return -ENODEV;
328 }
329
330 mcbsp = id_to_mcbsp_ptr(id);
331 st_data = mcbsp->st_data;
332
333 if (!st_data)
334 return -ENOENT;
335
336 spin_lock_irq(&mcbsp->lock);
337 if (channel == 0)
338 st_data->ch0gain = chgain;
339 else if (channel == 1)
340 st_data->ch1gain = chgain;
341 else
342 ret = -EINVAL;
343
344 if (st_data->enabled)
345 omap_st_chgain(mcbsp);
346 spin_unlock_irq(&mcbsp->lock);
347
348 return ret;
349}
350EXPORT_SYMBOL(omap_st_set_chgain);
351
352int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
353{
354 struct omap_mcbsp *mcbsp;
355 struct omap_mcbsp_st_data *st_data;
356 int ret = 0;
357
358 if (!omap_mcbsp_check_valid_id(id)) {
359 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
360 return -ENODEV;
361 }
362
363 mcbsp = id_to_mcbsp_ptr(id);
364 st_data = mcbsp->st_data;
365
366 if (!st_data)
367 return -ENOENT;
368
369 spin_lock_irq(&mcbsp->lock);
370 if (channel == 0)
371 *chgain = st_data->ch0gain;
372 else if (channel == 1)
373 *chgain = st_data->ch1gain;
374 else
375 ret = -EINVAL;
376 spin_unlock_irq(&mcbsp->lock);
377
378 return ret;
379}
380EXPORT_SYMBOL(omap_st_get_chgain);
381
382static int omap_st_start(struct omap_mcbsp *mcbsp)
383{
384 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
385
386 if (st_data && st_data->enabled && !st_data->running) {
387 omap_st_fir_write(mcbsp, st_data->taps);
388 omap_st_chgain(mcbsp);
389
390 if (!mcbsp->free) {
391 omap_st_on(mcbsp);
392 st_data->running = 1;
393 }
394 }
395
396 return 0;
397}
398
399int omap_st_enable(unsigned int id)
400{
401 struct omap_mcbsp *mcbsp;
402 struct omap_mcbsp_st_data *st_data;
403
404 if (!omap_mcbsp_check_valid_id(id)) {
405 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
406 return -ENODEV;
407 }
408
409 mcbsp = id_to_mcbsp_ptr(id);
410 st_data = mcbsp->st_data;
411
412 if (!st_data)
413 return -ENODEV;
414
415 spin_lock_irq(&mcbsp->lock);
416 st_data->enabled = 1;
417 omap_st_start(mcbsp);
418 spin_unlock_irq(&mcbsp->lock);
419
420 return 0;
421}
422EXPORT_SYMBOL(omap_st_enable);
423
424static int omap_st_stop(struct omap_mcbsp *mcbsp)
425{
426 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
427
428 if (st_data && st_data->running) {
429 if (!mcbsp->free) {
430 omap_st_off(mcbsp);
431 st_data->running = 0;
432 }
433 }
434
435 return 0;
436}
437
438int omap_st_disable(unsigned int id)
439{
440 struct omap_mcbsp *mcbsp;
441 struct omap_mcbsp_st_data *st_data;
442 int ret = 0;
443
444 if (!omap_mcbsp_check_valid_id(id)) {
445 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
446 return -ENODEV;
447 }
448
449 mcbsp = id_to_mcbsp_ptr(id);
450 st_data = mcbsp->st_data;
451
452 if (!st_data)
453 return -ENODEV;
454
455 spin_lock_irq(&mcbsp->lock);
456 omap_st_stop(mcbsp);
457 st_data->enabled = 0;
458 spin_unlock_irq(&mcbsp->lock);
459
460 return ret;
461}
462EXPORT_SYMBOL(omap_st_disable);
463
464int omap_st_is_enabled(unsigned int id)
465{
466 struct omap_mcbsp *mcbsp;
467 struct omap_mcbsp_st_data *st_data;
468
469 if (!omap_mcbsp_check_valid_id(id)) {
470 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
471 return -ENODEV;
472 }
473
474 mcbsp = id_to_mcbsp_ptr(id);
475 st_data = mcbsp->st_data;
476
477 if (!st_data)
478 return -ENODEV;
479
480
481 return st_data->enabled;
482}
483EXPORT_SYMBOL(omap_st_is_enabled);
484
7aa9ff56 485/*
451fd82d
PU		 486 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
487 * The threshold parameter is 1 based, and it is converted (threshold - 1)
488 * for the THRSH2 register.
7aa9ff56
EV		 489 */
490void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
491{
492 struct omap_mcbsp *mcbsp;
7aa9ff56 493
7aa9ff56
EV		 494 if (!omap_mcbsp_check_valid_id(id)) {
495 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
496 return;
497 }
498 mcbsp = id_to_mcbsp_ptr(id);
7bba67ab
JN		 499 if (mcbsp->pdata->buffer_size == 0)
500 return;
7aa9ff56 501
451fd82d
PU		 502 if (threshold && threshold <= mcbsp->max_tx_thres)
503 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
7aa9ff56
EV		 504}
505EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
506
507/*
451fd82d
PU		 508 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
509 * The threshold parameter is 1 based, and it is converted (threshold - 1)
510 * for the THRSH1 register.
7aa9ff56
EV		 511 */
512void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
513{
514 struct omap_mcbsp *mcbsp;
7aa9ff56 515
7aa9ff56
EV		 516 if (!omap_mcbsp_check_valid_id(id)) {
517 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
518 return;
519 }
520 mcbsp = id_to_mcbsp_ptr(id);
7bba67ab
JN		 521 if (mcbsp->pdata->buffer_size == 0)
522 return;
7aa9ff56 523
451fd82d
PU		 524 if (threshold && threshold <= mcbsp->max_rx_thres)
525 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
7aa9ff56
EV		 526}
527EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
a1a56f5f
EV		 528
529/*
530 * omap_mcbsp_get_max_tx_thres just return the current configured
531 * maximum threshold for transmission
532 */
533u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
534{
535 struct omap_mcbsp *mcbsp;
536
537 if (!omap_mcbsp_check_valid_id(id)) {
538 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
539 return -ENODEV;
540 }
541 mcbsp = id_to_mcbsp_ptr(id);
542
543 return mcbsp->max_tx_thres;
544}
545EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
546
547/*
548 * omap_mcbsp_get_max_rx_thres just return the current configured
549 * maximum threshold for reception
550 */
551u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
552{
553 struct omap_mcbsp *mcbsp;
554
555 if (!omap_mcbsp_check_valid_id(id)) {
556 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
557 return -ENODEV;
558 }
559 mcbsp = id_to_mcbsp_ptr(id);
560
561 return mcbsp->max_rx_thres;
562}
563EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
98cb20e8 564
0acce82b
PU		 565u16 omap_mcbsp_get_fifo_size(unsigned int id)
566{
567 struct omap_mcbsp *mcbsp;
568
569 if (!omap_mcbsp_check_valid_id(id)) {
570 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
571 return -ENODEV;
572 }
573 mcbsp = id_to_mcbsp_ptr(id);
574
575 return mcbsp->pdata->buffer_size;
576}
577EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
578
7dc976ed
PU		 579/*
580 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
581 */
582u16 omap_mcbsp_get_tx_delay(unsigned int id)
583{
584 struct omap_mcbsp *mcbsp;
585 u16 buffstat;
586
587 if (!omap_mcbsp_check_valid_id(id)) {
588 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
589 return -ENODEV;
590 }
591 mcbsp = id_to_mcbsp_ptr(id);
7bba67ab
JN		 592 if (mcbsp->pdata->buffer_size == 0)
593 return 0;
7dc976ed
PU		 594
595 /* Returns the number of free locations in the buffer */
596 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
597
598 /* Number of slots are different in McBSP ports */
f10b8ad1 599 return mcbsp->pdata->buffer_size - buffstat;
7dc976ed
PU		 600}
601EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
602
603/*
604 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
605 * to reach the threshold value (when the DMA will be triggered to read it)
606 */
607u16 omap_mcbsp_get_rx_delay(unsigned int id)
608{
609 struct omap_mcbsp *mcbsp;
610 u16 buffstat, threshold;
611
612 if (!omap_mcbsp_check_valid_id(id)) {
613 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
614 return -ENODEV;
615 }
616 mcbsp = id_to_mcbsp_ptr(id);
7bba67ab
JN		 617 if (mcbsp->pdata->buffer_size == 0)
618 return 0;
7dc976ed
PU		 619
620 /* Returns the number of used locations in the buffer */
621 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
622 /* RX threshold */
623 threshold = MCBSP_READ(mcbsp, THRSH1);
624
625 /* Return the number of location till we reach the threshold limit */
626 if (threshold <= buffstat)
627 return 0;
628 else
629 return threshold - buffstat;
630}
631EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
632
98cb20e8
PU		 633/*
634 * omap_mcbsp_get_dma_op_mode just return the current configured
635 * operating mode for the mcbsp channel
636 */
637int omap_mcbsp_get_dma_op_mode(unsigned int id)
638{
639 struct omap_mcbsp *mcbsp;
640 int dma_op_mode;
641
642 if (!omap_mcbsp_check_valid_id(id)) {
643 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
644 return -ENODEV;
645 }
646 mcbsp = id_to_mcbsp_ptr(id);
647
98cb20e8 648 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8
PU		 649
650 return dma_op_mode;
651}
652EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
2122fdc6 653
5e1c5ff4
TL		 654int omap_mcbsp_request(unsigned int id)
655{
b4b58f58 656 struct omap_mcbsp *mcbsp;
c8c99699 657 void *reg_cache;
5e1c5ff4
TL		 658 int err;
659
bc5d0c89
EV		 660 if (!omap_mcbsp_check_valid_id(id)) {
661 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
662 return -ENODEV;
120db2cb 663 }
b4b58f58 664 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 665
ac6747ca 666 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
c8c99699
JK		 667 if (!reg_cache) {
668 return -ENOMEM;
669 }
670
b4b58f58
CS		 671 spin_lock(&mcbsp->lock);
672 if (!mcbsp->free) {
673 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
674 mcbsp->id);
c8c99699
JK		 675 err = -EBUSY;
676 goto err_kfree;
5e1c5ff4
TL		 677 }
678
6722a723 679 mcbsp->free = false;
c8c99699 680 mcbsp->reg_cache = reg_cache;
b4b58f58 681 spin_unlock(&mcbsp->lock);
5e1c5ff4 682
b820ce4e
RK		 683 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
684 mcbsp->pdata->ops->request(id);
685
e95496d4 686 pm_runtime_get_sync(mcbsp->dev);
b820ce4e 687
1a645884
JN		 688 /* Enable wakeup behavior */
689 if (mcbsp->pdata->has_wakeup)
690 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
2122fdc6 691
5a07055a
JN		 692 /*
693 * Make sure that transmitter, receiver and sample-rate generator are
694 * not running before activating IRQs.
695 */
8ea3200f
JK		 696 MCBSP_WRITE(mcbsp, SPCR1, 0);
697 MCBSP_WRITE(mcbsp, SPCR2, 0);
5a07055a 698
bafe2721
JN		 699 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
700 0, "McBSP", (void *)mcbsp);
701 if (err != 0) {
702 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
703 "for McBSP%d\n", mcbsp->tx_irq,
704 mcbsp->id);
705 goto err_clk_disable;
706 }
707
708 if (mcbsp->rx_irq) {
709 err = request_irq(mcbsp->rx_irq,
710 omap_mcbsp_rx_irq_handler,
711 0, "McBSP", (void *)mcbsp);
120db2cb 712 if (err != 0) {
bafe2721
JN		 713 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
714 "for McBSP%d\n", mcbsp->rx_irq,
b4b58f58 715 mcbsp->id);
bafe2721 716 goto err_free_irq;
120db2cb 717 }
5e1c5ff4
TL		 718 }
719
5e1c5ff4 720 return 0;
c8c99699 721err_free_irq:
1866b545 722 free_irq(mcbsp->tx_irq, (void *)mcbsp);
c8c99699 723err_clk_disable:
1866b545 724 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
c8c99699 725 mcbsp->pdata->ops->free(id);
1866b545 726
1a645884
JN		 727 /* Disable wakeup behavior */
728 if (mcbsp->pdata->has_wakeup)
729 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
1866b545 730
e95496d4 731 pm_runtime_put_sync(mcbsp->dev);
1866b545 732
c8c99699 733 spin_lock(&mcbsp->lock);
6722a723 734 mcbsp->free = true;
c8c99699
JK		 735 mcbsp->reg_cache = NULL;
736err_kfree:
737 spin_unlock(&mcbsp->lock);
738 kfree(reg_cache);
1866b545
JK		 739
740 return err;
5e1c5ff4 741}
fb78d808 742EXPORT_SYMBOL(omap_mcbsp_request);
5e1c5ff4
TL		 743
744void omap_mcbsp_free(unsigned int id)
745{
b4b58f58 746 struct omap_mcbsp *mcbsp;
c8c99699 747 void *reg_cache;
b4b58f58 748
bc5d0c89
EV		 749 if (!omap_mcbsp_check_valid_id(id)) {
750 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 751 return;
120db2cb 752 }
b4b58f58 753 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 754
b4b58f58
CS		 755 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
756 mcbsp->pdata->ops->free(id);
bc5d0c89 757
1a645884
JN		 758 /* Disable wakeup behavior */
759 if (mcbsp->pdata->has_wakeup)
760 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
2122fdc6 761
e95496d4 762 pm_runtime_put_sync(mcbsp->dev);
b820ce4e 763
bafe2721
JN		 764 if (mcbsp->rx_irq)
765 free_irq(mcbsp->rx_irq, (void *)mcbsp);
766 free_irq(mcbsp->tx_irq, (void *)mcbsp);
5e1c5ff4 767
c8c99699 768 reg_cache = mcbsp->reg_cache;
5e1c5ff4 769
c8c99699
JK		 770 spin_lock(&mcbsp->lock);
771 if (mcbsp->free)
772 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
773 else
6722a723 774 mcbsp->free = true;
c8c99699 775 mcbsp->reg_cache = NULL;
b4b58f58 776 spin_unlock(&mcbsp->lock);
c8c99699
JK		 777
778 if (reg_cache)
779 kfree(reg_cache);
5e1c5ff4 780}
fb78d808 781EXPORT_SYMBOL(omap_mcbsp_free);
5e1c5ff4
TL		 782
783/*
c12abc01
JN		 784 * Here we start the McBSP, by enabling transmitter, receiver or both.
785 * If no transmitter or receiver is active prior calling, then sample-rate
786 * generator and frame sync are started.
5e1c5ff4 787 */
c12abc01 788void omap_mcbsp_start(unsigned int id, int tx, int rx)
5e1c5ff4 789{
b4b58f58 790 struct omap_mcbsp *mcbsp;
ce3f054b 791 int enable_srg = 0;
5e1c5ff4
TL		 792 u16 w;
793
bc5d0c89
EV		 794 if (!omap_mcbsp_check_valid_id(id)) {
795 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 796 return;
bc5d0c89 797 }
b4b58f58 798 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 799
f821eece 800 if (mcbsp->st_data)
d912fa92
EN		 801 omap_st_start(mcbsp);
802
ce3f054b
PU		 803 /* Only enable SRG, if McBSP is master */
804 w = MCBSP_READ_CACHE(mcbsp, PCR0);
805 if (w & (FSXM | FSRM | CLKXM | CLKRM))
806 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
807 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01 808
ce3f054b 809 if (enable_srg) {
c12abc01 810 /* Start the sample generator */
96fbd745 811 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 812 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
c12abc01 813 }
5e1c5ff4
TL		 814
815 /* Enable transmitter and receiver */
d09a2afc 816 tx &= 1;
96fbd745 817 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 818 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
5e1c5ff4 819
d09a2afc 820 rx &= 1;
96fbd745 821 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 822 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
5e1c5ff4 823
44a6311c
EV		 824 /*
825 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
826 * REVISIT: 100us may give enough time for two CLKSRG, however
827 * due to some unknown PM related, clock gating etc. reason it
828 * is now at 500us.
829 */
830 udelay(500);
5e1c5ff4 831
ce3f054b 832 if (enable_srg) {
c12abc01 833 /* Start frame sync */
96fbd745 834 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 835 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
c12abc01 836 }
5e1c5ff4 837
88408230 838 if (mcbsp->pdata->has_ccr) {
d09a2afc 839 /* Release the transmitter and receiver */
96fbd745 840 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 841 w &= ~(tx ? XDISABLE : 0);
8ea3200f 842 MCBSP_WRITE(mcbsp, XCCR, w);
96fbd745 843 w = MCBSP_READ_CACHE(mcbsp, RCCR);
d09a2afc 844 w &= ~(rx ? RDISABLE : 0);
8ea3200f 845 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc
JN		 846 }
847
5e1c5ff4
TL		 848 /* Dump McBSP Regs */
849 omap_mcbsp_dump_reg(id);
5e1c5ff4 850}
fb78d808 851EXPORT_SYMBOL(omap_mcbsp_start);
5e1c5ff4 852
c12abc01 853void omap_mcbsp_stop(unsigned int id, int tx, int rx)
5e1c5ff4 854{
b4b58f58 855 struct omap_mcbsp *mcbsp;
c12abc01 856 int idle;
5e1c5ff4
TL		 857 u16 w;
858
bc5d0c89
EV		 859 if (!omap_mcbsp_check_valid_id(id)) {
860 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 861 return;
bc5d0c89 862 }
5e1c5ff4 863
b4b58f58 864 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 865
fb78d808 866 /* Reset transmitter */
d09a2afc 867 tx &= 1;
88408230 868 if (mcbsp->pdata->has_ccr) {
96fbd745 869 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 870 w |= (tx ? XDISABLE : 0);
8ea3200f 871 MCBSP_WRITE(mcbsp, XCCR, w);
d09a2afc 872 }
96fbd745 873 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 874 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
5e1c5ff4
TL		 875
876 /* Reset receiver */
d09a2afc 877 rx &= 1;
88408230 878 if (mcbsp->pdata->has_ccr) {
96fbd745 879 w = MCBSP_READ_CACHE(mcbsp, RCCR);
a93d4ed2 880 w |= (rx ? RDISABLE : 0);
8ea3200f 881 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc 882 }
96fbd745 883 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 884 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
5e1c5ff4 885
96fbd745
JK		 886 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
887 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01
JN		 888
889 if (idle) {
890 /* Reset the sample rate generator */
96fbd745 891 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 892 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
c12abc01 893 }
d912fa92 894
f821eece 895 if (mcbsp->st_data)
d912fa92 896 omap_st_stop(mcbsp);
5e1c5ff4 897}
fb78d808 898EXPORT_SYMBOL(omap_mcbsp_stop);
5e1c5ff4 899
69d042d1
PW		 900int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
901{
09d28d2c
JN		 902 struct omap_mcbsp *mcbsp;
903 const char *src;
904
905 if (!omap_mcbsp_check_valid_id(id)) {
906 pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
907 return -EINVAL;
908 }
909 mcbsp = id_to_mcbsp_ptr(id);
910
911 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
912 src = "clks_ext";
913 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
914 src = "clks_fclk";
915 else
916 return -EINVAL;
917
918 if (mcbsp->pdata->set_clk_src)
919 return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
920 else
921 return -EINVAL;
69d042d1 922}
09d28d2c 923EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
69d042d1 924
09d28d2c 925#ifndef CONFIG_ARCH_OMAP2PLUS
69d042d1
PW		 926void omap2_mcbsp1_mux_clkr_src(u8 mux)
927{
928 WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
929 __func__);
930 return;
931}
932
933void omap2_mcbsp1_mux_fsr_src(u8 mux)
934{
935 WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
936 __func__);
937 return;
938}
939#endif
940
a1a56f5f
EV		 941#define max_thres(m) (mcbsp->pdata->buffer_size)
942#define valid_threshold(m, val) ((val) <= max_thres(m))
943#define THRESHOLD_PROP_BUILDER(prop) \
944static ssize_t prop##_show(struct device *dev, \
945 struct device_attribute *attr, char *buf) \
946{ \
947 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
948 \
949 return sprintf(buf, "%u\n", mcbsp->prop); \
950} \
951 \
952static ssize_t prop##_store(struct device *dev, \
953 struct device_attribute *attr, \
954 const char *buf, size_t size) \
955{ \
956 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
957 unsigned long val; \
958 int status; \
959 \
960 status = strict_strtoul(buf, 0, &val); \
961 if (status) \
962 return status; \
963 \
964 if (!valid_threshold(mcbsp, val)) \
965 return -EDOM; \
966 \
967 mcbsp->prop = val; \
968 return size; \
969} \
970 \
971static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
972
973THRESHOLD_PROP_BUILDER(max_tx_thres);
974THRESHOLD_PROP_BUILDER(max_rx_thres);
975
9b300509
JN		 976static const char *dma_op_modes[] = {
977 "element", "threshold", "frame",
978};
979
98cb20e8
PU		 980static ssize_t dma_op_mode_show(struct device *dev,
981 struct device_attribute *attr, char *buf)
982{
983 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 984 int dma_op_mode, i = 0;
985 ssize_t len = 0;
986 const char * const *s;
98cb20e8 987
98cb20e8 988 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8 989
9b300509
JN		 990 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
991 if (dma_op_mode == i)
992 len += sprintf(buf + len, "[%s] ", *s);
993 else
994 len += sprintf(buf + len, "%s ", *s);
995 }
996 len += sprintf(buf + len, "\n");
997
998 return len;
98cb20e8
PU		 999}
1000
1001static ssize_t dma_op_mode_store(struct device *dev,
1002 struct device_attribute *attr,
1003 const char *buf, size_t size)
1004{
1005 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 1006 const char * const *s;
1007 int i = 0;
98cb20e8 1008
9b300509
JN		 1009 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1010 if (sysfs_streq(buf, *s))
1011 break;
98cb20e8 1012
9b300509
JN		 1013 if (i == ARRAY_SIZE(dma_op_modes))
1014 return -EINVAL;
98cb20e8 1015
9b300509 1016 spin_lock_irq(&mcbsp->lock);
98cb20e8
PU		 1017 if (!mcbsp->free) {
1018 size = -EBUSY;
1019 goto unlock;
1020 }
9b300509 1021 mcbsp->dma_op_mode = i;
98cb20e8
PU		 1022
1023unlock:
1024 spin_unlock_irq(&mcbsp->lock);
1025
1026 return size;
1027}
1028
1029static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1030
7bba67ab
JN		 1031static const struct attribute *additional_attrs[] = {
1032 &dev_attr_max_tx_thres.attr,
1033 &dev_attr_max_rx_thres.attr,
1034 &dev_attr_dma_op_mode.attr,
1035 NULL,
1036};
1037
1038static const struct attribute_group additional_attr_group = {
1039 .attrs = (struct attribute **)additional_attrs,
1040};
1041
d912fa92
EN		 1042static ssize_t st_taps_show(struct device *dev,
1043 struct device_attribute *attr, char *buf)
1044{
1045 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1046 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1047 ssize_t status = 0;
1048 int i;
1049
1050 spin_lock_irq(&mcbsp->lock);
1051 for (i = 0; i < st_data->nr_taps; i++)
1052 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1053 st_data->taps[i]);
1054 if (i)
1055 status += sprintf(&buf[status], "\n");
1056 spin_unlock_irq(&mcbsp->lock);
1057
1058 return status;
1059}
1060
1061static ssize_t st_taps_store(struct device *dev,
1062 struct device_attribute *attr,
1063 const char *buf, size_t size)
1064{
1065 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1066 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1067 int val, tmp, status, i = 0;
1068
1069 spin_lock_irq(&mcbsp->lock);
1070 memset(st_data->taps, 0, sizeof(st_data->taps));
1071 st_data->nr_taps = 0;
1072
1073 do {
1074 status = sscanf(buf, "%d%n", &val, &tmp);
1075 if (status < 0 || status == 0) {
1076 size = -EINVAL;
1077 goto out;
1078 }
1079 if (val < -32768 || val > 32767) {
1080 size = -EINVAL;
1081 goto out;
1082 }
1083 st_data->taps[i++] = val;
1084 buf += tmp;
1085 if (*buf != ',')
1086 break;
1087 buf++;
1088 } while (1);
1089
1090 st_data->nr_taps = i;
1091
1092out:
1093 spin_unlock_irq(&mcbsp->lock);
1094
1095 return size;
1096}
1097
1098static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1099
d912fa92
EN		 1100static const struct attribute *sidetone_attrs[] = {
1101 &dev_attr_st_taps.attr,
1102 NULL,
1103};
1104
1105static const struct attribute_group sidetone_attr_group = {
1106 .attrs = (struct attribute **)sidetone_attrs,
1107};
1108
f821eece
JN		 1109static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
1110 struct resource *res)
d912fa92 1111{
d912fa92
EN		 1112 struct omap_mcbsp_st_data *st_data;
1113 int err;
1114
1115 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1116 if (!st_data) {
1117 err = -ENOMEM;
1118 goto err1;
1119 }
1120
3cf32bba 1121 st_data->io_base_st = ioremap(res->start, resource_size(res));
d912fa92
EN		 1122 if (!st_data->io_base_st) {
1123 err = -ENOMEM;
1124 goto err2;
1125 }
1126
1127 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1128 if (err)
1129 goto err3;
1130
1131 mcbsp->st_data = st_data;
1132 return 0;
1133
1134err3:
1135 iounmap(st_data->io_base_st);
1136err2:
1137 kfree(st_data);
1138err1:
1139 return err;
1140
1141}
1142
1143static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1144{
1145 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1146
f821eece
JN		 1147 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1148 iounmap(st_data->io_base_st);
1149 kfree(st_data);
a1a56f5f 1150}
a1a56f5f 1151
5e1c5ff4
TL		 1152/*
1153 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1154 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1155 */
25cef225 1156static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
bc5d0c89
EV		 1157{
1158 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
b4b58f58 1159 struct omap_mcbsp *mcbsp;
bc5d0c89 1160 int id = pdev->id - 1;
3cf32bba 1161 struct resource *res;
bc5d0c89 1162 int ret = 0;
5e1c5ff4 1163
bc5d0c89
EV		 1164 if (!pdata) {
1165 dev_err(&pdev->dev, "McBSP device initialized without"
1166 "platform data\n");
1167 ret = -EINVAL;
1168 goto exit;
1169 }
1170
1171 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1172
b4b58f58 1173 if (id >= omap_mcbsp_count) {
bc5d0c89
EV		 1174 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1175 ret = -EINVAL;
1176 goto exit;
1177 }
1178
b4b58f58
CS		 1179 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1180 if (!mcbsp) {
1181 ret = -ENOMEM;
1182 goto exit;
1183 }
b4b58f58
CS		 1184
1185 spin_lock_init(&mcbsp->lock);
1186 mcbsp->id = id + 1;
6722a723 1187 mcbsp->free = true;
bc5d0c89 1188
3cf32bba
KVA		 1189 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1190 if (!res) {
1191 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1192 if (!res) {
1193 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1194 "resource\n", __func__, pdev->id);
1195 ret = -ENOMEM;
1196 goto exit;
1197 }
1198 }
1199 mcbsp->phys_base = res->start;
ac6747ca 1200 mcbsp->reg_cache_size = resource_size(res);
3cf32bba 1201 mcbsp->io_base = ioremap(res->start, resource_size(res));
b4b58f58 1202 if (!mcbsp->io_base) {
d592dd1a
RK		 1203 ret = -ENOMEM;
1204 goto err_ioremap;
1205 }
1206
3cf32bba
KVA		 1207 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1208 if (!res)
1209 mcbsp->phys_dma_base = mcbsp->phys_base;
1210 else
1211 mcbsp->phys_dma_base = res->start;
1212
3cf32bba
KVA		 1213 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1214 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1215
cb7e9ded
KVA		 1216 /* From OMAP4 there will be a single irq line */
1217 if (mcbsp->tx_irq == -ENXIO)
1218 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1219
3cf32bba
KVA		 1220 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1221 if (!res) {
1222 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1223 __func__, pdev->id);
1224 ret = -ENODEV;
1225 goto err_res;
1226 }
1227 mcbsp->dma_rx_sync = res->start;
1228
1229 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1230 if (!res) {
1231 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1232 __func__, pdev->id);
1233 ret = -ENODEV;
1234 goto err_res;
1235 }
1236 mcbsp->dma_tx_sync = res->start;
bc5d0c89 1237
b820ce4e
RK		 1238 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1239 if (IS_ERR(mcbsp->fclk)) {
1240 ret = PTR_ERR(mcbsp->fclk);
1241 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
e95496d4 1242 goto err_res;
bc5d0c89
EV		 1243 }
1244
b4b58f58
CS		 1245 mcbsp->pdata = pdata;
1246 mcbsp->dev = &pdev->dev;
b820ce4e 1247 mcbsp_ptr[id] = mcbsp;
b4b58f58 1248 platform_set_drvdata(pdev, mcbsp);
e95496d4 1249 pm_runtime_enable(mcbsp->dev);
a1a56f5f 1250
7bba67ab
JN		 1251 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1252 if (mcbsp->pdata->buffer_size) {
1253 /*
1254 * Initially configure the maximum thresholds to a safe value.
1255 * The McBSP FIFO usage with these values should not go under
1256 * 16 locations.
1257 * If the whole FIFO without safety buffer is used, than there
1258 * is a possibility that the DMA will be not able to push the
1259 * new data on time, causing channel shifts in runtime.
1260 */
1261 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1262 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1263
1264 ret = sysfs_create_group(&mcbsp->dev->kobj,
1265 &additional_attr_group);
1266 if (ret) {
1267 dev_err(mcbsp->dev,
1268 "Unable to create additional controls\n");
1269 goto err_thres;
1270 }
1271 } else {
1272 mcbsp->max_tx_thres = -EINVAL;
1273 mcbsp->max_rx_thres = -EINVAL;
1274 }
1275
f821eece
JN		 1276 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1277 if (res) {
1278 ret = omap_st_add(mcbsp, res);
1279 if (ret) {
1280 dev_err(mcbsp->dev,
1281 "Unable to create sidetone controls\n");
1282 goto err_st;
1283 }
1284 }
a1a56f5f 1285
d592dd1a 1286 return 0;
bc5d0c89 1287
f821eece
JN		 1288err_st:
1289 if (mcbsp->pdata->buffer_size)
1290 sysfs_remove_group(&mcbsp->dev->kobj,
1291 &additional_attr_group);
7bba67ab
JN		 1292err_thres:
1293 clk_put(mcbsp->fclk);
3cf32bba 1294err_res:
b4b58f58 1295 iounmap(mcbsp->io_base);
d592dd1a 1296err_ioremap:
b820ce4e 1297 kfree(mcbsp);
bc5d0c89
EV		 1298exit:
1299 return ret;
1300}
120db2cb 1301
25cef225 1302static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
5e1c5ff4 1303{
bc5d0c89 1304 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
5e1c5ff4 1305
bc5d0c89
EV		 1306 platform_set_drvdata(pdev, NULL);
1307 if (mcbsp) {
5e1c5ff4 1308
bc5d0c89
EV		 1309 if (mcbsp->pdata && mcbsp->pdata->ops &&
1310 mcbsp->pdata->ops->free)
1311 mcbsp->pdata->ops->free(mcbsp->id);
5e1c5ff4 1312
7bba67ab
JN		 1313 if (mcbsp->pdata->buffer_size)
1314 sysfs_remove_group(&mcbsp->dev->kobj,
1315 &additional_attr_group);
1316
f821eece
JN		 1317 if (mcbsp->st_data)
1318 omap_st_remove(mcbsp);
a1a56f5f 1319
b820ce4e 1320 clk_put(mcbsp->fclk);
bc5d0c89 1321
d592dd1a 1322 iounmap(mcbsp->io_base);
5f3b7284 1323 kfree(mcbsp);
5e1c5ff4
TL		 1324 }
1325
1326 return 0;
1327}
1328
bc5d0c89
EV		 1329static struct platform_driver omap_mcbsp_driver = {
1330 .probe = omap_mcbsp_probe,
25cef225 1331 .remove = __devexit_p(omap_mcbsp_remove),
bc5d0c89
EV		 1332 .driver = {
1333 .name = "omap-mcbsp",
1334 },
1335};
1336
1337int __init omap_mcbsp_init(void)
1338{
1339 /* Register the McBSP driver */
1340 return platform_driver_register(&omap_mcbsp_driver);
1341}
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