[mirror_ubuntu-artful-kernel.git] / arch / arm / plat-omap / sram.c

/*
 * linux/arch/arm/plat-omap/sram.c
 *
 * OMAP SRAM detection and management
 *
 * Copyright (C) 2005 Nokia Corporation
 * Written by Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>

#include <asm/tlb.h>
#include <asm/cacheflush.h>

#include <asm/mach/map.h>

#include <mach/sram.h>
#include <mach/board.h>
#include <mach/cpu.h>

#include <mach/control.h>

#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
# include "../mach-omap2/prm.h"
# include "../mach-omap2/cm.h"
# include "../mach-omap2/sdrc.h"
#endif

#define OMAP1_SRAM_PA		0x20000000
#define OMAP1_SRAM_VA		VMALLOC_END
#define OMAP2_SRAM_PA		0x40200000
#define OMAP2_SRAM_PUB_PA	0x4020f800
#define OMAP2_SRAM_VA		0xe3000000
#define OMAP2_SRAM_PUB_VA	(OMAP2_SRAM_VA + 0x800)
#define OMAP3_SRAM_PA           0x40200000
#define OMAP3_SRAM_VA           0xe3000000
#define OMAP3_SRAM_PUB_PA       0x40208000
#define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
#define OMAP4_SRAM_PA		0x40200000		/*0x402f0000*/
#define OMAP4_SRAM_VA		0xd7000000		/*0xd70f0000*/

#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
#define SRAM_BOOTLOADER_SZ	0x00
#else
#define SRAM_BOOTLOADER_SZ	0x80
#endif

#define OMAP24XX_VA_REQINFOPERM0	IO_ADDRESS(0x68005048)
#define OMAP24XX_VA_READPERM0		IO_ADDRESS(0x68005050)
#define OMAP24XX_VA_WRITEPERM0		IO_ADDRESS(0x68005058)

#define OMAP34XX_VA_REQINFOPERM0	IO_ADDRESS(0x68012848)
#define OMAP34XX_VA_READPERM0		IO_ADDRESS(0x68012850)
#define OMAP34XX_VA_WRITEPERM0		IO_ADDRESS(0x68012858)
#define OMAP34XX_VA_ADDR_MATCH2		IO_ADDRESS(0x68012880)
#define OMAP34XX_VA_SMS_RG_ATT0		IO_ADDRESS(0x6C000048)
#define OMAP34XX_VA_CONTROL_STAT	IO_ADDRESS(0x480022F0)

#define GP_DEVICE		0x300

#define ROUND_DOWN(value,boundary)	((value) & (~((boundary)-1)))

static unsigned long omap_sram_start;
static unsigned long omap_sram_base;
static unsigned long omap_sram_size;
static unsigned long omap_sram_ceil;

extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
					 unsigned long sram_vstart,
					 unsigned long sram_size,
					 unsigned long pstart_avail,
					 unsigned long size_avail);

/*
 * Depending on the target RAMFS firewall setup, the public usable amount of
 * SRAM varies.  The default accessible size for all device types is 2k. A GP
 * device allows ARM11 but not other initiators for full size. This
 * functionality seems ok until some nice security API happens.
 */
static int is_sram_locked(void)
{
	int type = 0;

	if (cpu_is_omap44xx())
		/* Not yet supported */
		return 0;

	if (cpu_is_omap242x())
		type = omap_rev() & OMAP2_DEVICETYPE_MASK;

	if (type == GP_DEVICE) {
		/* RAMFW: R/W access to all initiators for all qualifier sets */
		if (cpu_is_omap242x()) {
			__raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
			__raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
			__raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
		}
		if (cpu_is_omap34xx()) {
			__raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
			__raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
			__raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
			__raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
			__raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
		}
		return 0;
	} else
		return 1; /* assume locked with no PPA or security driver */
}

/*
 * The amount of SRAM depends on the core type.
 * Note that we cannot try to test for SRAM here because writes
 * to secure SRAM will hang the system. Also the SRAM is not
 * yet mapped at this point.
 */
void __init omap_detect_sram(void)
{
	unsigned long reserved;

	if (cpu_class_is_omap2()) {
		if (is_sram_locked()) {
			if (cpu_is_omap34xx()) {
				omap_sram_base = OMAP3_SRAM_PUB_VA;
				omap_sram_start = OMAP3_SRAM_PUB_PA;
				if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
				    (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
					omap_sram_size = 0x7000; /* 28K */
				} else {
					omap_sram_size = 0x8000; /* 32K */
				}
			} else {
				omap_sram_base = OMAP2_SRAM_PUB_VA;
				omap_sram_start = OMAP2_SRAM_PUB_PA;
				omap_sram_size = 0x800; /* 2K */
			}
		} else {
			if (cpu_is_omap34xx()) {
				omap_sram_base = OMAP3_SRAM_VA;
				omap_sram_start = OMAP3_SRAM_PA;
				omap_sram_size = 0x10000; /* 64K */
			} else if (cpu_is_omap44xx()) {
				omap_sram_base = OMAP4_SRAM_VA;
				omap_sram_start = OMAP4_SRAM_PA;
				omap_sram_size = 0x8000; /* 32K */
			} else {
				omap_sram_base = OMAP2_SRAM_VA;
				omap_sram_start = OMAP2_SRAM_PA;
				if (cpu_is_omap242x())
					omap_sram_size = 0xa0000; /* 640K */
				else if (cpu_is_omap243x())
					omap_sram_size = 0x10000; /* 64K */
			}
		}
	} else {
		omap_sram_base = OMAP1_SRAM_VA;
		omap_sram_start = OMAP1_SRAM_PA;

		if (cpu_is_omap7xx())
			omap_sram_size = 0x32000;	/* 200K */
		else if (cpu_is_omap15xx())
			omap_sram_size = 0x30000;	/* 192K */
		else if (cpu_is_omap1610() || cpu_is_omap1621() ||
		     cpu_is_omap1710())
			omap_sram_size = 0x4000;	/* 16K */
		else if (cpu_is_omap1611())
			omap_sram_size = 0x3e800;	/* 250K */
		else {
			printk(KERN_ERR "Could not detect SRAM size\n");
			omap_sram_size = 0x4000;
		}
	}
	reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
				       omap_sram_size,
				       omap_sram_start + SRAM_BOOTLOADER_SZ,
				       omap_sram_size - SRAM_BOOTLOADER_SZ);
	omap_sram_size -= reserved;
	omap_sram_ceil = omap_sram_base + omap_sram_size;
}

static struct map_desc omap_sram_io_desc[] __initdata = {
	{	/* .length gets filled in at runtime */
		.virtual	= OMAP1_SRAM_VA,
		.pfn		= __phys_to_pfn(OMAP1_SRAM_PA),
		.type		= MT_MEMORY
	}
};

/*
 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 */
void __init omap_map_sram(void)
{
	unsigned long base;

	if (omap_sram_size == 0)
		return;

	if (cpu_is_omap24xx()) {
		omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;

		base = OMAP2_SRAM_PA;
		base = ROUND_DOWN(base, PAGE_SIZE);
		omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
	}

	if (cpu_is_omap34xx()) {
		omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
		base = OMAP3_SRAM_PA;
		base = ROUND_DOWN(base, PAGE_SIZE);
		omap_sram_io_desc[0].pfn = __phys_to_pfn(base);

		/*
		 * SRAM must be marked as non-cached on OMAP3 since the
		 * CORE DPLL M2 divider change code (in SRAM) runs with the
		 * SDRAM controller disabled, and if it is marked cached,
		 * the ARM may attempt to write cache lines back to SDRAM
		 * which will cause the system to hang.
		 */
		omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
	}

	if (cpu_is_omap44xx()) {
		omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
		base = OMAP4_SRAM_PA;
		base = ROUND_DOWN(base, PAGE_SIZE);
		omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
	}
	omap_sram_io_desc[0].length = 1024 * 1024;	/* Use section desc */
	iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));

	printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
	__pfn_to_phys(omap_sram_io_desc[0].pfn),
	omap_sram_io_desc[0].virtual,
	       omap_sram_io_desc[0].length);

	/*
	 * Normally devicemaps_init() would flush caches and tlb after
	 * mdesc->map_io(), but since we're called from map_io(), we
	 * must do it here.
	 */
	local_flush_tlb_all();
	flush_cache_all();

	/*
	 * Looks like we need to preserve some bootloader code at the
	 * beginning of SRAM for jumping to flash for reboot to work...
	 */
	memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
	       omap_sram_size - SRAM_BOOTLOADER_SZ);
}

void * omap_sram_push(void * start, unsigned long size)
{
	if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
		printk(KERN_ERR "Not enough space in SRAM\n");
		return NULL;
	}

	omap_sram_ceil -= size;
	omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
	memcpy((void *)omap_sram_ceil, start, size);
	flush_icache_range((unsigned long)start, (unsigned long)(start + size));

	return (void *)omap_sram_ceil;
}

#ifdef CONFIG_ARCH_OMAP1

static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);

void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
{
	BUG_ON(!_omap_sram_reprogram_clock);
	_omap_sram_reprogram_clock(dpllctl, ckctl);
}

int __init omap1_sram_init(void)
{
	_omap_sram_reprogram_clock =
			omap_sram_push(omap1_sram_reprogram_clock,
					omap1_sram_reprogram_clock_sz);

	return 0;
}

#else
#define omap1_sram_init()	do {} while (0)
#endif

#if defined(CONFIG_ARCH_OMAP2)

static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
			      u32 base_cs, u32 force_unlock);

void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
		   u32 base_cs, u32 force_unlock)
{
	BUG_ON(!_omap2_sram_ddr_init);
	_omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
			     base_cs, force_unlock);
}

static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
					  u32 mem_type);

void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
{
	BUG_ON(!_omap2_sram_reprogram_sdrc);
	_omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
}

static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);

u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
{
	BUG_ON(!_omap2_set_prcm);
	return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
}
#endif

#ifdef CONFIG_ARCH_OMAP2420
int __init omap242x_sram_init(void)
{
	_omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
					omap242x_sram_ddr_init_sz);

	_omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
					    omap242x_sram_reprogram_sdrc_sz);

	_omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
					 omap242x_sram_set_prcm_sz);

	return 0;
}
#else
static inline int omap242x_sram_init(void)
{
	return 0;
}
#endif

#ifdef CONFIG_ARCH_OMAP2430
int __init omap243x_sram_init(void)
{
	_omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
					omap243x_sram_ddr_init_sz);

	_omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
					    omap243x_sram_reprogram_sdrc_sz);

	_omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
					 omap243x_sram_set_prcm_sz);

	return 0;
}
#else
static inline int omap243x_sram_init(void)
{
	return 0;
}
#endif

#ifdef CONFIG_ARCH_OMAP3

static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
					      u32 sdrc_actim_ctrla,
					      u32 sdrc_actim_ctrlb,
					      u32 m2, u32 unlock_dll,
					      u32 f, u32 sdrc_mr, u32 inc);
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
			      u32 f, u32 sdrc_mr, u32 inc)
{
	BUG_ON(!_omap3_sram_configure_core_dpll);
	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
					       sdrc_actim_ctrla,
					       sdrc_actim_ctrlb, m2,
					       unlock_dll, f, sdrc_mr, inc);
}

/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
void restore_sram_functions(void)
{
	omap_sram_ceil = omap_sram_base + omap_sram_size;

	_omap3_sram_configure_core_dpll =
		omap_sram_push(omap3_sram_configure_core_dpll,
			       omap3_sram_configure_core_dpll_sz);
}

int __init omap34xx_sram_init(void)
{
	_omap3_sram_configure_core_dpll =
		omap_sram_push(omap3_sram_configure_core_dpll,
			       omap3_sram_configure_core_dpll_sz);

	return 0;
}
#else
static inline int omap34xx_sram_init(void)
{
	return 0;
}
#endif

int __init omap_sram_init(void)
{
	omap_detect_sram();
	omap_map_sram();

	if (!(cpu_class_is_omap2()))
		omap1_sram_init();
	else if (cpu_is_omap242x())
		omap242x_sram_init();
	else if (cpu_is_omap2430())
		omap243x_sram_init();
	else if (cpu_is_omap34xx())
		omap34xx_sram_init();
	else if (cpu_is_omap44xx())
		omap34xx_sram_init(); /* FIXME: */

	return 0;
}
Commit	Line	Data
92105bb7 TL	1	/*
	2	* linux/arch/arm/plat-omap/sram.c
	3	*
	4	* OMAP SRAM detection and management
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Written by Tony Lindgren <tony@atomide.com>
	8	*
44169075 SS	9	* Copyright (C) 2009 Texas Instruments
	10	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	11	*
92105bb7 TL	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
c2d43e39	16	#undef DEBUG
92105bb7	17
92105bb7 TL	18	#include <linux/module.h>
	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
fced80c7	21	#include <linux/io.h>
92105bb7	22
53d9cc73	23	#include <asm/tlb.h>
92105bb7 TL	24	#include <asm/cacheflush.h>
92105bb7 TL	25
670c104a TL	26	#include <asm/mach/map.h>
670c104a TL	27
a09e64fb RK	28	#include <mach/sram.h>
a09e64fb RK	29	#include <mach/board.h>
84a34344	30	#include <mach/cpu.h>
1a8bfa1e	31
a09e64fb	32	#include <mach/control.h>
c2d43e39 TL	33
	34	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3)
	35	# include "../mach-omap2/prm.h"
	36	# include "../mach-omap2/cm.h"
	37	# include "../mach-omap2/sdrc.h"
	38	#endif
	39
1a8bfa1e	40	#define OMAP1_SRAM_PA 0x20000000
c2d43e39	41	#define OMAP1_SRAM_VA VMALLOC_END
1a8bfa1e	42	#define OMAP2_SRAM_PA 0x40200000
670c104a	43	#define OMAP2_SRAM_PUB_PA 0x4020f800
e85c205a MR	44	#define OMAP2_SRAM_VA 0xe3000000
e85c205a MR	45	#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800)
c2d43e39	46	#define OMAP3_SRAM_PA 0x40200000
370bc1fd	47	#define OMAP3_SRAM_VA 0xe3000000
c2d43e39	48	#define OMAP3_SRAM_PUB_PA 0x40208000
370bc1fd	49	#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
44169075 SS	50	#define OMAP4_SRAM_PA 0x40200000 /0x402f0000/
44169075 SS	51	#define OMAP4_SRAM_VA 0xd7000000 /0xd70f0000/
c2d43e39 TL	52
c2d43e39 TL	53	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
670c104a TL	54	#define SRAM_BOOTLOADER_SZ 0x00
670c104a TL	55	#else
92105bb7	56	#define SRAM_BOOTLOADER_SZ 0x80
670c104a TL	57	#endif
670c104a TL	58
c2d43e39 TL	59	#define OMAP24XX_VA_REQINFOPERM0 IO_ADDRESS(0x68005048)
	60	#define OMAP24XX_VA_READPERM0 IO_ADDRESS(0x68005050)
	61	#define OMAP24XX_VA_WRITEPERM0 IO_ADDRESS(0x68005058)
	62
	63	#define OMAP34XX_VA_REQINFOPERM0 IO_ADDRESS(0x68012848)
	64	#define OMAP34XX_VA_READPERM0 IO_ADDRESS(0x68012850)
	65	#define OMAP34XX_VA_WRITEPERM0 IO_ADDRESS(0x68012858)
	66	#define OMAP34XX_VA_ADDR_MATCH2 IO_ADDRESS(0x68012880)
	67	#define OMAP34XX_VA_SMS_RG_ATT0 IO_ADDRESS(0x6C000048)
	68	#define OMAP34XX_VA_CONTROL_STAT IO_ADDRESS(0x480022F0)
	69
670c104a	70	#define GP_DEVICE 0x300
670c104a TL	71
670c104a TL	72	#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
92105bb7	73
c40fae95	74	static unsigned long omap_sram_start;
92105bb7 TL	75	static unsigned long omap_sram_base;
	76	static unsigned long omap_sram_size;
	77	static unsigned long omap_sram_ceil;
	78
b7cc6d46 ID	79	extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
	80	unsigned long sram_vstart,
	81	unsigned long sram_size,
	82	unsigned long pstart_avail,
	83	unsigned long size_avail);
670c104a	84
b7cc6d46 ID	85	/*
b7cc6d46 ID	86	* Depending on the target RAMFS firewall setup, the public usable amount of
6cbdc8c5 SA	87	* SRAM varies. The default accessible size for all device types is 2k. A GP
6cbdc8c5 SA	88	* device allows ARM11 but not other initiators for full size. This
670c104a TL	89	* functionality seems ok until some nice security API happens.
	90	*/
	91	static int is_sram_locked(void)
	92	{
	93	int type = 0;
	94
44169075 SS	95	if (cpu_is_omap44xx())
	96	/* Not yet supported */
	97	return 0;
	98
670c104a	99	if (cpu_is_omap242x())
84a34344	100	type = omap_rev() & OMAP2_DEVICETYPE_MASK;
670c104a TL	101
670c104a TL	102	if (type == GP_DEVICE) {
6cbdc8c5	103	/* RAMFW: R/W access to all initiators for all qualifier sets */
670c104a	104	if (cpu_is_omap242x()) {
c2d43e39 TL	105	__raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
	106	__raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
	107	__raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
	108	}
	109	if (cpu_is_omap34xx()) {
	110	__raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
	111	__raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
	112	__raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
	113	__raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
	114	__raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
670c104a TL	115	}
	116	return 0;
	117	} else
	118	return 1; /* assume locked with no PPA or security driver */
	119	}
	120
92105bb7	121	/*
1a8bfa1e	122	* The amount of SRAM depends on the core type.
92105bb7 TL	123	* Note that we cannot try to test for SRAM here because writes
	124	* to secure SRAM will hang the system. Also the SRAM is not
	125	* yet mapped at this point.
	126	*/
	127	void __init omap_detect_sram(void)
	128	{
b7cc6d46	129	unsigned long reserved;
670c104a	130
c2d43e39	131	if (cpu_class_is_omap2()) {
670c104a	132	if (is_sram_locked()) {
c2d43e39 TL	133	if (cpu_is_omap34xx()) {
	134	omap_sram_base = OMAP3_SRAM_PUB_VA;
	135	omap_sram_start = OMAP3_SRAM_PUB_PA;
5b0acc59 TK	136	if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) \|\|
	137	(omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
	138	omap_sram_size = 0x7000; /* 28K */
	139	} else {
	140	omap_sram_size = 0x8000; /* 32K */
	141	}
c2d43e39 TL	142	} else {
	143	omap_sram_base = OMAP2_SRAM_PUB_VA;
	144	omap_sram_start = OMAP2_SRAM_PUB_PA;
	145	omap_sram_size = 0x800; /* 2K */
	146	}
670c104a	147	} else {
c2d43e39 TL	148	if (cpu_is_omap34xx()) {
	149	omap_sram_base = OMAP3_SRAM_VA;
	150	omap_sram_start = OMAP3_SRAM_PA;
670c104a	151	omap_sram_size = 0x10000; /* 64K */
44169075 SS	152	} else if (cpu_is_omap44xx()) {
	153	omap_sram_base = OMAP4_SRAM_VA;
	154	omap_sram_start = OMAP4_SRAM_PA;
	155	omap_sram_size = 0x8000; /* 32K */
c2d43e39 TL	156	} else {
	157	omap_sram_base = OMAP2_SRAM_VA;
	158	omap_sram_start = OMAP2_SRAM_PA;
	159	if (cpu_is_omap242x())
	160	omap_sram_size = 0xa0000; /* 640K */
	161	else if (cpu_is_omap243x())
	162	omap_sram_size = 0x10000; /* 64K */
	163	}
670c104a TL	164	}
670c104a TL	165	} else {
1a8bfa1e	166	omap_sram_base = OMAP1_SRAM_VA;
c40fae95	167	omap_sram_start = OMAP1_SRAM_PA;
670c104a	168
557096fe	169	if (cpu_is_omap7xx())
670c104a TL	170	omap_sram_size = 0x32000; /* 200K */
	171	else if (cpu_is_omap15xx())
	172	omap_sram_size = 0x30000; /* 192K */
	173	else if (cpu_is_omap1610() \|\| cpu_is_omap1621() \|\|
	174	cpu_is_omap1710())
	175	omap_sram_size = 0x4000; /* 16K */
	176	else if (cpu_is_omap1611())
	177	omap_sram_size = 0x3e800; /* 250K */
	178	else {
	179	printk(KERN_ERR "Could not detect SRAM size\n");
	180	omap_sram_size = 0x4000;
	181	}
92105bb7	182	}
b7cc6d46 ID	183	reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
	184	omap_sram_size,
	185	omap_sram_start + SRAM_BOOTLOADER_SZ,
	186	omap_sram_size - SRAM_BOOTLOADER_SZ);
	187	omap_sram_size -= reserved;
92105bb7 TL	188	omap_sram_ceil = omap_sram_base + omap_sram_size;
	189	}
	190
	191	static struct map_desc omap_sram_io_desc[] __initdata = {
9fe133b1	192	{ /* .length gets filled in at runtime */
1a8bfa1e TL	193	.virtual = OMAP1_SRAM_VA,
1a8bfa1e TL	194	.pfn = __phys_to_pfn(OMAP1_SRAM_PA),
ce2deca2	195	.type = MT_MEMORY
9fe133b1	196	}
92105bb7 TL	197	};
	198
	199	/*
ce2deca2	200	* Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
92105bb7 TL	201	*/
	202	void __init omap_map_sram(void)
	203	{
670c104a TL	204	unsigned long base;
670c104a TL	205
92105bb7 TL	206	if (omap_sram_size == 0)
	207	return;
	208
1a8bfa1e TL	209	if (cpu_is_omap24xx()) {
1a8bfa1e TL	210	omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
670c104a	211
d1284b5f	212	base = OMAP2_SRAM_PA;
670c104a TL	213	base = ROUND_DOWN(base, PAGE_SIZE);
670c104a TL	214	omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
1a8bfa1e TL	215	}
1a8bfa1e TL	216
c2d43e39 TL	217	if (cpu_is_omap34xx()) {
	218	omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
	219	base = OMAP3_SRAM_PA;
	220	base = ROUND_DOWN(base, PAGE_SIZE);
	221	omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
d9295746 PW	222
	223	/*
	224	* SRAM must be marked as non-cached on OMAP3 since the
	225	* CORE DPLL M2 divider change code (in SRAM) runs with the
	226	* SDRAM controller disabled, and if it is marked cached,
	227	* the ARM may attempt to write cache lines back to SDRAM
	228	* which will cause the system to hang.
	229	*/
	230	omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
c2d43e39 TL	231	}
c2d43e39 TL	232
44169075 SS	233	if (cpu_is_omap44xx()) {
	234	omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
	235	base = OMAP4_SRAM_PA;
	236	base = ROUND_DOWN(base, PAGE_SIZE);
	237	omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
	238	}
ce2deca2	239	omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
92105bb7 TL	240	iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
92105bb7 TL	241
1a8bfa1e	242	printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
670c104a TL	243	__pfn_to_phys(omap_sram_io_desc[0].pfn),
670c104a TL	244	omap_sram_io_desc[0].virtual,
1a8bfa1e TL	245	omap_sram_io_desc[0].length);
1a8bfa1e TL	246
53d9cc73 TL	247	/*
	248	* Normally devicemaps_init() would flush caches and tlb after
	249	* mdesc->map_io(), but since we're called from map_io(), we
	250	* must do it here.
	251	*/
	252	local_flush_tlb_all();
	253	flush_cache_all();
	254
92105bb7 TL	255	/*
	256	* Looks like we need to preserve some bootloader code at the
	257	* beginning of SRAM for jumping to flash for reboot to work...
	258	*/
	259	memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
	260	omap_sram_size - SRAM_BOOTLOADER_SZ);
	261	}
	262
92105bb7 TL	263	void * omap_sram_push(void * start, unsigned long size)
	264	{
	265	if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
	266	printk(KERN_ERR "Not enough space in SRAM\n");
	267	return NULL;
	268	}
670c104a	269
92105bb7	270	omap_sram_ceil -= size;
670c104a	271	omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
92105bb7	272	memcpy((void *)omap_sram_ceil, start, size);
c2d43e39	273	flush_icache_range((unsigned long)start, (unsigned long)(start + size));
92105bb7 TL	274
	275	return (void *)omap_sram_ceil;
	276	}
	277
1a8bfa1e TL	278	#ifdef CONFIG_ARCH_OMAP1
	279
	280	static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
	281
	282	void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
	283	{
da7a0649	284	BUG_ON(!_omap_sram_reprogram_clock);
020f9706	285	_omap_sram_reprogram_clock(dpllctl, ckctl);
1a8bfa1e TL	286	}
	287
	288	int __init omap1_sram_init(void)
92105bb7	289	{
c2d43e39 TL	290	_omap_sram_reprogram_clock =
	291	omap_sram_push(omap1_sram_reprogram_clock,
	292	omap1_sram_reprogram_clock_sz);
1a8bfa1e TL	293
	294	return 0;
	295	}
	296
	297	#else
	298	#define omap1_sram_init() do {} while (0)
	299	#endif
	300
cc26b3b0	301	#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e TL	302
	303	static void (_omap2_sram_ddr_init)(u32 slow_dll_ctrl, u32 fast_dll_ctrl,
	304	u32 base_cs, u32 force_unlock);
	305
	306	void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
	307	u32 base_cs, u32 force_unlock)
	308	{
da7a0649	309	BUG_ON(!_omap2_sram_ddr_init);
020f9706 RK	310	_omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
020f9706 RK	311	base_cs, force_unlock);
1a8bfa1e TL	312	}
	313
	314	static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
	315	u32 mem_type);
	316
	317	void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
	318	{
da7a0649	319	BUG_ON(!_omap2_sram_reprogram_sdrc);
020f9706	320	_omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
1a8bfa1e TL	321	}
	322
	323	static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
	324
	325	u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
	326	{
da7a0649	327	BUG_ON(!_omap2_set_prcm);
1a8bfa1e TL	328	return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
1a8bfa1e TL	329	}
c2d43e39 TL	330	#endif
	331
	332	#ifdef CONFIG_ARCH_OMAP2420
	333	int __init omap242x_sram_init(void)
	334	{
	335	_omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
	336	omap242x_sram_ddr_init_sz);
	337
	338	_omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
	339	omap242x_sram_reprogram_sdrc_sz);
	340
	341	_omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
	342	omap242x_sram_set_prcm_sz);
	343
	344	return 0;
	345	}
	346	#else
	347	static inline int omap242x_sram_init(void)
	348	{
	349	return 0;
	350	}
	351	#endif
	352
	353	#ifdef CONFIG_ARCH_OMAP2430
	354	int __init omap243x_sram_init(void)
	355	{
	356	_omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
	357	omap243x_sram_ddr_init_sz);
	358
	359	_omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
	360	omap243x_sram_reprogram_sdrc_sz);
	361
	362	_omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
	363	omap243x_sram_set_prcm_sz);
	364
	365	return 0;
	366	}
	367	#else
	368	static inline int omap243x_sram_init(void)
	369	{
	370	return 0;
	371	}
	372	#endif
	373
	374	#ifdef CONFIG_ARCH_OMAP3
	375
cc26b3b0 SMK	376	static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
	377	u32 sdrc_actim_ctrla,
	378	u32 sdrc_actim_ctrlb,
c9812d04	379	u32 m2, u32 unlock_dll,
3afec633	380	u32 f, u32 sdrc_mr, u32 inc);
cc26b3b0	381	u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
c9812d04	382	u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
3afec633	383	u32 f, u32 sdrc_mr, u32 inc)
c2d43e39	384	{
da7a0649	385	BUG_ON(!_omap3_sram_configure_core_dpll);
cc26b3b0 SMK	386	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
cc26b3b0 SMK	387	sdrc_actim_ctrla,
4519c2bf	388	sdrc_actim_ctrlb, m2,
3afec633	389	unlock_dll, f, sdrc_mr, inc);
c2d43e39	390	}
1a8bfa1e	391
c2d43e39 TL	392	/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
c2d43e39 TL	393	void restore_sram_functions(void)
1a8bfa1e	394	{
c2d43e39	395	omap_sram_ceil = omap_sram_base + omap_sram_size;
1a8bfa1e	396
cc26b3b0 SMK	397	_omap3_sram_configure_core_dpll =
	398	omap_sram_push(omap3_sram_configure_core_dpll,
	399	omap3_sram_configure_core_dpll_sz);
c2d43e39 TL	400	}
	401
	402	int __init omap34xx_sram_init(void)
	403	{
cc26b3b0 SMK	404	_omap3_sram_configure_core_dpll =
	405	omap_sram_push(omap3_sram_configure_core_dpll,
	406	omap3_sram_configure_core_dpll_sz);
1a8bfa1e TL	407
	408	return 0;
	409	}
	410	#else
c2d43e39 TL	411	static inline int omap34xx_sram_init(void)
	412	{
	413	return 0;
	414	}
1a8bfa1e TL	415	#endif
	416
	417	int __init omap_sram_init(void)
	418	{
	419	omap_detect_sram();
	420	omap_map_sram();
	421
c2d43e39	422	if (!(cpu_class_is_omap2()))
1a8bfa1e	423	omap1_sram_init();
c2d43e39 TL	424	else if (cpu_is_omap242x())
	425	omap242x_sram_init();
	426	else if (cpu_is_omap2430())
	427	omap243x_sram_init();
	428	else if (cpu_is_omap34xx())
	429	omap34xx_sram_init();
44169075 SS	430	else if (cpu_is_omap44xx())
44169075 SS	431	omap34xx_sram_init(); /* FIXME: */
1a8bfa1e TL	432
1a8bfa1e TL	433	return 0;
92105bb7	434	}