[mirror_ubuntu-artful-kernel.git] / arch / arm / plat-omap / sram.c

/*
 * linux/arch/arm/plat-omap/sram.c
 *
 * OMAP SRAM detection and management
 *
 * Copyright (C) 2005 Nokia Corporation
 * Written by Tony Lindgren <tony@atomide.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>

#include <asm/tlb.h>
#include <asm/io.h>
#include <asm/cacheflush.h>

#include <asm/mach/map.h>

#include <asm/arch/sram.h>
#include <asm/arch/board.h>

#include <asm/arch/control.h>

#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
# include "../mach-omap2/prm.h"
# include "../mach-omap2/cm.h"
# include "../mach-omap2/sdrc.h"
#endif

#define OMAP1_SRAM_PA		0x20000000
#define OMAP1_SRAM_VA		VMALLOC_END
#define OMAP2_SRAM_PA		0x40200000
#define OMAP2_SRAM_PUB_PA	0x4020f800
#define OMAP2_SRAM_VA		VMALLOC_END
#define OMAP2_SRAM_PUB_VA	(VMALLOC_END + 0x800)
#define OMAP3_SRAM_PA           0x40200000
#define OMAP3_SRAM_VA           0xd7000000
#define OMAP3_SRAM_PUB_PA       0x40208000
#define OMAP3_SRAM_PUB_VA       0xd7008000

#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
#define SRAM_BOOTLOADER_SZ	0x00
#else
#define SRAM_BOOTLOADER_SZ	0x80
#endif

#define OMAP24XX_VA_REQINFOPERM0	IO_ADDRESS(0x68005048)
#define OMAP24XX_VA_READPERM0		IO_ADDRESS(0x68005050)
#define OMAP24XX_VA_WRITEPERM0		IO_ADDRESS(0x68005058)

#define OMAP34XX_VA_REQINFOPERM0	IO_ADDRESS(0x68012848)
#define OMAP34XX_VA_READPERM0		IO_ADDRESS(0x68012850)
#define OMAP34XX_VA_WRITEPERM0		IO_ADDRESS(0x68012858)
#define OMAP34XX_VA_ADDR_MATCH2		IO_ADDRESS(0x68012880)
#define OMAP34XX_VA_SMS_RG_ATT0		IO_ADDRESS(0x6C000048)
#define OMAP34XX_VA_CONTROL_STAT	IO_ADDRESS(0x480022F0)

#define GP_DEVICE		0x300

#define ROUND_DOWN(value,boundary)	((value) & (~((boundary)-1)))

static unsigned long omap_sram_start;
static unsigned long omap_sram_base;
static unsigned long omap_sram_size;
static unsigned long omap_sram_ceil;

extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
					 unsigned long sram_vstart,
					 unsigned long sram_size,
					 unsigned long pstart_avail,
					 unsigned long size_avail);

/*
 * Depending on the target RAMFS firewall setup, the public usable amount of
 * SRAM varies.  The default accessible size for all device types is 2k. A GP
 * device allows ARM11 but not other initiators for full size. This
 * functionality seems ok until some nice security API happens.
 */
static int is_sram_locked(void)
{
	int type = 0;

	if (cpu_is_omap242x())
		type = system_rev & OMAP2_DEVICETYPE_MASK;

	if (type == GP_DEVICE) {
		/* RAMFW: R/W access to all initiators for all qualifier sets */
		if (cpu_is_omap242x()) {
			__raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
			__raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
			__raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
		}
		if (cpu_is_omap34xx()) {
			__raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
			__raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
			__raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
			__raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
			__raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
		}
		return 0;
	} else
		return 1; /* assume locked with no PPA or security driver */
}

/*
 * The amount of SRAM depends on the core type.
 * Note that we cannot try to test for SRAM here because writes
 * to secure SRAM will hang the system. Also the SRAM is not
 * yet mapped at this point.
 */
void __init omap_detect_sram(void)
{
	unsigned long reserved;

	if (cpu_class_is_omap2()) {
		if (is_sram_locked()) {
			if (cpu_is_omap34xx()) {
				omap_sram_base = OMAP3_SRAM_PUB_VA;
				omap_sram_start = OMAP3_SRAM_PUB_PA;
				omap_sram_size = 0x8000; /* 32K */
			} else {
				omap_sram_base = OMAP2_SRAM_PUB_VA;
				omap_sram_start = OMAP2_SRAM_PUB_PA;
				omap_sram_size = 0x800; /* 2K */
			}
		} else {
			if (cpu_is_omap34xx()) {
				omap_sram_base = OMAP3_SRAM_VA;
				omap_sram_start = OMAP3_SRAM_PA;
				omap_sram_size = 0x10000; /* 64K */
			} else {
				omap_sram_base = OMAP2_SRAM_VA;
				omap_sram_start = OMAP2_SRAM_PA;
				if (cpu_is_omap242x())
					omap_sram_size = 0xa0000; /* 640K */
				else if (cpu_is_omap243x())
					omap_sram_size = 0x10000; /* 64K */
			}
		}
	} else {
		omap_sram_base = OMAP1_SRAM_VA;
		omap_sram_start = OMAP1_SRAM_PA;

		if (cpu_is_omap730())
			omap_sram_size = 0x32000;	/* 200K */
		else if (cpu_is_omap15xx())
			omap_sram_size = 0x30000;	/* 192K */
		else if (cpu_is_omap1610() || cpu_is_omap1621() ||
		     cpu_is_omap1710())
			omap_sram_size = 0x4000;	/* 16K */
		else if (cpu_is_omap1611())
			omap_sram_size = 0x3e800;	/* 250K */
		else {
			printk(KERN_ERR "Could not detect SRAM size\n");
			omap_sram_size = 0x4000;
		}
	}
	reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
				       omap_sram_size,
				       omap_sram_start + SRAM_BOOTLOADER_SZ,
				       omap_sram_size - SRAM_BOOTLOADER_SZ);
	omap_sram_size -= reserved;
	omap_sram_ceil = omap_sram_base + omap_sram_size;
}

static struct map_desc omap_sram_io_desc[] __initdata = {
	{	/* .length gets filled in at runtime */
		.virtual	= OMAP1_SRAM_VA,
		.pfn		= __phys_to_pfn(OMAP1_SRAM_PA),
		.type		= MT_MEMORY
	}
};

/*
 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 */
void __init omap_map_sram(void)
{
	unsigned long base;

	if (omap_sram_size == 0)
		return;

	if (cpu_is_omap24xx()) {
		omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;

		base = OMAP2_SRAM_PA;
		base = ROUND_DOWN(base, PAGE_SIZE);
		omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
	}

	if (cpu_is_omap34xx()) {
		omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
		base = OMAP3_SRAM_PA;
		base = ROUND_DOWN(base, PAGE_SIZE);
		omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
	}

	omap_sram_io_desc[0].length = 1024 * 1024;	/* Use section desc */
	iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));

	printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
	__pfn_to_phys(omap_sram_io_desc[0].pfn),
	omap_sram_io_desc[0].virtual,
	       omap_sram_io_desc[0].length);

	/*
	 * Normally devicemaps_init() would flush caches and tlb after
	 * mdesc->map_io(), but since we're called from map_io(), we
	 * must do it here.
	 */
	local_flush_tlb_all();
	flush_cache_all();

	/*
	 * Looks like we need to preserve some bootloader code at the
	 * beginning of SRAM for jumping to flash for reboot to work...
	 */
	memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
	       omap_sram_size - SRAM_BOOTLOADER_SZ);
}

void * omap_sram_push(void * start, unsigned long size)
{
	if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
		printk(KERN_ERR "Not enough space in SRAM\n");
		return NULL;
	}

	omap_sram_ceil -= size;
	omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
	memcpy((void *)omap_sram_ceil, start, size);
	flush_icache_range((unsigned long)start, (unsigned long)(start + size));

	return (void *)omap_sram_ceil;
}

static void omap_sram_error(void)
{
	panic("Uninitialized SRAM function\n");
}

#ifdef CONFIG_ARCH_OMAP1

static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);

void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
{
	if (!_omap_sram_reprogram_clock)
		omap_sram_error();

	return _omap_sram_reprogram_clock(dpllctl, ckctl);
}

int __init omap1_sram_init(void)
{
	_omap_sram_reprogram_clock =
			omap_sram_push(omap1_sram_reprogram_clock,
					omap1_sram_reprogram_clock_sz);

	return 0;
}

#else
#define omap1_sram_init()	do {} while (0)
#endif

#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)

static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
			      u32 base_cs, u32 force_unlock);

void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
		   u32 base_cs, u32 force_unlock)
{
	if (!_omap2_sram_ddr_init)
		omap_sram_error();

	return _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
				    base_cs, force_unlock);
}

static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
					  u32 mem_type);

void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
{
	if (!_omap2_sram_reprogram_sdrc)
		omap_sram_error();

	return _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
}

static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);

u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
{
	if (!_omap2_set_prcm)
		omap_sram_error();

	return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
}
#endif

#ifdef CONFIG_ARCH_OMAP2420
int __init omap242x_sram_init(void)
{
	_omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
					omap242x_sram_ddr_init_sz);

	_omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
					    omap242x_sram_reprogram_sdrc_sz);

	_omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
					 omap242x_sram_set_prcm_sz);

	return 0;
}
#else
static inline int omap242x_sram_init(void)
{
	return 0;
}
#endif

#ifdef CONFIG_ARCH_OMAP2430
int __init omap243x_sram_init(void)
{
	_omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
					omap243x_sram_ddr_init_sz);

	_omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
					    omap243x_sram_reprogram_sdrc_sz);

	_omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
					 omap243x_sram_set_prcm_sz);

	return 0;
}
#else
static inline int omap243x_sram_init(void)
{
	return 0;
}
#endif

#ifdef CONFIG_ARCH_OMAP3

static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level);
u32 omap2_sram_reprogram_gpmc(u32 perf_level)
{
	if (!_omap2_sram_reprogram_gpmc)
		omap_sram_error();

	return _omap2_sram_reprogram_gpmc(perf_level);
}

static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
						u32 freqsel, u32 m2);
u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
{
	if (!_omap2_sram_configure_core_dpll)
		omap_sram_error();

	return _omap2_sram_configure_core_dpll(m, n, freqsel, m2);
}

/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
void restore_sram_functions(void)
{
	omap_sram_ceil = omap_sram_base + omap_sram_size;

	_omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
		omap34xx_sram_reprogram_gpmc_sz);

	_omap2_sram_configure_core_dpll =
			omap_sram_push(omap34xx_sram_configure_core_dpll,
					omap34xx_sram_configure_core_dpll_sz);
}

int __init omap34xx_sram_init(void)
{
	_omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init,
					omap34xx_sram_ddr_init_sz);

	_omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
					omap34xx_sram_reprogram_sdrc_sz);

	_omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
					omap34xx_sram_set_prcm_sz);

	_omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
					omap34xx_sram_reprogram_gpmc_sz);

	_omap2_sram_configure_core_dpll =
				omap_sram_push(omap34xx_sram_configure_core_dpll,
					omap34xx_sram_configure_core_dpll_sz);

	return 0;
}
#else
static inline int omap34xx_sram_init(void)
{
	return 0;
}
#endif

int __init omap_sram_init(void)
{
	omap_detect_sram();
	omap_map_sram();

	if (!(cpu_class_is_omap2()))
		omap1_sram_init();
	else if (cpu_is_omap242x())
		omap242x_sram_init();
	else if (cpu_is_omap2430())
		omap243x_sram_init();
	else if (cpu_is_omap34xx())
		omap34xx_sram_init();

	return 0;
}
Commit	Line	Data
92105bb7 TL	1	/*
	2	* linux/arch/arm/plat-omap/sram.c
	3	*
	4	* OMAP SRAM detection and management
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Written by Tony Lindgren <tony@atomide.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
c2d43e39	13	#undef DEBUG
92105bb7	14
92105bb7 TL	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
	18
53d9cc73	19	#include <asm/tlb.h>
92105bb7 TL	20	#include <asm/io.h>
	21	#include <asm/cacheflush.h>
	22
670c104a TL	23	#include <asm/mach/map.h>
670c104a TL	24
1a8bfa1e	25	#include <asm/arch/sram.h>
670c104a	26	#include <asm/arch/board.h>
1a8bfa1e	27
c2d43e39 TL	28	#include <asm/arch/control.h>
	29
	30	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3)
	31	# include "../mach-omap2/prm.h"
	32	# include "../mach-omap2/cm.h"
	33	# include "../mach-omap2/sdrc.h"
	34	#endif
	35
1a8bfa1e	36	#define OMAP1_SRAM_PA 0x20000000
c2d43e39	37	#define OMAP1_SRAM_VA VMALLOC_END
1a8bfa1e	38	#define OMAP2_SRAM_PA 0x40200000
670c104a	39	#define OMAP2_SRAM_PUB_PA 0x4020f800
c2d43e39 TL	40	#define OMAP2_SRAM_VA VMALLOC_END
	41	#define OMAP2_SRAM_PUB_VA (VMALLOC_END + 0x800)
	42	#define OMAP3_SRAM_PA 0x40200000
	43	#define OMAP3_SRAM_VA 0xd7000000
	44	#define OMAP3_SRAM_PUB_PA 0x40208000
	45	#define OMAP3_SRAM_PUB_VA 0xd7008000
	46
	47	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
670c104a TL	48	#define SRAM_BOOTLOADER_SZ 0x00
670c104a TL	49	#else
92105bb7	50	#define SRAM_BOOTLOADER_SZ 0x80
670c104a TL	51	#endif
670c104a TL	52
c2d43e39 TL	53	#define OMAP24XX_VA_REQINFOPERM0 IO_ADDRESS(0x68005048)
	54	#define OMAP24XX_VA_READPERM0 IO_ADDRESS(0x68005050)
	55	#define OMAP24XX_VA_WRITEPERM0 IO_ADDRESS(0x68005058)
	56
	57	#define OMAP34XX_VA_REQINFOPERM0 IO_ADDRESS(0x68012848)
	58	#define OMAP34XX_VA_READPERM0 IO_ADDRESS(0x68012850)
	59	#define OMAP34XX_VA_WRITEPERM0 IO_ADDRESS(0x68012858)
	60	#define OMAP34XX_VA_ADDR_MATCH2 IO_ADDRESS(0x68012880)
	61	#define OMAP34XX_VA_SMS_RG_ATT0 IO_ADDRESS(0x6C000048)
	62	#define OMAP34XX_VA_CONTROL_STAT IO_ADDRESS(0x480022F0)
	63
670c104a	64	#define GP_DEVICE 0x300
670c104a TL	65
670c104a TL	66	#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
92105bb7	67
c40fae95	68	static unsigned long omap_sram_start;
92105bb7 TL	69	static unsigned long omap_sram_base;
	70	static unsigned long omap_sram_size;
	71	static unsigned long omap_sram_ceil;
	72
b7cc6d46 ID	73	extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
	74	unsigned long sram_vstart,
	75	unsigned long sram_size,
	76	unsigned long pstart_avail,
	77	unsigned long size_avail);
670c104a	78
b7cc6d46 ID	79	/*
b7cc6d46 ID	80	* Depending on the target RAMFS firewall setup, the public usable amount of
6cbdc8c5 SA	81	* SRAM varies. The default accessible size for all device types is 2k. A GP
6cbdc8c5 SA	82	* device allows ARM11 but not other initiators for full size. This
670c104a TL	83	* functionality seems ok until some nice security API happens.
	84	*/
	85	static int is_sram_locked(void)
	86	{
	87	int type = 0;
	88
	89	if (cpu_is_omap242x())
c2d43e39	90	type = system_rev & OMAP2_DEVICETYPE_MASK;
670c104a TL	91
670c104a TL	92	if (type == GP_DEVICE) {
6cbdc8c5	93	/* RAMFW: R/W access to all initiators for all qualifier sets */
670c104a	94	if (cpu_is_omap242x()) {
c2d43e39 TL	95	__raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
	96	__raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
	97	__raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
	98	}
	99	if (cpu_is_omap34xx()) {
	100	__raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
	101	__raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
	102	__raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
	103	__raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
	104	__raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
670c104a TL	105	}
	106	return 0;
	107	} else
	108	return 1; /* assume locked with no PPA or security driver */
	109	}
	110
92105bb7	111	/*
1a8bfa1e	112	* The amount of SRAM depends on the core type.
92105bb7 TL	113	* Note that we cannot try to test for SRAM here because writes
	114	* to secure SRAM will hang the system. Also the SRAM is not
	115	* yet mapped at this point.
	116	*/
	117	void __init omap_detect_sram(void)
	118	{
b7cc6d46	119	unsigned long reserved;
670c104a	120
c2d43e39	121	if (cpu_class_is_omap2()) {
670c104a	122	if (is_sram_locked()) {
c2d43e39 TL	123	if (cpu_is_omap34xx()) {
	124	omap_sram_base = OMAP3_SRAM_PUB_VA;
	125	omap_sram_start = OMAP3_SRAM_PUB_PA;
	126	omap_sram_size = 0x8000; /* 32K */
	127	} else {
	128	omap_sram_base = OMAP2_SRAM_PUB_VA;
	129	omap_sram_start = OMAP2_SRAM_PUB_PA;
	130	omap_sram_size = 0x800; /* 2K */
	131	}
670c104a	132	} else {
c2d43e39 TL	133	if (cpu_is_omap34xx()) {
	134	omap_sram_base = OMAP3_SRAM_VA;
	135	omap_sram_start = OMAP3_SRAM_PA;
670c104a	136	omap_sram_size = 0x10000; /* 64K */
c2d43e39 TL	137	} else {
	138	omap_sram_base = OMAP2_SRAM_VA;
	139	omap_sram_start = OMAP2_SRAM_PA;
	140	if (cpu_is_omap242x())
	141	omap_sram_size = 0xa0000; /* 640K */
	142	else if (cpu_is_omap243x())
	143	omap_sram_size = 0x10000; /* 64K */
	144	}
670c104a TL	145	}
670c104a TL	146	} else {
1a8bfa1e	147	omap_sram_base = OMAP1_SRAM_VA;
c40fae95	148	omap_sram_start = OMAP1_SRAM_PA;
670c104a TL	149
	150	if (cpu_is_omap730())
	151	omap_sram_size = 0x32000; /* 200K */
	152	else if (cpu_is_omap15xx())
	153	omap_sram_size = 0x30000; /* 192K */
	154	else if (cpu_is_omap1610() \|\| cpu_is_omap1621() \|\|
	155	cpu_is_omap1710())
	156	omap_sram_size = 0x4000; /* 16K */
	157	else if (cpu_is_omap1611())
	158	omap_sram_size = 0x3e800; /* 250K */
	159	else {
	160	printk(KERN_ERR "Could not detect SRAM size\n");
	161	omap_sram_size = 0x4000;
	162	}
92105bb7	163	}
b7cc6d46 ID	164	reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
	165	omap_sram_size,
	166	omap_sram_start + SRAM_BOOTLOADER_SZ,
	167	omap_sram_size - SRAM_BOOTLOADER_SZ);
	168	omap_sram_size -= reserved;
92105bb7 TL	169	omap_sram_ceil = omap_sram_base + omap_sram_size;
	170	}
	171
	172	static struct map_desc omap_sram_io_desc[] __initdata = {
9fe133b1	173	{ /* .length gets filled in at runtime */
1a8bfa1e TL	174	.virtual = OMAP1_SRAM_VA,
1a8bfa1e TL	175	.pfn = __phys_to_pfn(OMAP1_SRAM_PA),
ce2deca2	176	.type = MT_MEMORY
9fe133b1	177	}
92105bb7 TL	178	};
	179
	180	/*
ce2deca2	181	* Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
92105bb7 TL	182	*/
	183	void __init omap_map_sram(void)
	184	{
670c104a TL	185	unsigned long base;
670c104a TL	186
92105bb7 TL	187	if (omap_sram_size == 0)
	188	return;
	189
1a8bfa1e TL	190	if (cpu_is_omap24xx()) {
1a8bfa1e TL	191	omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
670c104a	192
d1284b5f	193	base = OMAP2_SRAM_PA;
670c104a TL	194	base = ROUND_DOWN(base, PAGE_SIZE);
670c104a TL	195	omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
1a8bfa1e TL	196	}
1a8bfa1e TL	197
c2d43e39 TL	198	if (cpu_is_omap34xx()) {
	199	omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
	200	base = OMAP3_SRAM_PA;
	201	base = ROUND_DOWN(base, PAGE_SIZE);
	202	omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
	203	}
	204
ce2deca2	205	omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
92105bb7 TL	206	iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
92105bb7 TL	207
1a8bfa1e	208	printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
670c104a TL	209	__pfn_to_phys(omap_sram_io_desc[0].pfn),
670c104a TL	210	omap_sram_io_desc[0].virtual,
1a8bfa1e TL	211	omap_sram_io_desc[0].length);
1a8bfa1e TL	212
53d9cc73 TL	213	/*
	214	* Normally devicemaps_init() would flush caches and tlb after
	215	* mdesc->map_io(), but since we're called from map_io(), we
	216	* must do it here.
	217	*/
	218	local_flush_tlb_all();
	219	flush_cache_all();
	220
92105bb7 TL	221	/*
	222	* Looks like we need to preserve some bootloader code at the
	223	* beginning of SRAM for jumping to flash for reboot to work...
	224	*/
	225	memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
	226	omap_sram_size - SRAM_BOOTLOADER_SZ);
	227	}
	228
92105bb7 TL	229	void * omap_sram_push(void * start, unsigned long size)
	230	{
	231	if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
	232	printk(KERN_ERR "Not enough space in SRAM\n");
	233	return NULL;
	234	}
670c104a	235
92105bb7	236	omap_sram_ceil -= size;
670c104a	237	omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
92105bb7	238	memcpy((void *)omap_sram_ceil, start, size);
c2d43e39	239	flush_icache_range((unsigned long)start, (unsigned long)(start + size));
92105bb7 TL	240
	241	return (void *)omap_sram_ceil;
	242	}
	243
1a8bfa1e TL	244	static void omap_sram_error(void)
	245	{
	246	panic("Uninitialized SRAM function\n");
	247	}
	248
	249	#ifdef CONFIG_ARCH_OMAP1
	250
	251	static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
	252
	253	void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
	254	{
	255	if (!_omap_sram_reprogram_clock)
	256	omap_sram_error();
	257
	258	return _omap_sram_reprogram_clock(dpllctl, ckctl);
	259	}
	260
	261	int __init omap1_sram_init(void)
92105bb7	262	{
c2d43e39 TL	263	_omap_sram_reprogram_clock =
	264	omap_sram_push(omap1_sram_reprogram_clock,
	265	omap1_sram_reprogram_clock_sz);
1a8bfa1e TL	266
	267	return 0;
	268	}
	269
	270	#else
	271	#define omap1_sram_init() do {} while (0)
	272	#endif
	273
c2d43e39	274	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3)
1a8bfa1e TL	275
	276	static void (_omap2_sram_ddr_init)(u32 slow_dll_ctrl, u32 fast_dll_ctrl,
	277	u32 base_cs, u32 force_unlock);
	278
	279	void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
	280	u32 base_cs, u32 force_unlock)
	281	{
	282	if (!_omap2_sram_ddr_init)
	283	omap_sram_error();
	284
	285	return _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
	286	base_cs, force_unlock);
	287	}
	288
	289	static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
	290	u32 mem_type);
	291
	292	void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
	293	{
	294	if (!_omap2_sram_reprogram_sdrc)
	295	omap_sram_error();
	296
	297	return _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
	298	}
	299
	300	static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
	301
	302	u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
	303	{
	304	if (!_omap2_set_prcm)
	305	omap_sram_error();
	306
	307	return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
	308	}
c2d43e39 TL	309	#endif
	310
	311	#ifdef CONFIG_ARCH_OMAP2420
	312	int __init omap242x_sram_init(void)
	313	{
	314	_omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
	315	omap242x_sram_ddr_init_sz);
	316
	317	_omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
	318	omap242x_sram_reprogram_sdrc_sz);
	319
	320	_omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
	321	omap242x_sram_set_prcm_sz);
	322
	323	return 0;
	324	}
	325	#else
	326	static inline int omap242x_sram_init(void)
	327	{
	328	return 0;
	329	}
	330	#endif
	331
	332	#ifdef CONFIG_ARCH_OMAP2430
	333	int __init omap243x_sram_init(void)
	334	{
	335	_omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
	336	omap243x_sram_ddr_init_sz);
	337
	338	_omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
	339	omap243x_sram_reprogram_sdrc_sz);
	340
	341	_omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
	342	omap243x_sram_set_prcm_sz);
	343
	344	return 0;
	345	}
	346	#else
	347	static inline int omap243x_sram_init(void)
	348	{
	349	return 0;
	350	}
	351	#endif
	352
	353	#ifdef CONFIG_ARCH_OMAP3
	354
	355	static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level);
	356	u32 omap2_sram_reprogram_gpmc(u32 perf_level)
	357	{
	358	if (!_omap2_sram_reprogram_gpmc)
	359	omap_sram_error();
	360
	361	return _omap2_sram_reprogram_gpmc(perf_level);
	362	}
	363
	364	static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
	365	u32 freqsel, u32 m2);
	366	u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
	367	{
	368	if (!_omap2_sram_configure_core_dpll)
	369	omap_sram_error();
	370
	371	return _omap2_sram_configure_core_dpll(m, n, freqsel, m2);
	372	}
1a8bfa1e	373
c2d43e39 TL	374	/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
c2d43e39 TL	375	void restore_sram_functions(void)
1a8bfa1e	376	{
c2d43e39	377	omap_sram_ceil = omap_sram_base + omap_sram_size;
1a8bfa1e	378
c2d43e39 TL	379	_omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
	380	omap34xx_sram_reprogram_gpmc_sz);
	381
	382	_omap2_sram_configure_core_dpll =
	383	omap_sram_push(omap34xx_sram_configure_core_dpll,
	384	omap34xx_sram_configure_core_dpll_sz);
	385	}
	386
	387	int __init omap34xx_sram_init(void)
	388	{
	389	_omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init,
	390	omap34xx_sram_ddr_init_sz);
	391
	392	_omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
	393	omap34xx_sram_reprogram_sdrc_sz);
	394
	395	_omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
	396	omap34xx_sram_set_prcm_sz);
	397
	398	_omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
	399	omap34xx_sram_reprogram_gpmc_sz);
	400
	401	_omap2_sram_configure_core_dpll =
	402	omap_sram_push(omap34xx_sram_configure_core_dpll,
	403	omap34xx_sram_configure_core_dpll_sz);
1a8bfa1e TL	404
	405	return 0;
	406	}
	407	#else
c2d43e39 TL	408	static inline int omap34xx_sram_init(void)
	409	{
	410	return 0;
	411	}
1a8bfa1e TL	412	#endif
	413
	414	int __init omap_sram_init(void)
	415	{
	416	omap_detect_sram();
	417	omap_map_sram();
	418
c2d43e39	419	if (!(cpu_class_is_omap2()))
1a8bfa1e	420	omap1_sram_init();
c2d43e39 TL	421	else if (cpu_is_omap242x())
	422	omap242x_sram_init();
	423	else if (cpu_is_omap2430())
	424	omap243x_sram_init();
	425	else if (cpu_is_omap34xx())
	426	omap34xx_sram_init();
1a8bfa1e TL	427
1a8bfa1e TL	428	return 0;
92105bb7	429	}