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92105bb7 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/sram.c | |
3 | * | |
4 | * OMAP SRAM detection and management | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
44169075 SS |
9 | * Copyright (C) 2009 Texas Instruments |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
11 | * | |
92105bb7 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
c2d43e39 | 16 | #undef DEBUG |
92105bb7 | 17 | |
92105bb7 TL |
18 | #include <linux/module.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/init.h> | |
fced80c7 | 21 | #include <linux/io.h> |
b0a330dc | 22 | #include <linux/omapfb.h> |
92105bb7 | 23 | |
53d9cc73 | 24 | #include <asm/tlb.h> |
92105bb7 TL |
25 | #include <asm/cacheflush.h> |
26 | ||
670c104a TL |
27 | #include <asm/mach/map.h> |
28 | ||
ce491cf8 TL |
29 | #include <plat/sram.h> |
30 | #include <plat/board.h> | |
31 | #include <plat/cpu.h> | |
afedec18 | 32 | #include <plat/vram.h> |
1a8bfa1e | 33 | |
b0a330dc MK |
34 | #include "sram.h" |
35 | #include "fb.h" | |
59fb659b PW |
36 | |
37 | /* XXX These "sideways" includes are a sign that something is wrong */ | |
c2d43e39 | 38 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
59fb659b | 39 | # include "../mach-omap2/prm2xxx_3xxx.h" |
c2d43e39 TL |
40 | # include "../mach-omap2/sdrc.h" |
41 | #endif | |
42 | ||
1a8bfa1e | 43 | #define OMAP1_SRAM_PA 0x20000000 |
c2d43e39 | 44 | #define OMAP1_SRAM_VA VMALLOC_END |
b4b36fd9 | 45 | #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800) |
e49b8244 | 46 | #define OMAP2_SRAM_VA 0xfe400000 |
e85c205a | 47 | #define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800) |
e49b8244 | 48 | #define OMAP3_SRAM_VA 0xfe400000 |
b4b36fd9 | 49 | #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000) |
370bc1fd | 50 | #define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000) |
a7c3ae2c SS |
51 | #define OMAP4_SRAM_VA 0xfe400000 |
52 | #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) | |
53 | #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) | |
c2d43e39 | 54 | |
f47d8c69 | 55 | #if defined(CONFIG_ARCH_OMAP2PLUS) |
670c104a TL |
56 | #define SRAM_BOOTLOADER_SZ 0x00 |
57 | #else | |
92105bb7 | 58 | #define SRAM_BOOTLOADER_SZ 0x80 |
670c104a TL |
59 | #endif |
60 | ||
233fd64e SS |
61 | #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048) |
62 | #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050) | |
63 | #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058) | |
c2d43e39 | 64 | |
233fd64e SS |
65 | #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848) |
66 | #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850) | |
67 | #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858) | |
68 | #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880) | |
69 | #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048) | |
c2d43e39 | 70 | |
670c104a | 71 | #define GP_DEVICE 0x300 |
670c104a TL |
72 | |
73 | #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) | |
92105bb7 | 74 | |
c40fae95 | 75 | static unsigned long omap_sram_start; |
92105bb7 TL |
76 | static unsigned long omap_sram_base; |
77 | static unsigned long omap_sram_size; | |
78 | static unsigned long omap_sram_ceil; | |
79 | ||
b7cc6d46 ID |
80 | /* |
81 | * Depending on the target RAMFS firewall setup, the public usable amount of | |
6cbdc8c5 SA |
82 | * SRAM varies. The default accessible size for all device types is 2k. A GP |
83 | * device allows ARM11 but not other initiators for full size. This | |
670c104a TL |
84 | * functionality seems ok until some nice security API happens. |
85 | */ | |
86 | static int is_sram_locked(void) | |
87 | { | |
2a27753f | 88 | if (OMAP2_DEVICE_TYPE_GP == omap_type()) { |
6cbdc8c5 | 89 | /* RAMFW: R/W access to all initiators for all qualifier sets */ |
670c104a | 90 | if (cpu_is_omap242x()) { |
c2d43e39 TL |
91 | __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ |
92 | __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */ | |
93 | __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */ | |
94 | } | |
95 | if (cpu_is_omap34xx()) { | |
96 | __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */ | |
97 | __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */ | |
98 | __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */ | |
99 | __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2); | |
100 | __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0); | |
670c104a TL |
101 | } |
102 | return 0; | |
103 | } else | |
104 | return 1; /* assume locked with no PPA or security driver */ | |
105 | } | |
106 | ||
92105bb7 | 107 | /* |
1a8bfa1e | 108 | * The amount of SRAM depends on the core type. |
92105bb7 TL |
109 | * Note that we cannot try to test for SRAM here because writes |
110 | * to secure SRAM will hang the system. Also the SRAM is not | |
111 | * yet mapped at this point. | |
112 | */ | |
b0a330dc | 113 | static void __init omap_detect_sram(void) |
92105bb7 | 114 | { |
b7cc6d46 | 115 | unsigned long reserved; |
670c104a | 116 | |
c2d43e39 | 117 | if (cpu_class_is_omap2()) { |
670c104a | 118 | if (is_sram_locked()) { |
c2d43e39 TL |
119 | if (cpu_is_omap34xx()) { |
120 | omap_sram_base = OMAP3_SRAM_PUB_VA; | |
121 | omap_sram_start = OMAP3_SRAM_PUB_PA; | |
5b0acc59 TK |
122 | if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || |
123 | (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { | |
124 | omap_sram_size = 0x7000; /* 28K */ | |
125 | } else { | |
126 | omap_sram_size = 0x8000; /* 32K */ | |
127 | } | |
a7c3ae2c SS |
128 | } else if (cpu_is_omap44xx()) { |
129 | omap_sram_base = OMAP4_SRAM_PUB_VA; | |
130 | omap_sram_start = OMAP4_SRAM_PUB_PA; | |
131 | omap_sram_size = 0xa000; /* 40K */ | |
c2d43e39 TL |
132 | } else { |
133 | omap_sram_base = OMAP2_SRAM_PUB_VA; | |
134 | omap_sram_start = OMAP2_SRAM_PUB_PA; | |
135 | omap_sram_size = 0x800; /* 2K */ | |
136 | } | |
670c104a | 137 | } else { |
c2d43e39 TL |
138 | if (cpu_is_omap34xx()) { |
139 | omap_sram_base = OMAP3_SRAM_VA; | |
140 | omap_sram_start = OMAP3_SRAM_PA; | |
670c104a | 141 | omap_sram_size = 0x10000; /* 64K */ |
44169075 SS |
142 | } else if (cpu_is_omap44xx()) { |
143 | omap_sram_base = OMAP4_SRAM_VA; | |
144 | omap_sram_start = OMAP4_SRAM_PA; | |
a7c3ae2c | 145 | omap_sram_size = 0xe000; /* 56K */ |
c2d43e39 TL |
146 | } else { |
147 | omap_sram_base = OMAP2_SRAM_VA; | |
148 | omap_sram_start = OMAP2_SRAM_PA; | |
149 | if (cpu_is_omap242x()) | |
150 | omap_sram_size = 0xa0000; /* 640K */ | |
151 | else if (cpu_is_omap243x()) | |
152 | omap_sram_size = 0x10000; /* 64K */ | |
153 | } | |
670c104a TL |
154 | } |
155 | } else { | |
1a8bfa1e | 156 | omap_sram_base = OMAP1_SRAM_VA; |
c40fae95 | 157 | omap_sram_start = OMAP1_SRAM_PA; |
670c104a | 158 | |
557096fe | 159 | if (cpu_is_omap7xx()) |
670c104a TL |
160 | omap_sram_size = 0x32000; /* 200K */ |
161 | else if (cpu_is_omap15xx()) | |
162 | omap_sram_size = 0x30000; /* 192K */ | |
163 | else if (cpu_is_omap1610() || cpu_is_omap1621() || | |
164 | cpu_is_omap1710()) | |
165 | omap_sram_size = 0x4000; /* 16K */ | |
166 | else if (cpu_is_omap1611()) | |
28dd3198 | 167 | omap_sram_size = SZ_256K; |
670c104a TL |
168 | else { |
169 | printk(KERN_ERR "Could not detect SRAM size\n"); | |
170 | omap_sram_size = 0x4000; | |
171 | } | |
92105bb7 | 172 | } |
b7cc6d46 ID |
173 | reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base, |
174 | omap_sram_size, | |
175 | omap_sram_start + SRAM_BOOTLOADER_SZ, | |
176 | omap_sram_size - SRAM_BOOTLOADER_SZ); | |
177 | omap_sram_size -= reserved; | |
afedec18 TV |
178 | |
179 | reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base, | |
180 | omap_sram_size, | |
181 | omap_sram_start + SRAM_BOOTLOADER_SZ, | |
182 | omap_sram_size - SRAM_BOOTLOADER_SZ); | |
183 | omap_sram_size -= reserved; | |
184 | ||
92105bb7 TL |
185 | omap_sram_ceil = omap_sram_base + omap_sram_size; |
186 | } | |
187 | ||
188 | static struct map_desc omap_sram_io_desc[] __initdata = { | |
9fe133b1 | 189 | { /* .length gets filled in at runtime */ |
1a8bfa1e TL |
190 | .virtual = OMAP1_SRAM_VA, |
191 | .pfn = __phys_to_pfn(OMAP1_SRAM_PA), | |
ce2deca2 | 192 | .type = MT_MEMORY |
9fe133b1 | 193 | } |
92105bb7 TL |
194 | }; |
195 | ||
196 | /* | |
ce2deca2 | 197 | * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early. |
92105bb7 | 198 | */ |
b0a330dc | 199 | static void __init omap_map_sram(void) |
92105bb7 | 200 | { |
670c104a TL |
201 | unsigned long base; |
202 | ||
92105bb7 TL |
203 | if (omap_sram_size == 0) |
204 | return; | |
205 | ||
c2d43e39 | 206 | if (cpu_is_omap34xx()) { |
d9295746 PW |
207 | /* |
208 | * SRAM must be marked as non-cached on OMAP3 since the | |
209 | * CORE DPLL M2 divider change code (in SRAM) runs with the | |
210 | * SDRAM controller disabled, and if it is marked cached, | |
211 | * the ARM may attempt to write cache lines back to SDRAM | |
212 | * which will cause the system to hang. | |
213 | */ | |
214 | omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED; | |
c2d43e39 TL |
215 | } |
216 | ||
e546f21b SS |
217 | omap_sram_io_desc[0].virtual = omap_sram_base; |
218 | base = omap_sram_start; | |
219 | base = ROUND_DOWN(base, PAGE_SIZE); | |
220 | omap_sram_io_desc[0].pfn = __phys_to_pfn(base); | |
221 | omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE); | |
92105bb7 TL |
222 | iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); |
223 | ||
1a8bfa1e | 224 | printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n", |
670c104a TL |
225 | __pfn_to_phys(omap_sram_io_desc[0].pfn), |
226 | omap_sram_io_desc[0].virtual, | |
1a8bfa1e TL |
227 | omap_sram_io_desc[0].length); |
228 | ||
53d9cc73 TL |
229 | /* |
230 | * Normally devicemaps_init() would flush caches and tlb after | |
231 | * mdesc->map_io(), but since we're called from map_io(), we | |
232 | * must do it here. | |
233 | */ | |
234 | local_flush_tlb_all(); | |
235 | flush_cache_all(); | |
236 | ||
92105bb7 TL |
237 | /* |
238 | * Looks like we need to preserve some bootloader code at the | |
239 | * beginning of SRAM for jumping to flash for reboot to work... | |
240 | */ | |
241 | memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0, | |
242 | omap_sram_size - SRAM_BOOTLOADER_SZ); | |
243 | } | |
244 | ||
92105bb7 TL |
245 | void * omap_sram_push(void * start, unsigned long size) |
246 | { | |
247 | if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) { | |
248 | printk(KERN_ERR "Not enough space in SRAM\n"); | |
249 | return NULL; | |
250 | } | |
670c104a | 251 | |
92105bb7 | 252 | omap_sram_ceil -= size; |
670c104a | 253 | omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *)); |
92105bb7 | 254 | memcpy((void *)omap_sram_ceil, start, size); |
913b143f | 255 | flush_icache_range((unsigned long)omap_sram_ceil, |
256 | (unsigned long)(omap_sram_ceil + size)); | |
92105bb7 TL |
257 | |
258 | return (void *)omap_sram_ceil; | |
259 | } | |
260 | ||
1a8bfa1e TL |
261 | #ifdef CONFIG_ARCH_OMAP1 |
262 | ||
263 | static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); | |
264 | ||
265 | void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) | |
266 | { | |
da7a0649 | 267 | BUG_ON(!_omap_sram_reprogram_clock); |
020f9706 | 268 | _omap_sram_reprogram_clock(dpllctl, ckctl); |
1a8bfa1e TL |
269 | } |
270 | ||
e6f16821 | 271 | static int __init omap1_sram_init(void) |
92105bb7 | 272 | { |
c2d43e39 TL |
273 | _omap_sram_reprogram_clock = |
274 | omap_sram_push(omap1_sram_reprogram_clock, | |
275 | omap1_sram_reprogram_clock_sz); | |
1a8bfa1e TL |
276 | |
277 | return 0; | |
278 | } | |
279 | ||
280 | #else | |
281 | #define omap1_sram_init() do {} while (0) | |
282 | #endif | |
283 | ||
cc26b3b0 | 284 | #if defined(CONFIG_ARCH_OMAP2) |
1a8bfa1e TL |
285 | |
286 | static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, | |
287 | u32 base_cs, u32 force_unlock); | |
288 | ||
289 | void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, | |
290 | u32 base_cs, u32 force_unlock) | |
291 | { | |
da7a0649 | 292 | BUG_ON(!_omap2_sram_ddr_init); |
020f9706 RK |
293 | _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl, |
294 | base_cs, force_unlock); | |
1a8bfa1e TL |
295 | } |
296 | ||
297 | static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val, | |
298 | u32 mem_type); | |
299 | ||
300 | void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type) | |
301 | { | |
da7a0649 | 302 | BUG_ON(!_omap2_sram_reprogram_sdrc); |
020f9706 | 303 | _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type); |
1a8bfa1e TL |
304 | } |
305 | ||
306 | static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); | |
307 | ||
308 | u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) | |
309 | { | |
da7a0649 | 310 | BUG_ON(!_omap2_set_prcm); |
1a8bfa1e TL |
311 | return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); |
312 | } | |
c2d43e39 TL |
313 | #endif |
314 | ||
315 | #ifdef CONFIG_ARCH_OMAP2420 | |
b0a330dc | 316 | static int __init omap242x_sram_init(void) |
c2d43e39 TL |
317 | { |
318 | _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init, | |
319 | omap242x_sram_ddr_init_sz); | |
320 | ||
321 | _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc, | |
322 | omap242x_sram_reprogram_sdrc_sz); | |
323 | ||
324 | _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm, | |
325 | omap242x_sram_set_prcm_sz); | |
326 | ||
327 | return 0; | |
328 | } | |
329 | #else | |
330 | static inline int omap242x_sram_init(void) | |
331 | { | |
332 | return 0; | |
333 | } | |
334 | #endif | |
335 | ||
336 | #ifdef CONFIG_ARCH_OMAP2430 | |
b0a330dc | 337 | static int __init omap243x_sram_init(void) |
c2d43e39 TL |
338 | { |
339 | _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init, | |
340 | omap243x_sram_ddr_init_sz); | |
341 | ||
342 | _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc, | |
343 | omap243x_sram_reprogram_sdrc_sz); | |
344 | ||
345 | _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm, | |
346 | omap243x_sram_set_prcm_sz); | |
347 | ||
348 | return 0; | |
349 | } | |
350 | #else | |
351 | static inline int omap243x_sram_init(void) | |
352 | { | |
353 | return 0; | |
354 | } | |
355 | #endif | |
356 | ||
357 | #ifdef CONFIG_ARCH_OMAP3 | |
358 | ||
58cda884 JP |
359 | static u32 (*_omap3_sram_configure_core_dpll)( |
360 | u32 m2, u32 unlock_dll, u32 f, u32 inc, | |
361 | u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0, | |
362 | u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, | |
363 | u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, | |
364 | u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); | |
365 | ||
366 | u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc, | |
367 | u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0, | |
368 | u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, | |
369 | u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, | |
370 | u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1) | |
c2d43e39 | 371 | { |
da7a0649 | 372 | BUG_ON(!_omap3_sram_configure_core_dpll); |
58cda884 JP |
373 | return _omap3_sram_configure_core_dpll( |
374 | m2, unlock_dll, f, inc, | |
375 | sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0, | |
376 | sdrc_actim_ctrl_b_0, sdrc_mr_0, | |
377 | sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1, | |
378 | sdrc_actim_ctrl_b_1, sdrc_mr_1); | |
c2d43e39 | 379 | } |
1a8bfa1e | 380 | |
3231fc88 RN |
381 | #ifdef CONFIG_PM |
382 | void omap3_sram_restore_context(void) | |
1a8bfa1e | 383 | { |
c2d43e39 | 384 | omap_sram_ceil = omap_sram_base + omap_sram_size; |
1a8bfa1e | 385 | |
cc26b3b0 SMK |
386 | _omap3_sram_configure_core_dpll = |
387 | omap_sram_push(omap3_sram_configure_core_dpll, | |
388 | omap3_sram_configure_core_dpll_sz); | |
3231fc88 | 389 | omap_push_sram_idle(); |
c2d43e39 | 390 | } |
3231fc88 | 391 | #endif /* CONFIG_PM */ |
c2d43e39 | 392 | |
b0a330dc | 393 | static int __init omap34xx_sram_init(void) |
c2d43e39 | 394 | { |
cc26b3b0 SMK |
395 | _omap3_sram_configure_core_dpll = |
396 | omap_sram_push(omap3_sram_configure_core_dpll, | |
397 | omap3_sram_configure_core_dpll_sz); | |
3231fc88 | 398 | omap_push_sram_idle(); |
1a8bfa1e TL |
399 | return 0; |
400 | } | |
401 | #else | |
c2d43e39 TL |
402 | static inline int omap34xx_sram_init(void) |
403 | { | |
404 | return 0; | |
405 | } | |
1a8bfa1e TL |
406 | #endif |
407 | ||
82cd4ade | 408 | #ifdef CONFIG_ARCH_OMAP4 |
b0a330dc | 409 | static int __init omap44xx_sram_init(void) |
82cd4ade TL |
410 | { |
411 | printk(KERN_ERR "FIXME: %s not implemented\n", __func__); | |
412 | ||
413 | return -ENODEV; | |
414 | } | |
415 | #else | |
416 | static inline int omap44xx_sram_init(void) | |
417 | { | |
418 | return 0; | |
419 | } | |
420 | #endif | |
421 | ||
1a8bfa1e TL |
422 | int __init omap_sram_init(void) |
423 | { | |
424 | omap_detect_sram(); | |
425 | omap_map_sram(); | |
426 | ||
c2d43e39 | 427 | if (!(cpu_class_is_omap2())) |
1a8bfa1e | 428 | omap1_sram_init(); |
c2d43e39 TL |
429 | else if (cpu_is_omap242x()) |
430 | omap242x_sram_init(); | |
431 | else if (cpu_is_omap2430()) | |
432 | omap243x_sram_init(); | |
433 | else if (cpu_is_omap34xx()) | |
434 | omap34xx_sram_init(); | |
44169075 | 435 | else if (cpu_is_omap44xx()) |
82cd4ade | 436 | omap44xx_sram_init(); |
1a8bfa1e TL |
437 | |
438 | return 0; | |
92105bb7 | 439 | } |