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92105bb7 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/sram.c | |
3 | * | |
4 | * OMAP SRAM detection and management | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
92105bb7 TL |
14 | #include <linux/module.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | ||
53d9cc73 | 18 | #include <asm/tlb.h> |
92105bb7 TL |
19 | #include <asm/io.h> |
20 | #include <asm/cacheflush.h> | |
21 | ||
670c104a TL |
22 | #include <asm/mach/map.h> |
23 | ||
1a8bfa1e | 24 | #include <asm/arch/sram.h> |
670c104a | 25 | #include <asm/arch/board.h> |
1a8bfa1e TL |
26 | |
27 | #define OMAP1_SRAM_PA 0x20000000 | |
28 | #define OMAP1_SRAM_VA 0xd0000000 | |
29 | #define OMAP2_SRAM_PA 0x40200000 | |
670c104a | 30 | #define OMAP2_SRAM_PUB_PA 0x4020f800 |
1a8bfa1e | 31 | #define OMAP2_SRAM_VA 0xd0000000 |
670c104a | 32 | #define OMAP2_SRAM_PUB_VA 0xd0000800 |
92105bb7 | 33 | |
670c104a TL |
34 | #if defined(CONFIG_ARCH_OMAP24XX) |
35 | #define SRAM_BOOTLOADER_SZ 0x00 | |
36 | #else | |
92105bb7 | 37 | #define SRAM_BOOTLOADER_SZ 0x80 |
670c104a TL |
38 | #endif |
39 | ||
40 | #define VA_REQINFOPERM0 IO_ADDRESS(0x68005048) | |
41 | #define VA_READPERM0 IO_ADDRESS(0x68005050) | |
42 | #define VA_WRITEPERM0 IO_ADDRESS(0x68005058) | |
43 | #define VA_CONTROL_STAT IO_ADDRESS(0x480002F8) | |
44 | #define GP_DEVICE 0x300 | |
45 | #define TYPE_MASK 0x700 | |
46 | ||
47 | #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) | |
92105bb7 | 48 | |
c40fae95 | 49 | static unsigned long omap_sram_start; |
92105bb7 TL |
50 | static unsigned long omap_sram_base; |
51 | static unsigned long omap_sram_size; | |
52 | static unsigned long omap_sram_ceil; | |
53 | ||
c40fae95 TL |
54 | int omap_fb_sram_plane = -1; |
55 | int omap_fb_sram_valid; | |
670c104a TL |
56 | |
57 | /* Depending on the target RAMFS firewall setup, the public usable amount of | |
58 | * SRAM varies. The default accessable size for all device types is 2k. A GP | |
59 | * device allows ARM11 but not other initators for full size. This | |
60 | * functionality seems ok until some nice security API happens. | |
61 | */ | |
62 | static int is_sram_locked(void) | |
63 | { | |
64 | int type = 0; | |
65 | ||
66 | if (cpu_is_omap242x()) | |
67 | type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK; | |
68 | ||
69 | if (type == GP_DEVICE) { | |
70 | /* RAMFW: R/W access to all initators for all qualifier sets */ | |
71 | if (cpu_is_omap242x()) { | |
72 | __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */ | |
73 | __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */ | |
74 | __raw_writel(0xCFDE, VA_WRITEPERM0); /* all i-write */ | |
75 | } | |
76 | return 0; | |
77 | } else | |
78 | return 1; /* assume locked with no PPA or security driver */ | |
79 | } | |
80 | ||
c40fae95 TL |
81 | static int get_fb_sram_conf(unsigned long start_avail, unsigned size_avail, |
82 | unsigned long *start, int *plane_idx) | |
670c104a TL |
83 | { |
84 | const struct omap_fbmem_config *fbmem_conf; | |
c40fae95 TL |
85 | unsigned long size = 0; |
86 | int i; | |
87 | ||
88 | i = 0; | |
89 | *start = 0; | |
90 | *plane_idx = -1; | |
91 | while ((fbmem_conf = omap_get_nr_config(OMAP_TAG_FBMEM, | |
92 | struct omap_fbmem_config, i)) != NULL) { | |
93 | u32 paddr, end; | |
94 | ||
95 | paddr = fbmem_conf->start; | |
96 | end = fbmem_conf->start + fbmem_conf->size; | |
97 | if (paddr > omap_sram_start && | |
98 | paddr < omap_sram_start + omap_sram_size) { | |
99 | if (*plane_idx != -1 || paddr < start_avail || | |
100 | paddr == end || | |
101 | end > start_avail + size_avail) { | |
102 | printk(KERN_ERR "invalid FB SRAM configuration"); | |
103 | *start = 0; | |
104 | return -1; | |
105 | } | |
106 | *plane_idx = i; | |
107 | *start = fbmem_conf->start; | |
108 | size = fbmem_conf->size; | |
109 | } | |
110 | i++; | |
670c104a TL |
111 | } |
112 | ||
c40fae95 TL |
113 | if (*plane_idx >= 0) |
114 | pr_info("Reserving %lu bytes SRAM frame buffer " | |
115 | "for plane %d\n", size, *plane_idx); | |
670c104a | 116 | |
c40fae95 | 117 | return 0; |
670c104a TL |
118 | } |
119 | ||
92105bb7 | 120 | /* |
1a8bfa1e | 121 | * The amount of SRAM depends on the core type. |
92105bb7 TL |
122 | * Note that we cannot try to test for SRAM here because writes |
123 | * to secure SRAM will hang the system. Also the SRAM is not | |
124 | * yet mapped at this point. | |
125 | */ | |
126 | void __init omap_detect_sram(void) | |
127 | { | |
c40fae95 | 128 | unsigned long fb_sram_start; |
670c104a TL |
129 | |
130 | if (cpu_is_omap24xx()) { | |
131 | if (is_sram_locked()) { | |
132 | omap_sram_base = OMAP2_SRAM_PUB_VA; | |
c40fae95 | 133 | omap_sram_start = OMAP2_SRAM_PUB_PA; |
670c104a TL |
134 | omap_sram_size = 0x800; /* 2K */ |
135 | } else { | |
136 | omap_sram_base = OMAP2_SRAM_VA; | |
c40fae95 | 137 | omap_sram_start = OMAP2_SRAM_PA; |
670c104a TL |
138 | if (cpu_is_omap242x()) |
139 | omap_sram_size = 0xa0000; /* 640K */ | |
140 | else if (cpu_is_omap243x()) | |
141 | omap_sram_size = 0x10000; /* 64K */ | |
142 | } | |
143 | } else { | |
1a8bfa1e | 144 | omap_sram_base = OMAP1_SRAM_VA; |
c40fae95 | 145 | omap_sram_start = OMAP1_SRAM_PA; |
670c104a TL |
146 | |
147 | if (cpu_is_omap730()) | |
148 | omap_sram_size = 0x32000; /* 200K */ | |
149 | else if (cpu_is_omap15xx()) | |
150 | omap_sram_size = 0x30000; /* 192K */ | |
151 | else if (cpu_is_omap1610() || cpu_is_omap1621() || | |
152 | cpu_is_omap1710()) | |
153 | omap_sram_size = 0x4000; /* 16K */ | |
154 | else if (cpu_is_omap1611()) | |
155 | omap_sram_size = 0x3e800; /* 250K */ | |
156 | else { | |
157 | printk(KERN_ERR "Could not detect SRAM size\n"); | |
158 | omap_sram_size = 0x4000; | |
159 | } | |
92105bb7 | 160 | } |
c40fae95 TL |
161 | if (get_fb_sram_conf(omap_sram_start + SRAM_BOOTLOADER_SZ, |
162 | omap_sram_size - SRAM_BOOTLOADER_SZ, | |
163 | &fb_sram_start, &omap_fb_sram_plane) == 0) | |
164 | omap_fb_sram_valid = 1; | |
165 | if (omap_fb_sram_valid && omap_fb_sram_plane >= 0) | |
166 | omap_sram_size -= omap_sram_start + omap_sram_size - | |
167 | fb_sram_start; | |
92105bb7 TL |
168 | omap_sram_ceil = omap_sram_base + omap_sram_size; |
169 | } | |
170 | ||
171 | static struct map_desc omap_sram_io_desc[] __initdata = { | |
9fe133b1 | 172 | { /* .length gets filled in at runtime */ |
1a8bfa1e TL |
173 | .virtual = OMAP1_SRAM_VA, |
174 | .pfn = __phys_to_pfn(OMAP1_SRAM_PA), | |
ce2deca2 | 175 | .type = MT_MEMORY |
9fe133b1 | 176 | } |
92105bb7 TL |
177 | }; |
178 | ||
179 | /* | |
ce2deca2 | 180 | * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early. |
92105bb7 TL |
181 | */ |
182 | void __init omap_map_sram(void) | |
183 | { | |
670c104a TL |
184 | unsigned long base; |
185 | ||
92105bb7 TL |
186 | if (omap_sram_size == 0) |
187 | return; | |
188 | ||
1a8bfa1e TL |
189 | if (cpu_is_omap24xx()) { |
190 | omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA; | |
670c104a | 191 | |
d1284b5f | 192 | base = OMAP2_SRAM_PA; |
670c104a TL |
193 | base = ROUND_DOWN(base, PAGE_SIZE); |
194 | omap_sram_io_desc[0].pfn = __phys_to_pfn(base); | |
1a8bfa1e TL |
195 | } |
196 | ||
ce2deca2 | 197 | omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ |
92105bb7 TL |
198 | iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); |
199 | ||
1a8bfa1e | 200 | printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n", |
670c104a TL |
201 | __pfn_to_phys(omap_sram_io_desc[0].pfn), |
202 | omap_sram_io_desc[0].virtual, | |
1a8bfa1e TL |
203 | omap_sram_io_desc[0].length); |
204 | ||
53d9cc73 TL |
205 | /* |
206 | * Normally devicemaps_init() would flush caches and tlb after | |
207 | * mdesc->map_io(), but since we're called from map_io(), we | |
208 | * must do it here. | |
209 | */ | |
210 | local_flush_tlb_all(); | |
211 | flush_cache_all(); | |
212 | ||
92105bb7 TL |
213 | /* |
214 | * Looks like we need to preserve some bootloader code at the | |
215 | * beginning of SRAM for jumping to flash for reboot to work... | |
216 | */ | |
217 | memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0, | |
218 | omap_sram_size - SRAM_BOOTLOADER_SZ); | |
219 | } | |
220 | ||
92105bb7 TL |
221 | void * omap_sram_push(void * start, unsigned long size) |
222 | { | |
223 | if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) { | |
224 | printk(KERN_ERR "Not enough space in SRAM\n"); | |
225 | return NULL; | |
226 | } | |
670c104a | 227 | |
92105bb7 | 228 | omap_sram_ceil -= size; |
670c104a | 229 | omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *)); |
92105bb7 TL |
230 | memcpy((void *)omap_sram_ceil, start, size); |
231 | ||
232 | return (void *)omap_sram_ceil; | |
233 | } | |
234 | ||
1a8bfa1e TL |
235 | static void omap_sram_error(void) |
236 | { | |
237 | panic("Uninitialized SRAM function\n"); | |
238 | } | |
239 | ||
240 | #ifdef CONFIG_ARCH_OMAP1 | |
241 | ||
242 | static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); | |
243 | ||
244 | void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) | |
245 | { | |
246 | if (!_omap_sram_reprogram_clock) | |
247 | omap_sram_error(); | |
248 | ||
249 | return _omap_sram_reprogram_clock(dpllctl, ckctl); | |
250 | } | |
251 | ||
252 | int __init omap1_sram_init(void) | |
92105bb7 | 253 | { |
92105bb7 TL |
254 | _omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock, |
255 | sram_reprogram_clock_sz); | |
1a8bfa1e TL |
256 | |
257 | return 0; | |
258 | } | |
259 | ||
260 | #else | |
261 | #define omap1_sram_init() do {} while (0) | |
262 | #endif | |
263 | ||
264 | #ifdef CONFIG_ARCH_OMAP2 | |
265 | ||
266 | static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, | |
267 | u32 base_cs, u32 force_unlock); | |
268 | ||
269 | void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, | |
270 | u32 base_cs, u32 force_unlock) | |
271 | { | |
272 | if (!_omap2_sram_ddr_init) | |
273 | omap_sram_error(); | |
274 | ||
275 | return _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl, | |
276 | base_cs, force_unlock); | |
277 | } | |
278 | ||
279 | static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val, | |
280 | u32 mem_type); | |
281 | ||
282 | void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type) | |
283 | { | |
284 | if (!_omap2_sram_reprogram_sdrc) | |
285 | omap_sram_error(); | |
286 | ||
287 | return _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type); | |
288 | } | |
289 | ||
290 | static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); | |
291 | ||
292 | u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) | |
293 | { | |
294 | if (!_omap2_set_prcm) | |
295 | omap_sram_error(); | |
296 | ||
297 | return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); | |
298 | } | |
299 | ||
300 | int __init omap2_sram_init(void) | |
301 | { | |
302 | _omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz); | |
303 | ||
304 | _omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc, | |
305 | sram_reprogram_sdrc_sz); | |
306 | _omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz); | |
307 | ||
308 | return 0; | |
309 | } | |
310 | #else | |
311 | #define omap2_sram_init() do {} while (0) | |
312 | #endif | |
313 | ||
314 | int __init omap_sram_init(void) | |
315 | { | |
316 | omap_detect_sram(); | |
317 | omap_map_sram(); | |
318 | ||
319 | if (!cpu_is_omap24xx()) | |
320 | omap1_sram_init(); | |
321 | else | |
322 | omap2_sram_init(); | |
323 | ||
324 | return 0; | |
92105bb7 | 325 | } |