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5e1c5ff4
TL		 1/*
2 * arch/arm/plat-omap/usb.c -- platform level USB initialization
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#undef DEBUG
22
5e1c5ff4
TL		 23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/types.h>
26#include <linux/errno.h>
27#include <linux/init.h>
d052d1be 28#include <linux/platform_device.h>
3a16f7b4 29#include <linux/usb/otg.h>
5e1c5ff4
TL		 30
31#include <asm/io.h>
32#include <asm/irq.h>
33#include <asm/system.h>
34#include <asm/hardware.h>
5e1c5ff4
TL		 35
36#include <asm/arch/mux.h>
37#include <asm/arch/usb.h>
38#include <asm/arch/board.h>
39
c40fae95
TL		 40#ifdef CONFIG_ARCH_OMAP1
41
42#define INT_USB_IRQ_GEN IH2_BASE + 20
43#define INT_USB_IRQ_NISO IH2_BASE + 30
44#define INT_USB_IRQ_ISO IH2_BASE + 29
45#define INT_USB_IRQ_HGEN INT_USB_HHC_1
46#define INT_USB_IRQ_OTG IH2_BASE + 8
47
48#else
49
50#define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN
51#define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO
52#define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO
53#define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN
54#define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG
55
56#endif
57
58
5e1c5ff4
TL		 59/* These routines should handle the standard chip-specific modes
60 * for usb0/1/2 ports, covering basic mux and transceiver setup.
61 *
62 * Some board-*.c files will need to set up additional mux options,
63 * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup.
64 */
65
66/* TESTED ON:
67 * - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables
68 * - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables
69 * - 5912 OSK UDC, with *nonstandard* A-to-A cable
70 * - 1510 Innovator UDC with bundled usb0 cable
71 * - 1510 Innovator OHCI with bundled usb1/usb2 cable
72 * - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS
73 * - 1710 custom development board using alternate pin group
74 * - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables
75 */
76
77/*-------------------------------------------------------------------------*/
78
79#ifdef CONFIG_ARCH_OMAP_OTG
80
81static struct otg_transceiver *xceiv;
82
83/**
84 * otg_get_transceiver - find the (single) OTG transceiver driver
85 *
86 * Returns the transceiver driver, after getting a refcount to it; or
87 * null if there is no such transceiver. The caller is responsible for
88 * releasing that count.
89 */
90struct otg_transceiver *otg_get_transceiver(void)
91{
92 if (xceiv)
93 get_device(xceiv->dev);
94 return xceiv;
95}
96EXPORT_SYMBOL(otg_get_transceiver);
97
98int otg_set_transceiver(struct otg_transceiver *x)
99{
100 if (xceiv && x)
101 return -EBUSY;
102 xceiv = x;
103 return 0;
104}
105EXPORT_SYMBOL(otg_set_transceiver);
106
107#endif
108
109/*-------------------------------------------------------------------------*/
110
1a8bfa1e
TL		 111#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
112
5e1c5ff4
TL		 113static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
114{
115 u32 syscon1 = 0;
116
c40fae95
TL		 117 if (cpu_is_omap24xx())
118 CONTROL_DEVCONF_REG &= ~USBT0WRMODEI(USB_BIDIR_TLL);
119
5e1c5ff4 120 if (nwires == 0) {
c40fae95 121 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
5e1c5ff4
TL		 122 /* pulldown D+/D- */
123 USB_TRANSCEIVER_CTRL_REG &= ~(3 << 1);
124 }
125 return 0;
126 }
127
c40fae95
TL		 128 if (is_device) {
129 if (cpu_is_omap24xx())
130 omap_cfg_reg(J20_24XX_USB0_PUEN);
131 else
132 omap_cfg_reg(W4_USB_PUEN);
133 }
5e1c5ff4 134
c40fae95
TL		 135 /* internal transceiver (unavailable on 17xx, 24xx) */
136 if (!cpu_class_is_omap2() && nwires == 2) {
5e1c5ff4
TL		 137 // omap_cfg_reg(P9_USB_DP);
138 // omap_cfg_reg(R8_USB_DM);
139
140 if (cpu_is_omap15xx()) {
141 /* This works on 1510-Innovator */
142 return 0;
143 }
144
145 /* NOTES:
146 * - peripheral should configure VBUS detection!
147 * - only peripherals may use the internal D+/D- pulldowns
148 * - OTG support on this port not yet written
149 */
150
151 USB_TRANSCEIVER_CTRL_REG &= ~(7 << 4);
152 if (!is_device)
153 USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
154
155 return 3 << 16;
156 }
157
158 /* alternate pin config, external transceiver */
159 if (cpu_is_omap15xx()) {
160 printk(KERN_ERR "no usb0 alt pin config on 15xx\n");
161 return 0;
162 }
163
c40fae95
TL		 164 if (cpu_is_omap24xx()) {
165 omap_cfg_reg(K18_24XX_USB0_DAT);
166 omap_cfg_reg(K19_24XX_USB0_TXEN);
167 omap_cfg_reg(J14_24XX_USB0_SE0);
168 if (nwires != 3)
169 omap_cfg_reg(J18_24XX_USB0_RCV);
170 } else {
171 omap_cfg_reg(V6_USB0_TXD);
172 omap_cfg_reg(W9_USB0_TXEN);
173 omap_cfg_reg(W5_USB0_SE0);
174 if (nwires != 3)
175 omap_cfg_reg(Y5_USB0_RCV);
176 }
5e1c5ff4 177
c40fae95
TL		 178 /* NOTE: SPEED and SUSP aren't configured here. OTG hosts
179 * may be able to use I2C requests to set those bits along
6cbdc8c5 180 * with VBUS switching and overcurrent detection.
c40fae95 181 */
5e1c5ff4 182
c40fae95 183 if (cpu_class_is_omap1() && nwires != 6)
5e1c5ff4
TL		 184 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
185
186 switch (nwires) {
187 case 3:
188 syscon1 = 2;
c40fae95
TL		 189 if (cpu_is_omap24xx())
190 CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR);
5e1c5ff4
TL		 191 break;
192 case 4:
193 syscon1 = 1;
c40fae95
TL		 194 if (cpu_is_omap24xx())
195 CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_BIDIR);
5e1c5ff4
TL		 196 break;
197 case 6:
198 syscon1 = 3;
c40fae95
TL		 199 if (cpu_is_omap24xx()) {
200 omap_cfg_reg(J19_24XX_USB0_VP);
201 omap_cfg_reg(K20_24XX_USB0_VM);
202 CONTROL_DEVCONF_REG |= USBT0WRMODEI(USB_UNIDIR);
203 } else {
204 omap_cfg_reg(AA9_USB0_VP);
205 omap_cfg_reg(R9_USB0_VM);
206 USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
207 }
5e1c5ff4
TL		 208 break;
209 default:
210 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
211 0, nwires);
212 }
213 return syscon1 << 16;
214}
215
216static u32 __init omap_usb1_init(unsigned nwires)
217{
218 u32 syscon1 = 0;
219
c40fae95 220 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
5e1c5ff4 221 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R;
c40fae95
TL		 222 if (cpu_is_omap24xx())
223 CONTROL_DEVCONF_REG &= ~USBT1WRMODEI(USB_BIDIR_TLL);
224
5e1c5ff4
TL		 225 if (nwires == 0)
226 return 0;
227
228 /* external transceiver */
c40fae95
TL		 229 if (cpu_class_is_omap1()) {
230 omap_cfg_reg(USB1_TXD);
231 omap_cfg_reg(USB1_TXEN);
232 if (nwires != 3)
233 omap_cfg_reg(USB1_RCV);
234 }
235
5e1c5ff4
TL		 236 if (cpu_is_omap15xx()) {
237 omap_cfg_reg(USB1_SEO);
238 omap_cfg_reg(USB1_SPEED);
239 // SUSP
240 } else if (cpu_is_omap1610() || cpu_is_omap5912()) {
241 omap_cfg_reg(W13_1610_USB1_SE0);
242 omap_cfg_reg(R13_1610_USB1_SPEED);
243 // SUSP
244 } else if (cpu_is_omap1710()) {
245 omap_cfg_reg(R13_1710_USB1_SE0);
246 // SUSP
c40fae95
TL		 247 } else if (cpu_is_omap24xx()) {
248 /* NOTE: board-specific code must set up pin muxing for usb1,
249 * since each signal could come out on either of two balls.
250 */
5e1c5ff4 251 } else {
c40fae95
TL		 252 pr_debug("usb%d cpu unrecognized\n", 1);
253 return 0;
5e1c5ff4 254 }
5e1c5ff4
TL		 255
256 switch (nwires) {
c40fae95
TL		 257 case 2:
258 if (!cpu_is_omap24xx())
259 goto bad;
260 /* NOTE: board-specific code must override this setting if
261 * this TLL link is not using DP/DM
262 */
263 syscon1 = 1;
264 CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR_TLL);
265 break;
5e1c5ff4
TL		 266 case 3:
267 syscon1 = 2;
c40fae95
TL		 268 if (cpu_is_omap24xx())
269 CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR);
5e1c5ff4
TL		 270 break;
271 case 4:
272 syscon1 = 1;
c40fae95
TL		 273 if (cpu_is_omap24xx())
274 CONTROL_DEVCONF_REG |= USBT1WRMODEI(USB_BIDIR);
5e1c5ff4
TL		 275 break;
276 case 6:
c40fae95
TL		 277 if (cpu_is_omap24xx())
278 goto bad;
5e1c5ff4
TL		 279 syscon1 = 3;
280 omap_cfg_reg(USB1_VP);
281 omap_cfg_reg(USB1_VM);
282 if (!cpu_is_omap15xx())
283 USB_TRANSCEIVER_CTRL_REG |= CONF_USB1_UNI_R;
284 break;
285 default:
c40fae95 286bad:
5e1c5ff4
TL		 287 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
288 1, nwires);
289 }
290 return syscon1 << 20;
291}
292
293static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
294{
295 u32 syscon1 = 0;
296
c40fae95
TL		 297 if (cpu_is_omap24xx()) {
298 CONTROL_DEVCONF_REG &= ~(USBT2WRMODEI(USB_BIDIR_TLL)
299 | USBT2TLL5PI);
300 alt_pingroup = 0;
301 }
302
303 /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
5e1c5ff4
TL		 304 if (alt_pingroup || nwires == 0)
305 return 0;
c40fae95
TL		 306
307 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6)
5e1c5ff4
TL		 308 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R;
309
310 /* external transceiver */
311 if (cpu_is_omap15xx()) {
312 omap_cfg_reg(USB2_TXD);
313 omap_cfg_reg(USB2_TXEN);
314 omap_cfg_reg(USB2_SEO);
315 if (nwires != 3)
316 omap_cfg_reg(USB2_RCV);
317 /* there is no USB2_SPEED */
318 } else if (cpu_is_omap16xx()) {
319 omap_cfg_reg(V6_USB2_TXD);
320 omap_cfg_reg(W9_USB2_TXEN);
321 omap_cfg_reg(W5_USB2_SE0);
322 if (nwires != 3)
323 omap_cfg_reg(Y5_USB2_RCV);
324 // FIXME omap_cfg_reg(USB2_SPEED);
c40fae95
TL		 325 } else if (cpu_is_omap24xx()) {
326 omap_cfg_reg(Y11_24XX_USB2_DAT);
327 omap_cfg_reg(AA10_24XX_USB2_SE0);
328 if (nwires > 2)
329 omap_cfg_reg(AA12_24XX_USB2_TXEN);
330 if (nwires > 3)
331 omap_cfg_reg(AA6_24XX_USB2_RCV);
5e1c5ff4 332 } else {
c40fae95
TL		 333 pr_debug("usb%d cpu unrecognized\n", 1);
334 return 0;
5e1c5ff4 335 }
c40fae95 336 // if (cpu_class_is_omap1()) omap_cfg_reg(USB2_SUSP);
5e1c5ff4
TL		 337
338 switch (nwires) {
c40fae95
TL		 339 case 2:
340 if (!cpu_is_omap24xx())
341 goto bad;
342 /* NOTE: board-specific code must override this setting if
343 * this TLL link is not using DP/DM
344 */
345 syscon1 = 1;
346 CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR_TLL);
347 break;
5e1c5ff4
TL		 348 case 3:
349 syscon1 = 2;
c40fae95
TL		 350 if (cpu_is_omap24xx())
351 CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR);
5e1c5ff4
TL		 352 break;
353 case 4:
354 syscon1 = 1;
c40fae95
TL		 355 if (cpu_is_omap24xx())
356 CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_BIDIR);
357 break;
358 case 5:
359 if (!cpu_is_omap24xx())
360 goto bad;
361 omap_cfg_reg(AA4_24XX_USB2_TLLSE0);
362 /* NOTE: board-specific code must override this setting if
363 * this TLL link is not using DP/DM. Something must also
364 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
365 */
366 syscon1 = 3;
367 CONTROL_DEVCONF_REG |= USBT2WRMODEI(USB_UNIDIR_TLL)
368 | USBT2TLL5PI;
5e1c5ff4
TL		 369 break;
370 case 6:
c40fae95
TL		 371 if (cpu_is_omap24xx())
372 goto bad;
5e1c5ff4
TL		 373 syscon1 = 3;
374 if (cpu_is_omap15xx()) {
375 omap_cfg_reg(USB2_VP);
376 omap_cfg_reg(USB2_VM);
377 } else {
378 omap_cfg_reg(AA9_USB2_VP);
379 omap_cfg_reg(R9_USB2_VM);
380 USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R;
381 }
382 break;
383 default:
c40fae95 384bad:
5e1c5ff4
TL		 385 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
386 2, nwires);
387 }
388 return syscon1 << 24;
389}
390
1a8bfa1e
TL		 391#endif
392
5e1c5ff4
TL		 393/*-------------------------------------------------------------------------*/
394
395#if defined(CONFIG_USB_GADGET_OMAP) || \
396 defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) || \
397 (defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG))
398static void usb_release(struct device *dev)
399{
400 /* normally not freed */
401}
402#endif
403
404#ifdef CONFIG_USB_GADGET_OMAP
405
406static struct resource udc_resources[] = {
407 /* order is significant! */
408 { /* registers */
409 .start = UDC_BASE,
410 .end = UDC_BASE + 0xff,
411 .flags = IORESOURCE_MEM,
412 }, { /* general IRQ */
c40fae95 413 .start = INT_USB_IRQ_GEN,
5e1c5ff4
TL		 414 .flags = IORESOURCE_IRQ,
415 }, { /* PIO IRQ */
c40fae95 416 .start = INT_USB_IRQ_NISO,
5e1c5ff4
TL		 417 .flags = IORESOURCE_IRQ,
418 }, { /* SOF IRQ */
c40fae95 419 .start = INT_USB_IRQ_ISO,
5e1c5ff4
TL		 420 .flags = IORESOURCE_IRQ,
421 },
422};
423
424static u64 udc_dmamask = ~(u32)0;
425
426static struct platform_device udc_device = {
427 .name = "omap_udc",
428 .id = -1,
429 .dev = {
430 .release = usb_release,
431 .dma_mask = &udc_dmamask,
432 .coherent_dma_mask = 0xffffffff,
433 },
434 .num_resources = ARRAY_SIZE(udc_resources),
435 .resource = udc_resources,
436};
437
438#endif
439
440#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
441
442/* The dmamask must be set for OHCI to work */
443static u64 ohci_dmamask = ~(u32)0;
444
445static struct resource ohci_resources[] = {
446 {
447 .start = OMAP_OHCI_BASE,
c40fae95 448 .end = OMAP_OHCI_BASE + 0xff,
5e1c5ff4
TL		 449 .flags = IORESOURCE_MEM,
450 },
451 {
c40fae95 452 .start = INT_USB_IRQ_HGEN,
5e1c5ff4
TL		 453 .flags = IORESOURCE_IRQ,
454 },
455};
456
457static struct platform_device ohci_device = {
458 .name = "ohci",
459 .id = -1,
460 .dev = {
461 .release = usb_release,
462 .dma_mask = &ohci_dmamask,
463 .coherent_dma_mask = 0xffffffff,
464 },
465 .num_resources = ARRAY_SIZE(ohci_resources),
466 .resource = ohci_resources,
467};
468
469#endif
470
471#if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
472
473static struct resource otg_resources[] = {
474 /* order is significant! */
475 {
476 .start = OTG_BASE,
477 .end = OTG_BASE + 0xff,
478 .flags = IORESOURCE_MEM,
479 }, {
c40fae95 480 .start = INT_USB_IRQ_OTG,
5e1c5ff4
TL		 481 .flags = IORESOURCE_IRQ,
482 },
483};
484
485static struct platform_device otg_device = {
486 .name = "omap_otg",
487 .id = -1,
488 .dev = {
489 .release = usb_release,
490 },
491 .num_resources = ARRAY_SIZE(otg_resources),
492 .resource = otg_resources,
493};
494
495#endif
496
497/*-------------------------------------------------------------------------*/
498
499#define ULPD_CLOCK_CTRL_REG __REG16(ULPD_CLOCK_CTRL)
500#define ULPD_SOFT_REQ_REG __REG16(ULPD_SOFT_REQ)
501
502
503// FIXME correct answer depends on hmc_mode,
c40fae95 504// as does (on omap1) any nonzero value for config->otg port number
5e1c5ff4
TL		 505#ifdef CONFIG_USB_GADGET_OMAP
506#define is_usb0_device(config) 1
507#else
508#define is_usb0_device(config) 0
509#endif
510
511/*-------------------------------------------------------------------------*/
512
513#ifdef CONFIG_ARCH_OMAP_OTG
514
515void __init
516omap_otg_init(struct omap_usb_config *config)
517{
518 u32 syscon = OTG_SYSCON_1_REG & 0xffff;
519 int status;
520 int alt_pingroup = 0;
521
522 /* NOTE: no bus or clock setup (yet?) */
523
524 syscon = OTG_SYSCON_1_REG & 0xffff;
525 if (!(syscon & OTG_RESET_DONE))
526 pr_debug("USB resets not complete?\n");
527
528 // OTG_IRQ_EN_REG = 0;
529
530 /* pin muxing and transceiver pinouts */
531 if (config->pins[0] > 2) /* alt pingroup 2 */
532 alt_pingroup = 1;
533 syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config));
534 syscon |= omap_usb1_init(config->pins[1]);
535 syscon |= omap_usb2_init(config->pins[2], alt_pingroup);
536 pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
537 OTG_SYSCON_1_REG = syscon;
538
539 syscon = config->hmc_mode;
540 syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
541#ifdef CONFIG_USB_OTG
542 if (config->otg)
543 syscon |= OTG_EN;
544#endif
c40fae95
TL		 545 if (cpu_class_is_omap1())
546 pr_debug("USB_TRANSCEIVER_CTRL_REG = %03x\n", USB_TRANSCEIVER_CTRL_REG);
5e1c5ff4
TL		 547 pr_debug("OTG_SYSCON_2_REG = %08x\n", syscon);
548 OTG_SYSCON_2_REG = syscon;
549
550 printk("USB: hmc %d", config->hmc_mode);
c40fae95 551 if (!alt_pingroup)
5e1c5ff4
TL		 552 printk(", usb2 alt %d wires", config->pins[2]);
553 else if (config->pins[0])
554 printk(", usb0 %d wires%s", config->pins[0],
555 is_usb0_device(config) ? " (dev)" : "");
556 if (config->pins[1])
557 printk(", usb1 %d wires", config->pins[1]);
558 if (!alt_pingroup && config->pins[2])
559 printk(", usb2 %d wires", config->pins[2]);
560 if (config->otg)
561 printk(", Mini-AB on usb%d", config->otg - 1);
562 printk("\n");
563
c40fae95
TL		 564 if (cpu_class_is_omap1()) {
565 /* leave USB clocks/controllers off until needed */
566 ULPD_SOFT_REQ_REG &= ~SOFT_USB_CLK_REQ;
567 ULPD_CLOCK_CTRL_REG &= ~USB_MCLK_EN;
568 ULPD_CLOCK_CTRL_REG |= DIS_USB_PVCI_CLK;
569 }
5e1c5ff4
TL		 570 syscon = OTG_SYSCON_1_REG;
571 syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
572
573#ifdef CONFIG_USB_GADGET_OMAP
574 if (config->otg || config->register_dev) {
575 syscon &= ~DEV_IDLE_EN;
576 udc_device.dev.platform_data = config;
577 /* FIXME patch IRQ numbers for omap730 */
578 status = platform_device_register(&udc_device);
579 if (status)
580 pr_debug("can't register UDC device, %d\n", status);
581 }
582#endif
583
584#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
585 if (config->otg || config->register_host) {
586 syscon &= ~HST_IDLE_EN;
587 ohci_device.dev.platform_data = config;
588 if (cpu_is_omap730())
589 ohci_resources[1].start = INT_730_USB_HHC_1;
590 status = platform_device_register(&ohci_device);
591 if (status)
592 pr_debug("can't register OHCI device, %d\n", status);
593 }
594#endif
595
596#ifdef CONFIG_USB_OTG
597 if (config->otg) {
598 syscon &= ~OTG_IDLE_EN;
599 otg_device.dev.platform_data = config;
600 if (cpu_is_omap730())
601 otg_resources[1].start = INT_730_USB_OTG;
602 status = platform_device_register(&otg_device);
603 if (status)
604 pr_debug("can't register OTG device, %d\n", status);
605 }
606#endif
607 pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon);
608 OTG_SYSCON_1_REG = syscon;
609
610 status = 0;
611}
612
613#else
614static inline void omap_otg_init(struct omap_usb_config *config) {}
615#endif
616
617/*-------------------------------------------------------------------------*/
618
1a8bfa1e 619#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 620
621#define ULPD_DPLL_CTRL_REG __REG16(ULPD_DPLL_CTRL)
622#define DPLL_IOB (1 << 13)
623#define DPLL_PLL_ENABLE (1 << 4)
624#define DPLL_LOCK (1 << 0)
625
626#define ULPD_APLL_CTRL_REG __REG16(ULPD_APLL_CTRL)
627#define APLL_NDPLL_SWITCH (1 << 0)
628
629
630static void __init omap_1510_usb_init(struct omap_usb_config *config)
631{
5e1c5ff4
TL		 632 unsigned int val;
633
634 omap_usb0_init(config->pins[0], is_usb0_device(config));
635 omap_usb1_init(config->pins[1]);
636 omap_usb2_init(config->pins[2], 0);
637
638 val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
639 val |= (config->hmc_mode << 1);
640 omap_writel(val, MOD_CONF_CTRL_0);
641
642 printk("USB: hmc %d", config->hmc_mode);
643 if (config->pins[0])
644 printk(", usb0 %d wires%s", config->pins[0],
645 is_usb0_device(config) ? " (dev)" : "");
646 if (config->pins[1])
647 printk(", usb1 %d wires", config->pins[1]);
648 if (config->pins[2])
649 printk(", usb2 %d wires", config->pins[2]);
650 printk("\n");
651
652 /* use DPLL for 48 MHz function clock */
653 pr_debug("APLL %04x DPLL %04x REQ %04x\n", ULPD_APLL_CTRL_REG,
654 ULPD_DPLL_CTRL_REG, ULPD_SOFT_REQ_REG);
655 ULPD_APLL_CTRL_REG &= ~APLL_NDPLL_SWITCH;
656 ULPD_DPLL_CTRL_REG |= DPLL_IOB | DPLL_PLL_ENABLE;
657 ULPD_SOFT_REQ_REG |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
658 while (!(ULPD_DPLL_CTRL_REG & DPLL_LOCK))
659 cpu_relax();
660
661#ifdef CONFIG_USB_GADGET_OMAP
662 if (config->register_dev) {
1a8bfa1e
TL		 663 int status;
664
5e1c5ff4
TL		 665 udc_device.dev.platform_data = config;
666 status = platform_device_register(&udc_device);
667 if (status)
668 pr_debug("can't register UDC device, %d\n", status);
669 /* udc driver gates 48MHz by D+ pullup */
670 }
671#endif
672
673#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
674 if (config->register_host) {
1a8bfa1e
TL		 675 int status;
676
5e1c5ff4
TL		 677 ohci_device.dev.platform_data = config;
678 status = platform_device_register(&ohci_device);
679 if (status)
680 pr_debug("can't register OHCI device, %d\n", status);
681 /* hcd explicitly gates 48MHz */
682 }
683#endif
684}
685
686#else
687static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
688#endif
689
690/*-------------------------------------------------------------------------*/
691
692static struct omap_usb_config platform_data;
693
694static int __init
695omap_usb_init(void)
696{
697 const struct omap_usb_config *config;
698
699 config = omap_get_config(OMAP_TAG_USB, struct omap_usb_config);
700 if (config == NULL) {
701 printk(KERN_ERR "USB: No board-specific "
702 "platform config found\n");
703 return -ENODEV;
704 }
705 platform_data = *config;
706
c40fae95 707 if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx())
5e1c5ff4
TL		 708 omap_otg_init(&platform_data);
709 else if (cpu_is_omap15xx())
710 omap_1510_usb_init(&platform_data);
711 else {
712 printk(KERN_ERR "USB: No init for your chip yet\n");
713 return -ENODEV;
714 }
715 return 0;
716}
717
718subsys_initcall(omap_usb_init);
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