[mirror_ubuntu-zesty-kernel.git] / arch / arm / plat-orion / gpio.c

/*
 * arch/arm/plat-orion/gpio.c
 *
 * Marvell Orion SoC GPIO handling.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#define DEBUG

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <plat/orion-gpio.h>

/*
 * GPIO unit register offsets.
 */
#define GPIO_OUT_OFF		0x0000
#define GPIO_IO_CONF_OFF	0x0004
#define GPIO_BLINK_EN_OFF	0x0008
#define GPIO_IN_POL_OFF		0x000c
#define GPIO_DATA_IN_OFF	0x0010
#define GPIO_EDGE_CAUSE_OFF	0x0014
#define GPIO_EDGE_MASK_OFF	0x0018
#define GPIO_LEVEL_MASK_OFF	0x001c

struct orion_gpio_chip {
	struct gpio_chip	chip;
	spinlock_t		lock;
	void __iomem		*base;
	unsigned long		valid_input;
	unsigned long		valid_output;
	int			mask_offset;
	int			secondary_irq_base;
	struct irq_domain       *domain;
};

static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
{
	return ochip->base + GPIO_OUT_OFF;
}

static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
{
	return ochip->base + GPIO_IO_CONF_OFF;
}

static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
{
	return ochip->base + GPIO_BLINK_EN_OFF;
}

static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
{
	return ochip->base + GPIO_IN_POL_OFF;
}

static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
{
	return ochip->base + GPIO_DATA_IN_OFF;
}

static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
{
	return ochip->base + GPIO_EDGE_CAUSE_OFF;
}

static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
{
	return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
}

static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
{
	return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
}


static struct orion_gpio_chip orion_gpio_chips[2];
static int orion_gpio_chip_count;

static inline void
__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
{
	u32 u;

	u = readl(GPIO_IO_CONF(ochip));
	if (input)
		u |= 1 << pin;
	else
		u &= ~(1 << pin);
	writel(u, GPIO_IO_CONF(ochip));
}

static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
{
	u32 u;

	u = readl(GPIO_OUT(ochip));
	if (high)
		u |= 1 << pin;
	else
		u &= ~(1 << pin);
	writel(u, GPIO_OUT(ochip));
}

static inline void
__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
{
	u32 u;

	u = readl(GPIO_BLINK_EN(ochip));
	if (blink)
		u |= 1 << pin;
	else
		u &= ~(1 << pin);
	writel(u, GPIO_BLINK_EN(ochip));
}

static inline int
orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
{
	if (pin >= ochip->chip.ngpio)
		goto err_out;

	if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
		goto err_out;

	if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
		goto err_out;

	return 1;

err_out:
	pr_debug("%s: invalid GPIO %d\n", __func__, pin);
	return false;
}

/*
 * GPIO primitives.
 */
static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
{
	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);

	if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
	    orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
		return 0;

	return -EINVAL;
}

static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
{
	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
	unsigned long flags;

	if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
		return -EINVAL;

	spin_lock_irqsave(&ochip->lock, flags);
	__set_direction(ochip, pin, 1);
	spin_unlock_irqrestore(&ochip->lock, flags);

	return 0;
}

static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
{
	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
	int val;

	if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
		val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
	} else {
		val = readl(GPIO_OUT(ochip));
	}

	return (val >> pin) & 1;
}

static int
orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
{
	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
	unsigned long flags;

	if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
		return -EINVAL;

	spin_lock_irqsave(&ochip->lock, flags);
	__set_blinking(ochip, pin, 0);
	__set_level(ochip, pin, value);
	__set_direction(ochip, pin, 0);
	spin_unlock_irqrestore(&ochip->lock, flags);

	return 0;
}

static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
{
	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
	unsigned long flags;

	spin_lock_irqsave(&ochip->lock, flags);
	__set_level(ochip, pin, value);
	spin_unlock_irqrestore(&ochip->lock, flags);
}

static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
{
	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);

	return irq_create_mapping(ochip->domain,
				  ochip->secondary_irq_base + pin);
}

/*
 * Orion-specific GPIO API extensions.
 */
static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
{
	int i;

	for (i = 0; i < orion_gpio_chip_count; i++) {
		struct orion_gpio_chip *ochip = orion_gpio_chips + i;
		struct gpio_chip *chip = &ochip->chip;

		if (pin >= chip->base && pin < chip->base + chip->ngpio)
			return ochip;
	}

	return NULL;
}

void __init orion_gpio_set_unused(unsigned pin)
{
	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);

	if (ochip == NULL)
		return;

	pin -= ochip->chip.base;

	/* Configure as output, drive low. */
	__set_level(ochip, pin, 0);
	__set_direction(ochip, pin, 0);
}

void __init orion_gpio_set_valid(unsigned pin, int mode)
{
	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);

	if (ochip == NULL)
		return;

	pin -= ochip->chip.base;

	if (mode == 1)
		mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;

	if (mode & GPIO_INPUT_OK)
		__set_bit(pin, &ochip->valid_input);
	else
		__clear_bit(pin, &ochip->valid_input);

	if (mode & GPIO_OUTPUT_OK)
		__set_bit(pin, &ochip->valid_output);
	else
		__clear_bit(pin, &ochip->valid_output);
}

void orion_gpio_set_blink(unsigned pin, int blink)
{
	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
	unsigned long flags;

	if (ochip == NULL)
		return;

	spin_lock_irqsave(&ochip->lock, flags);
	__set_level(ochip, pin & 31, 0);
	__set_blinking(ochip, pin & 31, blink);
	spin_unlock_irqrestore(&ochip->lock, flags);
}
EXPORT_SYMBOL(orion_gpio_set_blink);

#define ORION_BLINK_HALF_PERIOD 100 /* ms */

int orion_gpio_led_blink_set(struct gpio_desc *desc, int state,
	unsigned long *delay_on, unsigned long *delay_off)
{
	unsigned gpio = desc_to_gpio(desc);

	if (delay_on && delay_off && !*delay_on && !*delay_off)
		*delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;

	switch (state) {
	case GPIO_LED_NO_BLINK_LOW:
	case GPIO_LED_NO_BLINK_HIGH:
		orion_gpio_set_blink(gpio, 0);
		gpio_set_value(gpio, state);
		break;
	case GPIO_LED_BLINK:
		orion_gpio_set_blink(gpio, 1);
	}
	return 0;
}
EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set);


/*****************************************************************************
 * Orion GPIO IRQ
 *
 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
 * value of the line or the opposite value.
 *
 * Level IRQ handlers: DATA_IN is used directly as cause register.
 *                     Interrupt are masked by LEVEL_MASK registers.
 * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
 *                     Interrupt are masked by EDGE_MASK registers.
 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
 *                     the polarity to catch the next line transaction.
 *                     This is a race condition that might not perfectly
 *                     work on some use cases.
 *
 * Every eight GPIO lines are grouped (OR'ed) before going up to main
 * cause register.
 *
 *                    EDGE  cause    mask
 *        data-in   /--------| |-----| |----\
 *     -----| |-----                         ---- to main cause reg
 *           X      \----------------| |----/
 *        polarity    LEVEL          mask
 *
 ****************************************************************************/

static int gpio_irq_set_type(struct irq_data *d, u32 type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	struct orion_gpio_chip *ochip = gc->private;
	int pin;
	u32 u;

	pin = d->hwirq - ochip->secondary_irq_base;

	u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
	if (!u) {
		return -EINVAL;
	}

	type &= IRQ_TYPE_SENSE_MASK;
	if (type == IRQ_TYPE_NONE)
		return -EINVAL;

	/* Check if we need to change chip and handler */
	if (!(ct->type & type))
		if (irq_setup_alt_chip(d, type))
			return -EINVAL;

	/*
	 * Configure interrupt polarity.
	 */
	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
		u = readl(GPIO_IN_POL(ochip));
		u &= ~(1 << pin);
		writel(u, GPIO_IN_POL(ochip));
	} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
		u = readl(GPIO_IN_POL(ochip));
		u |= 1 << pin;
		writel(u, GPIO_IN_POL(ochip));
	} else if (type == IRQ_TYPE_EDGE_BOTH) {
		u32 v;

		v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));

		/*
		 * set initial polarity based on current input level
		 */
		u = readl(GPIO_IN_POL(ochip));
		if (v & (1 << pin))
			u |= 1 << pin;		/* falling */
		else
			u &= ~(1 << pin);	/* rising */
		writel(u, GPIO_IN_POL(ochip));
	}
	return 0;
}

static void gpio_irq_handler(struct irq_desc *desc)
{
	struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc);
	u32 cause, type;
	int i;

	if (ochip == NULL)
		return;

	cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
	cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));

	for (i = 0; i < ochip->chip.ngpio; i++) {
		int irq;

		irq = ochip->secondary_irq_base + i;

		if (!(cause & (1 << i)))
			continue;

		type = irq_get_trigger_type(irq);
		if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
			/* Swap polarity (race with GPIO line) */
			u32 polarity;

			polarity = readl(GPIO_IN_POL(ochip));
			polarity ^= 1 << i;
			writel(polarity, GPIO_IN_POL(ochip));
		}
		generic_handle_irq(irq);
	}
}

#ifdef CONFIG_DEBUG_FS
#include <linux/seq_file.h>

static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{

	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
	u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
	int i;

	out	= readl_relaxed(GPIO_OUT(ochip));
	io_conf	= readl_relaxed(GPIO_IO_CONF(ochip));
	blink	= readl_relaxed(GPIO_BLINK_EN(ochip));
	in_pol	= readl_relaxed(GPIO_IN_POL(ochip));
	data_in	= readl_relaxed(GPIO_DATA_IN(ochip));
	cause	= readl_relaxed(GPIO_EDGE_CAUSE(ochip));
	edg_msk	= readl_relaxed(GPIO_EDGE_MASK(ochip));
	lvl_msk	= readl_relaxed(GPIO_LEVEL_MASK(ochip));

	for (i = 0; i < chip->ngpio; i++) {
		const char *label;
		u32 msk;
		bool is_out;

		label = gpiochip_is_requested(chip, i);
		if (!label)
			continue;

		msk = 1 << i;
		is_out = !(io_conf & msk);

		seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);

		if (is_out) {
			seq_printf(s, " out %s %s\n",
				   out & msk ? "hi" : "lo",
				   blink & msk ? "(blink )" : "");
			continue;
		}

		seq_printf(s, " in  %s (act %s) - IRQ",
			   (data_in ^ in_pol) & msk  ? "hi" : "lo",
			   in_pol & msk ? "lo" : "hi");
		if (!((edg_msk | lvl_msk) & msk)) {
			seq_printf(s, " disabled\n");
			continue;
		}
		if (edg_msk & msk)
			seq_printf(s, " edge ");
		if (lvl_msk & msk)
			seq_printf(s, " level");
		seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear  ");
	}
}
#else
#define orion_gpio_dbg_show NULL
#endif

static void orion_gpio_unmask_irq(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 reg_val;
	u32 mask = d->mask;

	irq_gc_lock(gc);
	reg_val = irq_reg_readl(gc, ct->regs.mask);
	reg_val |= mask;
	irq_reg_writel(gc, reg_val, ct->regs.mask);
	irq_gc_unlock(gc);
}

static void orion_gpio_mask_irq(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;
	u32 reg_val;

	irq_gc_lock(gc);
	reg_val = irq_reg_readl(gc, ct->regs.mask);
	reg_val &= ~mask;
	irq_reg_writel(gc, reg_val, ct->regs.mask);
	irq_gc_unlock(gc);
}

void __init orion_gpio_init(struct device_node *np,
			    int gpio_base, int ngpio,
			    void __iomem *base, int mask_offset,
			    int secondary_irq_base,
			    int irqs[4])
{
	struct orion_gpio_chip *ochip;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	char gc_label[16];
	int i;

	if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
		return;

	snprintf(gc_label, sizeof(gc_label), "orion_gpio%d",
		orion_gpio_chip_count);

	ochip = orion_gpio_chips + orion_gpio_chip_count;
	ochip->chip.label = kstrdup(gc_label, GFP_KERNEL);
	ochip->chip.request = orion_gpio_request;
	ochip->chip.direction_input = orion_gpio_direction_input;
	ochip->chip.get = orion_gpio_get;
	ochip->chip.direction_output = orion_gpio_direction_output;
	ochip->chip.set = orion_gpio_set;
	ochip->chip.to_irq = orion_gpio_to_irq;
	ochip->chip.base = gpio_base;
	ochip->chip.ngpio = ngpio;
	ochip->chip.can_sleep = 0;
#ifdef CONFIG_OF
	ochip->chip.of_node = np;
#endif
	ochip->chip.dbg_show = orion_gpio_dbg_show;

	spin_lock_init(&ochip->lock);
	ochip->base = (void __iomem *)base;
	ochip->valid_input = 0;
	ochip->valid_output = 0;
	ochip->mask_offset = mask_offset;
	ochip->secondary_irq_base = secondary_irq_base;

	gpiochip_add_data(&ochip->chip, ochip);

	/*
	 * Mask and clear GPIO interrupts.
	 */
	writel(0, GPIO_EDGE_CAUSE(ochip));
	writel(0, GPIO_EDGE_MASK(ochip));
	writel(0, GPIO_LEVEL_MASK(ochip));

	/* Setup the interrupt handlers. Each chip can have up to 4
	 * interrupt handlers, with each handler dealing with 8 GPIO
	 * pins. */

	for (i = 0; i < 4; i++) {
		if (irqs[i]) {
			irq_set_chained_handler_and_data(irqs[i],
							 gpio_irq_handler,
							 ochip);
		}
	}

	gc = irq_alloc_generic_chip("orion_gpio_irq", 2,
				    secondary_irq_base,
				    ochip->base, handle_level_irq);
	gc->private = ochip;
	ct = gc->chip_types;
	ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
	ct->chip.irq_mask = orion_gpio_mask_irq;
	ct->chip.irq_unmask = orion_gpio_unmask_irq;
	ct->chip.irq_set_type = gpio_irq_set_type;
	ct->chip.name = ochip->chip.label;

	ct++;
	ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
	ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	ct->chip.irq_ack = irq_gc_ack_clr_bit;
	ct->chip.irq_mask = orion_gpio_mask_irq;
	ct->chip.irq_unmask = orion_gpio_unmask_irq;
	ct->chip.irq_set_type = gpio_irq_set_type;
	ct->handler = handle_edge_irq;
	ct->chip.name = ochip->chip.label;

	irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
			       IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);

	/* Setup irq domain on top of the generic chip. */
	ochip->domain = irq_domain_add_legacy(np,
					      ochip->chip.ngpio,
					      ochip->secondary_irq_base,
					      ochip->secondary_irq_base,
					      &irq_domain_simple_ops,
					      ochip);
	if (!ochip->domain)
		panic("%s: couldn't allocate irq domain (DT).\n",
		      ochip->chip.label);

	orion_gpio_chip_count++;
}
Commit	Line	Data
9569dae7 LB	1	/*
	2	* arch/arm/plat-orion/gpio.c
	3	*
	4	* Marvell Orion SoC GPIO handling.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
278b45b0 AL	11	#define DEBUG
278b45b0 AL	12
9569dae7 LB	13	#include <linux/kernel.h>
9569dae7 LB	14	#include <linux/init.h>
07332318	15	#include <linux/irq.h>
278b45b0	16	#include <linux/irqdomain.h>
9569dae7 LB	17	#include <linux/module.h>
	18	#include <linux/spinlock.h>
	19	#include <linux/bitops.h>
	20	#include <linux/io.h>
a8865655	21	#include <linux/gpio.h>
ff3e660b	22	#include <linux/leds.h>
278b45b0 AL	23	#include <linux/of.h>
	24	#include <linux/of_irq.h>
	25	#include <linux/of_address.h>
ce91574c	26	#include <plat/orion-gpio.h>
9569dae7	27
9eac6d0a LB	28	/*
	29	* GPIO unit register offsets.
	30	*/
	31	#define GPIO_OUT_OFF 0x0000
	32	#define GPIO_IO_CONF_OFF 0x0004
	33	#define GPIO_BLINK_EN_OFF 0x0008
	34	#define GPIO_IN_POL_OFF 0x000c
	35	#define GPIO_DATA_IN_OFF 0x0010
	36	#define GPIO_EDGE_CAUSE_OFF 0x0014
	37	#define GPIO_EDGE_MASK_OFF 0x0018
	38	#define GPIO_LEVEL_MASK_OFF 0x001c
	39
	40	struct orion_gpio_chip {
	41	struct gpio_chip chip;
	42	spinlock_t lock;
	43	void __iomem *base;
	44	unsigned long valid_input;
	45	unsigned long valid_output;
	46	int mask_offset;
	47	int secondary_irq_base;
278b45b0	48	struct irq_domain *domain;
9eac6d0a LB	49	};
	50
	51	static void __iomem GPIO_OUT(struct orion_gpio_chip ochip)
	52	{
	53	return ochip->base + GPIO_OUT_OFF;
	54	}
	55
	56	static void __iomem GPIO_IO_CONF(struct orion_gpio_chip ochip)
	57	{
	58	return ochip->base + GPIO_IO_CONF_OFF;
	59	}
	60
	61	static void __iomem GPIO_BLINK_EN(struct orion_gpio_chip ochip)
	62	{
	63	return ochip->base + GPIO_BLINK_EN_OFF;
	64	}
	65
	66	static void __iomem GPIO_IN_POL(struct orion_gpio_chip ochip)
	67	{
	68	return ochip->base + GPIO_IN_POL_OFF;
	69	}
	70
	71	static void __iomem GPIO_DATA_IN(struct orion_gpio_chip ochip)
	72	{
	73	return ochip->base + GPIO_DATA_IN_OFF;
	74	}
	75
	76	static void __iomem GPIO_EDGE_CAUSE(struct orion_gpio_chip ochip)
	77	{
	78	return ochip->base + GPIO_EDGE_CAUSE_OFF;
	79	}
	80
	81	static void __iomem GPIO_EDGE_MASK(struct orion_gpio_chip ochip)
	82	{
	83	return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
	84	}
	85
	86	static void __iomem GPIO_LEVEL_MASK(struct orion_gpio_chip ochip)
	87	{
	88	return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
	89	}
	90
9569dae7	91
9eac6d0a LB	92	static struct orion_gpio_chip orion_gpio_chips[2];
	93	static int orion_gpio_chip_count;
	94
	95	static inline void
	96	__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
9569dae7 LB	97	{
	98	u32 u;
	99
9eac6d0a	100	u = readl(GPIO_IO_CONF(ochip));
9569dae7	101	if (input)
9eac6d0a	102	u \|= 1 << pin;
9569dae7	103	else
9eac6d0a LB	104	u &= ~(1 << pin);
9eac6d0a LB	105	writel(u, GPIO_IO_CONF(ochip));
9569dae7 LB	106	}
9569dae7 LB	107
9eac6d0a	108	static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
9569dae7 LB	109	{
	110	u32 u;
	111
9eac6d0a	112	u = readl(GPIO_OUT(ochip));
9569dae7	113	if (high)
9eac6d0a	114	u \|= 1 << pin;
9569dae7	115	else
9eac6d0a LB	116	u &= ~(1 << pin);
9eac6d0a LB	117	writel(u, GPIO_OUT(ochip));
9569dae7 LB	118	}
9569dae7 LB	119
9eac6d0a LB	120	static inline void
9eac6d0a LB	121	__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
9569dae7	122	{
a8865655	123	u32 u;
9569dae7	124
9eac6d0a	125	u = readl(GPIO_BLINK_EN(ochip));
a8865655	126	if (blink)
9eac6d0a	127	u \|= 1 << pin;
a8865655	128	else
9eac6d0a LB	129	u &= ~(1 << pin);
9eac6d0a LB	130	writel(u, GPIO_BLINK_EN(ochip));
a8865655	131	}
9569dae7	132
9eac6d0a LB	133	static inline int
9eac6d0a LB	134	orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
a8865655	135	{
9eac6d0a LB	136	if (pin >= ochip->chip.ngpio)
	137	goto err_out;
	138
	139	if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
	140	goto err_out;
	141
	142	if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
	143	goto err_out;
	144
	145	return 1;
9569dae7	146
a8865655 EB	147	err_out:
	148	pr_debug("%s: invalid GPIO %d\n", __func__, pin);
	149	return false;
9569dae7	150	}
9569dae7	151
a8865655	152	/*
7fd2bf3d	153	* GPIO primitives.
a8865655	154	*/
9eac6d0a LB	155	static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
9eac6d0a LB	156	{
66d718dd	157	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
9eac6d0a LB	158
	159	if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) \|\|
	160	orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
	161	return 0;
	162
	163	return -EINVAL;
	164	}
	165
a8865655	166	static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
9569dae7	167	{
66d718dd	168	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
9569dae7	169	unsigned long flags;
9569dae7	170
9eac6d0a	171	if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
9569dae7	172	return -EINVAL;
9569dae7	173
9eac6d0a LB	174	spin_lock_irqsave(&ochip->lock, flags);
	175	__set_direction(ochip, pin, 1);
	176	spin_unlock_irqrestore(&ochip->lock, flags);
9569dae7 LB	177
	178	return 0;
	179	}
9569dae7	180
9eac6d0a	181	static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
9569dae7	182	{
66d718dd	183	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
9569dae7 LB	184	int val;
9569dae7 LB	185
9eac6d0a LB	186	if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
	187	val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
	188	} else {
	189	val = readl(GPIO_OUT(ochip));
	190	}
9569dae7	191
9eac6d0a	192	return (val >> pin) & 1;
9569dae7	193	}
9569dae7	194
9eac6d0a LB	195	static int
9eac6d0a LB	196	orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
9569dae7	197	{
66d718dd	198	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
9569dae7	199	unsigned long flags;
a8865655	200
9eac6d0a	201	if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
a8865655	202	return -EINVAL;
9569dae7	203
9eac6d0a LB	204	spin_lock_irqsave(&ochip->lock, flags);
	205	__set_blinking(ochip, pin, 0);
	206	__set_level(ochip, pin, value);
	207	__set_direction(ochip, pin, 0);
	208	spin_unlock_irqrestore(&ochip->lock, flags);
a8865655 EB	209
a8865655 EB	210	return 0;
9569dae7	211	}
9569dae7	212
9eac6d0a	213	static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
9569dae7	214	{
66d718dd	215	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
9569dae7	216	unsigned long flags;
9569dae7	217
9eac6d0a LB	218	spin_lock_irqsave(&ochip->lock, flags);
	219	__set_level(ochip, pin, value);
	220	spin_unlock_irqrestore(&ochip->lock, flags);
9569dae7	221	}
9569dae7	222
9eac6d0a	223	static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
9569dae7	224	{
66d718dd	225	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
9569dae7	226
278b45b0 AL	227	return irq_create_mapping(ochip->domain,
278b45b0 AL	228	ochip->secondary_irq_base + pin);
a8865655	229	}
9569dae7 LB	230
	231	/*
	232	* Orion-specific GPIO API extensions.
	233	*/
9eac6d0a LB	234	static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
	235	{
	236	int i;
	237
	238	for (i = 0; i < orion_gpio_chip_count; i++) {
	239	struct orion_gpio_chip *ochip = orion_gpio_chips + i;
	240	struct gpio_chip *chip = &ochip->chip;
	241
	242	if (pin >= chip->base && pin < chip->base + chip->ngpio)
	243	return ochip;
	244	}
	245
	246	return NULL;
	247	}
	248
9569dae7 LB	249	void __init orion_gpio_set_unused(unsigned pin)
9569dae7 LB	250	{
9eac6d0a LB	251	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
	252
	253	if (ochip == NULL)
	254	return;
	255
	256	pin -= ochip->chip.base;
	257
a8865655	258	/* Configure as output, drive low. */
9eac6d0a LB	259	__set_level(ochip, pin, 0);
9eac6d0a LB	260	__set_direction(ochip, pin, 0);
9569dae7 LB	261	}
9569dae7 LB	262
28d27cf4	263	void __init orion_gpio_set_valid(unsigned pin, int mode)
9569dae7	264	{
9eac6d0a LB	265	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
	266
	267	if (ochip == NULL)
	268	return;
	269
	270	pin -= ochip->chip.base;
	271
28d27cf4 NP	272	if (mode == 1)
28d27cf4 NP	273	mode = GPIO_INPUT_OK \| GPIO_OUTPUT_OK;
9eac6d0a	274
28d27cf4	275	if (mode & GPIO_INPUT_OK)
9eac6d0a	276	__set_bit(pin, &ochip->valid_input);
9569dae7	277	else
9eac6d0a LB	278	__clear_bit(pin, &ochip->valid_input);
9eac6d0a LB	279
28d27cf4	280	if (mode & GPIO_OUTPUT_OK)
9eac6d0a	281	__set_bit(pin, &ochip->valid_output);
28d27cf4	282	else
9eac6d0a	283	__clear_bit(pin, &ochip->valid_output);
9569dae7 LB	284	}
	285
	286	void orion_gpio_set_blink(unsigned pin, int blink)
	287	{
9eac6d0a	288	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
9569dae7	289	unsigned long flags;
9569dae7	290
9eac6d0a LB	291	if (ochip == NULL)
9eac6d0a LB	292	return;
9569dae7	293
9eac6d0a	294	spin_lock_irqsave(&ochip->lock, flags);
92a486ea AP	295	__set_level(ochip, pin & 31, 0);
92a486ea AP	296	__set_blinking(ochip, pin & 31, blink);
9eac6d0a	297	spin_unlock_irqrestore(&ochip->lock, flags);
9569dae7 LB	298	}
9569dae7 LB	299	EXPORT_SYMBOL(orion_gpio_set_blink);
07332318	300
ff3e660b AP	301	#define ORION_BLINK_HALF_PERIOD 100 /* ms */
ff3e660b AP	302
c673a2b4	303	int orion_gpio_led_blink_set(struct gpio_desc *desc, int state,
ff3e660b AP	304	unsigned long delay_on, unsigned long delay_off)
ff3e660b AP	305	{
c673a2b4	306	unsigned gpio = desc_to_gpio(desc);
ff3e660b AP	307
	308	if (delay_on && delay_off && !delay_on && !delay_off)
	309	delay_on = delay_off = ORION_BLINK_HALF_PERIOD;
	310
	311	switch (state) {
	312	case GPIO_LED_NO_BLINK_LOW:
	313	case GPIO_LED_NO_BLINK_HIGH:
	314	orion_gpio_set_blink(gpio, 0);
	315	gpio_set_value(gpio, state);
	316	break;
	317	case GPIO_LED_BLINK:
	318	orion_gpio_set_blink(gpio, 1);
	319	}
	320	return 0;
	321	}
	322	EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set);
	323
07332318 LB	324
	325	/*****************************************************************************
	326	* Orion GPIO IRQ
	327	*
	328	* GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
	329	* value of the line or the opposite value.
	330	*
	331	* Level IRQ handlers: DATA_IN is used directly as cause register.
	332	* Interrupt are masked by LEVEL_MASK registers.
	333	* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
	334	* Interrupt are masked by EDGE_MASK registers.
	335	* Both-edge handlers: Similar to regular Edge handlers, but also swaps
	336	* the polarity to catch the next line transaction.
	337	* This is a race condition that might not perfectly
	338	* work on some use cases.
	339	*
	340	* Every eight GPIO lines are grouped (OR'ed) before going up to main
	341	* cause register.
	342	*
	343	* EDGE cause mask
	344	* data-in /--------\| \|-----\| \|----\
	345	* -----\| \|----- ---- to main cause reg
	346	* X \----------------\| \|----/
	347	* polarity LEVEL mask
	348	*
	349	****************************************************************************/
07332318	350
3b0c8d40	351	static int gpio_irq_set_type(struct irq_data *d, u32 type)
07332318	352	{
e59347a1 TG	353	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	354	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	355	struct orion_gpio_chip *ochip = gc->private;
9eac6d0a	356	int pin;
07332318 LB	357	u32 u;
07332318 LB	358
278b45b0	359	pin = d->hwirq - ochip->secondary_irq_base;
9eac6d0a LB	360
9eac6d0a LB	361	u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
07332318	362	if (!u) {
07332318 LB	363	return -EINVAL;
	364	}
	365
e59347a1 TG	366	type &= IRQ_TYPE_SENSE_MASK;
e59347a1 TG	367	if (type == IRQ_TYPE_NONE)
07332318	368	return -EINVAL;
e59347a1 TG	369
	370	/* Check if we need to change chip and handler */
	371	if (!(ct->type & type))
	372	if (irq_setup_alt_chip(d, type))
	373	return -EINVAL;
07332318 LB	374
	375	/*
	376	* Configure interrupt polarity.
	377	*/
	378	if (type == IRQ_TYPE_EDGE_RISING \|\| type == IRQ_TYPE_LEVEL_HIGH) {
9eac6d0a LB	379	u = readl(GPIO_IN_POL(ochip));
	380	u &= ~(1 << pin);
	381	writel(u, GPIO_IN_POL(ochip));
07332318	382	} else if (type == IRQ_TYPE_EDGE_FALLING \|\| type == IRQ_TYPE_LEVEL_LOW) {
9eac6d0a LB	383	u = readl(GPIO_IN_POL(ochip));
	384	u \|= 1 << pin;
	385	writel(u, GPIO_IN_POL(ochip));
07332318 LB	386	} else if (type == IRQ_TYPE_EDGE_BOTH) {
	387	u32 v;
	388
9eac6d0a	389	v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
07332318 LB	390
	391	/*
	392	* set initial polarity based on current input level
	393	*/
9eac6d0a LB	394	u = readl(GPIO_IN_POL(ochip));
	395	if (v & (1 << pin))
	396	u \|= 1 << pin; /* falling */
07332318	397	else
9eac6d0a LB	398	u &= ~(1 << pin); /* rising */
9eac6d0a LB	399	writel(u, GPIO_IN_POL(ochip));
07332318	400	}
07332318 LB	401	return 0;
	402	}
	403
bd0b9ac4	404	static void gpio_irq_handler(struct irq_desc *desc)
278b45b0	405	{
f575398b	406	struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc);
278b45b0 AL	407	u32 cause, type;
	408	int i;
	409
	410	if (ochip == NULL)
	411	return;
	412
	413	cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
	414	cause \|= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
	415
	416	for (i = 0; i < ochip->chip.ngpio; i++) {
	417	int irq;
	418
	419	irq = ochip->secondary_irq_base + i;
	420
	421	if (!(cause & (1 << i)))
	422	continue;
	423
f88704c9	424	type = irq_get_trigger_type(irq);
278b45b0 AL	425	if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
	426	/* Swap polarity (race with GPIO line) */
	427	u32 polarity;
	428
	429	polarity = readl(GPIO_IN_POL(ochip));
	430	polarity ^= 1 << i;
	431	writel(polarity, GPIO_IN_POL(ochip));
	432	}
	433	generic_handle_irq(irq);
	434	}
	435	}
	436
8d007488 SG	437	#ifdef CONFIG_DEBUG_FS
	438	#include <linux/seq_file.h>
	439
	440	static void orion_gpio_dbg_show(struct seq_file s, struct gpio_chip chip)
	441	{
66d718dd LW	442
66d718dd LW	443	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
8d007488 SG	444	u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
	445	int i;
	446
	447	out = readl_relaxed(GPIO_OUT(ochip));
	448	io_conf = readl_relaxed(GPIO_IO_CONF(ochip));
	449	blink = readl_relaxed(GPIO_BLINK_EN(ochip));
	450	in_pol = readl_relaxed(GPIO_IN_POL(ochip));
	451	data_in = readl_relaxed(GPIO_DATA_IN(ochip));
	452	cause = readl_relaxed(GPIO_EDGE_CAUSE(ochip));
	453	edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip));
	454	lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip));
	455
	456	for (i = 0; i < chip->ngpio; i++) {
	457	const char *label;
	458	u32 msk;
	459	bool is_out;
	460
	461	label = gpiochip_is_requested(chip, i);
	462	if (!label)
	463	continue;
	464
	465	msk = 1 << i;
	466	is_out = !(io_conf & msk);
	467
	468	seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
	469
	470	if (is_out) {
	471	seq_printf(s, " out %s %s\n",
	472	out & msk ? "hi" : "lo",
	473	blink & msk ? "(blink )" : "");
	474	continue;
	475	}
	476
	477	seq_printf(s, " in %s (act %s) - IRQ",
	478	(data_in ^ in_pol) & msk ? "hi" : "lo",
	479	in_pol & msk ? "lo" : "hi");
	480	if (!((edg_msk \| lvl_msk) & msk)) {
	481	seq_printf(s, " disabled\n");
	482	continue;
	483	}
	484	if (edg_msk & msk)
	485	seq_printf(s, " edge ");
	486	if (lvl_msk & msk)
	487	seq_printf(s, " level");
	488	seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
	489	}
	490	}
	491	#else
	492	#define orion_gpio_dbg_show NULL
	493	#endif
	494
9ece8839 ED	495	static void orion_gpio_unmask_irq(struct irq_data *d)
	496	{
	497	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	498	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	499	u32 reg_val;
	500	u32 mask = d->mask;
	501
	502	irq_gc_lock(gc);
2f90bce7	503	reg_val = irq_reg_readl(gc, ct->regs.mask);
9ece8839	504	reg_val \|= mask;
2f90bce7	505	irq_reg_writel(gc, reg_val, ct->regs.mask);
9ece8839 ED	506	irq_gc_unlock(gc);
	507	}
	508
	509	static void orion_gpio_mask_irq(struct irq_data *d)
	510	{
	511	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	512	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	513	u32 mask = d->mask;
	514	u32 reg_val;
	515
	516	irq_gc_lock(gc);
2f90bce7	517	reg_val = irq_reg_readl(gc, ct->regs.mask);
9ece8839	518	reg_val &= ~mask;
2f90bce7	519	irq_reg_writel(gc, reg_val, ct->regs.mask);
9ece8839 ED	520	irq_gc_unlock(gc);
	521	}
	522
278b45b0 AL	523	void __init orion_gpio_init(struct device_node *np,
	524	int gpio_base, int ngpio,
	525	void __iomem *base, int mask_offset,
	526	int secondary_irq_base,
	527	int irqs[4])
9eac6d0a LB	528	{
9eac6d0a LB	529	struct orion_gpio_chip *ochip;
e59347a1 TG	530	struct irq_chip_generic *gc;
e59347a1 TG	531	struct irq_chip_type *ct;
0b35a45b	532	char gc_label[16];
278b45b0	533	int i;
9eac6d0a LB	534
	535	if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
	536	return;
	537
0b35a45b HB	538	snprintf(gc_label, sizeof(gc_label), "orion_gpio%d",
	539	orion_gpio_chip_count);
	540
9eac6d0a	541	ochip = orion_gpio_chips + orion_gpio_chip_count;
0b35a45b	542	ochip->chip.label = kstrdup(gc_label, GFP_KERNEL);
9eac6d0a LB	543	ochip->chip.request = orion_gpio_request;
	544	ochip->chip.direction_input = orion_gpio_direction_input;
	545	ochip->chip.get = orion_gpio_get;
	546	ochip->chip.direction_output = orion_gpio_direction_output;
	547	ochip->chip.set = orion_gpio_set;
	548	ochip->chip.to_irq = orion_gpio_to_irq;
	549	ochip->chip.base = gpio_base;
	550	ochip->chip.ngpio = ngpio;
	551	ochip->chip.can_sleep = 0;
278b45b0 AL	552	#ifdef CONFIG_OF
	553	ochip->chip.of_node = np;
	554	#endif
8d007488	555	ochip->chip.dbg_show = orion_gpio_dbg_show;
278b45b0	556
9eac6d0a LB	557	spin_lock_init(&ochip->lock);
	558	ochip->base = (void __iomem *)base;
	559	ochip->valid_input = 0;
	560	ochip->valid_output = 0;
	561	ochip->mask_offset = mask_offset;
	562	ochip->secondary_irq_base = secondary_irq_base;
	563
66d718dd	564	gpiochip_add_data(&ochip->chip, ochip);
9eac6d0a	565
9eac6d0a LB	566	/*
	567	* Mask and clear GPIO interrupts.
	568	*/
	569	writel(0, GPIO_EDGE_CAUSE(ochip));
	570	writel(0, GPIO_EDGE_MASK(ochip));
	571	writel(0, GPIO_LEVEL_MASK(ochip));
	572
278b45b0 AL	573	/* Setup the interrupt handlers. Each chip can have up to 4
	574	* interrupt handlers, with each handler dealing with 8 GPIO
	575	* pins. */
	576
	577	for (i = 0; i < 4; i++) {
	578	if (irqs[i]) {
206287c2 TG	579	irq_set_chained_handler_and_data(irqs[i],
	580	gpio_irq_handler,
	581	ochip);
278b45b0 AL	582	}
	583	}
	584
	585	gc = irq_alloc_generic_chip("orion_gpio_irq", 2,
	586	secondary_irq_base,
e59347a1 TG	587	ochip->base, handle_level_irq);
e59347a1 TG	588	gc->private = ochip;
e59347a1 TG	589	ct = gc->chip_types;
	590	ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
	591	ct->type = IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW;
9ece8839 ED	592	ct->chip.irq_mask = orion_gpio_mask_irq;
9ece8839 ED	593	ct->chip.irq_unmask = orion_gpio_unmask_irq;
e59347a1	594	ct->chip.irq_set_type = gpio_irq_set_type;
278b45b0	595	ct->chip.name = ochip->chip.label;
e59347a1 TG	596
	597	ct++;
	598	ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
	599	ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
	600	ct->type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
659fb32d	601	ct->chip.irq_ack = irq_gc_ack_clr_bit;
9ece8839 ED	602	ct->chip.irq_mask = orion_gpio_mask_irq;
9ece8839 ED	603	ct->chip.irq_unmask = orion_gpio_unmask_irq;
e59347a1 TG	604	ct->chip.irq_set_type = gpio_irq_set_type;
e59347a1 TG	605	ct->handler = handle_edge_irq;
278b45b0	606	ct->chip.name = ochip->chip.label;
e59347a1 TG	607
	608	irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
	609	IRQ_NOREQUEST, IRQ_LEVEL \| IRQ_NOPROBE);
9eac6d0a	610
278b45b0 AL	611	/* Setup irq domain on top of the generic chip. */
	612	ochip->domain = irq_domain_add_legacy(np,
	613	ochip->chip.ngpio,
	614	ochip->secondary_irq_base,
	615	ochip->secondary_irq_base,
	616	&irq_domain_simple_ops,
	617	ochip);
	618	if (!ochip->domain)
	619	panic("%s: couldn't allocate irq domain (DT).\n",
	620	ochip->chip.label);
9eac6d0a	621
278b45b0 AL	622	orion_gpio_chip_count++;
278b45b0 AL	623	}