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Commit | Line | Data |
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9569dae7 LB |
1 | /* |
2 | * arch/arm/plat-orion/gpio.c | |
3 | * | |
4 | * Marvell Orion SoC GPIO handling. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
278b45b0 AL |
11 | #define DEBUG |
12 | ||
9569dae7 LB |
13 | #include <linux/kernel.h> |
14 | #include <linux/init.h> | |
07332318 | 15 | #include <linux/irq.h> |
278b45b0 | 16 | #include <linux/irqdomain.h> |
9569dae7 LB |
17 | #include <linux/module.h> |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/bitops.h> | |
20 | #include <linux/io.h> | |
a8865655 | 21 | #include <linux/gpio.h> |
ff3e660b | 22 | #include <linux/leds.h> |
278b45b0 AL |
23 | #include <linux/of.h> |
24 | #include <linux/of_irq.h> | |
25 | #include <linux/of_address.h> | |
ce91574c | 26 | #include <plat/orion-gpio.h> |
9569dae7 | 27 | |
9eac6d0a LB |
28 | /* |
29 | * GPIO unit register offsets. | |
30 | */ | |
31 | #define GPIO_OUT_OFF 0x0000 | |
32 | #define GPIO_IO_CONF_OFF 0x0004 | |
33 | #define GPIO_BLINK_EN_OFF 0x0008 | |
34 | #define GPIO_IN_POL_OFF 0x000c | |
35 | #define GPIO_DATA_IN_OFF 0x0010 | |
36 | #define GPIO_EDGE_CAUSE_OFF 0x0014 | |
37 | #define GPIO_EDGE_MASK_OFF 0x0018 | |
38 | #define GPIO_LEVEL_MASK_OFF 0x001c | |
39 | ||
40 | struct orion_gpio_chip { | |
41 | struct gpio_chip chip; | |
42 | spinlock_t lock; | |
43 | void __iomem *base; | |
44 | unsigned long valid_input; | |
45 | unsigned long valid_output; | |
46 | int mask_offset; | |
47 | int secondary_irq_base; | |
278b45b0 | 48 | struct irq_domain *domain; |
9eac6d0a LB |
49 | }; |
50 | ||
51 | static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip) | |
52 | { | |
53 | return ochip->base + GPIO_OUT_OFF; | |
54 | } | |
55 | ||
56 | static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip) | |
57 | { | |
58 | return ochip->base + GPIO_IO_CONF_OFF; | |
59 | } | |
60 | ||
61 | static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip) | |
62 | { | |
63 | return ochip->base + GPIO_BLINK_EN_OFF; | |
64 | } | |
65 | ||
66 | static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip) | |
67 | { | |
68 | return ochip->base + GPIO_IN_POL_OFF; | |
69 | } | |
70 | ||
71 | static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip) | |
72 | { | |
73 | return ochip->base + GPIO_DATA_IN_OFF; | |
74 | } | |
75 | ||
76 | static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip) | |
77 | { | |
78 | return ochip->base + GPIO_EDGE_CAUSE_OFF; | |
79 | } | |
80 | ||
81 | static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip) | |
82 | { | |
83 | return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF; | |
84 | } | |
85 | ||
86 | static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip) | |
87 | { | |
88 | return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF; | |
89 | } | |
90 | ||
9569dae7 | 91 | |
9eac6d0a LB |
92 | static struct orion_gpio_chip orion_gpio_chips[2]; |
93 | static int orion_gpio_chip_count; | |
94 | ||
95 | static inline void | |
96 | __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input) | |
9569dae7 LB |
97 | { |
98 | u32 u; | |
99 | ||
9eac6d0a | 100 | u = readl(GPIO_IO_CONF(ochip)); |
9569dae7 | 101 | if (input) |
9eac6d0a | 102 | u |= 1 << pin; |
9569dae7 | 103 | else |
9eac6d0a LB |
104 | u &= ~(1 << pin); |
105 | writel(u, GPIO_IO_CONF(ochip)); | |
9569dae7 LB |
106 | } |
107 | ||
9eac6d0a | 108 | static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high) |
9569dae7 LB |
109 | { |
110 | u32 u; | |
111 | ||
9eac6d0a | 112 | u = readl(GPIO_OUT(ochip)); |
9569dae7 | 113 | if (high) |
9eac6d0a | 114 | u |= 1 << pin; |
9569dae7 | 115 | else |
9eac6d0a LB |
116 | u &= ~(1 << pin); |
117 | writel(u, GPIO_OUT(ochip)); | |
9569dae7 LB |
118 | } |
119 | ||
9eac6d0a LB |
120 | static inline void |
121 | __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink) | |
9569dae7 | 122 | { |
a8865655 | 123 | u32 u; |
9569dae7 | 124 | |
9eac6d0a | 125 | u = readl(GPIO_BLINK_EN(ochip)); |
a8865655 | 126 | if (blink) |
9eac6d0a | 127 | u |= 1 << pin; |
a8865655 | 128 | else |
9eac6d0a LB |
129 | u &= ~(1 << pin); |
130 | writel(u, GPIO_BLINK_EN(ochip)); | |
a8865655 | 131 | } |
9569dae7 | 132 | |
9eac6d0a LB |
133 | static inline int |
134 | orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode) | |
a8865655 | 135 | { |
9eac6d0a LB |
136 | if (pin >= ochip->chip.ngpio) |
137 | goto err_out; | |
138 | ||
139 | if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input)) | |
140 | goto err_out; | |
141 | ||
142 | if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output)) | |
143 | goto err_out; | |
144 | ||
145 | return 1; | |
9569dae7 | 146 | |
a8865655 EB |
147 | err_out: |
148 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | |
149 | return false; | |
9569dae7 | 150 | } |
9569dae7 | 151 | |
a8865655 | 152 | /* |
7fd2bf3d | 153 | * GPIO primitives. |
a8865655 | 154 | */ |
9eac6d0a LB |
155 | static int orion_gpio_request(struct gpio_chip *chip, unsigned pin) |
156 | { | |
157 | struct orion_gpio_chip *ochip = | |
158 | container_of(chip, struct orion_gpio_chip, chip); | |
159 | ||
160 | if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) || | |
161 | orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) | |
162 | return 0; | |
163 | ||
164 | return -EINVAL; | |
165 | } | |
166 | ||
a8865655 | 167 | static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin) |
9569dae7 | 168 | { |
9eac6d0a LB |
169 | struct orion_gpio_chip *ochip = |
170 | container_of(chip, struct orion_gpio_chip, chip); | |
9569dae7 | 171 | unsigned long flags; |
9569dae7 | 172 | |
9eac6d0a | 173 | if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK)) |
9569dae7 | 174 | return -EINVAL; |
9569dae7 | 175 | |
9eac6d0a LB |
176 | spin_lock_irqsave(&ochip->lock, flags); |
177 | __set_direction(ochip, pin, 1); | |
178 | spin_unlock_irqrestore(&ochip->lock, flags); | |
9569dae7 LB |
179 | |
180 | return 0; | |
181 | } | |
9569dae7 | 182 | |
9eac6d0a | 183 | static int orion_gpio_get(struct gpio_chip *chip, unsigned pin) |
9569dae7 | 184 | { |
9eac6d0a LB |
185 | struct orion_gpio_chip *ochip = |
186 | container_of(chip, struct orion_gpio_chip, chip); | |
9569dae7 LB |
187 | int val; |
188 | ||
9eac6d0a LB |
189 | if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) { |
190 | val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip)); | |
191 | } else { | |
192 | val = readl(GPIO_OUT(ochip)); | |
193 | } | |
9569dae7 | 194 | |
9eac6d0a | 195 | return (val >> pin) & 1; |
9569dae7 | 196 | } |
9569dae7 | 197 | |
9eac6d0a LB |
198 | static int |
199 | orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value) | |
9569dae7 | 200 | { |
9eac6d0a LB |
201 | struct orion_gpio_chip *ochip = |
202 | container_of(chip, struct orion_gpio_chip, chip); | |
9569dae7 | 203 | unsigned long flags; |
a8865655 | 204 | |
9eac6d0a | 205 | if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) |
a8865655 | 206 | return -EINVAL; |
9569dae7 | 207 | |
9eac6d0a LB |
208 | spin_lock_irqsave(&ochip->lock, flags); |
209 | __set_blinking(ochip, pin, 0); | |
210 | __set_level(ochip, pin, value); | |
211 | __set_direction(ochip, pin, 0); | |
212 | spin_unlock_irqrestore(&ochip->lock, flags); | |
a8865655 EB |
213 | |
214 | return 0; | |
9569dae7 | 215 | } |
9569dae7 | 216 | |
9eac6d0a | 217 | static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value) |
9569dae7 | 218 | { |
9eac6d0a LB |
219 | struct orion_gpio_chip *ochip = |
220 | container_of(chip, struct orion_gpio_chip, chip); | |
9569dae7 | 221 | unsigned long flags; |
9569dae7 | 222 | |
9eac6d0a LB |
223 | spin_lock_irqsave(&ochip->lock, flags); |
224 | __set_level(ochip, pin, value); | |
225 | spin_unlock_irqrestore(&ochip->lock, flags); | |
9569dae7 | 226 | } |
9569dae7 | 227 | |
9eac6d0a | 228 | static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin) |
9569dae7 | 229 | { |
9eac6d0a LB |
230 | struct orion_gpio_chip *ochip = |
231 | container_of(chip, struct orion_gpio_chip, chip); | |
9569dae7 | 232 | |
278b45b0 AL |
233 | return irq_create_mapping(ochip->domain, |
234 | ochip->secondary_irq_base + pin); | |
a8865655 | 235 | } |
9569dae7 LB |
236 | |
237 | /* | |
238 | * Orion-specific GPIO API extensions. | |
239 | */ | |
9eac6d0a LB |
240 | static struct orion_gpio_chip *orion_gpio_chip_find(int pin) |
241 | { | |
242 | int i; | |
243 | ||
244 | for (i = 0; i < orion_gpio_chip_count; i++) { | |
245 | struct orion_gpio_chip *ochip = orion_gpio_chips + i; | |
246 | struct gpio_chip *chip = &ochip->chip; | |
247 | ||
248 | if (pin >= chip->base && pin < chip->base + chip->ngpio) | |
249 | return ochip; | |
250 | } | |
251 | ||
252 | return NULL; | |
253 | } | |
254 | ||
9569dae7 LB |
255 | void __init orion_gpio_set_unused(unsigned pin) |
256 | { | |
9eac6d0a LB |
257 | struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); |
258 | ||
259 | if (ochip == NULL) | |
260 | return; | |
261 | ||
262 | pin -= ochip->chip.base; | |
263 | ||
a8865655 | 264 | /* Configure as output, drive low. */ |
9eac6d0a LB |
265 | __set_level(ochip, pin, 0); |
266 | __set_direction(ochip, pin, 0); | |
9569dae7 LB |
267 | } |
268 | ||
28d27cf4 | 269 | void __init orion_gpio_set_valid(unsigned pin, int mode) |
9569dae7 | 270 | { |
9eac6d0a LB |
271 | struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); |
272 | ||
273 | if (ochip == NULL) | |
274 | return; | |
275 | ||
276 | pin -= ochip->chip.base; | |
277 | ||
28d27cf4 NP |
278 | if (mode == 1) |
279 | mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; | |
9eac6d0a | 280 | |
28d27cf4 | 281 | if (mode & GPIO_INPUT_OK) |
9eac6d0a | 282 | __set_bit(pin, &ochip->valid_input); |
9569dae7 | 283 | else |
9eac6d0a LB |
284 | __clear_bit(pin, &ochip->valid_input); |
285 | ||
28d27cf4 | 286 | if (mode & GPIO_OUTPUT_OK) |
9eac6d0a | 287 | __set_bit(pin, &ochip->valid_output); |
28d27cf4 | 288 | else |
9eac6d0a | 289 | __clear_bit(pin, &ochip->valid_output); |
9569dae7 LB |
290 | } |
291 | ||
292 | void orion_gpio_set_blink(unsigned pin, int blink) | |
293 | { | |
9eac6d0a | 294 | struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); |
9569dae7 | 295 | unsigned long flags; |
9569dae7 | 296 | |
9eac6d0a LB |
297 | if (ochip == NULL) |
298 | return; | |
9569dae7 | 299 | |
9eac6d0a | 300 | spin_lock_irqsave(&ochip->lock, flags); |
92a486ea AP |
301 | __set_level(ochip, pin & 31, 0); |
302 | __set_blinking(ochip, pin & 31, blink); | |
9eac6d0a | 303 | spin_unlock_irqrestore(&ochip->lock, flags); |
9569dae7 LB |
304 | } |
305 | EXPORT_SYMBOL(orion_gpio_set_blink); | |
07332318 | 306 | |
ff3e660b AP |
307 | #define ORION_BLINK_HALF_PERIOD 100 /* ms */ |
308 | ||
c673a2b4 | 309 | int orion_gpio_led_blink_set(struct gpio_desc *desc, int state, |
ff3e660b AP |
310 | unsigned long *delay_on, unsigned long *delay_off) |
311 | { | |
c673a2b4 | 312 | unsigned gpio = desc_to_gpio(desc); |
ff3e660b AP |
313 | |
314 | if (delay_on && delay_off && !*delay_on && !*delay_off) | |
315 | *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD; | |
316 | ||
317 | switch (state) { | |
318 | case GPIO_LED_NO_BLINK_LOW: | |
319 | case GPIO_LED_NO_BLINK_HIGH: | |
320 | orion_gpio_set_blink(gpio, 0); | |
321 | gpio_set_value(gpio, state); | |
322 | break; | |
323 | case GPIO_LED_BLINK: | |
324 | orion_gpio_set_blink(gpio, 1); | |
325 | } | |
326 | return 0; | |
327 | } | |
328 | EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set); | |
329 | ||
07332318 LB |
330 | |
331 | /***************************************************************************** | |
332 | * Orion GPIO IRQ | |
333 | * | |
334 | * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same | |
335 | * value of the line or the opposite value. | |
336 | * | |
337 | * Level IRQ handlers: DATA_IN is used directly as cause register. | |
338 | * Interrupt are masked by LEVEL_MASK registers. | |
339 | * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. | |
340 | * Interrupt are masked by EDGE_MASK registers. | |
341 | * Both-edge handlers: Similar to regular Edge handlers, but also swaps | |
342 | * the polarity to catch the next line transaction. | |
343 | * This is a race condition that might not perfectly | |
344 | * work on some use cases. | |
345 | * | |
346 | * Every eight GPIO lines are grouped (OR'ed) before going up to main | |
347 | * cause register. | |
348 | * | |
349 | * EDGE cause mask | |
350 | * data-in /--------| |-----| |----\ | |
351 | * -----| |----- ---- to main cause reg | |
352 | * X \----------------| |----/ | |
353 | * polarity LEVEL mask | |
354 | * | |
355 | ****************************************************************************/ | |
07332318 | 356 | |
3b0c8d40 | 357 | static int gpio_irq_set_type(struct irq_data *d, u32 type) |
07332318 | 358 | { |
e59347a1 TG |
359 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
360 | struct irq_chip_type *ct = irq_data_get_chip_type(d); | |
361 | struct orion_gpio_chip *ochip = gc->private; | |
9eac6d0a | 362 | int pin; |
07332318 LB |
363 | u32 u; |
364 | ||
278b45b0 | 365 | pin = d->hwirq - ochip->secondary_irq_base; |
9eac6d0a LB |
366 | |
367 | u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); | |
07332318 | 368 | if (!u) { |
07332318 LB |
369 | return -EINVAL; |
370 | } | |
371 | ||
e59347a1 TG |
372 | type &= IRQ_TYPE_SENSE_MASK; |
373 | if (type == IRQ_TYPE_NONE) | |
07332318 | 374 | return -EINVAL; |
e59347a1 TG |
375 | |
376 | /* Check if we need to change chip and handler */ | |
377 | if (!(ct->type & type)) | |
378 | if (irq_setup_alt_chip(d, type)) | |
379 | return -EINVAL; | |
07332318 LB |
380 | |
381 | /* | |
382 | * Configure interrupt polarity. | |
383 | */ | |
384 | if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) { | |
9eac6d0a LB |
385 | u = readl(GPIO_IN_POL(ochip)); |
386 | u &= ~(1 << pin); | |
387 | writel(u, GPIO_IN_POL(ochip)); | |
07332318 | 388 | } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) { |
9eac6d0a LB |
389 | u = readl(GPIO_IN_POL(ochip)); |
390 | u |= 1 << pin; | |
391 | writel(u, GPIO_IN_POL(ochip)); | |
07332318 LB |
392 | } else if (type == IRQ_TYPE_EDGE_BOTH) { |
393 | u32 v; | |
394 | ||
9eac6d0a | 395 | v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip)); |
07332318 LB |
396 | |
397 | /* | |
398 | * set initial polarity based on current input level | |
399 | */ | |
9eac6d0a LB |
400 | u = readl(GPIO_IN_POL(ochip)); |
401 | if (v & (1 << pin)) | |
402 | u |= 1 << pin; /* falling */ | |
07332318 | 403 | else |
9eac6d0a LB |
404 | u &= ~(1 << pin); /* rising */ |
405 | writel(u, GPIO_IN_POL(ochip)); | |
07332318 | 406 | } |
07332318 LB |
407 | return 0; |
408 | } | |
409 | ||
bd0b9ac4 | 410 | static void gpio_irq_handler(struct irq_desc *desc) |
278b45b0 | 411 | { |
f575398b | 412 | struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc); |
278b45b0 AL |
413 | u32 cause, type; |
414 | int i; | |
415 | ||
416 | if (ochip == NULL) | |
417 | return; | |
418 | ||
419 | cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip)); | |
420 | cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip)); | |
421 | ||
422 | for (i = 0; i < ochip->chip.ngpio; i++) { | |
423 | int irq; | |
424 | ||
425 | irq = ochip->secondary_irq_base + i; | |
426 | ||
427 | if (!(cause & (1 << i))) | |
428 | continue; | |
429 | ||
f88704c9 | 430 | type = irq_get_trigger_type(irq); |
278b45b0 AL |
431 | if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
432 | /* Swap polarity (race with GPIO line) */ | |
433 | u32 polarity; | |
434 | ||
435 | polarity = readl(GPIO_IN_POL(ochip)); | |
436 | polarity ^= 1 << i; | |
437 | writel(polarity, GPIO_IN_POL(ochip)); | |
438 | } | |
439 | generic_handle_irq(irq); | |
440 | } | |
441 | } | |
442 | ||
8d007488 SG |
443 | #ifdef CONFIG_DEBUG_FS |
444 | #include <linux/seq_file.h> | |
445 | ||
446 | static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
447 | { | |
448 | struct orion_gpio_chip *ochip = | |
449 | container_of(chip, struct orion_gpio_chip, chip); | |
450 | u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; | |
451 | int i; | |
452 | ||
453 | out = readl_relaxed(GPIO_OUT(ochip)); | |
454 | io_conf = readl_relaxed(GPIO_IO_CONF(ochip)); | |
455 | blink = readl_relaxed(GPIO_BLINK_EN(ochip)); | |
456 | in_pol = readl_relaxed(GPIO_IN_POL(ochip)); | |
457 | data_in = readl_relaxed(GPIO_DATA_IN(ochip)); | |
458 | cause = readl_relaxed(GPIO_EDGE_CAUSE(ochip)); | |
459 | edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip)); | |
460 | lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip)); | |
461 | ||
462 | for (i = 0; i < chip->ngpio; i++) { | |
463 | const char *label; | |
464 | u32 msk; | |
465 | bool is_out; | |
466 | ||
467 | label = gpiochip_is_requested(chip, i); | |
468 | if (!label) | |
469 | continue; | |
470 | ||
471 | msk = 1 << i; | |
472 | is_out = !(io_conf & msk); | |
473 | ||
474 | seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); | |
475 | ||
476 | if (is_out) { | |
477 | seq_printf(s, " out %s %s\n", | |
478 | out & msk ? "hi" : "lo", | |
479 | blink & msk ? "(blink )" : ""); | |
480 | continue; | |
481 | } | |
482 | ||
483 | seq_printf(s, " in %s (act %s) - IRQ", | |
484 | (data_in ^ in_pol) & msk ? "hi" : "lo", | |
485 | in_pol & msk ? "lo" : "hi"); | |
486 | if (!((edg_msk | lvl_msk) & msk)) { | |
487 | seq_printf(s, " disabled\n"); | |
488 | continue; | |
489 | } | |
490 | if (edg_msk & msk) | |
491 | seq_printf(s, " edge "); | |
492 | if (lvl_msk & msk) | |
493 | seq_printf(s, " level"); | |
494 | seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); | |
495 | } | |
496 | } | |
497 | #else | |
498 | #define orion_gpio_dbg_show NULL | |
499 | #endif | |
500 | ||
9ece8839 ED |
501 | static void orion_gpio_unmask_irq(struct irq_data *d) |
502 | { | |
503 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
504 | struct irq_chip_type *ct = irq_data_get_chip_type(d); | |
505 | u32 reg_val; | |
506 | u32 mask = d->mask; | |
507 | ||
508 | irq_gc_lock(gc); | |
2f90bce7 | 509 | reg_val = irq_reg_readl(gc, ct->regs.mask); |
9ece8839 | 510 | reg_val |= mask; |
2f90bce7 | 511 | irq_reg_writel(gc, reg_val, ct->regs.mask); |
9ece8839 ED |
512 | irq_gc_unlock(gc); |
513 | } | |
514 | ||
515 | static void orion_gpio_mask_irq(struct irq_data *d) | |
516 | { | |
517 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
518 | struct irq_chip_type *ct = irq_data_get_chip_type(d); | |
519 | u32 mask = d->mask; | |
520 | u32 reg_val; | |
521 | ||
522 | irq_gc_lock(gc); | |
2f90bce7 | 523 | reg_val = irq_reg_readl(gc, ct->regs.mask); |
9ece8839 | 524 | reg_val &= ~mask; |
2f90bce7 | 525 | irq_reg_writel(gc, reg_val, ct->regs.mask); |
9ece8839 ED |
526 | irq_gc_unlock(gc); |
527 | } | |
528 | ||
278b45b0 AL |
529 | void __init orion_gpio_init(struct device_node *np, |
530 | int gpio_base, int ngpio, | |
531 | void __iomem *base, int mask_offset, | |
532 | int secondary_irq_base, | |
533 | int irqs[4]) | |
9eac6d0a LB |
534 | { |
535 | struct orion_gpio_chip *ochip; | |
e59347a1 TG |
536 | struct irq_chip_generic *gc; |
537 | struct irq_chip_type *ct; | |
0b35a45b | 538 | char gc_label[16]; |
278b45b0 | 539 | int i; |
9eac6d0a LB |
540 | |
541 | if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips)) | |
542 | return; | |
543 | ||
0b35a45b HB |
544 | snprintf(gc_label, sizeof(gc_label), "orion_gpio%d", |
545 | orion_gpio_chip_count); | |
546 | ||
9eac6d0a | 547 | ochip = orion_gpio_chips + orion_gpio_chip_count; |
0b35a45b | 548 | ochip->chip.label = kstrdup(gc_label, GFP_KERNEL); |
9eac6d0a LB |
549 | ochip->chip.request = orion_gpio_request; |
550 | ochip->chip.direction_input = orion_gpio_direction_input; | |
551 | ochip->chip.get = orion_gpio_get; | |
552 | ochip->chip.direction_output = orion_gpio_direction_output; | |
553 | ochip->chip.set = orion_gpio_set; | |
554 | ochip->chip.to_irq = orion_gpio_to_irq; | |
555 | ochip->chip.base = gpio_base; | |
556 | ochip->chip.ngpio = ngpio; | |
557 | ochip->chip.can_sleep = 0; | |
278b45b0 AL |
558 | #ifdef CONFIG_OF |
559 | ochip->chip.of_node = np; | |
560 | #endif | |
8d007488 | 561 | ochip->chip.dbg_show = orion_gpio_dbg_show; |
278b45b0 | 562 | |
9eac6d0a LB |
563 | spin_lock_init(&ochip->lock); |
564 | ochip->base = (void __iomem *)base; | |
565 | ochip->valid_input = 0; | |
566 | ochip->valid_output = 0; | |
567 | ochip->mask_offset = mask_offset; | |
568 | ochip->secondary_irq_base = secondary_irq_base; | |
569 | ||
570 | gpiochip_add(&ochip->chip); | |
571 | ||
9eac6d0a LB |
572 | /* |
573 | * Mask and clear GPIO interrupts. | |
574 | */ | |
575 | writel(0, GPIO_EDGE_CAUSE(ochip)); | |
576 | writel(0, GPIO_EDGE_MASK(ochip)); | |
577 | writel(0, GPIO_LEVEL_MASK(ochip)); | |
578 | ||
278b45b0 AL |
579 | /* Setup the interrupt handlers. Each chip can have up to 4 |
580 | * interrupt handlers, with each handler dealing with 8 GPIO | |
581 | * pins. */ | |
582 | ||
583 | for (i = 0; i < 4; i++) { | |
584 | if (irqs[i]) { | |
206287c2 TG |
585 | irq_set_chained_handler_and_data(irqs[i], |
586 | gpio_irq_handler, | |
587 | ochip); | |
278b45b0 AL |
588 | } |
589 | } | |
590 | ||
591 | gc = irq_alloc_generic_chip("orion_gpio_irq", 2, | |
592 | secondary_irq_base, | |
e59347a1 TG |
593 | ochip->base, handle_level_irq); |
594 | gc->private = ochip; | |
e59347a1 TG |
595 | ct = gc->chip_types; |
596 | ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF; | |
597 | ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; | |
9ece8839 ED |
598 | ct->chip.irq_mask = orion_gpio_mask_irq; |
599 | ct->chip.irq_unmask = orion_gpio_unmask_irq; | |
e59347a1 | 600 | ct->chip.irq_set_type = gpio_irq_set_type; |
278b45b0 | 601 | ct->chip.name = ochip->chip.label; |
e59347a1 TG |
602 | |
603 | ct++; | |
604 | ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF; | |
605 | ct->regs.ack = GPIO_EDGE_CAUSE_OFF; | |
606 | ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
659fb32d | 607 | ct->chip.irq_ack = irq_gc_ack_clr_bit; |
9ece8839 ED |
608 | ct->chip.irq_mask = orion_gpio_mask_irq; |
609 | ct->chip.irq_unmask = orion_gpio_unmask_irq; | |
e59347a1 TG |
610 | ct->chip.irq_set_type = gpio_irq_set_type; |
611 | ct->handler = handle_edge_irq; | |
278b45b0 | 612 | ct->chip.name = ochip->chip.label; |
e59347a1 TG |
613 | |
614 | irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, | |
615 | IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); | |
9eac6d0a | 616 | |
278b45b0 AL |
617 | /* Setup irq domain on top of the generic chip. */ |
618 | ochip->domain = irq_domain_add_legacy(np, | |
619 | ochip->chip.ngpio, | |
620 | ochip->secondary_irq_base, | |
621 | ochip->secondary_irq_base, | |
622 | &irq_domain_simple_ops, | |
623 | ochip); | |
624 | if (!ochip->domain) | |
625 | panic("%s: couldn't allocate irq domain (DT).\n", | |
626 | ochip->chip.label); | |
9eac6d0a | 627 | |
278b45b0 AL |
628 | orion_gpio_chip_count++; |
629 | } |