[mirror_ubuntu-zesty-kernel.git] / arch / arm / plat-orion / gpio.c

/*
 * arch/arm/plat-orion/gpio.c
 *
 * Marvell Orion SoC GPIO handling.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/leds.h>

/*
 * GPIO unit register offsets.
 */
#define GPIO_OUT_OFF		0x0000
#define GPIO_IO_CONF_OFF	0x0004
#define GPIO_BLINK_EN_OFF	0x0008
#define GPIO_IN_POL_OFF		0x000c
#define GPIO_DATA_IN_OFF	0x0010
#define GPIO_EDGE_CAUSE_OFF	0x0014
#define GPIO_EDGE_MASK_OFF	0x0018
#define GPIO_LEVEL_MASK_OFF	0x001c

struct orion_gpio_chip {
	struct gpio_chip	chip;
	spinlock_t		lock;
	void __iomem		*base;
	unsigned long		valid_input;
	unsigned long		valid_output;
	int			mask_offset;
	int			secondary_irq_base;
};

static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
{
	return ochip->base + GPIO_OUT_OFF;
}

static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
{
	return ochip->base + GPIO_IO_CONF_OFF;
}

static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
{
	return ochip->base + GPIO_BLINK_EN_OFF;
}

static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
{
	return ochip->base + GPIO_IN_POL_OFF;
}

static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
{
	return ochip->base + GPIO_DATA_IN_OFF;
}

static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
{
	return ochip->base + GPIO_EDGE_CAUSE_OFF;
}

static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
{
	return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
}

static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
{
	return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
}


static struct orion_gpio_chip orion_gpio_chips[2];
static int orion_gpio_chip_count;

static inline void
__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
{
	u32 u;

	u = readl(GPIO_IO_CONF(ochip));
	if (input)
		u |= 1 << pin;
	else
		u &= ~(1 << pin);
	writel(u, GPIO_IO_CONF(ochip));
}

static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
{
	u32 u;

	u = readl(GPIO_OUT(ochip));
	if (high)
		u |= 1 << pin;
	else
		u &= ~(1 << pin);
	writel(u, GPIO_OUT(ochip));
}

static inline void
__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
{
	u32 u;

	u = readl(GPIO_BLINK_EN(ochip));
	if (blink)
		u |= 1 << pin;
	else
		u &= ~(1 << pin);
	writel(u, GPIO_BLINK_EN(ochip));
}

static inline int
orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
{
	if (pin >= ochip->chip.ngpio)
		goto err_out;

	if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
		goto err_out;

	if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
		goto err_out;

	return 1;

err_out:
	pr_debug("%s: invalid GPIO %d\n", __func__, pin);
	return false;
}

/*
 * GENERIC_GPIO primitives.
 */
static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
{
	struct orion_gpio_chip *ochip =
		container_of(chip, struct orion_gpio_chip, chip);

	if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
	    orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
		return 0;

	return -EINVAL;
}

static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
{
	struct orion_gpio_chip *ochip =
		container_of(chip, struct orion_gpio_chip, chip);
	unsigned long flags;

	if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
		return -EINVAL;

	spin_lock_irqsave(&ochip->lock, flags);
	__set_direction(ochip, pin, 1);
	spin_unlock_irqrestore(&ochip->lock, flags);

	return 0;
}

static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
{
	struct orion_gpio_chip *ochip =
		container_of(chip, struct orion_gpio_chip, chip);
	int val;

	if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
		val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
	} else {
		val = readl(GPIO_OUT(ochip));
	}

	return (val >> pin) & 1;
}

static int
orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
{
	struct orion_gpio_chip *ochip =
		container_of(chip, struct orion_gpio_chip, chip);
	unsigned long flags;

	if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
		return -EINVAL;

	spin_lock_irqsave(&ochip->lock, flags);
	__set_blinking(ochip, pin, 0);
	__set_level(ochip, pin, value);
	__set_direction(ochip, pin, 0);
	spin_unlock_irqrestore(&ochip->lock, flags);

	return 0;
}

static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
{
	struct orion_gpio_chip *ochip =
		container_of(chip, struct orion_gpio_chip, chip);
	unsigned long flags;

	spin_lock_irqsave(&ochip->lock, flags);
	__set_level(ochip, pin, value);
	spin_unlock_irqrestore(&ochip->lock, flags);
}

static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
{
	struct orion_gpio_chip *ochip =
		container_of(chip, struct orion_gpio_chip, chip);

	return ochip->secondary_irq_base + pin;
}


/*
 * Orion-specific GPIO API extensions.
 */
static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
{
	int i;

	for (i = 0; i < orion_gpio_chip_count; i++) {
		struct orion_gpio_chip *ochip = orion_gpio_chips + i;
		struct gpio_chip *chip = &ochip->chip;

		if (pin >= chip->base && pin < chip->base + chip->ngpio)
			return ochip;
	}

	return NULL;
}

void __init orion_gpio_set_unused(unsigned pin)
{
	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);

	if (ochip == NULL)
		return;

	pin -= ochip->chip.base;

	/* Configure as output, drive low. */
	__set_level(ochip, pin, 0);
	__set_direction(ochip, pin, 0);
}

void __init orion_gpio_set_valid(unsigned pin, int mode)
{
	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);

	if (ochip == NULL)
		return;

	pin -= ochip->chip.base;

	if (mode == 1)
		mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;

	if (mode & GPIO_INPUT_OK)
		__set_bit(pin, &ochip->valid_input);
	else
		__clear_bit(pin, &ochip->valid_input);

	if (mode & GPIO_OUTPUT_OK)
		__set_bit(pin, &ochip->valid_output);
	else
		__clear_bit(pin, &ochip->valid_output);
}

void orion_gpio_set_blink(unsigned pin, int blink)
{
	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
	unsigned long flags;

	if (ochip == NULL)
		return;

	spin_lock_irqsave(&ochip->lock, flags);
	__set_level(ochip, pin & 31, 0);
	__set_blinking(ochip, pin & 31, blink);
	spin_unlock_irqrestore(&ochip->lock, flags);
}
EXPORT_SYMBOL(orion_gpio_set_blink);

#define ORION_BLINK_HALF_PERIOD 100 /* ms */

int orion_gpio_led_blink_set(unsigned gpio, int state,
	unsigned long *delay_on, unsigned long *delay_off)
{

	if (delay_on && delay_off && !*delay_on && !*delay_off)
		*delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;

	switch (state) {
	case GPIO_LED_NO_BLINK_LOW:
	case GPIO_LED_NO_BLINK_HIGH:
		orion_gpio_set_blink(gpio, 0);
		gpio_set_value(gpio, state);
		break;
	case GPIO_LED_BLINK:
		orion_gpio_set_blink(gpio, 1);
	}
	return 0;
}
EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set);


/*****************************************************************************
 * Orion GPIO IRQ
 *
 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
 * value of the line or the opposite value.
 *
 * Level IRQ handlers: DATA_IN is used directly as cause register.
 *                     Interrupt are masked by LEVEL_MASK registers.
 * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
 *                     Interrupt are masked by EDGE_MASK registers.
 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
 *                     the polarity to catch the next line transaction.
 *                     This is a race condition that might not perfectly
 *                     work on some use cases.
 *
 * Every eight GPIO lines are grouped (OR'ed) before going up to main
 * cause register.
 *
 *                    EDGE  cause    mask
 *        data-in   /--------| |-----| |----\
 *     -----| |-----                         ---- to main cause reg
 *           X      \----------------| |----/
 *        polarity    LEVEL          mask
 *
 ****************************************************************************/

static int gpio_irq_set_type(struct irq_data *d, u32 type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	struct orion_gpio_chip *ochip = gc->private;
	int pin;
	u32 u;

	pin = d->irq - gc->irq_base;

	u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
	if (!u) {
		printk(KERN_ERR "orion gpio_irq_set_type failed "
				"(irq %d, pin %d).\n", d->irq, pin);
		return -EINVAL;
	}

	type &= IRQ_TYPE_SENSE_MASK;
	if (type == IRQ_TYPE_NONE)
		return -EINVAL;

	/* Check if we need to change chip and handler */
	if (!(ct->type & type))
		if (irq_setup_alt_chip(d, type))
			return -EINVAL;

	/*
	 * Configure interrupt polarity.
	 */
	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
		u = readl(GPIO_IN_POL(ochip));
		u &= ~(1 << pin);
		writel(u, GPIO_IN_POL(ochip));
	} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
		u = readl(GPIO_IN_POL(ochip));
		u |= 1 << pin;
		writel(u, GPIO_IN_POL(ochip));
	} else if (type == IRQ_TYPE_EDGE_BOTH) {
		u32 v;

		v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));

		/*
		 * set initial polarity based on current input level
		 */
		u = readl(GPIO_IN_POL(ochip));
		if (v & (1 << pin))
			u |= 1 << pin;		/* falling */
		else
			u &= ~(1 << pin);	/* rising */
		writel(u, GPIO_IN_POL(ochip));
	}

	return 0;
}

void __init orion_gpio_init(int gpio_base, int ngpio,
			    u32 base, int mask_offset, int secondary_irq_base)
{
	struct orion_gpio_chip *ochip;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	char gc_label[16];

	if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
		return;

	snprintf(gc_label, sizeof(gc_label), "orion_gpio%d",
		orion_gpio_chip_count);

	ochip = orion_gpio_chips + orion_gpio_chip_count;
	ochip->chip.label = kstrdup(gc_label, GFP_KERNEL);
	ochip->chip.request = orion_gpio_request;
	ochip->chip.direction_input = orion_gpio_direction_input;
	ochip->chip.get = orion_gpio_get;
	ochip->chip.direction_output = orion_gpio_direction_output;
	ochip->chip.set = orion_gpio_set;
	ochip->chip.to_irq = orion_gpio_to_irq;
	ochip->chip.base = gpio_base;
	ochip->chip.ngpio = ngpio;
	ochip->chip.can_sleep = 0;
	spin_lock_init(&ochip->lock);
	ochip->base = (void __iomem *)base;
	ochip->valid_input = 0;
	ochip->valid_output = 0;
	ochip->mask_offset = mask_offset;
	ochip->secondary_irq_base = secondary_irq_base;

	gpiochip_add(&ochip->chip);

	orion_gpio_chip_count++;

	/*
	 * Mask and clear GPIO interrupts.
	 */
	writel(0, GPIO_EDGE_CAUSE(ochip));
	writel(0, GPIO_EDGE_MASK(ochip));
	writel(0, GPIO_LEVEL_MASK(ochip));

	gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
				    ochip->base, handle_level_irq);
	gc->private = ochip;

	ct = gc->chip_types;
	ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	ct->chip.irq_set_type = gpio_irq_set_type;

	ct++;
	ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
	ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	ct->chip.irq_ack = irq_gc_ack_clr_bit;
	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	ct->chip.irq_set_type = gpio_irq_set_type;
	ct->handler = handle_edge_irq;

	irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
			       IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
}

void orion_gpio_irq_handler(int pinoff)
{
	struct orion_gpio_chip *ochip;
	u32 cause, type;
	int i;

	ochip = orion_gpio_chip_find(pinoff);
	if (ochip == NULL)
		return;

	cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
	cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));

	for (i = 0; i < ochip->chip.ngpio; i++) {
		int irq;

		irq = ochip->secondary_irq_base + i;

		if (!(cause & (1 << i)))
			continue;

		type = irqd_get_trigger_type(irq_get_irq_data(irq));
		if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
			/* Swap polarity (race with GPIO line) */
			u32 polarity;

			polarity = readl(GPIO_IN_POL(ochip));
			polarity ^= 1 << i;
			writel(polarity, GPIO_IN_POL(ochip));
		}
		generic_handle_irq(irq);
	}
}
Commit	Line	Data
9569dae7 LB	1	/*
	2	* arch/arm/plat-orion/gpio.c
	3	*
	4	* Marvell Orion SoC GPIO handling.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
07332318	13	#include <linux/irq.h>
9569dae7 LB	14	#include <linux/module.h>
	15	#include <linux/spinlock.h>
	16	#include <linux/bitops.h>
	17	#include <linux/io.h>
a8865655	18	#include <linux/gpio.h>
ff3e660b	19	#include <linux/leds.h>
9569dae7	20
9eac6d0a LB	21	/*
	22	* GPIO unit register offsets.
	23	*/
	24	#define GPIO_OUT_OFF 0x0000
	25	#define GPIO_IO_CONF_OFF 0x0004
	26	#define GPIO_BLINK_EN_OFF 0x0008
	27	#define GPIO_IN_POL_OFF 0x000c
	28	#define GPIO_DATA_IN_OFF 0x0010
	29	#define GPIO_EDGE_CAUSE_OFF 0x0014
	30	#define GPIO_EDGE_MASK_OFF 0x0018
	31	#define GPIO_LEVEL_MASK_OFF 0x001c
	32
	33	struct orion_gpio_chip {
	34	struct gpio_chip chip;
	35	spinlock_t lock;
	36	void __iomem *base;
	37	unsigned long valid_input;
	38	unsigned long valid_output;
	39	int mask_offset;
	40	int secondary_irq_base;
	41	};
	42
	43	static void __iomem GPIO_OUT(struct orion_gpio_chip ochip)
	44	{
	45	return ochip->base + GPIO_OUT_OFF;
	46	}
	47
	48	static void __iomem GPIO_IO_CONF(struct orion_gpio_chip ochip)
	49	{
	50	return ochip->base + GPIO_IO_CONF_OFF;
	51	}
	52
	53	static void __iomem GPIO_BLINK_EN(struct orion_gpio_chip ochip)
	54	{
	55	return ochip->base + GPIO_BLINK_EN_OFF;
	56	}
	57
	58	static void __iomem GPIO_IN_POL(struct orion_gpio_chip ochip)
	59	{
	60	return ochip->base + GPIO_IN_POL_OFF;
	61	}
	62
	63	static void __iomem GPIO_DATA_IN(struct orion_gpio_chip ochip)
	64	{
	65	return ochip->base + GPIO_DATA_IN_OFF;
	66	}
	67
	68	static void __iomem GPIO_EDGE_CAUSE(struct orion_gpio_chip ochip)
	69	{
	70	return ochip->base + GPIO_EDGE_CAUSE_OFF;
	71	}
	72
	73	static void __iomem GPIO_EDGE_MASK(struct orion_gpio_chip ochip)
	74	{
	75	return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
	76	}
	77
	78	static void __iomem GPIO_LEVEL_MASK(struct orion_gpio_chip ochip)
	79	{
	80	return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
	81	}
	82
9569dae7	83
9eac6d0a LB	84	static struct orion_gpio_chip orion_gpio_chips[2];
	85	static int orion_gpio_chip_count;
	86
	87	static inline void
	88	__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
9569dae7 LB	89	{
	90	u32 u;
	91
9eac6d0a	92	u = readl(GPIO_IO_CONF(ochip));
9569dae7	93	if (input)
9eac6d0a	94	u \|= 1 << pin;
9569dae7	95	else
9eac6d0a LB	96	u &= ~(1 << pin);
9eac6d0a LB	97	writel(u, GPIO_IO_CONF(ochip));
9569dae7 LB	98	}
9569dae7 LB	99
9eac6d0a	100	static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
9569dae7 LB	101	{
	102	u32 u;
	103
9eac6d0a	104	u = readl(GPIO_OUT(ochip));
9569dae7	105	if (high)
9eac6d0a	106	u \|= 1 << pin;
9569dae7	107	else
9eac6d0a LB	108	u &= ~(1 << pin);
9eac6d0a LB	109	writel(u, GPIO_OUT(ochip));
9569dae7 LB	110	}
9569dae7 LB	111
9eac6d0a LB	112	static inline void
9eac6d0a LB	113	__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
9569dae7	114	{
a8865655	115	u32 u;
9569dae7	116
9eac6d0a	117	u = readl(GPIO_BLINK_EN(ochip));
a8865655	118	if (blink)
9eac6d0a	119	u \|= 1 << pin;
a8865655	120	else
9eac6d0a LB	121	u &= ~(1 << pin);
9eac6d0a LB	122	writel(u, GPIO_BLINK_EN(ochip));
a8865655	123	}
9569dae7	124
9eac6d0a LB	125	static inline int
9eac6d0a LB	126	orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
a8865655	127	{
9eac6d0a LB	128	if (pin >= ochip->chip.ngpio)
	129	goto err_out;
	130
	131	if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
	132	goto err_out;
	133
	134	if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
	135	goto err_out;
	136
	137	return 1;
9569dae7	138
a8865655 EB	139	err_out:
	140	pr_debug("%s: invalid GPIO %d\n", __func__, pin);
	141	return false;
9569dae7	142	}
9569dae7	143
a8865655 EB	144	/*
	145	* GENERIC_GPIO primitives.
	146	*/
9eac6d0a LB	147	static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
	148	{
	149	struct orion_gpio_chip *ochip =
	150	container_of(chip, struct orion_gpio_chip, chip);
	151
	152	if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) \|\|
	153	orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
	154	return 0;
	155
	156	return -EINVAL;
	157	}
	158
a8865655	159	static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
9569dae7	160	{
9eac6d0a LB	161	struct orion_gpio_chip *ochip =
9eac6d0a LB	162	container_of(chip, struct orion_gpio_chip, chip);
9569dae7	163	unsigned long flags;
9569dae7	164
9eac6d0a	165	if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
9569dae7	166	return -EINVAL;
9569dae7	167
9eac6d0a LB	168	spin_lock_irqsave(&ochip->lock, flags);
	169	__set_direction(ochip, pin, 1);
	170	spin_unlock_irqrestore(&ochip->lock, flags);
9569dae7 LB	171
	172	return 0;
	173	}
9569dae7	174
9eac6d0a	175	static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
9569dae7	176	{
9eac6d0a LB	177	struct orion_gpio_chip *ochip =
9eac6d0a LB	178	container_of(chip, struct orion_gpio_chip, chip);
9569dae7 LB	179	int val;
9569dae7 LB	180
9eac6d0a LB	181	if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
	182	val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
	183	} else {
	184	val = readl(GPIO_OUT(ochip));
	185	}
9569dae7	186
9eac6d0a	187	return (val >> pin) & 1;
9569dae7	188	}
9569dae7	189
9eac6d0a LB	190	static int
9eac6d0a LB	191	orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
9569dae7	192	{
9eac6d0a LB	193	struct orion_gpio_chip *ochip =
9eac6d0a LB	194	container_of(chip, struct orion_gpio_chip, chip);
9569dae7	195	unsigned long flags;
a8865655	196
9eac6d0a	197	if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
a8865655	198	return -EINVAL;
9569dae7	199
9eac6d0a LB	200	spin_lock_irqsave(&ochip->lock, flags);
	201	__set_blinking(ochip, pin, 0);
	202	__set_level(ochip, pin, value);
	203	__set_direction(ochip, pin, 0);
	204	spin_unlock_irqrestore(&ochip->lock, flags);
a8865655 EB	205
a8865655 EB	206	return 0;
9569dae7	207	}
9569dae7	208
9eac6d0a	209	static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
9569dae7	210	{
9eac6d0a LB	211	struct orion_gpio_chip *ochip =
9eac6d0a LB	212	container_of(chip, struct orion_gpio_chip, chip);
9569dae7	213	unsigned long flags;
9569dae7	214
9eac6d0a LB	215	spin_lock_irqsave(&ochip->lock, flags);
	216	__set_level(ochip, pin, value);
	217	spin_unlock_irqrestore(&ochip->lock, flags);
9569dae7	218	}
9569dae7	219
9eac6d0a	220	static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
9569dae7	221	{
9eac6d0a LB	222	struct orion_gpio_chip *ochip =
9eac6d0a LB	223	container_of(chip, struct orion_gpio_chip, chip);
9569dae7	224
9eac6d0a	225	return ochip->secondary_irq_base + pin;
a8865655	226	}
9569dae7	227
9eac6d0a	228
9569dae7 LB	229	/*
	230	* Orion-specific GPIO API extensions.
	231	*/
9eac6d0a LB	232	static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
	233	{
	234	int i;
	235
	236	for (i = 0; i < orion_gpio_chip_count; i++) {
	237	struct orion_gpio_chip *ochip = orion_gpio_chips + i;
	238	struct gpio_chip *chip = &ochip->chip;
	239
	240	if (pin >= chip->base && pin < chip->base + chip->ngpio)
	241	return ochip;
	242	}
	243
	244	return NULL;
	245	}
	246
9569dae7 LB	247	void __init orion_gpio_set_unused(unsigned pin)
9569dae7 LB	248	{
9eac6d0a LB	249	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
	250
	251	if (ochip == NULL)
	252	return;
	253
	254	pin -= ochip->chip.base;
	255
a8865655	256	/* Configure as output, drive low. */
9eac6d0a LB	257	__set_level(ochip, pin, 0);
9eac6d0a LB	258	__set_direction(ochip, pin, 0);
9569dae7 LB	259	}
9569dae7 LB	260
28d27cf4	261	void __init orion_gpio_set_valid(unsigned pin, int mode)
9569dae7	262	{
9eac6d0a LB	263	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
	264
	265	if (ochip == NULL)
	266	return;
	267
	268	pin -= ochip->chip.base;
	269
28d27cf4 NP	270	if (mode == 1)
28d27cf4 NP	271	mode = GPIO_INPUT_OK \| GPIO_OUTPUT_OK;
9eac6d0a	272
28d27cf4	273	if (mode & GPIO_INPUT_OK)
9eac6d0a	274	__set_bit(pin, &ochip->valid_input);
9569dae7	275	else
9eac6d0a LB	276	__clear_bit(pin, &ochip->valid_input);
9eac6d0a LB	277
28d27cf4	278	if (mode & GPIO_OUTPUT_OK)
9eac6d0a	279	__set_bit(pin, &ochip->valid_output);
28d27cf4	280	else
9eac6d0a	281	__clear_bit(pin, &ochip->valid_output);
9569dae7 LB	282	}
	283
	284	void orion_gpio_set_blink(unsigned pin, int blink)
	285	{
9eac6d0a	286	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
9569dae7	287	unsigned long flags;
9569dae7	288
9eac6d0a LB	289	if (ochip == NULL)
9eac6d0a LB	290	return;
9569dae7	291
9eac6d0a	292	spin_lock_irqsave(&ochip->lock, flags);
92a486ea AP	293	__set_level(ochip, pin & 31, 0);
92a486ea AP	294	__set_blinking(ochip, pin & 31, blink);
9eac6d0a	295	spin_unlock_irqrestore(&ochip->lock, flags);
9569dae7 LB	296	}
9569dae7 LB	297	EXPORT_SYMBOL(orion_gpio_set_blink);
07332318	298
ff3e660b AP	299	#define ORION_BLINK_HALF_PERIOD 100 /* ms */
	300
	301	int orion_gpio_led_blink_set(unsigned gpio, int state,
	302	unsigned long delay_on, unsigned long delay_off)
	303	{
	304
	305	if (delay_on && delay_off && !delay_on && !delay_off)
	306	delay_on = delay_off = ORION_BLINK_HALF_PERIOD;
	307
	308	switch (state) {
	309	case GPIO_LED_NO_BLINK_LOW:
	310	case GPIO_LED_NO_BLINK_HIGH:
	311	orion_gpio_set_blink(gpio, 0);
	312	gpio_set_value(gpio, state);
	313	break;
	314	case GPIO_LED_BLINK:
	315	orion_gpio_set_blink(gpio, 1);
	316	}
	317	return 0;
	318	}
	319	EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set);
	320
07332318 LB	321
	322	/*****************************************************************************
	323	* Orion GPIO IRQ
	324	*
	325	* GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
	326	* value of the line or the opposite value.
	327	*
	328	* Level IRQ handlers: DATA_IN is used directly as cause register.
	329	* Interrupt are masked by LEVEL_MASK registers.
	330	* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
	331	* Interrupt are masked by EDGE_MASK registers.
	332	* Both-edge handlers: Similar to regular Edge handlers, but also swaps
	333	* the polarity to catch the next line transaction.
	334	* This is a race condition that might not perfectly
	335	* work on some use cases.
	336	*
	337	* Every eight GPIO lines are grouped (OR'ed) before going up to main
	338	* cause register.
	339	*
	340	* EDGE cause mask
	341	* data-in /--------\| \|-----\| \|----\
	342	* -----\| \|----- ---- to main cause reg
	343	* X \----------------\| \|----/
	344	* polarity LEVEL mask
	345	*
	346	****************************************************************************/
07332318	347
3b0c8d40	348	static int gpio_irq_set_type(struct irq_data *d, u32 type)
07332318	349	{
e59347a1 TG	350	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	351	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	352	struct orion_gpio_chip *ochip = gc->private;
9eac6d0a	353	int pin;
07332318 LB	354	u32 u;
07332318 LB	355
e59347a1	356	pin = d->irq - gc->irq_base;
9eac6d0a LB	357
9eac6d0a LB	358	u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
07332318 LB	359	if (!u) {
07332318 LB	360	printk(KERN_ERR "orion gpio_irq_set_type failed "
3b0c8d40	361	"(irq %d, pin %d).\n", d->irq, pin);
07332318 LB	362	return -EINVAL;
	363	}
	364
e59347a1 TG	365	type &= IRQ_TYPE_SENSE_MASK;
e59347a1 TG	366	if (type == IRQ_TYPE_NONE)
07332318	367	return -EINVAL;
e59347a1 TG	368
	369	/* Check if we need to change chip and handler */
	370	if (!(ct->type & type))
	371	if (irq_setup_alt_chip(d, type))
	372	return -EINVAL;
07332318 LB	373
	374	/*
	375	* Configure interrupt polarity.
	376	*/
	377	if (type == IRQ_TYPE_EDGE_RISING \|\| type == IRQ_TYPE_LEVEL_HIGH) {
9eac6d0a LB	378	u = readl(GPIO_IN_POL(ochip));
	379	u &= ~(1 << pin);
	380	writel(u, GPIO_IN_POL(ochip));
07332318	381	} else if (type == IRQ_TYPE_EDGE_FALLING \|\| type == IRQ_TYPE_LEVEL_LOW) {
9eac6d0a LB	382	u = readl(GPIO_IN_POL(ochip));
	383	u \|= 1 << pin;
	384	writel(u, GPIO_IN_POL(ochip));
07332318 LB	385	} else if (type == IRQ_TYPE_EDGE_BOTH) {
	386	u32 v;
	387
9eac6d0a	388	v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
07332318 LB	389
	390	/*
	391	* set initial polarity based on current input level
	392	*/
9eac6d0a LB	393	u = readl(GPIO_IN_POL(ochip));
	394	if (v & (1 << pin))
	395	u \|= 1 << pin; /* falling */
07332318	396	else
9eac6d0a LB	397	u &= ~(1 << pin); /* rising */
9eac6d0a LB	398	writel(u, GPIO_IN_POL(ochip));
07332318 LB	399	}
07332318 LB	400
07332318 LB	401	return 0;
	402	}
	403
9eac6d0a LB	404	void __init orion_gpio_init(int gpio_base, int ngpio,
	405	u32 base, int mask_offset, int secondary_irq_base)
	406	{
	407	struct orion_gpio_chip *ochip;
e59347a1 TG	408	struct irq_chip_generic *gc;
e59347a1 TG	409	struct irq_chip_type *ct;
0b35a45b	410	char gc_label[16];
9eac6d0a LB	411
	412	if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
	413	return;
	414
0b35a45b HB	415	snprintf(gc_label, sizeof(gc_label), "orion_gpio%d",
	416	orion_gpio_chip_count);
	417
9eac6d0a	418	ochip = orion_gpio_chips + orion_gpio_chip_count;
0b35a45b	419	ochip->chip.label = kstrdup(gc_label, GFP_KERNEL);
9eac6d0a LB	420	ochip->chip.request = orion_gpio_request;
	421	ochip->chip.direction_input = orion_gpio_direction_input;
	422	ochip->chip.get = orion_gpio_get;
	423	ochip->chip.direction_output = orion_gpio_direction_output;
	424	ochip->chip.set = orion_gpio_set;
	425	ochip->chip.to_irq = orion_gpio_to_irq;
	426	ochip->chip.base = gpio_base;
	427	ochip->chip.ngpio = ngpio;
	428	ochip->chip.can_sleep = 0;
	429	spin_lock_init(&ochip->lock);
	430	ochip->base = (void __iomem *)base;
	431	ochip->valid_input = 0;
	432	ochip->valid_output = 0;
	433	ochip->mask_offset = mask_offset;
	434	ochip->secondary_irq_base = secondary_irq_base;
	435
	436	gpiochip_add(&ochip->chip);
	437
	438	orion_gpio_chip_count++;
	439
	440	/*
	441	* Mask and clear GPIO interrupts.
	442	*/
	443	writel(0, GPIO_EDGE_CAUSE(ochip));
	444	writel(0, GPIO_EDGE_MASK(ochip));
	445	writel(0, GPIO_LEVEL_MASK(ochip));
	446
e59347a1 TG	447	gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
	448	ochip->base, handle_level_irq);
	449	gc->private = ochip;
	450
	451	ct = gc->chip_types;
	452	ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
	453	ct->type = IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW;
	454	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	455	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	456	ct->chip.irq_set_type = gpio_irq_set_type;
	457
	458	ct++;
	459	ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
	460	ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
	461	ct->type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
659fb32d	462	ct->chip.irq_ack = irq_gc_ack_clr_bit;
e59347a1 TG	463	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	464	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	465	ct->chip.irq_set_type = gpio_irq_set_type;
	466	ct->handler = handle_edge_irq;
	467
	468	irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
	469	IRQ_NOREQUEST, IRQ_LEVEL \| IRQ_NOPROBE);
9eac6d0a LB	470	}
9eac6d0a LB	471
07332318 LB	472	void orion_gpio_irq_handler(int pinoff)
07332318 LB	473	{
9eac6d0a	474	struct orion_gpio_chip *ochip;
e83bbb11	475	u32 cause, type;
9eac6d0a	476	int i;
07332318	477
9eac6d0a LB	478	ochip = orion_gpio_chip_find(pinoff);
	479	if (ochip == NULL)
	480	return;
07332318	481
9eac6d0a LB	482	cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
9eac6d0a LB	483	cause \|= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
07332318	484
9eac6d0a LB	485	for (i = 0; i < ochip->chip.ngpio; i++) {
9eac6d0a LB	486	int irq;
9eac6d0a LB	487
	488	irq = ochip->secondary_irq_base + i;
	489
	490	if (!(cause & (1 << i)))
07332318 LB	491	continue;
07332318 LB	492
e83bbb11 TG	493	type = irqd_get_trigger_type(irq_get_irq_data(irq));
e83bbb11 TG	494	if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
07332318 LB	495	/* Swap polarity (race with GPIO line) */
	496	u32 polarity;
	497
9eac6d0a LB	498	polarity = readl(GPIO_IN_POL(ochip));
	499	polarity ^= 1 << i;
	500	writel(polarity, GPIO_IN_POL(ochip));
07332318	501	}
e83bbb11	502	generic_handle_irq(irq);
07332318 LB	503	}
07332318 LB	504	}