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1 | /* linux/arch/arm/plat-s3c24xx/clock.c |
2 | * | |
3 | * Copyright (c) 2004-2005 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C24XX Core clock control support | |
7 | * | |
8 | * Based on, and code from linux/arch/arm/mach-versatile/clock.c | |
9 | ** | |
10 | ** Copyright (C) 2004 ARM Limited. | |
11 | ** Written by Deep Blue Solutions Limited. | |
12 | * | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/sysdev.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/clk.h> | |
40 | #include <linux/spinlock.h> | |
41 | #include <linux/delay.h> | |
42 | #include <linux/io.h> | |
43 | ||
44 | #include <mach/hardware.h> | |
45 | #include <asm/irq.h> | |
46 | ||
47 | #include <plat/cpu-freq.h> | |
48 | ||
49 | #include <plat/clock.h> | |
50 | #include <plat/cpu.h> | |
51 | ||
52 | /* clock information */ | |
53 | ||
54 | static LIST_HEAD(clocks); | |
55 | ||
56 | /* We originally used an mutex here, but some contexts (see resume) | |
57 | * are calling functions such as clk_set_parent() with IRQs disabled | |
58 | * causing an BUG to be triggered. | |
59 | */ | |
60 | DEFINE_SPINLOCK(clocks_lock); | |
61 | ||
62 | /* enable and disable calls for use with the clk struct */ | |
63 | ||
64 | static int clk_null_enable(struct clk *clk, int enable) | |
65 | { | |
66 | return 0; | |
67 | } | |
68 | ||
69 | /* Clock API calls */ | |
70 | ||
71 | struct clk *clk_get(struct device *dev, const char *id) | |
72 | { | |
73 | struct clk *p; | |
74 | struct clk *clk = ERR_PTR(-ENOENT); | |
75 | int idno; | |
76 | ||
77 | if (dev == NULL || dev->bus != &platform_bus_type) | |
78 | idno = -1; | |
79 | else | |
80 | idno = to_platform_device(dev)->id; | |
81 | ||
82 | spin_lock(&clocks_lock); | |
83 | ||
84 | list_for_each_entry(p, &clocks, list) { | |
85 | if (p->id == idno && | |
86 | strcmp(id, p->name) == 0 && | |
87 | try_module_get(p->owner)) { | |
88 | clk = p; | |
89 | break; | |
90 | } | |
91 | } | |
92 | ||
93 | /* check for the case where a device was supplied, but the | |
94 | * clock that was being searched for is not device specific */ | |
95 | ||
96 | if (IS_ERR(clk)) { | |
97 | list_for_each_entry(p, &clocks, list) { | |
98 | if (p->id == -1 && strcmp(id, p->name) == 0 && | |
99 | try_module_get(p->owner)) { | |
100 | clk = p; | |
101 | break; | |
102 | } | |
103 | } | |
104 | } | |
105 | ||
106 | spin_unlock(&clocks_lock); | |
107 | return clk; | |
108 | } | |
109 | ||
110 | void clk_put(struct clk *clk) | |
111 | { | |
112 | module_put(clk->owner); | |
113 | } | |
114 | ||
115 | int clk_enable(struct clk *clk) | |
116 | { | |
117 | if (IS_ERR(clk) || clk == NULL) | |
118 | return -EINVAL; | |
119 | ||
120 | clk_enable(clk->parent); | |
121 | ||
122 | spin_lock(&clocks_lock); | |
123 | ||
124 | if ((clk->usage++) == 0) | |
125 | (clk->enable)(clk, 1); | |
126 | ||
127 | spin_unlock(&clocks_lock); | |
128 | return 0; | |
129 | } | |
130 | ||
131 | void clk_disable(struct clk *clk) | |
132 | { | |
133 | if (IS_ERR(clk) || clk == NULL) | |
134 | return; | |
135 | ||
136 | spin_lock(&clocks_lock); | |
137 | ||
138 | if ((--clk->usage) == 0) | |
139 | (clk->enable)(clk, 0); | |
140 | ||
141 | spin_unlock(&clocks_lock); | |
142 | clk_disable(clk->parent); | |
143 | } | |
144 | ||
145 | ||
146 | unsigned long clk_get_rate(struct clk *clk) | |
147 | { | |
148 | if (IS_ERR(clk)) | |
149 | return 0; | |
150 | ||
151 | if (clk->rate != 0) | |
152 | return clk->rate; | |
153 | ||
154 | if (clk->get_rate != NULL) | |
155 | return (clk->get_rate)(clk); | |
156 | ||
157 | if (clk->parent != NULL) | |
158 | return clk_get_rate(clk->parent); | |
159 | ||
160 | return clk->rate; | |
161 | } | |
162 | ||
163 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
164 | { | |
165 | if (!IS_ERR(clk) && clk->round_rate) | |
166 | return (clk->round_rate)(clk, rate); | |
167 | ||
168 | return rate; | |
169 | } | |
170 | ||
171 | int clk_set_rate(struct clk *clk, unsigned long rate) | |
172 | { | |
173 | int ret; | |
174 | ||
175 | if (IS_ERR(clk)) | |
176 | return -EINVAL; | |
177 | ||
178 | /* We do not default just do a clk->rate = rate as | |
179 | * the clock may have been made this way by choice. | |
180 | */ | |
181 | ||
182 | WARN_ON(clk->set_rate == NULL); | |
183 | ||
184 | if (clk->set_rate == NULL) | |
185 | return -EINVAL; | |
186 | ||
187 | spin_lock(&clocks_lock); | |
188 | ret = (clk->set_rate)(clk, rate); | |
189 | spin_unlock(&clocks_lock); | |
190 | ||
191 | return ret; | |
192 | } | |
193 | ||
194 | struct clk *clk_get_parent(struct clk *clk) | |
195 | { | |
196 | return clk->parent; | |
197 | } | |
198 | ||
199 | int clk_set_parent(struct clk *clk, struct clk *parent) | |
200 | { | |
201 | int ret = 0; | |
202 | ||
203 | if (IS_ERR(clk)) | |
204 | return -EINVAL; | |
205 | ||
206 | spin_lock(&clocks_lock); | |
207 | ||
208 | if (clk->set_parent) | |
209 | ret = (clk->set_parent)(clk, parent); | |
210 | ||
211 | spin_unlock(&clocks_lock); | |
212 | ||
213 | return ret; | |
214 | } | |
215 | ||
216 | EXPORT_SYMBOL(clk_get); | |
217 | EXPORT_SYMBOL(clk_put); | |
218 | EXPORT_SYMBOL(clk_enable); | |
219 | EXPORT_SYMBOL(clk_disable); | |
220 | EXPORT_SYMBOL(clk_get_rate); | |
221 | EXPORT_SYMBOL(clk_round_rate); | |
222 | EXPORT_SYMBOL(clk_set_rate); | |
223 | EXPORT_SYMBOL(clk_get_parent); | |
224 | EXPORT_SYMBOL(clk_set_parent); | |
225 | ||
226 | /* base clocks */ | |
227 | ||
228 | static int clk_default_setrate(struct clk *clk, unsigned long rate) | |
229 | { | |
230 | clk->rate = rate; | |
231 | return 0; | |
232 | } | |
233 | ||
234 | struct clk clk_xtal = { | |
235 | .name = "xtal", | |
236 | .id = -1, | |
237 | .rate = 0, | |
238 | .parent = NULL, | |
239 | .ctrlbit = 0, | |
240 | }; | |
241 | ||
242 | struct clk clk_mpll = { | |
243 | .name = "mpll", | |
244 | .id = -1, | |
245 | .set_rate = clk_default_setrate, | |
246 | }; | |
247 | ||
248 | struct clk clk_upll = { | |
249 | .name = "upll", | |
250 | .id = -1, | |
251 | .parent = NULL, | |
252 | .ctrlbit = 0, | |
253 | }; | |
254 | ||
255 | struct clk clk_f = { | |
256 | .name = "fclk", | |
257 | .id = -1, | |
258 | .rate = 0, | |
259 | .parent = &clk_mpll, | |
260 | .ctrlbit = 0, | |
261 | .set_rate = clk_default_setrate, | |
262 | }; | |
263 | ||
264 | struct clk clk_h = { | |
265 | .name = "hclk", | |
266 | .id = -1, | |
267 | .rate = 0, | |
268 | .parent = NULL, | |
269 | .ctrlbit = 0, | |
270 | .set_rate = clk_default_setrate, | |
271 | }; | |
272 | ||
273 | struct clk clk_p = { | |
274 | .name = "pclk", | |
275 | .id = -1, | |
276 | .rate = 0, | |
277 | .parent = NULL, | |
278 | .ctrlbit = 0, | |
279 | .set_rate = clk_default_setrate, | |
280 | }; | |
281 | ||
282 | struct clk clk_usb_bus = { | |
283 | .name = "usb-bus", | |
284 | .id = -1, | |
285 | .rate = 0, | |
286 | .parent = &clk_upll, | |
287 | }; | |
288 | ||
289 | ||
290 | ||
291 | struct clk s3c24xx_uclk = { | |
292 | .name = "uclk", | |
293 | .id = -1, | |
294 | }; | |
295 | ||
296 | /* initialise the clock system */ | |
297 | ||
298 | int s3c24xx_register_clock(struct clk *clk) | |
299 | { | |
300 | clk->owner = THIS_MODULE; | |
301 | ||
302 | if (clk->enable == NULL) | |
303 | clk->enable = clk_null_enable; | |
304 | ||
305 | /* add to the list of available clocks */ | |
306 | ||
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307 | /* Quick check to see if this clock has already been registered. */ |
308 | BUG_ON(clk->list.prev != clk->list.next); | |
309 | ||
adbefaa5 BD |
310 | spin_lock(&clocks_lock); |
311 | list_add(&clk->list, &clocks); | |
312 | spin_unlock(&clocks_lock); | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | int s3c24xx_register_clocks(struct clk **clks, int nr_clks) | |
318 | { | |
319 | int fails = 0; | |
320 | ||
321 | for (; nr_clks > 0; nr_clks--, clks++) { | |
322 | if (s3c24xx_register_clock(*clks) < 0) | |
323 | fails++; | |
324 | } | |
325 | ||
326 | return fails; | |
327 | } | |
328 | ||
329 | /* initalise all the clocks */ | |
330 | ||
331 | int __init s3c24xx_register_baseclocks(unsigned long xtal) | |
332 | { | |
333 | printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); | |
334 | ||
335 | clk_xtal.rate = xtal; | |
336 | ||
337 | /* register our clocks */ | |
338 | ||
339 | if (s3c24xx_register_clock(&clk_xtal) < 0) | |
340 | printk(KERN_ERR "failed to register master xtal\n"); | |
341 | ||
342 | if (s3c24xx_register_clock(&clk_mpll) < 0) | |
343 | printk(KERN_ERR "failed to register mpll clock\n"); | |
344 | ||
345 | if (s3c24xx_register_clock(&clk_upll) < 0) | |
346 | printk(KERN_ERR "failed to register upll clock\n"); | |
347 | ||
348 | if (s3c24xx_register_clock(&clk_f) < 0) | |
349 | printk(KERN_ERR "failed to register cpu fclk\n"); | |
350 | ||
351 | if (s3c24xx_register_clock(&clk_h) < 0) | |
352 | printk(KERN_ERR "failed to register cpu hclk\n"); | |
353 | ||
354 | if (s3c24xx_register_clock(&clk_p) < 0) | |
355 | printk(KERN_ERR "failed to register cpu pclk\n"); | |
356 | ||
357 | return 0; | |
358 | } | |
359 |