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a21765a7
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1/* linux/arch/arm/plat-s3c24xx/dma.c
2 *
3 * Copyright (c) 2003-2005,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 DMA core
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15
16#ifdef CONFIG_S3C2410_DMA_DEBUG
17#define DEBUG
18#endif
19
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/sched.h>
23#include <linux/spinlock.h>
24#include <linux/interrupt.h>
25#include <linux/sysdev.h>
26#include <linux/slab.h>
27#include <linux/errno.h>
28#include <linux/delay.h>
29
30#include <asm/system.h>
31#include <asm/irq.h>
32#include <asm/hardware.h>
33#include <asm/io.h>
34#include <asm/dma.h>
35
36#include <asm/mach/dma.h>
37#include <asm/arch/map.h>
38
39#include <asm/plat-s3c24xx/dma.h>
40
41/* io map for dma */
42static void __iomem *dma_base;
43static struct kmem_cache *dma_kmem;
44
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45static int dma_channels;
46
a7717435 47static struct s3c24xx_dma_selection dma_sel;
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48
49/* dma channel state information */
50struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
51
52/* debugging functions */
53
54#define BUF_MAGIC (0xcafebabe)
55
56#define dmawarn(fmt...) printk(KERN_DEBUG fmt)
57
58#define dma_regaddr(chan, reg) ((chan)->regs + (reg))
59
60#if 1
61#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
62#else
63static inline void
64dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
65{
66 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
67 writel(val, dma_regaddr(chan, reg));
68}
69#endif
70
71#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
72
73/* captured register state for debug */
74
75struct s3c2410_dma_regstate {
76 unsigned long dcsrc;
77 unsigned long disrc;
78 unsigned long dstat;
79 unsigned long dcon;
80 unsigned long dmsktrig;
81};
82
83#ifdef CONFIG_S3C2410_DMA_DEBUG
84
85/* dmadbg_showregs
86 *
87 * simple debug routine to print the current state of the dma registers
88*/
89
90static void
91dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
92{
93 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
94 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
95 regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT);
96 regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON);
97 regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
98}
99
100static void
101dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
102 struct s3c2410_dma_regstate *regs)
103{
104 printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
105 chan->number, fname, line,
106 regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
107 regs->dcon);
108}
109
110static void
111dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
112{
113 struct s3c2410_dma_regstate state;
114
115 dmadbg_capture(chan, &state);
116
117 printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
118 chan->number, fname, line, chan->load_state,
119 chan->curr, chan->next, chan->end);
120
121 dmadbg_dumpregs(fname, line, chan, &state);
122}
123
124static void
125dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
126{
127 struct s3c2410_dma_regstate state;
128
129 dmadbg_capture(chan, &state);
130 dmadbg_dumpregs(fname, line, chan, &state);
131}
132
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133#define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
134#define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
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135#else
136#define dbg_showregs(chan) do { } while(0)
137#define dbg_showchan(chan) do { } while(0)
138#endif /* CONFIG_S3C2410_DMA_DEBUG */
139
140static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
141
142/* lookup_dma_channel
143 *
144 * change the dma channel number given into a real dma channel id
145*/
146
147static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
148{
149 if (channel & DMACH_LOW_LEVEL)
150 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
151 else
152 return dma_chan_map[channel];
153}
154
155/* s3c2410_dma_stats_timeout
156 *
157 * Update DMA stats from timeout info
158*/
159
160static void
161s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
162{
163 if (stats == NULL)
164 return;
165
166 if (val > stats->timeout_longest)
167 stats->timeout_longest = val;
168 if (val < stats->timeout_shortest)
169 stats->timeout_shortest = val;
170
171 stats->timeout_avg += val;
172}
173
174/* s3c2410_dma_waitforload
175 *
176 * wait for the DMA engine to load a buffer, and update the state accordingly
177*/
178
179static int
180s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
181{
182 int timeout = chan->load_timeout;
183 int took;
184
185 if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
186 printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
187 return 0;
188 }
189
190 if (chan->stats != NULL)
191 chan->stats->loads++;
192
193 while (--timeout > 0) {
194 if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
195 took = chan->load_timeout - timeout;
196
197 s3c2410_dma_stats_timeout(chan->stats, took);
198
199 switch (chan->load_state) {
200 case S3C2410_DMALOAD_1LOADED:
201 chan->load_state = S3C2410_DMALOAD_1RUNNING;
202 break;
203
204 default:
205 printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
206 }
207
208 return 1;
209 }
210 }
211
212 if (chan->stats != NULL) {
213 chan->stats->timeout_failed++;
214 }
215
216 return 0;
217}
218
219
220
221/* s3c2410_dma_loadbuffer
222 *
223 * load a buffer, and update the channel state
224*/
225
226static inline int
227s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
228 struct s3c2410_dma_buf *buf)
229{
230 unsigned long reload;
231
232 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
233 buf, (unsigned long)buf->data, buf->size);
234
235 if (buf == NULL) {
236 dmawarn("buffer is NULL\n");
237 return -EINVAL;
238 }
239
240 /* check the state of the channel before we do anything */
241
242 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
243 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
244 }
245
246 if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
247 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
248 }
249
250 /* it would seem sensible if we are the last buffer to not bother
251 * with the auto-reload bit, so that the DMA engine will not try
252 * and load another transfer after this one has finished...
253 */
254 if (chan->load_state == S3C2410_DMALOAD_NONE) {
255 pr_debug("load_state is none, checking for noreload (next=%p)\n",
256 buf->next);
257 reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
258 } else {
259 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
260 reload = S3C2410_DCON_AUTORELOAD;
261 }
262
263 if ((buf->data & 0xf0000000) != 0x30000000) {
264 dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
265 }
266
267 writel(buf->data, chan->addr_reg);
268
269 dma_wrreg(chan, S3C2410_DMA_DCON,
270 chan->dcon | reload | (buf->size/chan->xfer_unit));
271
272 chan->next = buf->next;
273
274 /* update the state of the channel */
275
276 switch (chan->load_state) {
277 case S3C2410_DMALOAD_NONE:
278 chan->load_state = S3C2410_DMALOAD_1LOADED;
279 break;
280
281 case S3C2410_DMALOAD_1RUNNING:
282 chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
283 break;
284
285 default:
286 dmawarn("dmaload: unknown state %d in loadbuffer\n",
287 chan->load_state);
288 break;
289 }
290
291 return 0;
292}
293
294/* s3c2410_dma_call_op
295 *
296 * small routine to call the op routine with the given op if it has been
297 * registered
298*/
299
300static void
301s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
302{
303 if (chan->op_fn != NULL) {
304 (chan->op_fn)(chan, op);
305 }
306}
307
308/* s3c2410_dma_buffdone
309 *
310 * small wrapper to check if callback routine needs to be called, and
311 * if so, call it
312*/
313
314static inline void
315s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
316 enum s3c2410_dma_buffresult result)
317{
318#if 0
319 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
320 chan->callback_fn, buf, buf->id, buf->size, result);
321#endif
322
323 if (chan->callback_fn != NULL) {
324 (chan->callback_fn)(chan, buf->id, buf->size, result);
325 }
326}
327
328/* s3c2410_dma_start
329 *
330 * start a dma channel going
331*/
332
333static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
334{
335 unsigned long tmp;
336 unsigned long flags;
337
338 pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
339
340 local_irq_save(flags);
341
342 if (chan->state == S3C2410_DMA_RUNNING) {
343 pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
344 local_irq_restore(flags);
345 return 0;
346 }
347
348 chan->state = S3C2410_DMA_RUNNING;
349
350 /* check wether there is anything to load, and if not, see
351 * if we can find anything to load
352 */
353
354 if (chan->load_state == S3C2410_DMALOAD_NONE) {
355 if (chan->next == NULL) {
356 printk(KERN_ERR "dma%d: channel has nothing loaded\n",
357 chan->number);
358 chan->state = S3C2410_DMA_IDLE;
359 local_irq_restore(flags);
360 return -EINVAL;
361 }
362
363 s3c2410_dma_loadbuffer(chan, chan->next);
364 }
365
366 dbg_showchan(chan);
367
368 /* enable the channel */
369
370 if (!chan->irq_enabled) {
371 enable_irq(chan->irq);
372 chan->irq_enabled = 1;
373 }
374
375 /* start the channel going */
376
377 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
378 tmp &= ~S3C2410_DMASKTRIG_STOP;
379 tmp |= S3C2410_DMASKTRIG_ON;
380 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
381
382 pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
383
384#if 0
385 /* the dma buffer loads should take care of clearing the AUTO
386 * reloading feature */
387 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
388 tmp &= ~S3C2410_DCON_NORELOAD;
389 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
390#endif
391
392 s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
393
394 dbg_showchan(chan);
395
396 /* if we've only loaded one buffer onto the channel, then chec
397 * to see if we have another, and if so, try and load it so when
398 * the first buffer is finished, the new one will be loaded onto
399 * the channel */
400
401 if (chan->next != NULL) {
402 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
403
404 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
405 pr_debug("%s: buff not yet loaded, no more todo\n",
8e86f427 406 __func__);
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407 } else {
408 chan->load_state = S3C2410_DMALOAD_1RUNNING;
409 s3c2410_dma_loadbuffer(chan, chan->next);
410 }
411
412 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
413 s3c2410_dma_loadbuffer(chan, chan->next);
414 }
415 }
416
417
418 local_irq_restore(flags);
419
420 return 0;
421}
422
423/* s3c2410_dma_canload
424 *
425 * work out if we can queue another buffer into the DMA engine
426*/
427
428static int
429s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
430{
431 if (chan->load_state == S3C2410_DMALOAD_NONE ||
432 chan->load_state == S3C2410_DMALOAD_1RUNNING)
433 return 1;
434
435 return 0;
436}
437
438/* s3c2410_dma_enqueue
439 *
440 * queue an given buffer for dma transfer.
441 *
442 * id the device driver's id information for this buffer
443 * data the physical address of the buffer data
444 * size the size of the buffer in bytes
445 *
446 * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
447 * is checked, and if set, the channel is started. If this flag isn't set,
448 * then an error will be returned.
449 *
450 * It is possible to queue more than one DMA buffer onto a channel at
451 * once, and the code will deal with the re-loading of the next buffer
452 * when necessary.
453*/
454
455int s3c2410_dma_enqueue(unsigned int channel, void *id,
456 dma_addr_t data, int size)
457{
458 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
459 struct s3c2410_dma_buf *buf;
460 unsigned long flags;
461
462 if (chan == NULL)
463 return -EINVAL;
464
465 pr_debug("%s: id=%p, data=%08x, size=%d\n",
8e86f427 466 __func__, id, (unsigned int)data, size);
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BD
467
468 buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
469 if (buf == NULL) {
470 pr_debug("%s: out of memory (%ld alloc)\n",
8e86f427 471 __func__, (long)sizeof(*buf));
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BD
472 return -ENOMEM;
473 }
474
8e86f427 475 //pr_debug("%s: new buffer %p\n", __func__, buf);
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BD
476 //dbg_showchan(chan);
477
478 buf->next = NULL;
479 buf->data = buf->ptr = data;
480 buf->size = size;
481 buf->id = id;
482 buf->magic = BUF_MAGIC;
483
484 local_irq_save(flags);
485
486 if (chan->curr == NULL) {
487 /* we've got nothing loaded... */
488 pr_debug("%s: buffer %p queued onto empty channel\n",
8e86f427 489 __func__, buf);
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490
491 chan->curr = buf;
492 chan->end = buf;
493 chan->next = NULL;
494 } else {
495 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
8e86f427 496 chan->number, __func__, buf);
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497
498 if (chan->end == NULL)
499 pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
8e86f427 500 chan->number, __func__, chan);
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BD
501
502 chan->end->next = buf;
503 chan->end = buf;
504 }
505
506 /* if necessary, update the next buffer field */
507 if (chan->next == NULL)
508 chan->next = buf;
509
510 /* check to see if we can load a buffer */
511 if (chan->state == S3C2410_DMA_RUNNING) {
512 if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
513 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
514 printk(KERN_ERR "dma%d: loadbuffer:"
515 "timeout loading buffer\n",
516 chan->number);
517 dbg_showchan(chan);
518 local_irq_restore(flags);
519 return -EINVAL;
520 }
521 }
522
523 while (s3c2410_dma_canload(chan) && chan->next != NULL) {
524 s3c2410_dma_loadbuffer(chan, chan->next);
525 }
526 } else if (chan->state == S3C2410_DMA_IDLE) {
527 if (chan->flags & S3C2410_DMAF_AUTOSTART) {
046c9d32
BD
528 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
529 S3C2410_DMAOP_START);
a21765a7
BD
530 }
531 }
532
533 local_irq_restore(flags);
534 return 0;
535}
536
537EXPORT_SYMBOL(s3c2410_dma_enqueue);
538
539static inline void
540s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
541{
542 int magicok = (buf->magic == BUF_MAGIC);
543
544 buf->magic = -1;
545
546 if (magicok) {
547 kmem_cache_free(dma_kmem, buf);
548 } else {
549 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
550 }
551}
552
553/* s3c2410_dma_lastxfer
554 *
555 * called when the system is out of buffers, to ensure that the channel
556 * is prepared for shutdown.
557*/
558
559static inline void
560s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
561{
562#if 0
563 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
564 chan->number, chan->load_state);
565#endif
566
567 switch (chan->load_state) {
568 case S3C2410_DMALOAD_NONE:
569 break;
570
571 case S3C2410_DMALOAD_1LOADED:
572 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
573 /* flag error? */
574 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
8e86f427 575 chan->number, __func__);
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BD
576 return;
577 }
578 break;
579
580 case S3C2410_DMALOAD_1LOADED_1RUNNING:
581 /* I belive in this case we do not have anything to do
582 * until the next buffer comes along, and we turn off the
583 * reload */
584 return;
585
586 default:
587 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
588 chan->number, chan->load_state);
589 return;
590
591 }
592
593 /* hopefully this'll shut the damned thing up after the transfer... */
594 dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
595}
596
597
598#define dmadbg2(x...)
599
600static irqreturn_t
601s3c2410_dma_irq(int irq, void *devpw)
602{
603 struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
604 struct s3c2410_dma_buf *buf;
605
606 buf = chan->curr;
607
608 dbg_showchan(chan);
609
610 /* modify the channel state */
611
612 switch (chan->load_state) {
613 case S3C2410_DMALOAD_1RUNNING:
614 /* TODO - if we are running only one buffer, we probably
615 * want to reload here, and then worry about the buffer
616 * callback */
617
618 chan->load_state = S3C2410_DMALOAD_NONE;
619 break;
620
621 case S3C2410_DMALOAD_1LOADED:
622 /* iirc, we should go back to NONE loaded here, we
623 * had a buffer, and it was never verified as being
624 * loaded.
625 */
626
627 chan->load_state = S3C2410_DMALOAD_NONE;
628 break;
629
630 case S3C2410_DMALOAD_1LOADED_1RUNNING:
631 /* we'll worry about checking to see if another buffer is
632 * ready after we've called back the owner. This should
633 * ensure we do not wait around too long for the DMA
634 * engine to start the next transfer
635 */
636
637 chan->load_state = S3C2410_DMALOAD_1LOADED;
638 break;
639
640 case S3C2410_DMALOAD_NONE:
641 printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
642 chan->number);
643 break;
644
645 default:
646 printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
647 chan->number, chan->load_state);
648 break;
649 }
650
651 if (buf != NULL) {
652 /* update the chain to make sure that if we load any more
653 * buffers when we call the callback function, things should
654 * work properly */
655
656 chan->curr = buf->next;
657 buf->next = NULL;
658
659 if (buf->magic != BUF_MAGIC) {
660 printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
8e86f427 661 chan->number, __func__, buf);
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BD
662 return IRQ_HANDLED;
663 }
664
665 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
666
667 /* free resouces */
668 s3c2410_dma_freebuf(buf);
669 } else {
670 }
671
672 /* only reload if the channel is still running... our buffer done
673 * routine may have altered the state by requesting the dma channel
674 * to stop or shutdown... */
675
676 /* todo: check that when the channel is shut-down from inside this
677 * function, we cope with unsetting reload, etc */
678
679 if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
680 unsigned long flags;
681
682 switch (chan->load_state) {
683 case S3C2410_DMALOAD_1RUNNING:
684 /* don't need to do anything for this state */
685 break;
686
687 case S3C2410_DMALOAD_NONE:
688 /* can load buffer immediately */
689 break;
690
691 case S3C2410_DMALOAD_1LOADED:
692 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
693 /* flag error? */
694 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
8e86f427 695 chan->number, __func__);
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BD
696 return IRQ_HANDLED;
697 }
698
699 break;
700
701 case S3C2410_DMALOAD_1LOADED_1RUNNING:
702 goto no_load;
703
704 default:
705 printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
706 chan->number, chan->load_state);
707 return IRQ_HANDLED;
708 }
709
710 local_irq_save(flags);
711 s3c2410_dma_loadbuffer(chan, chan->next);
712 local_irq_restore(flags);
713 } else {
714 s3c2410_dma_lastxfer(chan);
715
716 /* see if we can stop this channel.. */
717 if (chan->load_state == S3C2410_DMALOAD_NONE) {
718 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
719 chan->number, jiffies);
720 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
721 S3C2410_DMAOP_STOP);
722 }
723 }
724
725 no_load:
726 return IRQ_HANDLED;
727}
728
729static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
730
731/* s3c2410_request_dma
732 *
733 * get control of an dma channel
734*/
735
736int s3c2410_dma_request(unsigned int channel,
737 struct s3c2410_dma_client *client,
738 void *dev)
739{
740 struct s3c2410_dma_chan *chan;
741 unsigned long flags;
742 int err;
743
744 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
745 channel, client->name, dev);
746
747 local_irq_save(flags);
748
749 chan = s3c2410_dma_map_channel(channel);
750 if (chan == NULL) {
751 local_irq_restore(flags);
752 return -EBUSY;
753 }
754
755 dbg_showchan(chan);
756
757 chan->client = client;
758 chan->in_use = 1;
759
760 if (!chan->irq_claimed) {
761 pr_debug("dma%d: %s : requesting irq %d\n",
8e86f427 762 channel, __func__, chan->irq);
a21765a7
BD
763
764 chan->irq_claimed = 1;
765 local_irq_restore(flags);
766
767 err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
768 client->name, (void *)chan);
769
770 local_irq_save(flags);
771
772 if (err) {
773 chan->in_use = 0;
774 chan->irq_claimed = 0;
775 local_irq_restore(flags);
776
777 printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
778 client->name, chan->irq, chan->number);
779 return err;
780 }
781
782 chan->irq_enabled = 1;
783 }
784
785 local_irq_restore(flags);
786
787 /* need to setup */
788
8e86f427 789 pr_debug("%s: channel initialised, %p\n", __func__, chan);
a21765a7 790
a07c438f 791 return chan->number | DMACH_LOW_LEVEL;
a21765a7
BD
792}
793
794EXPORT_SYMBOL(s3c2410_dma_request);
795
796/* s3c2410_dma_free
797 *
798 * release the given channel back to the system, will stop and flush
799 * any outstanding transfers, and ensure the channel is ready for the
800 * next claimant.
801 *
802 * Note, although a warning is currently printed if the freeing client
803 * info is not the same as the registrant's client info, the free is still
804 * allowed to go through.
805*/
806
807int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client)
808{
809 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
810 unsigned long flags;
811
812 if (chan == NULL)
813 return -EINVAL;
814
815 local_irq_save(flags);
816
817 if (chan->client != client) {
818 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
819 channel, chan->client, client);
820 }
821
822 /* sort out stopping and freeing the channel */
823
824 if (chan->state != S3C2410_DMA_IDLE) {
825 pr_debug("%s: need to stop dma channel %p\n",
8e86f427 826 __func__, chan);
a21765a7
BD
827
828 /* possibly flush the channel */
829 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
830 }
831
832 chan->client = NULL;
833 chan->in_use = 0;
834
835 if (chan->irq_claimed)
836 free_irq(chan->irq, (void *)chan);
837
838 chan->irq_claimed = 0;
839
840 if (!(channel & DMACH_LOW_LEVEL))
841 dma_chan_map[channel] = NULL;
842
843 local_irq_restore(flags);
844
845 return 0;
846}
847
848EXPORT_SYMBOL(s3c2410_dma_free);
849
850static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
851{
852 unsigned long flags;
853 unsigned long tmp;
854
8e86f427 855 pr_debug("%s:\n", __func__);
a21765a7
BD
856
857 dbg_showchan(chan);
858
859 local_irq_save(flags);
860
861 s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP);
862
863 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
864 tmp |= S3C2410_DMASKTRIG_STOP;
865 //tmp &= ~S3C2410_DMASKTRIG_ON;
866 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
867
868#if 0
869 /* should also clear interrupts, according to WinCE BSP */
870 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
871 tmp |= S3C2410_DCON_NORELOAD;
872 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
873#endif
874
875 /* should stop do this, or should we wait for flush? */
876 chan->state = S3C2410_DMA_IDLE;
877 chan->load_state = S3C2410_DMALOAD_NONE;
878
879 local_irq_restore(flags);
880
881 return 0;
882}
883
a7717435 884static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
a21765a7
BD
885{
886 unsigned long tmp;
887 unsigned int timeout = 0x10000;
888
889 while (timeout-- > 0) {
890 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
891
892 if (!(tmp & S3C2410_DMASKTRIG_ON))
893 return;
894 }
895
896 pr_debug("dma%d: failed to stop?\n", chan->number);
897}
898
899
900/* s3c2410_dma_flush
901 *
902 * stop the channel, and remove all current and pending transfers
903*/
904
905static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
906{
907 struct s3c2410_dma_buf *buf, *next;
908 unsigned long flags;
909
8e86f427 910 pr_debug("%s: chan %p (%d)\n", __func__, chan, chan->number);
a21765a7
BD
911
912 dbg_showchan(chan);
913
914 local_irq_save(flags);
915
916 if (chan->state != S3C2410_DMA_IDLE) {
8e86f427 917 pr_debug("%s: stopping channel...\n", __func__ );
a21765a7
BD
918 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
919 }
920
921 buf = chan->curr;
922 if (buf == NULL)
923 buf = chan->next;
924
925 chan->curr = chan->next = chan->end = NULL;
926
927 if (buf != NULL) {
928 for ( ; buf != NULL; buf = next) {
929 next = buf->next;
930
931 pr_debug("%s: free buffer %p, next %p\n",
8e86f427 932 __func__, buf, buf->next);
a21765a7
BD
933
934 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
935 s3c2410_dma_freebuf(buf);
936 }
937 }
938
939 dbg_showregs(chan);
940
941 s3c2410_dma_waitforstop(chan);
942
943#if 0
944 /* should also clear interrupts, according to WinCE BSP */
945 {
946 unsigned long tmp;
947
948 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
949 tmp |= S3C2410_DCON_NORELOAD;
950 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
951 }
952#endif
953
954 dbg_showregs(chan);
955
956 local_irq_restore(flags);
957
958 return 0;
959}
960
a7717435 961static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
a21765a7
BD
962{
963 unsigned long flags;
964
965 local_irq_save(flags);
966
967 dbg_showchan(chan);
968
969 /* if we've only loaded one buffer onto the channel, then chec
970 * to see if we have another, and if so, try and load it so when
971 * the first buffer is finished, the new one will be loaded onto
972 * the channel */
973
974 if (chan->next != NULL) {
975 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
976
977 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
978 pr_debug("%s: buff not yet loaded, no more todo\n",
8e86f427 979 __func__);
a21765a7
BD
980 } else {
981 chan->load_state = S3C2410_DMALOAD_1RUNNING;
982 s3c2410_dma_loadbuffer(chan, chan->next);
983 }
984
985 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
986 s3c2410_dma_loadbuffer(chan, chan->next);
987 }
988 }
989
990
991 local_irq_restore(flags);
992
993 return 0;
994
995}
996
997int
998s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op)
999{
1000 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1001
1002 if (chan == NULL)
1003 return -EINVAL;
1004
1005 switch (op) {
1006 case S3C2410_DMAOP_START:
1007 return s3c2410_dma_start(chan);
1008
1009 case S3C2410_DMAOP_STOP:
1010 return s3c2410_dma_dostop(chan);
1011
1012 case S3C2410_DMAOP_PAUSE:
1013 case S3C2410_DMAOP_RESUME:
1014 return -ENOENT;
1015
1016 case S3C2410_DMAOP_FLUSH:
1017 return s3c2410_dma_flush(chan);
1018
1019 case S3C2410_DMAOP_STARTED:
1020 return s3c2410_dma_started(chan);
1021
1022 case S3C2410_DMAOP_TIMEOUT:
1023 return 0;
1024
1025 }
1026
1027 return -ENOENT; /* unknown, don't bother */
1028}
1029
1030EXPORT_SYMBOL(s3c2410_dma_ctrl);
1031
1032/* DMA configuration for each channel
1033 *
1034 * DISRCC -> source of the DMA (AHB,APB)
1035 * DISRC -> source address of the DMA
1036 * DIDSTC -> destination of the DMA (AHB,APD)
1037 * DIDST -> destination address of the DMA
1038*/
1039
1040/* s3c2410_dma_config
1041 *
1042 * xfersize: size of unit in bytes (1,2,4)
1043 * dcon: base value of the DCONx register
1044*/
1045
1046int s3c2410_dma_config(dmach_t channel,
1047 int xferunit,
1048 int dcon)
1049{
1050 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1051
1052 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
8e86f427 1053 __func__, channel, xferunit, dcon);
a21765a7
BD
1054
1055 if (chan == NULL)
1056 return -EINVAL;
1057
8e86f427 1058 pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
a21765a7
BD
1059
1060 dcon |= chan->dcon & dma_sel.dcon_mask;
1061
8e86f427 1062 pr_debug("%s: New dcon is %08x\n", __func__, dcon);
a21765a7
BD
1063
1064 switch (xferunit) {
1065 case 1:
1066 dcon |= S3C2410_DCON_BYTE;
1067 break;
1068
1069 case 2:
1070 dcon |= S3C2410_DCON_HALFWORD;
1071 break;
1072
1073 case 4:
1074 dcon |= S3C2410_DCON_WORD;
1075 break;
1076
1077 default:
8e86f427 1078 pr_debug("%s: bad transfer size %d\n", __func__, xferunit);
a21765a7
BD
1079 return -EINVAL;
1080 }
1081
1082 dcon |= S3C2410_DCON_HWTRIG;
1083 dcon |= S3C2410_DCON_INTREQ;
1084
8e86f427 1085 pr_debug("%s: dcon now %08x\n", __func__, dcon);
a21765a7
BD
1086
1087 chan->dcon = dcon;
1088 chan->xfer_unit = xferunit;
1089
1090 return 0;
1091}
1092
1093EXPORT_SYMBOL(s3c2410_dma_config);
1094
1095int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
1096{
1097 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1098
1099 if (chan == NULL)
1100 return -EINVAL;
1101
8e86f427 1102 pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags);
a21765a7
BD
1103
1104 chan->flags = flags;
1105
1106 return 0;
1107}
1108
1109EXPORT_SYMBOL(s3c2410_dma_setflags);
1110
1111
1112/* do we need to protect the settings of the fields from
1113 * irq?
1114*/
1115
1116int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
1117{
1118 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1119
1120 if (chan == NULL)
1121 return -EINVAL;
1122
8e86f427 1123 pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
a21765a7
BD
1124
1125 chan->op_fn = rtn;
1126
1127 return 0;
1128}
1129
1130EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1131
1132int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
1133{
1134 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1135
1136 if (chan == NULL)
1137 return -EINVAL;
1138
8e86f427 1139 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
a21765a7
BD
1140
1141 chan->callback_fn = rtn;
1142
1143 return 0;
1144}
1145
1146EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1147
1148/* s3c2410_dma_devconfig
1149 *
1150 * configure the dma source/destination hardware type and address
1151 *
1152 * source: S3C2410_DMASRC_HW: source is hardware
1153 * S3C2410_DMASRC_MEM: source is memory
1154 *
1155 * hwcfg: the value for xxxSTCn register,
1156 * bit 0: 0=increment pointer, 1=leave pointer
6cbdc8c5 1157 * bit 1: 0=source is AHB, 1=source is APB
a21765a7
BD
1158 *
1159 * devaddr: physical address of the source
1160*/
1161
1162int s3c2410_dma_devconfig(int channel,
1163 enum s3c2410_dmasrc source,
1164 int hwcfg,
1165 unsigned long devaddr)
1166{
1167 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1168
1169 if (chan == NULL)
1170 return -EINVAL;
1171
1172 pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
8e86f427 1173 __func__, (int)source, hwcfg, devaddr);
a21765a7
BD
1174
1175 chan->source = source;
1176 chan->dev_addr = devaddr;
c58f7a1d 1177 chan->hw_cfg = hwcfg;
a21765a7
BD
1178
1179 switch (source) {
1180 case S3C2410_DMASRC_HW:
1181 /* source is hardware */
1182 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
8e86f427 1183 __func__, devaddr, hwcfg);
a21765a7
BD
1184 dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
1185 dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
1186 dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
1187
1188 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
c6709e8e 1189 break;
a21765a7
BD
1190
1191 case S3C2410_DMASRC_MEM:
1192 /* source is memory */
8e86f427
HH
1193 pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1194 __func__, devaddr, hwcfg);
a21765a7
BD
1195 dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
1196 dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
1197 dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
1198
1199 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
c6709e8e
BD
1200 break;
1201
1202 default:
1203 printk(KERN_ERR "dma%d: invalid source type (%d)\n",
1204 channel, source);
1205
1206 return -EINVAL;
a21765a7
BD
1207 }
1208
c6709e8e
BD
1209 if (dma_sel.direction != NULL)
1210 (dma_sel.direction)(chan, chan->map, source);
1211
1212 return 0;
a21765a7
BD
1213}
1214
1215EXPORT_SYMBOL(s3c2410_dma_devconfig);
1216
1217/* s3c2410_dma_getposition
1218 *
1219 * returns the current transfer points for the dma source and destination
1220*/
1221
1222int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
1223{
1224 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1225
1226 if (chan == NULL)
1227 return -EINVAL;
1228
1229 if (src != NULL)
1230 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
1231
1232 if (dst != NULL)
1233 *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
1234
1235 return 0;
1236}
1237
1238EXPORT_SYMBOL(s3c2410_dma_getposition);
1239
c58f7a1d
BD
1240static struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev)
1241{
1242 return container_of(dev, struct s3c2410_dma_chan, dev);
1243}
a21765a7
BD
1244
1245/* system device class */
1246
1247#ifdef CONFIG_PM
1248
1249static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state)
1250{
c58f7a1d 1251 struct s3c2410_dma_chan *cp = to_dma_chan(dev);
a21765a7
BD
1252
1253 printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1254
1255 if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
1256 /* the dma channel is still working, which is probably
1257 * a bad thing to do over suspend/resume. We stop the
1258 * channel and assume that the client is either going to
1259 * retry after resume, or that it is broken.
1260 */
1261
1262 printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
1263 cp->number);
1264
1265 s3c2410_dma_dostop(cp);
1266 }
1267
1268 return 0;
1269}
1270
1271static int s3c2410_dma_resume(struct sys_device *dev)
1272{
c58f7a1d
BD
1273 struct s3c2410_dma_chan *cp = to_dma_chan(dev);
1274 unsigned int no = cp->number | DMACH_LOW_LEVEL;
1275
1276 /* restore channel's hardware configuration */
1277
1278 if (!cp->in_use)
1279 return 0;
1280
1281 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
1282
1283 s3c2410_dma_config(no, cp->xfer_unit, cp->dcon);
1284 s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr);
1285
1286 /* re-select the dma source for this channel */
1287
1288 if (cp->map != NULL)
1289 dma_sel.select(cp, cp->map);
1290
a21765a7
BD
1291 return 0;
1292}
1293
1294#else
1295#define s3c2410_dma_suspend NULL
1296#define s3c2410_dma_resume NULL
1297#endif /* CONFIG_PM */
1298
1299struct sysdev_class dma_sysclass = {
af5ca3f4 1300 .name = "s3c24xx-dma",
a21765a7
BD
1301 .suspend = s3c2410_dma_suspend,
1302 .resume = s3c2410_dma_resume,
1303};
1304
1305/* kmem cache implementation */
1306
51cc5068 1307static void s3c2410_dma_cache_ctor(void *p)
a21765a7
BD
1308{
1309 memset(p, 0, sizeof(struct s3c2410_dma_buf));
1310}
1311
1312/* initialisation code */
1313
a7717435 1314static int __init s3c24xx_dma_sysclass_init(void)
48adbcf3
BD
1315{
1316 int ret = sysdev_class_register(&dma_sysclass);
1317
1318 if (ret != 0)
1319 printk(KERN_ERR "dma sysclass registration failed\n");
1320
1321 return ret;
1322}
1323
1324core_initcall(s3c24xx_dma_sysclass_init);
1325
a7717435 1326static int __init s3c24xx_dma_sysdev_register(void)
48adbcf3
BD
1327{
1328 struct s3c2410_dma_chan *cp = s3c2410_chans;
1329 int channel, ret;
1330
1331 for (channel = 0; channel < dma_channels; cp++, channel++) {
1332 cp->dev.cls = &dma_sysclass;
1333 cp->dev.id = channel;
1334 ret = sysdev_register(&cp->dev);
1335
1336 if (ret) {
1337 printk(KERN_ERR "error registering dev for dma %d\n",
1338 channel);
1339 return ret;
1340 }
1341 }
1342
1343 return 0;
1344}
1345
1346late_initcall(s3c24xx_dma_sysdev_register);
1347
1348int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
1349 unsigned int stride)
a21765a7
BD
1350{
1351 struct s3c2410_dma_chan *cp;
1352 int channel;
1353 int ret;
1354
1355 printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
1356
48adbcf3
BD
1357 dma_channels = channels;
1358
1359 dma_base = ioremap(S3C24XX_PA_DMA, stride * channels);
a21765a7
BD
1360 if (dma_base == NULL) {
1361 printk(KERN_ERR "dma failed to remap register block\n");
1362 return -ENOMEM;
1363 }
1364
48adbcf3
BD
1365 dma_kmem = kmem_cache_create("dma_desc",
1366 sizeof(struct s3c2410_dma_buf), 0,
a21765a7 1367 SLAB_HWCACHE_ALIGN,
20c2df83 1368 s3c2410_dma_cache_ctor);
a21765a7
BD
1369
1370 if (dma_kmem == NULL) {
1371 printk(KERN_ERR "dma failed to make kmem cache\n");
1372 ret = -ENOMEM;
1373 goto err;
1374 }
1375
48adbcf3 1376 for (channel = 0; channel < channels; channel++) {
a21765a7
BD
1377 cp = &s3c2410_chans[channel];
1378
1379 memset(cp, 0, sizeof(struct s3c2410_dma_chan));
1380
1381 /* dma channel irqs are in order.. */
1382 cp->number = channel;
48adbcf3
BD
1383 cp->irq = channel + irq;
1384 cp->regs = dma_base + (channel * stride);
a21765a7
BD
1385
1386 /* point current stats somewhere */
1387 cp->stats = &cp->stats_store;
1388 cp->stats_store.timeout_shortest = LONG_MAX;
1389
1390 /* basic channel configuration */
1391
1392 cp->load_timeout = 1<<18;
1393
a21765a7
BD
1394 printk("DMA channel %d at %p, irq %d\n",
1395 cp->number, cp->regs, cp->irq);
1396 }
1397
1398 return 0;
1399
1400 err:
1401 kmem_cache_destroy(dma_kmem);
1402 iounmap(dma_base);
1403 dma_base = NULL;
1404 return ret;
1405}
1406
f2c10d6c 1407int __init s3c2410_dma_init(void)
48adbcf3
BD
1408{
1409 return s3c24xx_dma_init(4, IRQ_DMA0, 0x40);
1410}
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BD
1411
1412static inline int is_channel_valid(unsigned int channel)
1413{
1414 return (channel & DMA_CH_VALID);
1415}
1416
0c6022d4
BD
1417static struct s3c24xx_dma_order *dma_order;
1418
1419
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BD
1420/* s3c2410_dma_map_channel()
1421 *
1422 * turn the virtual channel number into a real, and un-used hardware
1423 * channel.
1424 *
0c6022d4
BD
1425 * first, try the dma ordering given to us by either the relevant
1426 * dma code, or the board. Then just find the first usable free
1427 * channel
a21765a7
BD
1428*/
1429
a7717435 1430static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
a21765a7 1431{
0c6022d4 1432 struct s3c24xx_dma_order_ch *ord = NULL;
a21765a7
BD
1433 struct s3c24xx_dma_map *ch_map;
1434 struct s3c2410_dma_chan *dmach;
1435 int ch;
1436
1437 if (dma_sel.map == NULL || channel > dma_sel.map_size)
1438 return NULL;
1439
1440 ch_map = dma_sel.map + channel;
1441
0c6022d4
BD
1442 /* first, try the board mapping */
1443
1444 if (dma_order) {
1445 ord = &dma_order->channels[channel];
1446
48adbcf3 1447 for (ch = 0; ch < dma_channels; ch++) {
0c6022d4
BD
1448 if (!is_channel_valid(ord->list[ch]))
1449 continue;
1450
1451 if (s3c2410_chans[ord->list[ch]].in_use == 0) {
1452 ch = ord->list[ch] & ~DMA_CH_VALID;
1453 goto found;
1454 }
1455 }
1456
1457 if (ord->flags & DMA_CH_NEVER)
1458 return NULL;
1459 }
1460
1461 /* second, search the channel map for first free */
1462
48adbcf3 1463 for (ch = 0; ch < dma_channels; ch++) {
a21765a7
BD
1464 if (!is_channel_valid(ch_map->channels[ch]))
1465 continue;
1466
1467 if (s3c2410_chans[ch].in_use == 0) {
1468 printk("mapped channel %d to %d\n", channel, ch);
1469 break;
1470 }
1471 }
1472
48adbcf3 1473 if (ch >= dma_channels)
a21765a7
BD
1474 return NULL;
1475
1476 /* update our channel mapping */
1477
0c6022d4 1478 found:
a21765a7 1479 dmach = &s3c2410_chans[ch];
c58f7a1d 1480 dmach->map = ch_map;
a21765a7
BD
1481 dma_chan_map[channel] = dmach;
1482
1483 /* select the channel */
1484
1485 (dma_sel.select)(dmach, ch_map);
1486
1487 return dmach;
1488}
1489
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BD
1490static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
1491{
a21765a7
BD
1492 return 0;
1493}
1494
1495int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
1496{
1497 struct s3c24xx_dma_map *nmap;
1498 size_t map_sz = sizeof(*nmap) * sel->map_size;
1499 int ptr;
1500
1501 nmap = kmalloc(map_sz, GFP_KERNEL);
1502 if (nmap == NULL)
1503 return -ENOMEM;
1504
1505 memcpy(nmap, sel->map, map_sz);
1506 memcpy(&dma_sel, sel, sizeof(*sel));
1507
1508 dma_sel.map = nmap;
1509
1510 for (ptr = 0; ptr < sel->map_size; ptr++)
1511 s3c24xx_dma_check_entry(nmap+ptr, ptr);
1512
1513 return 0;
1514}
0c6022d4
BD
1515
1516int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord)
1517{
1518 struct s3c24xx_dma_order *nord = dma_order;
1519
1520 if (nord == NULL)
1521 nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
1522
1523 if (nord == NULL) {
1524 printk(KERN_ERR "no memory to store dma channel order\n");
1525 return -ENOMEM;
1526 }
1527
1528 dma_order = nord;
1529 memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
1530 return 0;
1531}