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1 | /* linux/arch/arm/plat-s3c24xx/gpiolib.c |
2 | * | |
3 | * Copyright (c) 2008 Simtec Electronics | |
4 | * http://armlinux.simtec.co.uk/ | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * | |
7 | * S3C24XX GPIOlib support | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/interrupt.h> | |
86c03c52 | 18 | #include <linux/sysdev.h> |
f348a2a2 BD |
19 | #include <linux/ioport.h> |
20 | #include <linux/io.h> | |
21 | #include <linux/gpio.h> | |
22 | ||
ec5cfbfc | 23 | #include <mach/gpio-core.h> |
a09e64fb | 24 | #include <mach/hardware.h> |
f348a2a2 | 25 | #include <asm/irq.h> |
d87964c4 | 26 | #include <plat/pm.h> |
f348a2a2 | 27 | |
a09e64fb | 28 | #include <mach/regs-gpio.h> |
f348a2a2 | 29 | |
f348a2a2 BD |
30 | static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) |
31 | { | |
32 | return -EINVAL; | |
33 | } | |
34 | ||
35 | static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, | |
36 | unsigned offset, int value) | |
37 | { | |
7db6c82a | 38 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); |
f348a2a2 BD |
39 | void __iomem *base = ourchip->base; |
40 | unsigned long flags; | |
41 | unsigned long dat; | |
42 | unsigned long con; | |
43 | ||
44 | local_irq_save(flags); | |
45 | ||
46 | con = __raw_readl(base + 0x00); | |
47 | dat = __raw_readl(base + 0x04); | |
48 | ||
49 | dat &= ~(1 << offset); | |
50 | if (value) | |
51 | dat |= 1 << offset; | |
52 | ||
53 | __raw_writel(dat, base + 0x04); | |
54 | ||
55 | con &= ~(1 << offset); | |
56 | ||
57 | __raw_writel(con, base + 0x00); | |
58 | __raw_writel(dat, base + 0x04); | |
59 | ||
60 | local_irq_restore(flags); | |
61 | return 0; | |
62 | } | |
63 | ||
43ae6599 BD |
64 | static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset) |
65 | { | |
66 | if (offset < 4) | |
67 | return IRQ_EINT0 + offset; | |
68 | ||
69 | if (offset < 8) | |
70 | return IRQ_EINT4 + offset - 4; | |
71 | ||
72 | return -EINVAL; | |
73 | } | |
74 | ||
75 | static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset) | |
76 | { | |
77 | return IRQ_EINT8 + offset; | |
78 | } | |
79 | ||
21b23664 | 80 | struct s3c_gpio_chip s3c24xx_gpios[] = { |
f348a2a2 | 81 | [0] = { |
fda7b2b0 | 82 | .base = S3C2410_GPACON, |
d87964c4 | 83 | .pm = __gpio_pm(&s3c_gpio_pm_1bit), |
f348a2a2 | 84 | .chip = { |
070276d5 | 85 | .base = S3C2410_GPA(0), |
f348a2a2 BD |
86 | .owner = THIS_MODULE, |
87 | .label = "GPIOA", | |
88 | .ngpio = 24, | |
89 | .direction_input = s3c24xx_gpiolib_banka_input, | |
90 | .direction_output = s3c24xx_gpiolib_banka_output, | |
f348a2a2 BD |
91 | }, |
92 | }, | |
93 | [1] = { | |
fda7b2b0 | 94 | .base = S3C2410_GPBCON, |
d87964c4 | 95 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), |
f348a2a2 | 96 | .chip = { |
070276d5 | 97 | .base = S3C2410_GPB(0), |
f348a2a2 BD |
98 | .owner = THIS_MODULE, |
99 | .label = "GPIOB", | |
100 | .ngpio = 16, | |
f348a2a2 BD |
101 | }, |
102 | }, | |
103 | [2] = { | |
fda7b2b0 | 104 | .base = S3C2410_GPCCON, |
d87964c4 | 105 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), |
f348a2a2 | 106 | .chip = { |
070276d5 | 107 | .base = S3C2410_GPC(0), |
f348a2a2 BD |
108 | .owner = THIS_MODULE, |
109 | .label = "GPIOC", | |
110 | .ngpio = 16, | |
f348a2a2 BD |
111 | }, |
112 | }, | |
113 | [3] = { | |
fda7b2b0 | 114 | .base = S3C2410_GPDCON, |
d87964c4 | 115 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), |
f348a2a2 | 116 | .chip = { |
070276d5 | 117 | .base = S3C2410_GPD(0), |
f348a2a2 BD |
118 | .owner = THIS_MODULE, |
119 | .label = "GPIOD", | |
120 | .ngpio = 16, | |
f348a2a2 BD |
121 | }, |
122 | }, | |
123 | [4] = { | |
fda7b2b0 | 124 | .base = S3C2410_GPECON, |
d87964c4 | 125 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), |
f348a2a2 | 126 | .chip = { |
070276d5 | 127 | .base = S3C2410_GPE(0), |
f348a2a2 BD |
128 | .label = "GPIOE", |
129 | .owner = THIS_MODULE, | |
130 | .ngpio = 16, | |
f348a2a2 BD |
131 | }, |
132 | }, | |
133 | [5] = { | |
fda7b2b0 | 134 | .base = S3C2410_GPFCON, |
d87964c4 | 135 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), |
f348a2a2 | 136 | .chip = { |
070276d5 | 137 | .base = S3C2410_GPF(0), |
f348a2a2 BD |
138 | .owner = THIS_MODULE, |
139 | .label = "GPIOF", | |
140 | .ngpio = 8, | |
43ae6599 | 141 | .to_irq = s3c24xx_gpiolib_bankf_toirq, |
f348a2a2 BD |
142 | }, |
143 | }, | |
144 | [6] = { | |
fda7b2b0 | 145 | .base = S3C2410_GPGCON, |
d87964c4 | 146 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), |
f348a2a2 | 147 | .chip = { |
070276d5 | 148 | .base = S3C2410_GPG(0), |
f348a2a2 BD |
149 | .owner = THIS_MODULE, |
150 | .label = "GPIOG", | |
5233c178 | 151 | .ngpio = 16, |
43ae6599 | 152 | .to_irq = s3c24xx_gpiolib_bankg_toirq, |
f348a2a2 | 153 | }, |
5233c178 BD |
154 | }, { |
155 | .base = S3C2410_GPHCON, | |
156 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | |
157 | .chip = { | |
158 | .base = S3C2410_GPH(0), | |
159 | .owner = THIS_MODULE, | |
160 | .label = "GPIOH", | |
161 | .ngpio = 11, | |
162 | }, | |
f348a2a2 BD |
163 | }, |
164 | }; | |
165 | ||
166 | static __init int s3c24xx_gpiolib_init(void) | |
167 | { | |
21b23664 | 168 | struct s3c_gpio_chip *chip = s3c24xx_gpios; |
f348a2a2 BD |
169 | int gpn; |
170 | ||
21b23664 | 171 | for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) |
7db6c82a | 172 | s3c_gpiolib_add(chip); |
f348a2a2 BD |
173 | |
174 | return 0; | |
175 | } | |
176 | ||
9c0ec957 | 177 | core_initcall(s3c24xx_gpiolib_init); |