[mirror_ubuntu-artful-kernel.git] / arch / arm / plat-s3c24xx / irq.c

/* linux/arch/arm/plat-s3c24xx/irq.c
 *
 * Copyright (c) 2003-2004 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/sysdev.h>

#include <asm/irq.h>
#include <asm/mach/irq.h>

#include <plat/regs-irqtype.h>

#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/irq.h>

static void
s3c_irq_mask(struct irq_data *data)
{
	unsigned int irqno = data->irq - IRQ_EINT0;
	unsigned long mask;

	mask = __raw_readl(S3C2410_INTMSK);
	mask |= 1UL << irqno;
	__raw_writel(mask, S3C2410_INTMSK);
}

static inline void
s3c_irq_ack(struct irq_data *data)
{
	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);

	__raw_writel(bitval, S3C2410_SRCPND);
	__raw_writel(bitval, S3C2410_INTPND);
}

static inline void
s3c_irq_maskack(struct irq_data *data)
{
	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
	unsigned long mask;

	mask = __raw_readl(S3C2410_INTMSK);
	__raw_writel(mask|bitval, S3C2410_INTMSK);

	__raw_writel(bitval, S3C2410_SRCPND);
	__raw_writel(bitval, S3C2410_INTPND);
}


static void
s3c_irq_unmask(struct irq_data *data)
{
	unsigned int irqno = data->irq;
	unsigned long mask;

	if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
		irqdbf2("s3c_irq_unmask %d\n", irqno);

	irqno -= IRQ_EINT0;

	mask = __raw_readl(S3C2410_INTMSK);
	mask &= ~(1UL << irqno);
	__raw_writel(mask, S3C2410_INTMSK);
}

struct irq_chip s3c_irq_level_chip = {
	.name		= "s3c-level",
	.irq_ack	= s3c_irq_maskack,
	.irq_mask	= s3c_irq_mask,
	.irq_unmask	= s3c_irq_unmask,
	.irq_set_wake	= s3c_irq_wake
};

struct irq_chip s3c_irq_chip = {
	.name		= "s3c",
	.irq_ack	= s3c_irq_ack,
	.irq_mask	= s3c_irq_mask,
	.irq_unmask	= s3c_irq_unmask,
	.irq_set_wake	= s3c_irq_wake
};

static void
s3c_irqext_mask(struct irq_data *data)
{
	unsigned int irqno = data->irq - EXTINT_OFF;
	unsigned long mask;

	mask = __raw_readl(S3C24XX_EINTMASK);
	mask |= ( 1UL << irqno);
	__raw_writel(mask, S3C24XX_EINTMASK);
}

static void
s3c_irqext_ack(struct irq_data *data)
{
	unsigned long req;
	unsigned long bit;
	unsigned long mask;

	bit = 1UL << (data->irq - EXTINT_OFF);

	mask = __raw_readl(S3C24XX_EINTMASK);

	__raw_writel(bit, S3C24XX_EINTPEND);

	req = __raw_readl(S3C24XX_EINTPEND);
	req &= ~mask;

	/* not sure if we should be acking the parent irq... */

	if (data->irq <= IRQ_EINT7) {
		if ((req & 0xf0) == 0)
			s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7));
	} else {
		if ((req >> 8) == 0)
			s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23));
	}
}

static void
s3c_irqext_unmask(struct irq_data *data)
{
	unsigned int irqno = data->irq - EXTINT_OFF;
	unsigned long mask;

	mask = __raw_readl(S3C24XX_EINTMASK);
	mask &= ~(1UL << irqno);
	__raw_writel(mask, S3C24XX_EINTMASK);
}

int
s3c_irqext_type(struct irq_data *data, unsigned int type)
{
	void __iomem *extint_reg;
	void __iomem *gpcon_reg;
	unsigned long gpcon_offset, extint_offset;
	unsigned long newvalue = 0, value;

	if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) {
		gpcon_reg = S3C2410_GPFCON;
		extint_reg = S3C24XX_EXTINT0;
		gpcon_offset = (data->irq - IRQ_EINT0) * 2;
		extint_offset = (data->irq - IRQ_EINT0) * 4;
	} else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) {
		gpcon_reg = S3C2410_GPFCON;
		extint_reg = S3C24XX_EXTINT0;
		gpcon_offset = (data->irq - (EXTINT_OFF)) * 2;
		extint_offset = (data->irq - (EXTINT_OFF)) * 4;
	} else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) {
		gpcon_reg = S3C2410_GPGCON;
		extint_reg = S3C24XX_EXTINT1;
		gpcon_offset = (data->irq - IRQ_EINT8) * 2;
		extint_offset = (data->irq - IRQ_EINT8) * 4;
	} else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) {
		gpcon_reg = S3C2410_GPGCON;
		extint_reg = S3C24XX_EXTINT2;
		gpcon_offset = (data->irq - IRQ_EINT8) * 2;
		extint_offset = (data->irq - IRQ_EINT16) * 4;
	} else {
		return -1;
	}

	/* Set the GPIO to external interrupt mode */
	value = __raw_readl(gpcon_reg);
	value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
	__raw_writel(value, gpcon_reg);

	/* Set the external interrupt to pointed trigger type */
	switch (type)
	{
		case IRQ_TYPE_NONE:
			printk(KERN_WARNING "No edge setting!\n");
			break;

		case IRQ_TYPE_EDGE_RISING:
			newvalue = S3C2410_EXTINT_RISEEDGE;
			break;

		case IRQ_TYPE_EDGE_FALLING:
			newvalue = S3C2410_EXTINT_FALLEDGE;
			break;

		case IRQ_TYPE_EDGE_BOTH:
			newvalue = S3C2410_EXTINT_BOTHEDGE;
			break;

		case IRQ_TYPE_LEVEL_LOW:
			newvalue = S3C2410_EXTINT_LOWLEV;
			break;

		case IRQ_TYPE_LEVEL_HIGH:
			newvalue = S3C2410_EXTINT_HILEV;
			break;

		default:
			printk(KERN_ERR "No such irq type %d", type);
			return -1;
	}

	value = __raw_readl(extint_reg);
	value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
	__raw_writel(value, extint_reg);

	return 0;
}

static struct irq_chip s3c_irqext_chip = {
	.name		= "s3c-ext",
	.irq_mask	= s3c_irqext_mask,
	.irq_unmask	= s3c_irqext_unmask,
	.irq_ack	= s3c_irqext_ack,
	.irq_set_type	= s3c_irqext_type,
	.irq_set_wake	= s3c_irqext_wake
};

static struct irq_chip s3c_irq_eint0t4 = {
	.name		= "s3c-ext0",
	.irq_ack	= s3c_irq_ack,
	.irq_mask	= s3c_irq_mask,
	.irq_unmask	= s3c_irq_unmask,
	.irq_set_wake	= s3c_irq_wake,
	.irq_set_type	= s3c_irqext_type,
};

/* mask values for the parent registers for each of the interrupt types */

#define INTMSK_UART0	 (1UL << (IRQ_UART0 - IRQ_EINT0))
#define INTMSK_UART1	 (1UL << (IRQ_UART1 - IRQ_EINT0))
#define INTMSK_UART2	 (1UL << (IRQ_UART2 - IRQ_EINT0))
#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))


/* UART0 */

static void
s3c_irq_uart0_mask(struct irq_data *data)
{
	s3c_irqsub_mask(data->irq, INTMSK_UART0, 7);
}

static void
s3c_irq_uart0_unmask(struct irq_data *data)
{
	s3c_irqsub_unmask(data->irq, INTMSK_UART0);
}

static void
s3c_irq_uart0_ack(struct irq_data *data)
{
	s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7);
}

static struct irq_chip s3c_irq_uart0 = {
	.name		= "s3c-uart0",
	.irq_mask	= s3c_irq_uart0_mask,
	.irq_unmask	= s3c_irq_uart0_unmask,
	.irq_ack	= s3c_irq_uart0_ack,
};

/* UART1 */

static void
s3c_irq_uart1_mask(struct irq_data *data)
{
	s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3);
}

static void
s3c_irq_uart1_unmask(struct irq_data *data)
{
	s3c_irqsub_unmask(data->irq, INTMSK_UART1);
}

static void
s3c_irq_uart1_ack(struct irq_data *data)
{
	s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3);
}

static struct irq_chip s3c_irq_uart1 = {
	.name		= "s3c-uart1",
	.irq_mask	= s3c_irq_uart1_mask,
	.irq_unmask	= s3c_irq_uart1_unmask,
	.irq_ack	= s3c_irq_uart1_ack,
};

/* UART2 */

static void
s3c_irq_uart2_mask(struct irq_data *data)
{
	s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6);
}

static void
s3c_irq_uart2_unmask(struct irq_data *data)
{
	s3c_irqsub_unmask(data->irq, INTMSK_UART2);
}

static void
s3c_irq_uart2_ack(struct irq_data *data)
{
	s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6);
}

static struct irq_chip s3c_irq_uart2 = {
	.name		= "s3c-uart2",
	.irq_mask	= s3c_irq_uart2_mask,
	.irq_unmask	= s3c_irq_uart2_unmask,
	.irq_ack	= s3c_irq_uart2_ack,
};

/* ADC and Touchscreen */

static void
s3c_irq_adc_mask(struct irq_data *d)
{
	s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9);
}

static void
s3c_irq_adc_unmask(struct irq_data *d)
{
	s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT);
}

static void
s3c_irq_adc_ack(struct irq_data *d)
{
	s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9);
}

static struct irq_chip s3c_irq_adc = {
	.name		= "s3c-adc",
	.irq_mask	= s3c_irq_adc_mask,
	.irq_unmask	= s3c_irq_adc_unmask,
	.irq_ack	= s3c_irq_adc_ack,
};

/* irq demux for adc */
static void s3c_irq_demux_adc(unsigned int irq,
			      struct irq_desc *desc)
{
	unsigned int subsrc, submsk;
	unsigned int offset = 9;

	/* read the current pending interrupts, and the mask
	 * for what it is available */

	subsrc = __raw_readl(S3C2410_SUBSRCPND);
	submsk = __raw_readl(S3C2410_INTSUBMSK);

	subsrc &= ~submsk;
	subsrc >>= offset;
	subsrc &= 3;

	if (subsrc != 0) {
		if (subsrc & 1) {
			generic_handle_irq(IRQ_TC);
		}
		if (subsrc & 2) {
			generic_handle_irq(IRQ_ADC);
		}
	}
}

static void s3c_irq_demux_uart(unsigned int start)
{
	unsigned int subsrc, submsk;
	unsigned int offset = start - IRQ_S3CUART_RX0;

	/* read the current pending interrupts, and the mask
	 * for what it is available */

	subsrc = __raw_readl(S3C2410_SUBSRCPND);
	submsk = __raw_readl(S3C2410_INTSUBMSK);

	irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
		start, offset, subsrc, submsk);

	subsrc &= ~submsk;
	subsrc >>= offset;
	subsrc &= 7;

	if (subsrc != 0) {
		if (subsrc & 1)
			generic_handle_irq(start);

		if (subsrc & 2)
			generic_handle_irq(start+1);

		if (subsrc & 4)
			generic_handle_irq(start+2);
	}
}

/* uart demux entry points */

static void
s3c_irq_demux_uart0(unsigned int irq,
		    struct irq_desc *desc)
{
	irq = irq;
	s3c_irq_demux_uart(IRQ_S3CUART_RX0);
}

static void
s3c_irq_demux_uart1(unsigned int irq,
		    struct irq_desc *desc)
{
	irq = irq;
	s3c_irq_demux_uart(IRQ_S3CUART_RX1);
}

static void
s3c_irq_demux_uart2(unsigned int irq,
		    struct irq_desc *desc)
{
	irq = irq;
	s3c_irq_demux_uart(IRQ_S3CUART_RX2);
}

static void
s3c_irq_demux_extint8(unsigned int irq,
		      struct irq_desc *desc)
{
	unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
	unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);

	eintpnd &= ~eintmsk;
	eintpnd &= ~0xff;	/* ignore lower irqs */

	/* we may as well handle all the pending IRQs here */

	while (eintpnd) {
		irq = __ffs(eintpnd);
		eintpnd &= ~(1<<irq);

		irq += (IRQ_EINT4 - 4);
		generic_handle_irq(irq);
	}

}

static void
s3c_irq_demux_extint4t7(unsigned int irq,
			struct irq_desc *desc)
{
	unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
	unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);

	eintpnd &= ~eintmsk;
	eintpnd &= 0xff;	/* only lower irqs */

	/* we may as well handle all the pending IRQs here */

	while (eintpnd) {
		irq = __ffs(eintpnd);
		eintpnd &= ~(1<<irq);

		irq += (IRQ_EINT4 - 4);

		generic_handle_irq(irq);
	}
}

#ifdef CONFIG_FIQ
/**
 * s3c24xx_set_fiq - set the FIQ routing
 * @irq: IRQ number to route to FIQ on processor.
 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
 *
 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
 * @on is true, the @irq is checked to see if it can be routed and the
 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
 * routing is cleared, regardless of which @irq is specified.
 */
int s3c24xx_set_fiq(unsigned int irq, bool on)
{
	u32 intmod;
	unsigned offs;

	if (on) {
		offs = irq - FIQ_START;
		if (offs > 31)
			return -EINVAL;

		intmod = 1 << offs;
	} else {
		intmod = 0;
	}

	__raw_writel(intmod, S3C2410_INTMOD);
	return 0;
}

EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
#endif


/* s3c24xx_init_irq
 *
 * Initialise S3C2410 IRQ system
*/

void __init s3c24xx_init_irq(void)
{
	unsigned long pend;
	unsigned long last;
	int irqno;
	int i;

#ifdef CONFIG_FIQ
	init_FIQ();
#endif

	irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");

	/* first, clear all interrupts pending... */

	last = 0;
	for (i = 0; i < 4; i++) {
		pend = __raw_readl(S3C24XX_EINTPEND);

		if (pend == 0 || pend == last)
			break;

		__raw_writel(pend, S3C24XX_EINTPEND);
		printk("irq: clearing pending ext status %08x\n", (int)pend);
		last = pend;
	}

	last = 0;
	for (i = 0; i < 4; i++) {
		pend = __raw_readl(S3C2410_INTPND);

		if (pend == 0 || pend == last)
			break;

		__raw_writel(pend, S3C2410_SRCPND);
		__raw_writel(pend, S3C2410_INTPND);
		printk("irq: clearing pending status %08x\n", (int)pend);
		last = pend;
	}

	last = 0;
	for (i = 0; i < 4; i++) {
		pend = __raw_readl(S3C2410_SUBSRCPND);

		if (pend == 0 || pend == last)
			break;

		printk("irq: clearing subpending status %08x\n", (int)pend);
		__raw_writel(pend, S3C2410_SUBSRCPND);
		last = pend;
	}

	/* register the main interrupts */

	irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");

	for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
		/* set all the s3c2410 internal irqs */

		switch (irqno) {
			/* deal with the special IRQs (cascaded) */

		case IRQ_EINT4t7:
		case IRQ_EINT8t23:
		case IRQ_UART0:
		case IRQ_UART1:
		case IRQ_UART2:
		case IRQ_ADCPARENT:
			irq_set_chip(irqno, &s3c_irq_level_chip);
			irq_set_handler(irqno, handle_level_irq);
			break;

		case IRQ_RESERVED6:
		case IRQ_RESERVED24:
			/* no IRQ here */
			break;

		default:
			//irqdbf("registering irq %d (s3c irq)\n", irqno);
			irq_set_chip(irqno, &s3c_irq_chip);
			irq_set_handler(irqno, handle_edge_irq);
			set_irq_flags(irqno, IRQF_VALID);
		}
	}

	/* setup the cascade irq handlers */

	irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
	irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);

	irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
	irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
	irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
	irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);

	/* external interrupts */

	for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
		irqdbf("registering irq %d (ext int)\n", irqno);
		irq_set_chip(irqno, &s3c_irq_eint0t4);
		irq_set_handler(irqno, handle_edge_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
		irqdbf("registering irq %d (extended s3c irq)\n", irqno);
		irq_set_chip(irqno, &s3c_irqext_chip);
		irq_set_handler(irqno, handle_edge_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	/* register the uart interrupts */

	irqdbf("s3c2410: registering external interrupts\n");

	for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
		irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
		irq_set_chip(irqno, &s3c_irq_uart0);
		irq_set_handler(irqno, handle_level_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
		irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
		irq_set_chip(irqno, &s3c_irq_uart1);
		irq_set_handler(irqno, handle_level_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
		irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
		irq_set_chip(irqno, &s3c_irq_uart2);
		irq_set_handler(irqno, handle_level_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
		irqdbf("registering irq %d (s3c adc irq)\n", irqno);
		irq_set_chip(irqno, &s3c_irq_adc);
		irq_set_handler(irqno, handle_edge_irq);
		set_irq_flags(irqno, IRQF_VALID);
	}

	irqdbf("s3c2410: registered interrupt handlers\n");
}
Commit	Line	Data
a21765a7 BD	1	/* linux/arch/arm/plat-s3c24xx/irq.c
a21765a7 BD	2	*
e02f8664	3	* Copyright (c) 2003-2004 Simtec Electronics
a21765a7 BD	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
a21765a7 BD	19	*/
	20
	21	#include <linux/init.h>
	22	#include <linux/module.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
a21765a7 BD	25	#include <linux/sysdev.h>
a21765a7 BD	26
a21765a7	27	#include <asm/irq.h>
a21765a7 BD	28	#include <asm/mach/irq.h>
a21765a7 BD	29
6af0e929	30	#include <plat/regs-irqtype.h>
a21765a7	31
a2b7ba9c BD	32	#include <plat/cpu.h>
	33	#include <plat/pm.h>
	34	#include <plat/irq.h>
a21765a7	35
a21765a7	36	static void
57436c2d	37	s3c_irq_mask(struct irq_data *data)
a21765a7	38	{
57436c2d	39	unsigned int irqno = data->irq - IRQ_EINT0;
a21765a7 BD	40	unsigned long mask;
a21765a7 BD	41
a21765a7 BD	42	mask = __raw_readl(S3C2410_INTMSK);
	43	mask \|= 1UL << irqno;
	44	__raw_writel(mask, S3C2410_INTMSK);
	45	}
	46
	47	static inline void
57436c2d	48	s3c_irq_ack(struct irq_data *data)
a21765a7	49	{
57436c2d	50	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
a21765a7 BD	51
	52	__raw_writel(bitval, S3C2410_SRCPND);
	53	__raw_writel(bitval, S3C2410_INTPND);
	54	}
	55
	56	static inline void
57436c2d	57	s3c_irq_maskack(struct irq_data *data)
a21765a7	58	{
57436c2d	59	unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
a21765a7 BD	60	unsigned long mask;
	61
	62	mask = __raw_readl(S3C2410_INTMSK);
	63	__raw_writel(mask\|bitval, S3C2410_INTMSK);
	64
	65	__raw_writel(bitval, S3C2410_SRCPND);
	66	__raw_writel(bitval, S3C2410_INTPND);
	67	}
	68
	69
	70	static void
57436c2d	71	s3c_irq_unmask(struct irq_data *data)
a21765a7	72	{
57436c2d	73	unsigned int irqno = data->irq;
a21765a7 BD	74	unsigned long mask;
	75
	76	if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
	77	irqdbf2("s3c_irq_unmask %d\n", irqno);
	78
	79	irqno -= IRQ_EINT0;
	80
	81	mask = __raw_readl(S3C2410_INTMSK);
	82	mask &= ~(1UL << irqno);
	83	__raw_writel(mask, S3C2410_INTMSK);
	84	}
	85
	86	struct irq_chip s3c_irq_level_chip = {
	87	.name = "s3c-level",
57436c2d LB	88	.irq_ack = s3c_irq_maskack,
	89	.irq_mask = s3c_irq_mask,
	90	.irq_unmask = s3c_irq_unmask,
	91	.irq_set_wake = s3c_irq_wake
a21765a7 BD	92	};
a21765a7 BD	93
0baada27	94	struct irq_chip s3c_irq_chip = {
a21765a7	95	.name = "s3c",
57436c2d LB	96	.irq_ack = s3c_irq_ack,
	97	.irq_mask = s3c_irq_mask,
	98	.irq_unmask = s3c_irq_unmask,
	99	.irq_set_wake = s3c_irq_wake
a21765a7 BD	100	};
	101
	102	static void
57436c2d	103	s3c_irqext_mask(struct irq_data *data)
a21765a7	104	{
57436c2d	105	unsigned int irqno = data->irq - EXTINT_OFF;
a21765a7 BD	106	unsigned long mask;
a21765a7 BD	107
a21765a7 BD	108	mask = __raw_readl(S3C24XX_EINTMASK);
	109	mask \|= ( 1UL << irqno);
	110	__raw_writel(mask, S3C24XX_EINTMASK);
	111	}
	112
	113	static void
57436c2d	114	s3c_irqext_ack(struct irq_data *data)
a21765a7 BD	115	{
	116	unsigned long req;
	117	unsigned long bit;
	118	unsigned long mask;
	119
57436c2d	120	bit = 1UL << (data->irq - EXTINT_OFF);
a21765a7 BD	121
	122	mask = __raw_readl(S3C24XX_EINTMASK);
	123
	124	__raw_writel(bit, S3C24XX_EINTPEND);
	125
	126	req = __raw_readl(S3C24XX_EINTPEND);
	127	req &= ~mask;
	128
	129	/* not sure if we should be acking the parent irq... */
	130
57436c2d	131	if (data->irq <= IRQ_EINT7) {
a21765a7	132	if ((req & 0xf0) == 0)
57436c2d	133	s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7));
a21765a7 BD	134	} else {
a21765a7 BD	135	if ((req >> 8) == 0)
57436c2d	136	s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23));
a21765a7 BD	137	}
	138	}
	139
	140	static void
57436c2d	141	s3c_irqext_unmask(struct irq_data *data)
a21765a7	142	{
57436c2d	143	unsigned int irqno = data->irq - EXTINT_OFF;
a21765a7 BD	144	unsigned long mask;
a21765a7 BD	145
a21765a7	146	mask = __raw_readl(S3C24XX_EINTMASK);
57436c2d	147	mask &= ~(1UL << irqno);
a21765a7 BD	148	__raw_writel(mask, S3C24XX_EINTMASK);
	149	}
	150
	151	int
57436c2d	152	s3c_irqext_type(struct irq_data *data, unsigned int type)
a21765a7 BD	153	{
	154	void __iomem *extint_reg;
	155	void __iomem *gpcon_reg;
	156	unsigned long gpcon_offset, extint_offset;
	157	unsigned long newvalue = 0, value;
	158
57436c2d	159	if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) {
a21765a7 BD	160	gpcon_reg = S3C2410_GPFCON;
a21765a7 BD	161	extint_reg = S3C24XX_EXTINT0;
57436c2d LB	162	gpcon_offset = (data->irq - IRQ_EINT0) * 2;
	163	extint_offset = (data->irq - IRQ_EINT0) * 4;
	164	} else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) {
a21765a7 BD	165	gpcon_reg = S3C2410_GPFCON;
a21765a7 BD	166	extint_reg = S3C24XX_EXTINT0;
57436c2d LB	167	gpcon_offset = (data->irq - (EXTINT_OFF)) * 2;
	168	extint_offset = (data->irq - (EXTINT_OFF)) * 4;
	169	} else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) {
a21765a7 BD	170	gpcon_reg = S3C2410_GPGCON;
a21765a7 BD	171	extint_reg = S3C24XX_EXTINT1;
57436c2d LB	172	gpcon_offset = (data->irq - IRQ_EINT8) * 2;
	173	extint_offset = (data->irq - IRQ_EINT8) * 4;
	174	} else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) {
a21765a7 BD	175	gpcon_reg = S3C2410_GPGCON;
a21765a7 BD	176	extint_reg = S3C24XX_EXTINT2;
57436c2d LB	177	gpcon_offset = (data->irq - IRQ_EINT8) * 2;
	178	extint_offset = (data->irq - IRQ_EINT16) * 4;
	179	} else {
a21765a7	180	return -1;
57436c2d	181	}
a21765a7 BD	182
	183	/* Set the GPIO to external interrupt mode */
	184	value = __raw_readl(gpcon_reg);
	185	value = (value & ~(3 << gpcon_offset)) \| (0x02 << gpcon_offset);
	186	__raw_writel(value, gpcon_reg);
	187
	188	/* Set the external interrupt to pointed trigger type */
	189	switch (type)
	190	{
6cab4860	191	case IRQ_TYPE_NONE:
a21765a7 BD	192	printk(KERN_WARNING "No edge setting!\n");
	193	break;
	194
6cab4860	195	case IRQ_TYPE_EDGE_RISING:
a21765a7 BD	196	newvalue = S3C2410_EXTINT_RISEEDGE;
	197	break;
	198
6cab4860	199	case IRQ_TYPE_EDGE_FALLING:
a21765a7 BD	200	newvalue = S3C2410_EXTINT_FALLEDGE;
	201	break;
	202
6cab4860	203	case IRQ_TYPE_EDGE_BOTH:
a21765a7 BD	204	newvalue = S3C2410_EXTINT_BOTHEDGE;
	205	break;
	206
6cab4860	207	case IRQ_TYPE_LEVEL_LOW:
a21765a7 BD	208	newvalue = S3C2410_EXTINT_LOWLEV;
	209	break;
	210
6cab4860	211	case IRQ_TYPE_LEVEL_HIGH:
a21765a7 BD	212	newvalue = S3C2410_EXTINT_HILEV;
	213	break;
	214
	215	default:
	216	printk(KERN_ERR "No such irq type %d", type);
	217	return -1;
	218	}
	219
	220	value = __raw_readl(extint_reg);
	221	value = (value & ~(7 << extint_offset)) \| (newvalue << extint_offset);
	222	__raw_writel(value, extint_reg);
	223
	224	return 0;
	225	}
	226
	227	static struct irq_chip s3c_irqext_chip = {
	228	.name = "s3c-ext",
57436c2d LB	229	.irq_mask = s3c_irqext_mask,
	230	.irq_unmask = s3c_irqext_unmask,
	231	.irq_ack = s3c_irqext_ack,
	232	.irq_set_type = s3c_irqext_type,
f5aeffb7	233	.irq_set_wake = s3c_irqext_wake
a21765a7 BD	234	};
	235
	236	static struct irq_chip s3c_irq_eint0t4 = {
	237	.name = "s3c-ext0",
57436c2d LB	238	.irq_ack = s3c_irq_ack,
	239	.irq_mask = s3c_irq_mask,
	240	.irq_unmask = s3c_irq_unmask,
	241	.irq_set_wake = s3c_irq_wake,
	242	.irq_set_type = s3c_irqext_type,
a21765a7 BD	243	};
	244
	245	/* mask values for the parent registers for each of the interrupt types */
	246
	247	#define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
	248	#define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
	249	#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
	250	#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
	251
	252
	253	/* UART0 */
	254
	255	static void
57436c2d	256	s3c_irq_uart0_mask(struct irq_data *data)
a21765a7	257	{
57436c2d	258	s3c_irqsub_mask(data->irq, INTMSK_UART0, 7);
a21765a7 BD	259	}
	260
	261	static void
57436c2d	262	s3c_irq_uart0_unmask(struct irq_data *data)
a21765a7	263	{
57436c2d	264	s3c_irqsub_unmask(data->irq, INTMSK_UART0);
a21765a7 BD	265	}
	266
	267	static void
57436c2d	268	s3c_irq_uart0_ack(struct irq_data *data)
a21765a7	269	{
57436c2d	270	s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7);
a21765a7 BD	271	}
	272
	273	static struct irq_chip s3c_irq_uart0 = {
	274	.name = "s3c-uart0",
57436c2d LB	275	.irq_mask = s3c_irq_uart0_mask,
	276	.irq_unmask = s3c_irq_uart0_unmask,
	277	.irq_ack = s3c_irq_uart0_ack,
a21765a7 BD	278	};
	279
	280	/* UART1 */
	281
	282	static void
57436c2d	283	s3c_irq_uart1_mask(struct irq_data *data)
a21765a7	284	{
57436c2d	285	s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3);
a21765a7 BD	286	}
	287
	288	static void
57436c2d	289	s3c_irq_uart1_unmask(struct irq_data *data)
a21765a7	290	{
57436c2d	291	s3c_irqsub_unmask(data->irq, INTMSK_UART1);
a21765a7 BD	292	}
	293
	294	static void
57436c2d	295	s3c_irq_uart1_ack(struct irq_data *data)
a21765a7	296	{
57436c2d	297	s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3);
a21765a7 BD	298	}
	299
	300	static struct irq_chip s3c_irq_uart1 = {
	301	.name = "s3c-uart1",
57436c2d LB	302	.irq_mask = s3c_irq_uart1_mask,
	303	.irq_unmask = s3c_irq_uart1_unmask,
	304	.irq_ack = s3c_irq_uart1_ack,
a21765a7 BD	305	};
	306
	307	/* UART2 */
	308
	309	static void
57436c2d	310	s3c_irq_uart2_mask(struct irq_data *data)
a21765a7	311	{
57436c2d	312	s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6);
a21765a7 BD	313	}
	314
	315	static void
57436c2d	316	s3c_irq_uart2_unmask(struct irq_data *data)
a21765a7	317	{
57436c2d	318	s3c_irqsub_unmask(data->irq, INTMSK_UART2);
a21765a7 BD	319	}
	320
	321	static void
57436c2d	322	s3c_irq_uart2_ack(struct irq_data *data)
a21765a7	323	{
57436c2d	324	s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6);
a21765a7 BD	325	}
	326
	327	static struct irq_chip s3c_irq_uart2 = {
	328	.name = "s3c-uart2",
57436c2d LB	329	.irq_mask = s3c_irq_uart2_mask,
	330	.irq_unmask = s3c_irq_uart2_unmask,
	331	.irq_ack = s3c_irq_uart2_ack,
a21765a7 BD	332	};
	333
	334	/* ADC and Touchscreen */
	335
	336	static void
57436c2d	337	s3c_irq_adc_mask(struct irq_data *d)
a21765a7	338	{
57436c2d	339	s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9);
a21765a7 BD	340	}
	341
	342	static void
57436c2d	343	s3c_irq_adc_unmask(struct irq_data *d)
a21765a7	344	{
57436c2d	345	s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT);
a21765a7 BD	346	}
	347
	348	static void
57436c2d	349	s3c_irq_adc_ack(struct irq_data *d)
a21765a7	350	{
57436c2d	351	s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9);
a21765a7 BD	352	}
	353
	354	static struct irq_chip s3c_irq_adc = {
	355	.name = "s3c-adc",
57436c2d LB	356	.irq_mask = s3c_irq_adc_mask,
	357	.irq_unmask = s3c_irq_adc_unmask,
	358	.irq_ack = s3c_irq_adc_ack,
a21765a7 BD	359	};
	360
	361	/* irq demux for adc */
	362	static void s3c_irq_demux_adc(unsigned int irq,
	363	struct irq_desc *desc)
	364	{
	365	unsigned int subsrc, submsk;
	366	unsigned int offset = 9;
a21765a7 BD	367
	368	/* read the current pending interrupts, and the mask
	369	* for what it is available */
	370
	371	subsrc = __raw_readl(S3C2410_SUBSRCPND);
	372	submsk = __raw_readl(S3C2410_INTSUBMSK);
	373
	374	subsrc &= ~submsk;
	375	subsrc >>= offset;
	376	subsrc &= 3;
	377
	378	if (subsrc != 0) {
	379	if (subsrc & 1) {
d8aa0251	380	generic_handle_irq(IRQ_TC);
a21765a7 BD	381	}
a21765a7 BD	382	if (subsrc & 2) {
d8aa0251	383	generic_handle_irq(IRQ_ADC);
a21765a7 BD	384	}
	385	}
	386	}
	387
	388	static void s3c_irq_demux_uart(unsigned int start)
	389	{
	390	unsigned int subsrc, submsk;
	391	unsigned int offset = start - IRQ_S3CUART_RX0;
a21765a7 BD	392
	393	/* read the current pending interrupts, and the mask
	394	* for what it is available */
	395
	396	subsrc = __raw_readl(S3C2410_SUBSRCPND);
	397	submsk = __raw_readl(S3C2410_INTSUBMSK);
	398
	399	irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
	400	start, offset, subsrc, submsk);
	401
	402	subsrc &= ~submsk;
	403	subsrc >>= offset;
	404	subsrc &= 7;
	405
	406	if (subsrc != 0) {
a21765a7	407	if (subsrc & 1)
d8aa0251	408	generic_handle_irq(start);
a21765a7 BD	409
a21765a7 BD	410	if (subsrc & 2)
d8aa0251	411	generic_handle_irq(start+1);
a21765a7 BD	412
a21765a7 BD	413	if (subsrc & 4)
d8aa0251	414	generic_handle_irq(start+2);
a21765a7 BD	415	}
	416	}
	417
	418	/* uart demux entry points */
	419
	420	static void
	421	s3c_irq_demux_uart0(unsigned int irq,
	422	struct irq_desc *desc)
	423	{
	424	irq = irq;
	425	s3c_irq_demux_uart(IRQ_S3CUART_RX0);
	426	}
	427
	428	static void
	429	s3c_irq_demux_uart1(unsigned int irq,
	430	struct irq_desc *desc)
	431	{
	432	irq = irq;
	433	s3c_irq_demux_uart(IRQ_S3CUART_RX1);
	434	}
	435
	436	static void
	437	s3c_irq_demux_uart2(unsigned int irq,
	438	struct irq_desc *desc)
	439	{
	440	irq = irq;
	441	s3c_irq_demux_uart(IRQ_S3CUART_RX2);
	442	}
	443
	444	static void
	445	s3c_irq_demux_extint8(unsigned int irq,
	446	struct irq_desc *desc)
	447	{
	448	unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
	449	unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
	450
	451	eintpnd &= ~eintmsk;
	452	eintpnd &= ~0xff; /* ignore lower irqs */
	453
	454	/* we may as well handle all the pending IRQs here */
	455
	456	while (eintpnd) {
	457	irq = __ffs(eintpnd);
	458	eintpnd &= ~(1<<irq);
	459
	460	irq += (IRQ_EINT4 - 4);
d8aa0251	461	generic_handle_irq(irq);
a21765a7 BD	462	}
	463
	464	}
	465
	466	static void
	467	s3c_irq_demux_extint4t7(unsigned int irq,
	468	struct irq_desc *desc)
	469	{
	470	unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
	471	unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
	472
	473	eintpnd &= ~eintmsk;
	474	eintpnd &= 0xff; /* only lower irqs */
	475
	476	/* we may as well handle all the pending IRQs here */
	477
	478	while (eintpnd) {
	479	irq = __ffs(eintpnd);
	480	eintpnd &= ~(1<<irq);
	481
	482	irq += (IRQ_EINT4 - 4);
	483
d8aa0251	484	generic_handle_irq(irq);
a21765a7 BD	485	}
	486	}
	487
229fd8ff BD	488	#ifdef CONFIG_FIQ
	489	/**
	490	* s3c24xx_set_fiq - set the FIQ routing
	491	* @irq: IRQ number to route to FIQ on processor.
	492	* @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
	493	*
	494	* Change the state of the IRQ to FIQ routing depending on @irq and @on. If
	495	* @on is true, the @irq is checked to see if it can be routed and the
	496	* interrupt controller updated to route the IRQ. If @on is false, the FIQ
	497	* routing is cleared, regardless of which @irq is specified.
	498	*/
	499	int s3c24xx_set_fiq(unsigned int irq, bool on)
	500	{
	501	u32 intmod;
	502	unsigned offs;
	503
	504	if (on) {
	505	offs = irq - FIQ_START;
	506	if (offs > 31)
	507	return -EINVAL;
	508
	509	intmod = 1 << offs;
	510	} else {
	511	intmod = 0;
	512	}
	513
	514	__raw_writel(intmod, S3C2410_INTMOD);
	515	return 0;
	516	}
0f13c824 BD	517
0f13c824 BD	518	EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
229fd8ff BD	519	#endif
	520
	521
a21765a7 BD	522	/* s3c24xx_init_irq
	523	*
	524	* Initialise S3C2410 IRQ system
	525	*/
	526
	527	void __init s3c24xx_init_irq(void)
	528	{
	529	unsigned long pend;
	530	unsigned long last;
	531	int irqno;
	532	int i;
	533
229fd8ff BD	534	#ifdef CONFIG_FIQ
	535	init_FIQ();
	536	#endif
	537
a21765a7 BD	538	irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
	539
	540	/* first, clear all interrupts pending... */
	541
	542	last = 0;
	543	for (i = 0; i < 4; i++) {
	544	pend = __raw_readl(S3C24XX_EINTPEND);
	545
	546	if (pend == 0 \|\| pend == last)
	547	break;
	548
	549	__raw_writel(pend, S3C24XX_EINTPEND);
	550	printk("irq: clearing pending ext status %08x\n", (int)pend);
	551	last = pend;
	552	}
	553
	554	last = 0;
	555	for (i = 0; i < 4; i++) {
	556	pend = __raw_readl(S3C2410_INTPND);
	557
	558	if (pend == 0 \|\| pend == last)
	559	break;
	560
	561	__raw_writel(pend, S3C2410_SRCPND);
	562	__raw_writel(pend, S3C2410_INTPND);
	563	printk("irq: clearing pending status %08x\n", (int)pend);
	564	last = pend;
	565	}
	566
	567	last = 0;
	568	for (i = 0; i < 4; i++) {
	569	pend = __raw_readl(S3C2410_SUBSRCPND);
	570
	571	if (pend == 0 \|\| pend == last)
	572	break;
	573
	574	printk("irq: clearing subpending status %08x\n", (int)pend);
	575	__raw_writel(pend, S3C2410_SUBSRCPND);
	576	last = pend;
	577	}
	578
	579	/* register the main interrupts */
	580
	581	irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
	582
	583	for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
	584	/* set all the s3c2410 internal irqs */
	585
	586	switch (irqno) {
	587	/* deal with the special IRQs (cascaded) */
	588
	589	case IRQ_EINT4t7:
	590	case IRQ_EINT8t23:
	591	case IRQ_UART0:
	592	case IRQ_UART1:
	593	case IRQ_UART2:
	594	case IRQ_ADCPARENT:
6845664a TG	595	irq_set_chip(irqno, &s3c_irq_level_chip);
6845664a TG	596	irq_set_handler(irqno, handle_level_irq);
a21765a7 BD	597	break;
	598
	599	case IRQ_RESERVED6:
	600	case IRQ_RESERVED24:
	601	/* no IRQ here */
	602	break;
	603
	604	default:
	605	//irqdbf("registering irq %d (s3c irq)\n", irqno);
6845664a TG	606	irq_set_chip(irqno, &s3c_irq_chip);
6845664a TG	607	irq_set_handler(irqno, handle_edge_irq);
a21765a7 BD	608	set_irq_flags(irqno, IRQF_VALID);
	609	}
	610	}
	611
	612	/* setup the cascade irq handlers */
	613
6845664a TG	614	irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
6845664a TG	615	irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
a21765a7	616
6845664a TG	617	irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
	618	irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
	619	irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
	620	irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
a21765a7 BD	621
	622	/* external interrupts */
	623
	624	for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
	625	irqdbf("registering irq %d (ext int)\n", irqno);
6845664a TG	626	irq_set_chip(irqno, &s3c_irq_eint0t4);
6845664a TG	627	irq_set_handler(irqno, handle_edge_irq);
a21765a7 BD	628	set_irq_flags(irqno, IRQF_VALID);
	629	}
	630
	631	for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
	632	irqdbf("registering irq %d (extended s3c irq)\n", irqno);
6845664a TG	633	irq_set_chip(irqno, &s3c_irqext_chip);
6845664a TG	634	irq_set_handler(irqno, handle_edge_irq);
a21765a7 BD	635	set_irq_flags(irqno, IRQF_VALID);
	636	}
	637
	638	/* register the uart interrupts */
	639
	640	irqdbf("s3c2410: registering external interrupts\n");
	641
	642	for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
	643	irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
6845664a TG	644	irq_set_chip(irqno, &s3c_irq_uart0);
6845664a TG	645	irq_set_handler(irqno, handle_level_irq);
a21765a7 BD	646	set_irq_flags(irqno, IRQF_VALID);
	647	}
	648
	649	for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
	650	irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
6845664a TG	651	irq_set_chip(irqno, &s3c_irq_uart1);
6845664a TG	652	irq_set_handler(irqno, handle_level_irq);
a21765a7 BD	653	set_irq_flags(irqno, IRQF_VALID);
	654	}
	655
	656	for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
	657	irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
6845664a TG	658	irq_set_chip(irqno, &s3c_irq_uart2);
6845664a TG	659	irq_set_handler(irqno, handle_level_irq);
a21765a7 BD	660	set_irq_flags(irqno, IRQF_VALID);
	661	}
	662
	663	for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
	664	irqdbf("registering irq %d (s3c adc irq)\n", irqno);
6845664a TG	665	irq_set_chip(irqno, &s3c_irq_adc);
6845664a TG	666	irq_set_handler(irqno, handle_edge_irq);
a21765a7 BD	667	set_irq_flags(irqno, IRQF_VALID);
	668	}
	669
	670	irqdbf("s3c2410: registered interrupt handlers\n");
	671	}