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Commit | Line | Data |
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1f629b7a HS |
1 | /* |
2 | * S3C24XX IRQ handling | |
a21765a7 | 3 | * |
e02f8664 | 4 | * Copyright (c) 2003-2004 Simtec Electronics |
a21765a7 | 5 | * Ben Dooks <ben@simtec.co.uk> |
1f629b7a | 6 | * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de> |
a21765a7 BD |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
a21765a7 BD |
17 | */ |
18 | ||
19 | #include <linux/init.h> | |
1f629b7a | 20 | #include <linux/slab.h> |
a21765a7 | 21 | #include <linux/module.h> |
1f629b7a HS |
22 | #include <linux/io.h> |
23 | #include <linux/err.h> | |
a21765a7 BD |
24 | #include <linux/interrupt.h> |
25 | #include <linux/ioport.h> | |
edbaa603 | 26 | #include <linux/device.h> |
1f629b7a | 27 | #include <linux/irqdomain.h> |
a21765a7 | 28 | |
a21765a7 BD |
29 | #include <asm/mach/irq.h> |
30 | ||
1f629b7a HS |
31 | #include <mach/regs-irq.h> |
32 | #include <mach/regs-gpio.h> | |
a21765a7 | 33 | |
a2b7ba9c | 34 | #include <plat/cpu.h> |
1f629b7a | 35 | #include <plat/regs-irqtype.h> |
a2b7ba9c BD |
36 | #include <plat/pm.h> |
37 | #include <plat/irq.h> | |
a21765a7 | 38 | |
1f629b7a HS |
39 | #define S3C_IRQTYPE_NONE 0 |
40 | #define S3C_IRQTYPE_EINT 1 | |
41 | #define S3C_IRQTYPE_EDGE 2 | |
42 | #define S3C_IRQTYPE_LEVEL 3 | |
a21765a7 | 43 | |
1f629b7a HS |
44 | struct s3c_irq_data { |
45 | unsigned int type; | |
46 | unsigned long parent_irq; | |
a21765a7 | 47 | |
1f629b7a HS |
48 | /* data gets filled during init */ |
49 | struct s3c_irq_intc *intc; | |
50 | unsigned long sub_bits; | |
51 | struct s3c_irq_intc *sub_intc; | |
a21765a7 BD |
52 | }; |
53 | ||
1f629b7a HS |
54 | /* |
55 | * Sructure holding the controller data | |
56 | * @reg_pending register holding pending irqs | |
57 | * @reg_intpnd special register intpnd in main intc | |
58 | * @reg_mask mask register | |
59 | * @domain irq_domain of the controller | |
60 | * @parent parent controller for ext and sub irqs | |
61 | * @irqs irq-data, always s3c_irq_data[32] | |
62 | */ | |
63 | struct s3c_irq_intc { | |
64 | void __iomem *reg_pending; | |
65 | void __iomem *reg_intpnd; | |
66 | void __iomem *reg_mask; | |
67 | struct irq_domain *domain; | |
68 | struct s3c_irq_intc *parent; | |
69 | struct s3c_irq_data *irqs; | |
a21765a7 BD |
70 | }; |
71 | ||
1f629b7a | 72 | static void s3c_irq_mask(struct irq_data *data) |
a21765a7 | 73 | { |
1f629b7a HS |
74 | struct s3c_irq_intc *intc = data->domain->host_data; |
75 | struct s3c_irq_intc *parent_intc = intc->parent; | |
76 | struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq]; | |
77 | struct s3c_irq_data *parent_data; | |
a21765a7 | 78 | unsigned long mask; |
1f629b7a HS |
79 | unsigned int irqno; |
80 | ||
81 | mask = __raw_readl(intc->reg_mask); | |
82 | mask |= (1UL << data->hwirq); | |
83 | __raw_writel(mask, intc->reg_mask); | |
84 | ||
85 | if (parent_intc && irq_data->parent_irq) { | |
86 | parent_data = &parent_intc->irqs[irq_data->parent_irq]; | |
a21765a7 | 87 | |
1f629b7a HS |
88 | /* check to see if we need to mask the parent IRQ */ |
89 | if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { | |
90 | irqno = irq_find_mapping(parent_intc->domain, | |
91 | irq_data->parent_irq); | |
92 | s3c_irq_mask(irq_get_irq_data(irqno)); | |
93 | } | |
94 | } | |
a21765a7 BD |
95 | } |
96 | ||
1f629b7a | 97 | static void s3c_irq_unmask(struct irq_data *data) |
a21765a7 | 98 | { |
1f629b7a HS |
99 | struct s3c_irq_intc *intc = data->domain->host_data; |
100 | struct s3c_irq_intc *parent_intc = intc->parent; | |
101 | struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq]; | |
a21765a7 | 102 | unsigned long mask; |
1f629b7a | 103 | unsigned int irqno; |
a21765a7 | 104 | |
1f629b7a HS |
105 | mask = __raw_readl(intc->reg_mask); |
106 | mask &= ~(1UL << data->hwirq); | |
107 | __raw_writel(mask, intc->reg_mask); | |
a21765a7 | 108 | |
1f629b7a HS |
109 | if (parent_intc && irq_data->parent_irq) { |
110 | irqno = irq_find_mapping(parent_intc->domain, | |
111 | irq_data->parent_irq); | |
112 | s3c_irq_unmask(irq_get_irq_data(irqno)); | |
a21765a7 BD |
113 | } |
114 | } | |
115 | ||
1f629b7a | 116 | static inline void s3c_irq_ack(struct irq_data *data) |
a21765a7 | 117 | { |
1f629b7a HS |
118 | struct s3c_irq_intc *intc = data->domain->host_data; |
119 | unsigned long bitval = 1UL << data->hwirq; | |
a21765a7 | 120 | |
1f629b7a HS |
121 | __raw_writel(bitval, intc->reg_pending); |
122 | if (intc->reg_intpnd) | |
123 | __raw_writel(bitval, intc->reg_intpnd); | |
a21765a7 BD |
124 | } |
125 | ||
1f629b7a HS |
126 | static int s3c_irqext_type_set(void __iomem *gpcon_reg, |
127 | void __iomem *extint_reg, | |
128 | unsigned long gpcon_offset, | |
129 | unsigned long extint_offset, | |
130 | unsigned int type) | |
a21765a7 | 131 | { |
a21765a7 BD |
132 | unsigned long newvalue = 0, value; |
133 | ||
a21765a7 BD |
134 | /* Set the GPIO to external interrupt mode */ |
135 | value = __raw_readl(gpcon_reg); | |
136 | value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); | |
137 | __raw_writel(value, gpcon_reg); | |
138 | ||
139 | /* Set the external interrupt to pointed trigger type */ | |
140 | switch (type) | |
141 | { | |
6cab4860 | 142 | case IRQ_TYPE_NONE: |
1f629b7a | 143 | pr_warn("No edge setting!\n"); |
a21765a7 BD |
144 | break; |
145 | ||
6cab4860 | 146 | case IRQ_TYPE_EDGE_RISING: |
a21765a7 BD |
147 | newvalue = S3C2410_EXTINT_RISEEDGE; |
148 | break; | |
149 | ||
6cab4860 | 150 | case IRQ_TYPE_EDGE_FALLING: |
a21765a7 BD |
151 | newvalue = S3C2410_EXTINT_FALLEDGE; |
152 | break; | |
153 | ||
6cab4860 | 154 | case IRQ_TYPE_EDGE_BOTH: |
a21765a7 BD |
155 | newvalue = S3C2410_EXTINT_BOTHEDGE; |
156 | break; | |
157 | ||
6cab4860 | 158 | case IRQ_TYPE_LEVEL_LOW: |
a21765a7 BD |
159 | newvalue = S3C2410_EXTINT_LOWLEV; |
160 | break; | |
161 | ||
6cab4860 | 162 | case IRQ_TYPE_LEVEL_HIGH: |
a21765a7 BD |
163 | newvalue = S3C2410_EXTINT_HILEV; |
164 | break; | |
165 | ||
166 | default: | |
1f629b7a HS |
167 | pr_err("No such irq type %d", type); |
168 | return -EINVAL; | |
a21765a7 BD |
169 | } |
170 | ||
171 | value = __raw_readl(extint_reg); | |
172 | value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); | |
173 | __raw_writel(value, extint_reg); | |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
1f629b7a HS |
178 | /* FIXME: make static when it's out of plat-samsung/irq.h */ |
179 | int s3c_irqext_type(struct irq_data *data, unsigned int type) | |
a21765a7 | 180 | { |
1f629b7a HS |
181 | void __iomem *extint_reg; |
182 | void __iomem *gpcon_reg; | |
183 | unsigned long gpcon_offset, extint_offset; | |
a21765a7 | 184 | |
1f629b7a HS |
185 | if ((data->hwirq >= 4) && (data->hwirq <= 7)) { |
186 | gpcon_reg = S3C2410_GPFCON; | |
187 | extint_reg = S3C24XX_EXTINT0; | |
188 | gpcon_offset = (data->hwirq) * 2; | |
189 | extint_offset = (data->hwirq) * 4; | |
190 | } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) { | |
191 | gpcon_reg = S3C2410_GPGCON; | |
192 | extint_reg = S3C24XX_EXTINT1; | |
193 | gpcon_offset = (data->hwirq - 8) * 2; | |
194 | extint_offset = (data->hwirq - 8) * 4; | |
195 | } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) { | |
196 | gpcon_reg = S3C2410_GPGCON; | |
197 | extint_reg = S3C24XX_EXTINT2; | |
198 | gpcon_offset = (data->hwirq - 8) * 2; | |
199 | extint_offset = (data->hwirq - 16) * 4; | |
200 | } else { | |
201 | return -EINVAL; | |
202 | } | |
a21765a7 | 203 | |
1f629b7a HS |
204 | return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, |
205 | extint_offset, type); | |
a21765a7 BD |
206 | } |
207 | ||
1f629b7a | 208 | static int s3c_irqext0_type(struct irq_data *data, unsigned int type) |
a21765a7 | 209 | { |
1f629b7a HS |
210 | void __iomem *extint_reg; |
211 | void __iomem *gpcon_reg; | |
212 | unsigned long gpcon_offset, extint_offset; | |
a21765a7 | 213 | |
1f629b7a HS |
214 | if ((data->hwirq >= 0) && (data->hwirq <= 3)) { |
215 | gpcon_reg = S3C2410_GPFCON; | |
216 | extint_reg = S3C24XX_EXTINT0; | |
217 | gpcon_offset = (data->hwirq) * 2; | |
218 | extint_offset = (data->hwirq) * 4; | |
219 | } else { | |
220 | return -EINVAL; | |
221 | } | |
a21765a7 | 222 | |
1f629b7a HS |
223 | return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, |
224 | extint_offset, type); | |
a21765a7 BD |
225 | } |
226 | ||
1f629b7a HS |
227 | struct irq_chip s3c_irq_chip = { |
228 | .name = "s3c", | |
229 | .irq_ack = s3c_irq_ack, | |
230 | .irq_mask = s3c_irq_mask, | |
231 | .irq_unmask = s3c_irq_unmask, | |
232 | .irq_set_wake = s3c_irq_wake | |
a21765a7 BD |
233 | }; |
234 | ||
1f629b7a HS |
235 | struct irq_chip s3c_irq_level_chip = { |
236 | .name = "s3c-level", | |
237 | .irq_mask = s3c_irq_mask, | |
238 | .irq_unmask = s3c_irq_unmask, | |
239 | .irq_ack = s3c_irq_ack, | |
a21765a7 BD |
240 | }; |
241 | ||
1f629b7a HS |
242 | static struct irq_chip s3c_irqext_chip = { |
243 | .name = "s3c-ext", | |
244 | .irq_mask = s3c_irq_mask, | |
245 | .irq_unmask = s3c_irq_unmask, | |
246 | .irq_ack = s3c_irq_ack, | |
247 | .irq_set_type = s3c_irqext_type, | |
248 | .irq_set_wake = s3c_irqext_wake | |
a21765a7 BD |
249 | }; |
250 | ||
1f629b7a HS |
251 | static struct irq_chip s3c_irq_eint0t4 = { |
252 | .name = "s3c-ext0", | |
253 | .irq_ack = s3c_irq_ack, | |
254 | .irq_mask = s3c_irq_mask, | |
255 | .irq_unmask = s3c_irq_unmask, | |
256 | .irq_set_wake = s3c_irq_wake, | |
257 | .irq_set_type = s3c_irqext0_type, | |
258 | }; | |
a21765a7 | 259 | |
1f629b7a | 260 | static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc) |
a21765a7 | 261 | { |
1f629b7a HS |
262 | struct irq_chip *chip = irq_desc_get_chip(desc); |
263 | struct s3c_irq_intc *intc = desc->irq_data.domain->host_data; | |
264 | struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq]; | |
265 | struct s3c_irq_intc *sub_intc = irq_data->sub_intc; | |
266 | unsigned long src; | |
267 | unsigned long msk; | |
268 | unsigned int n; | |
269 | ||
270 | chained_irq_enter(chip, desc); | |
271 | ||
272 | src = __raw_readl(sub_intc->reg_pending); | |
273 | msk = __raw_readl(sub_intc->reg_mask); | |
274 | ||
275 | src &= ~msk; | |
276 | src &= irq_data->sub_bits; | |
277 | ||
278 | while (src) { | |
279 | n = __ffs(src); | |
280 | src &= ~(1 << n); | |
281 | generic_handle_irq(irq_find_mapping(sub_intc->domain, n)); | |
a21765a7 BD |
282 | } |
283 | ||
1f629b7a | 284 | chained_irq_exit(chip, desc); |
a21765a7 BD |
285 | } |
286 | ||
229fd8ff BD |
287 | #ifdef CONFIG_FIQ |
288 | /** | |
289 | * s3c24xx_set_fiq - set the FIQ routing | |
290 | * @irq: IRQ number to route to FIQ on processor. | |
291 | * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing. | |
292 | * | |
293 | * Change the state of the IRQ to FIQ routing depending on @irq and @on. If | |
294 | * @on is true, the @irq is checked to see if it can be routed and the | |
295 | * interrupt controller updated to route the IRQ. If @on is false, the FIQ | |
296 | * routing is cleared, regardless of which @irq is specified. | |
297 | */ | |
298 | int s3c24xx_set_fiq(unsigned int irq, bool on) | |
299 | { | |
300 | u32 intmod; | |
301 | unsigned offs; | |
302 | ||
303 | if (on) { | |
304 | offs = irq - FIQ_START; | |
305 | if (offs > 31) | |
306 | return -EINVAL; | |
307 | ||
308 | intmod = 1 << offs; | |
309 | } else { | |
310 | intmod = 0; | |
311 | } | |
312 | ||
313 | __raw_writel(intmod, S3C2410_INTMOD); | |
314 | return 0; | |
315 | } | |
0f13c824 BD |
316 | |
317 | EXPORT_SYMBOL_GPL(s3c24xx_set_fiq); | |
229fd8ff BD |
318 | #endif |
319 | ||
1f629b7a HS |
320 | static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, |
321 | irq_hw_number_t hw) | |
a21765a7 | 322 | { |
1f629b7a HS |
323 | struct s3c_irq_intc *intc = h->host_data; |
324 | struct s3c_irq_data *irq_data = &intc->irqs[hw]; | |
325 | struct s3c_irq_intc *parent_intc; | |
326 | struct s3c_irq_data *parent_irq_data; | |
327 | unsigned int irqno; | |
328 | ||
329 | if (!intc) { | |
330 | pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw); | |
331 | return -EINVAL; | |
332 | } | |
a21765a7 | 333 | |
1f629b7a HS |
334 | if (!irq_data) { |
335 | pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw); | |
336 | return -EINVAL; | |
337 | } | |
a21765a7 | 338 | |
1f629b7a HS |
339 | /* attach controller pointer to irq_data */ |
340 | irq_data->intc = intc; | |
a21765a7 | 341 | |
1f629b7a HS |
342 | /* set handler and flags */ |
343 | switch (irq_data->type) { | |
344 | case S3C_IRQTYPE_NONE: | |
345 | return 0; | |
346 | case S3C_IRQTYPE_EINT: | |
347 | if (irq_data->parent_irq) | |
348 | irq_set_chip_and_handler(virq, &s3c_irqext_chip, | |
349 | handle_edge_irq); | |
350 | else | |
351 | irq_set_chip_and_handler(virq, &s3c_irq_eint0t4, | |
352 | handle_edge_irq); | |
353 | break; | |
354 | case S3C_IRQTYPE_EDGE: | |
355 | if (irq_data->parent_irq) | |
356 | irq_set_chip_and_handler(virq, &s3c_irq_level_chip, | |
357 | handle_edge_irq); | |
358 | else | |
359 | irq_set_chip_and_handler(virq, &s3c_irq_chip, | |
360 | handle_edge_irq); | |
361 | break; | |
362 | case S3C_IRQTYPE_LEVEL: | |
363 | if (irq_data->parent_irq) | |
364 | irq_set_chip_and_handler(virq, &s3c_irq_level_chip, | |
365 | handle_level_irq); | |
366 | else | |
367 | irq_set_chip_and_handler(virq, &s3c_irq_chip, | |
368 | handle_level_irq); | |
369 | break; | |
370 | default: | |
371 | pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type); | |
372 | return -EINVAL; | |
a21765a7 | 373 | } |
1f629b7a HS |
374 | set_irq_flags(virq, IRQF_VALID); |
375 | ||
376 | if (irq_data->parent_irq) { | |
377 | parent_intc = intc->parent; | |
378 | if (!parent_intc) { | |
379 | pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n", | |
380 | hw); | |
381 | goto err; | |
382 | } | |
a21765a7 | 383 | |
1f629b7a HS |
384 | parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; |
385 | if (!irq_data) { | |
386 | pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", | |
387 | hw); | |
388 | goto err; | |
389 | } | |
a21765a7 | 390 | |
1f629b7a HS |
391 | parent_irq_data->sub_intc = intc; |
392 | parent_irq_data->sub_bits |= (1UL << hw); | |
a21765a7 | 393 | |
1f629b7a HS |
394 | /* attach the demuxer to the parent irq */ |
395 | irqno = irq_find_mapping(parent_intc->domain, | |
396 | irq_data->parent_irq); | |
397 | if (!irqno) { | |
398 | pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n", | |
399 | irq_data->parent_irq); | |
400 | goto err; | |
401 | } | |
402 | irq_set_chained_handler(irqno, s3c_irq_demux); | |
a21765a7 BD |
403 | } |
404 | ||
1f629b7a | 405 | return 0; |
a21765a7 | 406 | |
1f629b7a HS |
407 | err: |
408 | set_irq_flags(virq, 0); | |
a21765a7 | 409 | |
1f629b7a HS |
410 | /* the only error can result from bad mapping data*/ |
411 | return -EINVAL; | |
412 | } | |
a21765a7 | 413 | |
1f629b7a HS |
414 | static struct irq_domain_ops s3c24xx_irq_ops = { |
415 | .map = s3c24xx_irq_map, | |
416 | .xlate = irq_domain_xlate_twocell, | |
417 | }; | |
a21765a7 | 418 | |
1f629b7a HS |
419 | static void s3c24xx_clear_intc(struct s3c_irq_intc *intc) |
420 | { | |
421 | void __iomem *reg_source; | |
422 | unsigned long pend; | |
423 | unsigned long last; | |
424 | int i; | |
a21765a7 | 425 | |
1f629b7a HS |
426 | /* if intpnd is set, read the next pending irq from there */ |
427 | reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending; | |
a21765a7 | 428 | |
1f629b7a HS |
429 | last = 0; |
430 | for (i = 0; i < 4; i++) { | |
431 | pend = __raw_readl(reg_source); | |
a21765a7 | 432 | |
1f629b7a | 433 | if (pend == 0 || pend == last) |
a21765a7 BD |
434 | break; |
435 | ||
1f629b7a HS |
436 | __raw_writel(pend, intc->reg_pending); |
437 | if (intc->reg_intpnd) | |
438 | __raw_writel(pend, intc->reg_intpnd); | |
a21765a7 | 439 | |
1f629b7a HS |
440 | pr_info("irq: clearing pending status %08x\n", (int)pend); |
441 | last = pend; | |
a21765a7 | 442 | } |
1f629b7a | 443 | } |
a21765a7 | 444 | |
1f629b7a HS |
445 | struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np, |
446 | struct s3c_irq_data *irq_data, | |
447 | struct s3c_irq_intc *parent, | |
448 | unsigned long address) | |
449 | { | |
450 | struct s3c_irq_intc *intc; | |
451 | void __iomem *base = (void *)0xf6000000; /* static mapping */ | |
452 | int irq_num; | |
453 | int irq_start; | |
454 | int irq_offset; | |
455 | int ret; | |
456 | ||
457 | intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); | |
458 | if (!intc) | |
459 | return ERR_PTR(-ENOMEM); | |
460 | ||
461 | intc->irqs = irq_data; | |
462 | ||
463 | if (parent) | |
464 | intc->parent = parent; | |
465 | ||
466 | /* select the correct data for the controller. | |
467 | * Need to hard code the irq num start and offset | |
468 | * to preserve the static mapping for now | |
469 | */ | |
470 | switch (address) { | |
471 | case 0x4a000000: | |
472 | pr_debug("irq: found main intc\n"); | |
473 | intc->reg_pending = base; | |
474 | intc->reg_mask = base + 0x08; | |
475 | intc->reg_intpnd = base + 0x10; | |
476 | irq_num = 32; | |
477 | irq_start = S3C2410_IRQ(0); | |
478 | irq_offset = 0; | |
479 | break; | |
480 | case 0x4a000018: | |
481 | pr_debug("irq: found subintc\n"); | |
482 | intc->reg_pending = base + 0x18; | |
483 | intc->reg_mask = base + 0x1c; | |
484 | irq_num = 29; | |
485 | irq_start = S3C2410_IRQSUB(0); | |
486 | irq_offset = 0; | |
487 | break; | |
488 | case 0x4a000040: | |
489 | pr_debug("irq: found intc2\n"); | |
490 | intc->reg_pending = base + 0x40; | |
491 | intc->reg_mask = base + 0x48; | |
492 | intc->reg_intpnd = base + 0x50; | |
493 | irq_num = 8; | |
494 | irq_start = S3C2416_IRQ(0); | |
495 | irq_offset = 0; | |
496 | break; | |
497 | case 0x560000a4: | |
498 | pr_debug("irq: found eintc\n"); | |
499 | base = (void *)0xfd000000; | |
500 | ||
501 | intc->reg_mask = base + 0xa4; | |
502 | intc->reg_pending = base + 0x08; | |
503 | irq_num = 20; | |
504 | irq_start = S3C2410_IRQ(32); | |
505 | irq_offset = 4; | |
506 | break; | |
507 | default: | |
508 | pr_err("irq: unsupported controller address\n"); | |
509 | ret = -EINVAL; | |
510 | goto err; | |
511 | } | |
a21765a7 | 512 | |
1f629b7a HS |
513 | /* now that all the data is complete, init the irq-domain */ |
514 | s3c24xx_clear_intc(intc); | |
515 | intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, | |
516 | irq_offset, &s3c24xx_irq_ops, | |
517 | intc); | |
518 | if (!intc->domain) { | |
519 | pr_err("irq: could not create irq-domain\n"); | |
520 | ret = -EINVAL; | |
521 | goto err; | |
522 | } | |
a21765a7 | 523 | |
1f629b7a | 524 | return intc; |
a21765a7 | 525 | |
1f629b7a HS |
526 | err: |
527 | kfree(intc); | |
528 | return ERR_PTR(ret); | |
529 | } | |
a21765a7 | 530 | |
1f629b7a HS |
531 | /* s3c24xx_init_irq |
532 | * | |
533 | * Initialise S3C2410 IRQ system | |
534 | */ | |
a21765a7 | 535 | |
1f629b7a HS |
536 | static struct s3c_irq_data init_base[32] = { |
537 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ | |
538 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ | |
539 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ | |
540 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ | |
541 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | |
542 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | |
543 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
544 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | |
545 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | |
546 | { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ | |
547 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | |
548 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | |
549 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | |
550 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | |
551 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | |
552 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | |
553 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ | |
554 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ | |
555 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ | |
556 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ | |
557 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ | |
558 | { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ | |
559 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | |
560 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | |
561 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
562 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | |
563 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | |
564 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | |
565 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | |
566 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ | |
567 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | |
568 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | |
569 | }; | |
a21765a7 | 570 | |
1f629b7a HS |
571 | static struct s3c_irq_data init_eint[32] = { |
572 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
573 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
574 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
575 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | |
576 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ | |
577 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ | |
578 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ | |
579 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ | |
580 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ | |
581 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ | |
582 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ | |
583 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ | |
584 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ | |
585 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ | |
586 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ | |
587 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ | |
588 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ | |
589 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ | |
590 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ | |
591 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ | |
592 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ | |
593 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ | |
594 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ | |
595 | { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ | |
596 | }; | |
a21765a7 | 597 | |
1f629b7a HS |
598 | static struct s3c_irq_data init_subint[32] = { |
599 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ | |
600 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | |
601 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | |
602 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | |
603 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | |
604 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | |
605 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | |
606 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | |
607 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | |
608 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | |
609 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | |
610 | }; | |
a21765a7 | 611 | |
1f629b7a HS |
612 | void __init s3c24xx_init_irq(void) |
613 | { | |
614 | struct s3c_irq_intc *main_intc; | |
a21765a7 | 615 | |
1f629b7a HS |
616 | #ifdef CONFIG_FIQ |
617 | init_FIQ(FIQ_START); | |
618 | #endif | |
a21765a7 | 619 | |
1f629b7a HS |
620 | main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000); |
621 | if (IS_ERR(main_intc)) { | |
622 | pr_err("irq: could not create main interrupt controller\n"); | |
623 | return; | |
a21765a7 BD |
624 | } |
625 | ||
1f629b7a HS |
626 | s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018); |
627 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); | |
a21765a7 | 628 | } |
ef602eb5 HS |
629 | |
630 | #ifdef CONFIG_CPU_S3C2416 | |
631 | #define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) | |
632 | ||
633 | static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len) | |
634 | { | |
635 | unsigned int subsrc, submsk; | |
636 | unsigned int end; | |
637 | ||
638 | /* read the current pending interrupts, and the mask | |
639 | * for what it is available */ | |
640 | ||
641 | subsrc = __raw_readl(S3C2410_SUBSRCPND); | |
642 | submsk = __raw_readl(S3C2410_INTSUBMSK); | |
643 | ||
644 | subsrc &= ~submsk; | |
645 | subsrc >>= (irq - S3C2410_IRQSUB(0)); | |
646 | subsrc &= (1 << len)-1; | |
647 | ||
648 | end = len + irq; | |
649 | ||
650 | for (; irq < end && subsrc; irq++) { | |
651 | if (subsrc & 1) | |
652 | generic_handle_irq(irq); | |
653 | ||
654 | subsrc >>= 1; | |
655 | } | |
656 | } | |
657 | ||
658 | /* WDT/AC97 sub interrupts */ | |
659 | ||
660 | static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc) | |
661 | { | |
662 | s3c2416_irq_demux(IRQ_S3C2443_WDT, 4); | |
663 | } | |
664 | ||
665 | #define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0)) | |
666 | #define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97) | |
667 | ||
668 | static void s3c2416_irq_wdtac97_mask(struct irq_data *data) | |
669 | { | |
670 | s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); | |
671 | } | |
672 | ||
673 | static void s3c2416_irq_wdtac97_unmask(struct irq_data *data) | |
674 | { | |
675 | s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97); | |
676 | } | |
677 | ||
678 | static void s3c2416_irq_wdtac97_ack(struct irq_data *data) | |
679 | { | |
680 | s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); | |
681 | } | |
682 | ||
683 | static struct irq_chip s3c2416_irq_wdtac97 = { | |
684 | .irq_mask = s3c2416_irq_wdtac97_mask, | |
685 | .irq_unmask = s3c2416_irq_wdtac97_unmask, | |
686 | .irq_ack = s3c2416_irq_wdtac97_ack, | |
687 | }; | |
688 | ||
689 | /* LCD sub interrupts */ | |
690 | ||
691 | static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) | |
692 | { | |
693 | s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4); | |
694 | } | |
695 | ||
696 | #define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0)) | |
697 | #define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4) | |
698 | ||
699 | static void s3c2416_irq_lcd_mask(struct irq_data *data) | |
700 | { | |
701 | s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD); | |
702 | } | |
703 | ||
704 | static void s3c2416_irq_lcd_unmask(struct irq_data *data) | |
705 | { | |
706 | s3c_irqsub_unmask(data->irq, INTMSK_LCD); | |
707 | } | |
708 | ||
709 | static void s3c2416_irq_lcd_ack(struct irq_data *data) | |
710 | { | |
711 | s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD); | |
712 | } | |
713 | ||
714 | static struct irq_chip s3c2416_irq_lcd = { | |
715 | .irq_mask = s3c2416_irq_lcd_mask, | |
716 | .irq_unmask = s3c2416_irq_lcd_unmask, | |
717 | .irq_ack = s3c2416_irq_lcd_ack, | |
718 | }; | |
719 | ||
720 | /* DMA sub interrupts */ | |
721 | ||
722 | static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc) | |
723 | { | |
724 | s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6); | |
725 | } | |
726 | ||
727 | #define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0)) | |
728 | #define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5) | |
729 | ||
730 | ||
731 | static void s3c2416_irq_dma_mask(struct irq_data *data) | |
732 | { | |
733 | s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA); | |
734 | } | |
735 | ||
736 | static void s3c2416_irq_dma_unmask(struct irq_data *data) | |
737 | { | |
738 | s3c_irqsub_unmask(data->irq, INTMSK_DMA); | |
739 | } | |
740 | ||
741 | static void s3c2416_irq_dma_ack(struct irq_data *data) | |
742 | { | |
743 | s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA); | |
744 | } | |
745 | ||
746 | static struct irq_chip s3c2416_irq_dma = { | |
747 | .irq_mask = s3c2416_irq_dma_mask, | |
748 | .irq_unmask = s3c2416_irq_dma_unmask, | |
749 | .irq_ack = s3c2416_irq_dma_ack, | |
750 | }; | |
751 | ||
752 | /* UART3 sub interrupts */ | |
753 | ||
754 | static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) | |
755 | { | |
756 | s3c2416_irq_demux(IRQ_S3C2443_RX3, 3); | |
757 | } | |
758 | ||
759 | #define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0)) | |
760 | #define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0))) | |
761 | ||
762 | static void s3c2416_irq_uart3_mask(struct irq_data *data) | |
763 | { | |
764 | s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3); | |
765 | } | |
766 | ||
767 | static void s3c2416_irq_uart3_unmask(struct irq_data *data) | |
768 | { | |
769 | s3c_irqsub_unmask(data->irq, INTMSK_UART3); | |
770 | } | |
771 | ||
772 | static void s3c2416_irq_uart3_ack(struct irq_data *data) | |
773 | { | |
774 | s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3); | |
775 | } | |
776 | ||
777 | static struct irq_chip s3c2416_irq_uart3 = { | |
778 | .irq_mask = s3c2416_irq_uart3_mask, | |
779 | .irq_unmask = s3c2416_irq_uart3_unmask, | |
780 | .irq_ack = s3c2416_irq_uart3_ack, | |
781 | }; | |
782 | ||
783 | /* second interrupt register */ | |
784 | ||
785 | static inline void s3c2416_irq_ack_second(struct irq_data *data) | |
786 | { | |
787 | unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D); | |
788 | ||
789 | __raw_writel(bitval, S3C2416_SRCPND2); | |
790 | __raw_writel(bitval, S3C2416_INTPND2); | |
791 | } | |
792 | ||
793 | static void s3c2416_irq_mask_second(struct irq_data *data) | |
794 | { | |
795 | unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D); | |
796 | unsigned long mask; | |
797 | ||
798 | mask = __raw_readl(S3C2416_INTMSK2); | |
799 | mask |= bitval; | |
800 | __raw_writel(mask, S3C2416_INTMSK2); | |
801 | } | |
802 | ||
803 | static void s3c2416_irq_unmask_second(struct irq_data *data) | |
804 | { | |
805 | unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D); | |
806 | unsigned long mask; | |
807 | ||
808 | mask = __raw_readl(S3C2416_INTMSK2); | |
809 | mask &= ~bitval; | |
810 | __raw_writel(mask, S3C2416_INTMSK2); | |
811 | } | |
812 | ||
813 | static struct irq_chip s3c2416_irq_second = { | |
814 | .irq_ack = s3c2416_irq_ack_second, | |
815 | .irq_mask = s3c2416_irq_mask_second, | |
816 | .irq_unmask = s3c2416_irq_unmask_second, | |
817 | }; | |
818 | ||
819 | ||
820 | /* IRQ initialisation code */ | |
821 | ||
822 | static int s3c2416_add_sub(unsigned int base, | |
823 | void (*demux)(unsigned int, | |
824 | struct irq_desc *), | |
825 | struct irq_chip *chip, | |
826 | unsigned int start, unsigned int end) | |
827 | { | |
828 | unsigned int irqno; | |
829 | ||
830 | irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq); | |
831 | irq_set_chained_handler(base, demux); | |
832 | ||
833 | for (irqno = start; irqno <= end; irqno++) { | |
834 | irq_set_chip_and_handler(irqno, chip, handle_level_irq); | |
835 | set_irq_flags(irqno, IRQF_VALID); | |
836 | } | |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
841 | static void s3c2416_irq_add_second(void) | |
842 | { | |
843 | unsigned long pend; | |
844 | unsigned long last; | |
845 | int irqno; | |
846 | int i; | |
847 | ||
848 | /* first, clear all interrupts pending... */ | |
849 | last = 0; | |
850 | for (i = 0; i < 4; i++) { | |
851 | pend = __raw_readl(S3C2416_INTPND2); | |
852 | ||
853 | if (pend == 0 || pend == last) | |
854 | break; | |
855 | ||
856 | __raw_writel(pend, S3C2416_SRCPND2); | |
857 | __raw_writel(pend, S3C2416_INTPND2); | |
858 | printk(KERN_INFO "irq: clearing pending status %08x\n", | |
859 | (int)pend); | |
860 | last = pend; | |
861 | } | |
862 | ||
863 | for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) { | |
864 | switch (irqno) { | |
865 | case IRQ_S3C2416_RESERVED2: | |
866 | case IRQ_S3C2416_RESERVED3: | |
867 | /* no IRQ here */ | |
868 | break; | |
869 | default: | |
870 | irq_set_chip_and_handler(irqno, &s3c2416_irq_second, | |
871 | handle_edge_irq); | |
872 | set_irq_flags(irqno, IRQF_VALID); | |
873 | } | |
874 | } | |
875 | } | |
876 | ||
877 | static int s3c2416_irq_add(struct device *dev, | |
878 | struct subsys_interface *sif) | |
879 | { | |
880 | printk(KERN_INFO "S3C2416: IRQ Support\n"); | |
881 | ||
882 | s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd, | |
883 | IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4); | |
884 | ||
885 | s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma, | |
886 | &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5); | |
887 | ||
888 | s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3, | |
889 | &s3c2416_irq_uart3, | |
890 | IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3); | |
891 | ||
892 | s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97, | |
893 | &s3c2416_irq_wdtac97, | |
894 | IRQ_S3C2443_WDT, IRQ_S3C2443_AC97); | |
895 | ||
896 | s3c2416_irq_add_second(); | |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
901 | static struct subsys_interface s3c2416_irq_interface = { | |
902 | .name = "s3c2416_irq", | |
903 | .subsys = &s3c2416_subsys, | |
904 | .add_dev = s3c2416_irq_add, | |
905 | }; | |
906 | ||
907 | static int __init s3c2416_irq_init(void) | |
908 | { | |
909 | return subsys_interface_register(&s3c2416_irq_interface); | |
910 | } | |
911 | ||
912 | arch_initcall(s3c2416_irq_init); | |
913 | ||
914 | #endif |