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1 | /* arch/arm/plat-s3c64xx/irq-eint.c |
2 | * | |
3 | * Copyright 2008 Openmoko, Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * S3C64XX - Interrupt handling for IRQ_EINT(x) | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/interrupt.h> | |
28fd2d39 | 17 | #include <linux/gpio.h> |
80789e79 BD |
18 | #include <linux/irq.h> |
19 | #include <linux/io.h> | |
20 | ||
21 | #include <asm/hardware/vic.h> | |
22 | ||
23 | #include <plat/regs-irqtype.h> | |
28fd2d39 BD |
24 | #include <plat/regs-gpio.h> |
25 | #include <plat/gpio-cfg.h> | |
80789e79 BD |
26 | |
27 | #include <mach/map.h> | |
28 | #include <plat/cpu.h> | |
29 | ||
30 | /* GPIO is 0x7F008xxx, */ | |
31 | #define S3C64XX_GPIOREG(x) (S3C64XX_VA_GPIO + (x)) | |
32 | ||
33 | #define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) | |
34 | #define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) | |
35 | #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) | |
36 | #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) | |
37 | #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) | |
38 | #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) | |
39 | ||
40 | #define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) | |
41 | #define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) | |
42 | ||
43 | ||
44 | #define eint_offset(irq) ((irq) - IRQ_EINT(0)) | |
45 | #define eint_irq_to_bit(irq) (1 << eint_offset(irq)) | |
46 | ||
47 | static inline void s3c_irq_eint_mask(unsigned int irq) | |
48 | { | |
49 | u32 mask; | |
50 | ||
51 | mask = __raw_readl(S3C64XX_EINT0MASK); | |
52 | mask |= eint_irq_to_bit(irq); | |
53 | __raw_writel(mask, S3C64XX_EINT0MASK); | |
54 | } | |
55 | ||
56 | static void s3c_irq_eint_unmask(unsigned int irq) | |
57 | { | |
58 | u32 mask; | |
59 | ||
60 | mask = __raw_readl(S3C64XX_EINT0MASK); | |
61 | mask |= eint_irq_to_bit(irq); | |
62 | __raw_writel(mask, S3C64XX_EINT0MASK); | |
63 | } | |
64 | ||
65 | static inline void s3c_irq_eint_ack(unsigned int irq) | |
66 | { | |
67 | __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND); | |
68 | } | |
69 | ||
70 | static void s3c_irq_eint_maskack(unsigned int irq) | |
71 | { | |
72 | /* compiler should in-line these */ | |
73 | s3c_irq_eint_mask(irq); | |
74 | s3c_irq_eint_ack(irq); | |
75 | } | |
76 | ||
77 | static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) | |
78 | { | |
79 | int offs = eint_offset(irq); | |
28fd2d39 | 80 | int pin; |
80789e79 BD |
81 | int shift; |
82 | u32 ctrl, mask; | |
83 | u32 newvalue = 0; | |
84 | void __iomem *reg; | |
85 | ||
86 | if (offs > 27) | |
87 | return -EINVAL; | |
88 | ||
a9c5d23a | 89 | if (offs <= 15) |
80789e79 BD |
90 | reg = S3C64XX_EINT0CON0; |
91 | else | |
92 | reg = S3C64XX_EINT0CON1; | |
93 | ||
94 | switch (type) { | |
95 | case IRQ_TYPE_NONE: | |
96 | printk(KERN_WARNING "No edge setting!\n"); | |
97 | break; | |
98 | ||
99 | case IRQ_TYPE_EDGE_RISING: | |
100 | newvalue = S3C2410_EXTINT_RISEEDGE; | |
101 | break; | |
102 | ||
103 | case IRQ_TYPE_EDGE_FALLING: | |
104 | newvalue = S3C2410_EXTINT_FALLEDGE; | |
105 | break; | |
106 | ||
107 | case IRQ_TYPE_EDGE_BOTH: | |
108 | newvalue = S3C2410_EXTINT_BOTHEDGE; | |
109 | break; | |
110 | ||
111 | case IRQ_TYPE_LEVEL_LOW: | |
112 | newvalue = S3C2410_EXTINT_LOWLEV; | |
113 | break; | |
114 | ||
115 | case IRQ_TYPE_LEVEL_HIGH: | |
116 | newvalue = S3C2410_EXTINT_HILEV; | |
117 | break; | |
118 | ||
119 | default: | |
120 | printk(KERN_ERR "No such irq type %d", type); | |
121 | return -1; | |
122 | } | |
123 | ||
124 | shift = (offs / 2) * 4; | |
125 | mask = 0x7 << shift; | |
126 | ||
127 | ctrl = __raw_readl(reg); | |
128 | ctrl &= ~mask; | |
129 | ctrl |= newvalue << shift; | |
130 | __raw_writel(ctrl, reg); | |
131 | ||
28fd2d39 BD |
132 | /* set the GPIO pin appropriately */ |
133 | ||
134 | if (offs < 23) | |
135 | pin = S3C64XX_GPN(offs); | |
136 | else | |
137 | pin = S3C64XX_GPM(offs - 23); | |
138 | ||
139 | s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2)); | |
140 | ||
80789e79 BD |
141 | return 0; |
142 | } | |
143 | ||
144 | static struct irq_chip s3c_irq_eint = { | |
145 | .name = "s3c-eint", | |
146 | .mask = s3c_irq_eint_mask, | |
147 | .unmask = s3c_irq_eint_unmask, | |
148 | .mask_ack = s3c_irq_eint_maskack, | |
149 | .ack = s3c_irq_eint_ack, | |
150 | .set_type = s3c_irq_eint_set_type, | |
151 | }; | |
152 | ||
153 | /* s3c_irq_demux_eint | |
154 | * | |
155 | * This function demuxes the IRQ from the group0 external interrupts, | |
156 | * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into | |
157 | * the specific handlers s3c_irq_demux_eintX_Y. | |
158 | */ | |
159 | static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) | |
160 | { | |
161 | u32 status = __raw_readl(S3C64XX_EINT0PEND); | |
162 | u32 mask = __raw_readl(S3C64XX_EINT0MASK); | |
163 | unsigned int irq; | |
164 | ||
165 | status &= ~mask; | |
166 | status >>= start; | |
167 | status &= (1 << (end - start + 1)) - 1; | |
168 | ||
169 | for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { | |
170 | if (status & 1) | |
171 | generic_handle_irq(irq); | |
172 | ||
173 | status >>= 1; | |
174 | } | |
175 | } | |
176 | ||
177 | static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc) | |
178 | { | |
179 | s3c_irq_demux_eint(0, 3); | |
180 | } | |
181 | ||
182 | static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc) | |
183 | { | |
184 | s3c_irq_demux_eint(4, 11); | |
185 | } | |
186 | ||
187 | static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc) | |
188 | { | |
189 | s3c_irq_demux_eint(12, 19); | |
190 | } | |
191 | ||
192 | static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc) | |
193 | { | |
194 | s3c_irq_demux_eint(20, 27); | |
195 | } | |
196 | ||
197 | int __init s3c64xx_init_irq_eint(void) | |
198 | { | |
199 | int irq; | |
200 | ||
201 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { | |
202 | set_irq_chip(irq, &s3c_irq_eint); | |
203 | set_irq_handler(irq, handle_level_irq); | |
204 | set_irq_flags(irq, IRQF_VALID); | |
205 | } | |
206 | ||
207 | set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); | |
208 | set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); | |
209 | set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); | |
210 | set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
215 | arch_initcall(s3c64xx_init_irq_eint); |