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1 | /* linux/arch/arm/plat-s3c64xx/pm.c |
2 | * | |
3 | * Copyright 2008 Openmoko, Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * S3C64XX CPU PM support. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/suspend.h> | |
17 | #include <linux/serial_core.h> | |
18 | #include <linux/io.h> | |
19 | ||
20 | #include <mach/map.h> | |
21 | ||
22 | #include <plat/pm.h> | |
23 | #include <plat/regs-sys.h> | |
24 | #include <plat/regs-gpio.h> | |
25 | #include <plat/regs-clock.h> | |
26 | #include <plat/regs-syscon-power.h> | |
27 | #include <plat/regs-gpio-memport.h> | |
28 | ||
29 | #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK | |
30 | #include <plat/gpio-bank-n.h> | |
31 | ||
32 | void s3c_pm_debug_smdkled(u32 set, u32 clear) | |
33 | { | |
34 | unsigned long flags; | |
35 | u32 reg; | |
36 | ||
37 | local_irq_save(flags); | |
38 | reg = __raw_readl(S3C64XX_GPNCON); | |
39 | reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | | |
40 | S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)); | |
41 | reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | | |
42 | S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15); | |
43 | __raw_writel(reg, S3C64XX_GPNCON); | |
44 | ||
45 | reg = __raw_readl(S3C64XX_GPNDAT); | |
46 | reg &= ~(clear << 12); | |
47 | reg |= set << 12; | |
48 | __raw_writel(reg, S3C64XX_GPNDAT); | |
49 | ||
50 | local_irq_restore(flags); | |
51 | } | |
52 | #endif | |
53 | ||
54 | static struct sleep_save core_save[] = { | |
55 | SAVE_ITEM(S3C_APLL_LOCK), | |
56 | SAVE_ITEM(S3C_MPLL_LOCK), | |
57 | SAVE_ITEM(S3C_EPLL_LOCK), | |
58 | SAVE_ITEM(S3C_CLK_SRC), | |
59 | SAVE_ITEM(S3C_CLK_DIV0), | |
60 | SAVE_ITEM(S3C_CLK_DIV1), | |
61 | SAVE_ITEM(S3C_CLK_DIV2), | |
62 | SAVE_ITEM(S3C_CLK_OUT), | |
63 | SAVE_ITEM(S3C_HCLK_GATE), | |
64 | SAVE_ITEM(S3C_PCLK_GATE), | |
65 | SAVE_ITEM(S3C_SCLK_GATE), | |
66 | SAVE_ITEM(S3C_MEM0_GATE), | |
67 | ||
68 | SAVE_ITEM(S3C_EPLL_CON1), | |
69 | SAVE_ITEM(S3C_EPLL_CON0), | |
70 | ||
71 | SAVE_ITEM(S3C64XX_MEM0DRVCON), | |
72 | SAVE_ITEM(S3C64XX_MEM1DRVCON), | |
73 | ||
74 | #ifndef CONFIG_CPU_FREQ | |
75 | SAVE_ITEM(S3C_APLL_CON), | |
76 | SAVE_ITEM(S3C_MPLL_CON), | |
77 | #endif | |
78 | }; | |
79 | ||
80 | static struct sleep_save misc_save[] = { | |
81 | SAVE_ITEM(S3C64XX_AHB_CON0), | |
82 | SAVE_ITEM(S3C64XX_AHB_CON1), | |
83 | SAVE_ITEM(S3C64XX_AHB_CON2), | |
84 | ||
85 | SAVE_ITEM(S3C64XX_SPCON), | |
86 | ||
87 | SAVE_ITEM(S3C64XX_MEM0CONSTOP), | |
88 | SAVE_ITEM(S3C64XX_MEM1CONSTOP), | |
89 | SAVE_ITEM(S3C64XX_MEM0CONSLP0), | |
90 | SAVE_ITEM(S3C64XX_MEM0CONSLP1), | |
91 | SAVE_ITEM(S3C64XX_MEM1CONSLP), | |
92 | }; | |
93 | ||
94 | void s3c_pm_configure_extint(void) | |
95 | { | |
96 | __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK); | |
97 | } | |
98 | ||
bd117bd1 BD |
99 | void s3c_pm_restore_core(void) |
100 | { | |
101 | __raw_writel(0, S3C64XX_EINT_MASK); | |
102 | ||
103 | s3c_pm_debug_smdkled(1 << 2, 0); | |
104 | ||
105 | s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); | |
106 | s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); | |
107 | } | |
108 | ||
109 | void s3c_pm_save_core(void) | |
110 | { | |
111 | s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); | |
112 | s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); | |
113 | } | |
114 | ||
115 | /* since both s3c6400 and s3c6410 share the same sleep pm calls, we | |
116 | * put the per-cpu code in here until any new cpu comes along and changes | |
117 | * this. | |
118 | */ | |
119 | ||
bd117bd1 BD |
120 | static void s3c64xx_cpu_suspend(void) |
121 | { | |
122 | unsigned long tmp; | |
123 | ||
124 | /* set our standby method to sleep */ | |
125 | ||
126 | tmp = __raw_readl(S3C64XX_PWR_CFG); | |
127 | tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK; | |
128 | tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP; | |
129 | __raw_writel(tmp, S3C64XX_PWR_CFG); | |
130 | ||
131 | /* clear any old wakeup */ | |
132 | ||
133 | __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), | |
134 | S3C64XX_WAKEUP_STAT); | |
135 | ||
136 | /* set the LED state to 0110 over sleep */ | |
137 | s3c_pm_debug_smdkled(3 << 1, 0xf); | |
138 | ||
139 | /* issue the standby signal into the pm unit. Note, we | |
140 | * issue a write-buffer drain just in case */ | |
141 | ||
142 | tmp = 0; | |
143 | ||
144 | asm("b 1f\n\t" | |
145 | ".align 5\n\t" | |
146 | "1:\n\t" | |
147 | "mcr p15, 0, %0, c7, c10, 5\n\t" | |
148 | "mcr p15, 0, %0, c7, c10, 4\n\t" | |
149 | "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); | |
150 | ||
151 | /* we should never get past here */ | |
152 | ||
153 | panic("sleep resumed to originator?"); | |
154 | } | |
155 | ||
156 | static void s3c64xx_pm_prepare(void) | |
157 | { | |
158 | /* store address of resume. */ | |
159 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0); | |
160 | ||
161 | /* ensure previous wakeup state is cleared before sleeping */ | |
162 | __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT); | |
163 | } | |
164 | ||
165 | static int s3c64xx_pm_init(void) | |
166 | { | |
167 | pm_cpu_prep = s3c64xx_pm_prepare; | |
168 | pm_cpu_sleep = s3c64xx_cpu_suspend; | |
169 | pm_uart_udivslot = 1; | |
170 | return 0; | |
171 | } | |
172 | ||
173 | arch_initcall(s3c64xx_pm_init); |