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adbefaa5 BD |
1 | /* linux/arch/arm/plat-s3c24xx/clock.c |
2 | * | |
50f430e3 | 3 | * Copyright 2004-2005 Simtec Electronics |
adbefaa5 BD |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C24XX Core clock control support | |
7 | * | |
8 | * Based on, and code from linux/arch/arm/mach-versatile/clock.c | |
9 | ** | |
10 | ** Copyright (C) 2004 ARM Limited. | |
11 | ** Written by Deep Blue Solutions Limited. | |
12 | * | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/err.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/sysdev.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/clk.h> | |
40 | #include <linux/spinlock.h> | |
adbefaa5 BD |
41 | #include <linux/io.h> |
42 | ||
43 | #include <mach/hardware.h> | |
44 | #include <asm/irq.h> | |
45 | ||
46 | #include <plat/cpu-freq.h> | |
47 | ||
48 | #include <plat/clock.h> | |
49 | #include <plat/cpu.h> | |
50 | ||
51 | /* clock information */ | |
52 | ||
53 | static LIST_HEAD(clocks); | |
54 | ||
55 | /* We originally used an mutex here, but some contexts (see resume) | |
56 | * are calling functions such as clk_set_parent() with IRQs disabled | |
57 | * causing an BUG to be triggered. | |
58 | */ | |
59 | DEFINE_SPINLOCK(clocks_lock); | |
60 | ||
61 | /* enable and disable calls for use with the clk struct */ | |
62 | ||
63 | static int clk_null_enable(struct clk *clk, int enable) | |
64 | { | |
65 | return 0; | |
66 | } | |
67 | ||
68 | /* Clock API calls */ | |
69 | ||
70 | struct clk *clk_get(struct device *dev, const char *id) | |
71 | { | |
72 | struct clk *p; | |
73 | struct clk *clk = ERR_PTR(-ENOENT); | |
74 | int idno; | |
75 | ||
76 | if (dev == NULL || dev->bus != &platform_bus_type) | |
77 | idno = -1; | |
78 | else | |
79 | idno = to_platform_device(dev)->id; | |
80 | ||
81 | spin_lock(&clocks_lock); | |
82 | ||
83 | list_for_each_entry(p, &clocks, list) { | |
84 | if (p->id == idno && | |
85 | strcmp(id, p->name) == 0 && | |
86 | try_module_get(p->owner)) { | |
87 | clk = p; | |
88 | break; | |
89 | } | |
90 | } | |
91 | ||
92 | /* check for the case where a device was supplied, but the | |
93 | * clock that was being searched for is not device specific */ | |
94 | ||
95 | if (IS_ERR(clk)) { | |
96 | list_for_each_entry(p, &clocks, list) { | |
97 | if (p->id == -1 && strcmp(id, p->name) == 0 && | |
98 | try_module_get(p->owner)) { | |
99 | clk = p; | |
100 | break; | |
101 | } | |
102 | } | |
103 | } | |
104 | ||
105 | spin_unlock(&clocks_lock); | |
106 | return clk; | |
107 | } | |
108 | ||
109 | void clk_put(struct clk *clk) | |
110 | { | |
111 | module_put(clk->owner); | |
112 | } | |
113 | ||
114 | int clk_enable(struct clk *clk) | |
115 | { | |
116 | if (IS_ERR(clk) || clk == NULL) | |
117 | return -EINVAL; | |
118 | ||
119 | clk_enable(clk->parent); | |
120 | ||
121 | spin_lock(&clocks_lock); | |
122 | ||
123 | if ((clk->usage++) == 0) | |
124 | (clk->enable)(clk, 1); | |
125 | ||
126 | spin_unlock(&clocks_lock); | |
127 | return 0; | |
128 | } | |
129 | ||
130 | void clk_disable(struct clk *clk) | |
131 | { | |
132 | if (IS_ERR(clk) || clk == NULL) | |
133 | return; | |
134 | ||
135 | spin_lock(&clocks_lock); | |
136 | ||
137 | if ((--clk->usage) == 0) | |
138 | (clk->enable)(clk, 0); | |
139 | ||
140 | spin_unlock(&clocks_lock); | |
141 | clk_disable(clk->parent); | |
142 | } | |
143 | ||
144 | ||
145 | unsigned long clk_get_rate(struct clk *clk) | |
146 | { | |
147 | if (IS_ERR(clk)) | |
148 | return 0; | |
149 | ||
150 | if (clk->rate != 0) | |
151 | return clk->rate; | |
152 | ||
b3bf41be BD |
153 | if (clk->ops != NULL && clk->ops->get_rate != NULL) |
154 | return (clk->ops->get_rate)(clk); | |
adbefaa5 BD |
155 | |
156 | if (clk->parent != NULL) | |
157 | return clk_get_rate(clk->parent); | |
158 | ||
159 | return clk->rate; | |
160 | } | |
161 | ||
162 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
163 | { | |
b3bf41be BD |
164 | if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate) |
165 | return (clk->ops->round_rate)(clk, rate); | |
adbefaa5 BD |
166 | |
167 | return rate; | |
168 | } | |
169 | ||
170 | int clk_set_rate(struct clk *clk, unsigned long rate) | |
171 | { | |
172 | int ret; | |
173 | ||
174 | if (IS_ERR(clk)) | |
175 | return -EINVAL; | |
176 | ||
177 | /* We do not default just do a clk->rate = rate as | |
178 | * the clock may have been made this way by choice. | |
179 | */ | |
180 | ||
b3bf41be BD |
181 | WARN_ON(clk->ops == NULL); |
182 | WARN_ON(clk->ops && clk->ops->set_rate == NULL); | |
adbefaa5 | 183 | |
b3bf41be | 184 | if (clk->ops == NULL || clk->ops->set_rate == NULL) |
adbefaa5 BD |
185 | return -EINVAL; |
186 | ||
187 | spin_lock(&clocks_lock); | |
b3bf41be | 188 | ret = (clk->ops->set_rate)(clk, rate); |
adbefaa5 BD |
189 | spin_unlock(&clocks_lock); |
190 | ||
191 | return ret; | |
192 | } | |
193 | ||
194 | struct clk *clk_get_parent(struct clk *clk) | |
195 | { | |
196 | return clk->parent; | |
197 | } | |
198 | ||
199 | int clk_set_parent(struct clk *clk, struct clk *parent) | |
200 | { | |
201 | int ret = 0; | |
202 | ||
203 | if (IS_ERR(clk)) | |
204 | return -EINVAL; | |
205 | ||
206 | spin_lock(&clocks_lock); | |
207 | ||
b3bf41be BD |
208 | if (clk->ops && clk->ops->set_parent) |
209 | ret = (clk->ops->set_parent)(clk, parent); | |
adbefaa5 BD |
210 | |
211 | spin_unlock(&clocks_lock); | |
212 | ||
213 | return ret; | |
214 | } | |
215 | ||
216 | EXPORT_SYMBOL(clk_get); | |
217 | EXPORT_SYMBOL(clk_put); | |
218 | EXPORT_SYMBOL(clk_enable); | |
219 | EXPORT_SYMBOL(clk_disable); | |
220 | EXPORT_SYMBOL(clk_get_rate); | |
221 | EXPORT_SYMBOL(clk_round_rate); | |
222 | EXPORT_SYMBOL(clk_set_rate); | |
223 | EXPORT_SYMBOL(clk_get_parent); | |
224 | EXPORT_SYMBOL(clk_set_parent); | |
225 | ||
226 | /* base clocks */ | |
227 | ||
ed276849 | 228 | int clk_default_setrate(struct clk *clk, unsigned long rate) |
adbefaa5 BD |
229 | { |
230 | clk->rate = rate; | |
231 | return 0; | |
232 | } | |
233 | ||
ed276849 | 234 | struct clk_ops clk_ops_def_setrate = { |
b3bf41be BD |
235 | .set_rate = clk_default_setrate, |
236 | }; | |
237 | ||
adbefaa5 BD |
238 | struct clk clk_xtal = { |
239 | .name = "xtal", | |
240 | .id = -1, | |
241 | .rate = 0, | |
242 | .parent = NULL, | |
243 | .ctrlbit = 0, | |
244 | }; | |
245 | ||
4b31d8b2 BD |
246 | struct clk clk_ext = { |
247 | .name = "ext", | |
248 | .id = -1, | |
249 | }; | |
250 | ||
251 | struct clk clk_epll = { | |
252 | .name = "epll", | |
253 | .id = -1, | |
254 | }; | |
255 | ||
adbefaa5 BD |
256 | struct clk clk_mpll = { |
257 | .name = "mpll", | |
258 | .id = -1, | |
b3bf41be | 259 | .ops = &clk_ops_def_setrate, |
adbefaa5 BD |
260 | }; |
261 | ||
262 | struct clk clk_upll = { | |
263 | .name = "upll", | |
264 | .id = -1, | |
265 | .parent = NULL, | |
266 | .ctrlbit = 0, | |
267 | }; | |
268 | ||
269 | struct clk clk_f = { | |
270 | .name = "fclk", | |
271 | .id = -1, | |
272 | .rate = 0, | |
273 | .parent = &clk_mpll, | |
274 | .ctrlbit = 0, | |
adbefaa5 BD |
275 | }; |
276 | ||
277 | struct clk clk_h = { | |
278 | .name = "hclk", | |
279 | .id = -1, | |
280 | .rate = 0, | |
281 | .parent = NULL, | |
282 | .ctrlbit = 0, | |
b3bf41be | 283 | .ops = &clk_ops_def_setrate, |
adbefaa5 BD |
284 | }; |
285 | ||
286 | struct clk clk_p = { | |
287 | .name = "pclk", | |
288 | .id = -1, | |
289 | .rate = 0, | |
290 | .parent = NULL, | |
291 | .ctrlbit = 0, | |
b3bf41be | 292 | .ops = &clk_ops_def_setrate, |
adbefaa5 BD |
293 | }; |
294 | ||
295 | struct clk clk_usb_bus = { | |
296 | .name = "usb-bus", | |
297 | .id = -1, | |
298 | .rate = 0, | |
299 | .parent = &clk_upll, | |
300 | }; | |
301 | ||
302 | ||
adbefaa5 BD |
303 | struct clk s3c24xx_uclk = { |
304 | .name = "uclk", | |
305 | .id = -1, | |
306 | }; | |
307 | ||
308 | /* initialise the clock system */ | |
309 | ||
8428d47a BD |
310 | /** |
311 | * s3c24xx_register_clock() - register a clock | |
312 | * @clk: The clock to register | |
313 | * | |
314 | * Add the specified clock to the list of clocks known by the system. | |
315 | */ | |
adbefaa5 BD |
316 | int s3c24xx_register_clock(struct clk *clk) |
317 | { | |
adbefaa5 BD |
318 | if (clk->enable == NULL) |
319 | clk->enable = clk_null_enable; | |
320 | ||
321 | /* add to the list of available clocks */ | |
322 | ||
cec444b7 BD |
323 | /* Quick check to see if this clock has already been registered. */ |
324 | BUG_ON(clk->list.prev != clk->list.next); | |
325 | ||
adbefaa5 BD |
326 | spin_lock(&clocks_lock); |
327 | list_add(&clk->list, &clocks); | |
328 | spin_unlock(&clocks_lock); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
8428d47a BD |
333 | /** |
334 | * s3c24xx_register_clocks() - register an array of clock pointers | |
335 | * @clks: Pointer to an array of struct clk pointers | |
336 | * @nr_clks: The number of clocks in the @clks array. | |
337 | * | |
338 | * Call s3c24xx_register_clock() for all the clock pointers contained | |
339 | * in the @clks list. Returns the number of failures. | |
340 | */ | |
adbefaa5 BD |
341 | int s3c24xx_register_clocks(struct clk **clks, int nr_clks) |
342 | { | |
343 | int fails = 0; | |
344 | ||
345 | for (; nr_clks > 0; nr_clks--, clks++) { | |
50ee2d35 BD |
346 | if (s3c24xx_register_clock(*clks) < 0) { |
347 | struct clk *clk = *clks; | |
348 | printk(KERN_ERR "%s: failed to register %p: %s\n", | |
349 | __func__, clk, clk->name); | |
adbefaa5 | 350 | fails++; |
50ee2d35 | 351 | } |
adbefaa5 BD |
352 | } |
353 | ||
354 | return fails; | |
355 | } | |
356 | ||
1d9f13c4 BD |
357 | /** |
358 | * s3c_register_clocks() - register an array of clocks | |
359 | * @clkp: Pointer to the first clock in the array. | |
360 | * @nr_clks: Number of clocks to register. | |
361 | * | |
362 | * Call s3c24xx_register_clock() on the @clkp array given, printing an | |
363 | * error if it fails to register the clock (unlikely). | |
364 | */ | |
ab5d97db | 365 | void __init s3c_register_clocks(struct clk *clkp, int nr_clks) |
1d9f13c4 BD |
366 | { |
367 | int ret; | |
368 | ||
369 | for (; nr_clks > 0; nr_clks--, clkp++) { | |
370 | ret = s3c24xx_register_clock(clkp); | |
371 | ||
372 | if (ret < 0) { | |
373 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | |
374 | clkp->name, ret); | |
375 | } | |
376 | } | |
377 | } | |
378 | ||
4e04691b BD |
379 | /** |
380 | * s3c_disable_clocks() - disable an array of clocks | |
381 | * @clkp: Pointer to the first clock in the array. | |
382 | * @nr_clks: Number of clocks to register. | |
383 | * | |
384 | * for internal use only at initialisation time. disable the clocks in the | |
385 | * @clkp array. | |
386 | */ | |
387 | ||
388 | void __init s3c_disable_clocks(struct clk *clkp, int nr_clks) | |
389 | { | |
390 | for (; nr_clks > 0; nr_clks--, clkp++) | |
391 | (clkp->enable)(clkp, 0); | |
392 | } | |
393 | ||
421f91d2 | 394 | /* initialise all the clocks */ |
adbefaa5 BD |
395 | |
396 | int __init s3c24xx_register_baseclocks(unsigned long xtal) | |
397 | { | |
50f430e3 | 398 | printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n"); |
adbefaa5 BD |
399 | |
400 | clk_xtal.rate = xtal; | |
401 | ||
402 | /* register our clocks */ | |
403 | ||
404 | if (s3c24xx_register_clock(&clk_xtal) < 0) | |
405 | printk(KERN_ERR "failed to register master xtal\n"); | |
406 | ||
407 | if (s3c24xx_register_clock(&clk_mpll) < 0) | |
408 | printk(KERN_ERR "failed to register mpll clock\n"); | |
409 | ||
410 | if (s3c24xx_register_clock(&clk_upll) < 0) | |
411 | printk(KERN_ERR "failed to register upll clock\n"); | |
412 | ||
413 | if (s3c24xx_register_clock(&clk_f) < 0) | |
414 | printk(KERN_ERR "failed to register cpu fclk\n"); | |
415 | ||
416 | if (s3c24xx_register_clock(&clk_h) < 0) | |
417 | printk(KERN_ERR "failed to register cpu hclk\n"); | |
418 | ||
419 | if (s3c24xx_register_clock(&clk_p) < 0) | |
420 | printk(KERN_ERR "failed to register cpu pclk\n"); | |
421 | ||
422 | return 0; | |
423 | } | |
424 |