[mirror_ubuntu-eoan-kernel.git] / arch / arm / vfp / vfphw.S

/*
 *  linux/arch/arm/vfp/vfphw.S
 *
 *  Copyright (C) 2004 ARM Limited.
 *  Written by Deep Blue Solutions Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This code is called from the kernel's undefined instruction trap.
 * r9 holds the return address for successful handling.
 * lr holds the return address for unrecognised instructions.
 * r10 points at the start of the private FP workspace in the thread structure
 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
 */
#include <asm/thread_info.h>
#include <asm/vfpmacros.h>
#include "../kernel/entry-header.S"

	.macro	DBGSTR, str
#ifdef DEBUG
	stmfd	sp!, {r0-r3, ip, lr}
	add	r0, pc, #4
	bl	printk
	b	1f
	.asciz  "<7>VFP: \str\n"
	.balign 4
1:	ldmfd	sp!, {r0-r3, ip, lr}
#endif
	.endm

	.macro  DBGSTR1, str, arg
#ifdef DEBUG
	stmfd	sp!, {r0-r3, ip, lr}
	mov	r1, \arg
	add	r0, pc, #4
	bl	printk
	b	1f
	.asciz  "<7>VFP: \str\n"
	.balign 4
1:	ldmfd	sp!, {r0-r3, ip, lr}
#endif
	.endm

	.macro  DBGSTR3, str, arg1, arg2, arg3
#ifdef DEBUG
	stmfd	sp!, {r0-r3, ip, lr}
	mov	r3, \arg3
	mov	r2, \arg2
	mov	r1, \arg1
	add	r0, pc, #4
	bl	printk
	b	1f
	.asciz  "<7>VFP: \str\n"
	.balign 4
1:	ldmfd	sp!, {r0-r3, ip, lr}
#endif
	.endm


@ VFP hardware support entry point.
@
@  r0  = faulted instruction
@  r2  = faulted PC+4
@  r9  = successful return
@  r10 = vfp_state union
@  r11 = CPU number
@  lr  = failure return

ENTRY(vfp_support_entry)
	DBGSTR3	"instr %08x pc %08x state %p", r0, r2, r10

	VFPFMRX	r1, FPEXC		@ Is the VFP enabled?
	DBGSTR1	"fpexc %08x", r1
	tst	r1, #FPEXC_EN
	bne	look_for_VFP_exceptions	@ VFP is already enabled

	DBGSTR1 "enable %x", r10
	ldr	r3, last_VFP_context_address
	orr	r1, r1, #FPEXC_EN	@ user FPEXC has the enable bit set
	ldr	r4, [r3, r11, lsl #2]	@ last_VFP_context pointer
	bic	r5, r1, #FPEXC_EX	@ make sure exceptions are disabled
	cmp	r4, r10
	beq	check_for_exception	@ we are returning to the same
					@ process, so the registers are
					@ still there.  In this case, we do
					@ not want to drop a pending exception.

	VFPFMXR	FPEXC, r5		@ enable VFP, disable any pending
					@ exceptions, so we can get at the
					@ rest of it

#ifndef CONFIG_SMP
	@ Save out the current registers to the old thread state
	@ No need for SMP since this is not done lazily

	DBGSTR1	"save old state %p", r4
	cmp	r4, #0
	beq	no_old_VFP_process
	VFPFSTMIA r4, r5		@ save the working registers
	VFPFMRX	r5, FPSCR		@ current status
	tst	r1, #FPEXC_EX		@ is there additional state to save?
	beq	1f
	VFPFMRX	r6, FPINST		@ FPINST (only if FPEXC.EX is set)
	tst	r1, #FPEXC_FP2V		@ is there an FPINST2 to read?
	beq	1f
	VFPFMRX	r8, FPINST2		@ FPINST2 if needed (and present)
1:
	stmia	r4, {r1, r5, r6, r8}	@ save FPEXC, FPSCR, FPINST, FPINST2
					@ and point r4 at the word at the
					@ start of the register dump
#endif

no_old_VFP_process:
	DBGSTR1	"load state %p", r10
	str	r10, [r3, r11, lsl #2]	@ update the last_VFP_context pointer
					@ Load the saved state back into the VFP
	VFPFLDMIA r10, r5		@ reload the working registers while
					@ FPEXC is in a safe state
	ldmia	r10, {r1, r5, r6, r8}	@ load FPEXC, FPSCR, FPINST, FPINST2
	tst	r1, #FPEXC_EX		@ is there additional state to restore?
	beq	1f
	VFPFMXR	FPINST, r6		@ restore FPINST (only if FPEXC.EX is set)
	tst	r1, #FPEXC_FP2V		@ is there an FPINST2 to write?
	beq	1f
	VFPFMXR	FPINST2, r8		@ FPINST2 if needed (and present)
1:
	VFPFMXR	FPSCR, r5		@ restore status

check_for_exception:
	tst	r1, #FPEXC_EX
	bne	process_exception	@ might as well handle the pending
					@ exception before retrying branch
					@ out before setting an FPEXC that
					@ stops us reading stuff
	VFPFMXR	FPEXC, r1		@ restore FPEXC last
	sub	r2, r2, #4
	str	r2, [sp, #S_PC]		@ retry the instruction
	mov	pc, r9			@ we think we have handled things


look_for_VFP_exceptions:
	@ Check for synchronous or asynchronous exception
	tst	r1, #FPEXC_EX | FPEXC_DEX
	bne	process_exception
	@ On some implementations of the VFP subarch 1, setting FPSCR.IXE
	@ causes all the CDP instructions to be bounced synchronously without
	@ setting the FPEXC.EX bit
	VFPFMRX	r5, FPSCR
	tst	r5, #FPSCR_IXE
	bne	process_exception

	@ Fall into hand on to next handler - appropriate coproc instr
	@ not recognised by VFP

	DBGSTR	"not VFP"
	mov	pc, lr

process_exception:
	DBGSTR	"bounce"
	mov	r2, sp			@ nothing stacked - regdump is at TOS
	mov	lr, r9			@ setup for a return to the user code.

	@ Now call the C code to package up the bounce to the support code
	@   r0 holds the trigger instruction
	@   r1 holds the FPEXC value
	@   r2 pointer to register dump
	b	VFP_bounce		@ we have handled this - the support
					@ code will raise an exception if
					@ required. If not, the user code will
					@ retry the faulted instruction
ENDPROC(vfp_support_entry)

#ifdef CONFIG_SMP
ENTRY(vfp_save_state)
	@ Save the current VFP state
	@ r0 - save location
	@ r1 - FPEXC
	DBGSTR1	"save VFP state %p", r0
	VFPFSTMIA r0, r2		@ save the working registers
	VFPFMRX	r2, FPSCR		@ current status
	tst	r1, #FPEXC_EX		@ is there additional state to save?
	beq	1f
	VFPFMRX	r3, FPINST		@ FPINST (only if FPEXC.EX is set)
	tst	r1, #FPEXC_FP2V		@ is there an FPINST2 to read?
	beq	1f
	VFPFMRX	r12, FPINST2		@ FPINST2 if needed (and present)
1:
	stmia	r0, {r1, r2, r3, r12}	@ save FPEXC, FPSCR, FPINST, FPINST2
	mov	pc, lr
ENDPROC(vfp_save_state)
#endif

last_VFP_context_address:
	.word	last_VFP_context

ENTRY(vfp_get_float)
	add	pc, pc, r0, lsl #3
	mov	r0, r0
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
	mrc	p10, 0, r0, c\dr, c0, 0	@ fmrs	r0, s0
	mov	pc, lr
	mrc	p10, 0, r0, c\dr, c0, 4	@ fmrs	r0, s1
	mov	pc, lr
	.endr
ENDPROC(vfp_get_float)

ENTRY(vfp_put_float)
	add	pc, pc, r1, lsl #3
	mov	r0, r0
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
	mcr	p10, 0, r0, c\dr, c0, 0	@ fmsr	r0, s0
	mov	pc, lr
	mcr	p10, 0, r0, c\dr, c0, 4	@ fmsr	r0, s1
	mov	pc, lr
	.endr
ENDPROC(vfp_put_float)

ENTRY(vfp_get_double)
	add	pc, pc, r0, lsl #3
	mov	r0, r0
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
	fmrrd	r0, r1, d\dr
	mov	pc, lr
	.endr
#ifdef CONFIG_VFPv3
	@ d16 - d31 registers
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
	mrrc	p11, 3, r0, r1, c\dr	@ fmrrd	r0, r1, d\dr
	mov	pc, lr
	.endr
#endif

	@ virtual register 16 (or 32 if VFPv3) for compare with zero
	mov	r0, #0
	mov	r1, #0
	mov	pc, lr
ENDPROC(vfp_get_double)

ENTRY(vfp_put_double)
	add	pc, pc, r2, lsl #3
	mov	r0, r0
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
	fmdrr	d\dr, r0, r1
	mov	pc, lr
	.endr
#ifdef CONFIG_VFPv3
	@ d16 - d31 registers
	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
	mcrr	p11, 3, r1, r2, c\dr	@ fmdrr	r1, r2, d\dr
	mov	pc, lr
	.endr
#endif
ENDPROC(vfp_put_double)
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/vfp/vfphw.S
	3	*
	4	* Copyright (C) 2004 ARM Limited.
	5	* Written by Deep Blue Solutions Limited.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This code is called from the kernel's undefined instruction trap.
	12	* r9 holds the return address for successful handling.
	13	* lr holds the return address for unrecognised instructions.
	14	* r10 points at the start of the private FP workspace in the thread structure
	15	* sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
	16	*/
	17	#include <asm/thread_info.h>
	18	#include <asm/vfpmacros.h>
	19	#include "../kernel/entry-header.S"
	20
	21	.macro DBGSTR, str
	22	#ifdef DEBUG
	23	stmfd sp!, {r0-r3, ip, lr}
	24	add r0, pc, #4
	25	bl printk
	26	b 1f
	27	.asciz "<7>VFP: \str\n"
	28	.balign 4
	29	1: ldmfd sp!, {r0-r3, ip, lr}
	30	#endif
	31	.endm
	32
	33	.macro DBGSTR1, str, arg
	34	#ifdef DEBUG
	35	stmfd sp!, {r0-r3, ip, lr}
	36	mov r1, \arg
	37	add r0, pc, #4
	38	bl printk
	39	b 1f
	40	.asciz "<7>VFP: \str\n"
	41	.balign 4
	42	1: ldmfd sp!, {r0-r3, ip, lr}
	43	#endif
	44	.endm
	45
	46	.macro DBGSTR3, str, arg1, arg2, arg3
	47	#ifdef DEBUG
	48	stmfd sp!, {r0-r3, ip, lr}
	49	mov r3, \arg3
	50	mov r2, \arg2
	51	mov r1, \arg1
	52	add r0, pc, #4
	53	bl printk
	54	b 1f
	55	.asciz "<7>VFP: \str\n"
	56	.balign 4
	57	1: ldmfd sp!, {r0-r3, ip, lr}
	58	#endif
	59	.endm
	60
	61
	62	@ VFP hardware support entry point.
	63	@
	64	@ r0 = faulted instruction
65	@ r2 = faulted PC+4
66	@ r9 = successful return
67	@ r10 = vfp_state union
c6428464	68	@ r11 = CPU number
1da177e4 LT	69	@ lr = failure return
1da177e4 LT	70
93ed3970	71	ENTRY(vfp_support_entry)
1da177e4 LT	72	DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
	73
	74	VFPFMRX r1, FPEXC @ Is the VFP enabled?
	75	DBGSTR1 "fpexc %08x", r1
228adef1	76	tst r1, #FPEXC_EN
1da177e4 LT	77	bne look_for_VFP_exceptions @ VFP is already enabled
	78
	79	DBGSTR1 "enable %x", r10
	80	ldr r3, last_VFP_context_address
228adef1	81	orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set
c6428464	82	ldr r4, [r3, r11, lsl #2] @ last_VFP_context pointer
228adef1	83	bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled
1da177e4 LT	84	cmp r4, r10
	85	beq check_for_exception @ we are returning to the same
	86	@ process, so the registers are
	87	@ still there. In this case, we do
	88	@ not want to drop a pending exception.
	89
	90	VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
	91	@ exceptions, so we can get at the
	92	@ rest of it
	93
c6428464	94	#ifndef CONFIG_SMP
1da177e4	95	@ Save out the current registers to the old thread state
c6428464	96	@ No need for SMP since this is not done lazily
1da177e4 LT	97
	98	DBGSTR1 "save old state %p", r4
	99	cmp r4, #0
	100	beq no_old_VFP_process
25ebee02	101	VFPFSTMIA r4, r5 @ save the working registers
1da177e4	102	VFPFMRX r5, FPSCR @ current status
c98929c0	103	tst r1, #FPEXC_EX @ is there additional state to save?
24b647a0 CM	104	beq 1f
	105	VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
	106	tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
	107	beq 1f
	108	VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
	109	1:
1da177e4 LT	110	stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
	111	@ and point r4 at the word at the
	112	@ start of the register dump
c6428464	113	#endif
1da177e4 LT	114
	115	no_old_VFP_process:
	116	DBGSTR1 "load state %p", r10
c6428464	117	str r10, [r3, r11, lsl #2] @ update the last_VFP_context pointer
1da177e4	118	@ Load the saved state back into the VFP
25ebee02	119	VFPFLDMIA r10, r5 @ reload the working registers while
1da177e4	120	@ FPEXC is in a safe state
80ed3547	121	ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
c98929c0	122	tst r1, #FPEXC_EX @ is there additional state to restore?
24b647a0 CM	123	beq 1f
	124	VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
	125	tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
	126	beq 1f
	127	VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
	128	1:
1da177e4 LT	129	VFPFMXR FPSCR, r5 @ restore status
	130
	131	check_for_exception:
228adef1	132	tst r1, #FPEXC_EX
1da177e4 LT	133	bne process_exception @ might as well handle the pending
	134	@ exception before retrying branch
	135	@ out before setting an FPEXC that
	136	@ stops us reading stuff
	137	VFPFMXR FPEXC, r1 @ restore FPEXC last
	138	sub r2, r2, #4
	139	str r2, [sp, #S_PC] @ retry the instruction
	140	mov pc, r9 @ we think we have handled things
	141
	142
	143	look_for_VFP_exceptions:
c98929c0 CM	144	@ Check for synchronous or asynchronous exception
c98929c0 CM	145	tst r1, #FPEXC_EX \| FPEXC_DEX
1da177e4	146	bne process_exception
c98929c0 CM	147	@ On some implementations of the VFP subarch 1, setting FPSCR.IXE
	148	@ causes all the CDP instructions to be bounced synchronously without
	149	@ setting the FPEXC.EX bit
1da177e4	150	VFPFMRX r5, FPSCR
c98929c0	151	tst r5, #FPSCR_IXE
1da177e4 LT	152	bne process_exception
	153
	154	@ Fall into hand on to next handler - appropriate coproc instr
	155	@ not recognised by VFP
	156
	157	DBGSTR "not VFP"
	158	mov pc, lr
	159
	160	process_exception:
	161	DBGSTR "bounce"
1da177e4 LT	162	mov r2, sp @ nothing stacked - regdump is at TOS
	163	mov lr, r9 @ setup for a return to the user code.
	164
	165	@ Now call the C code to package up the bounce to the support code
	166	@ r0 holds the trigger instruction
	167	@ r1 holds the FPEXC value
	168	@ r2 pointer to register dump
c98929c0	169	b VFP_bounce @ we have handled this - the support
1da177e4 LT	170	@ code will raise an exception if
	171	@ required. If not, the user code will
	172	@ retry the faulted instruction
93ed3970	173	ENDPROC(vfp_support_entry)
1da177e4	174
c6428464	175	#ifdef CONFIG_SMP
93ed3970	176	ENTRY(vfp_save_state)
c6428464 CM	177	@ Save the current VFP state
	178	@ r0 - save location
	179	@ r1 - FPEXC
	180	DBGSTR1 "save VFP state %p", r0
25ebee02	181	VFPFSTMIA r0, r2 @ save the working registers
c6428464	182	VFPFMRX r2, FPSCR @ current status
c98929c0	183	tst r1, #FPEXC_EX @ is there additional state to save?
24b647a0 CM	184	beq 1f
	185	VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
	186	tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
	187	beq 1f
	188	VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
	189	1:
c6428464 CM	190	stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
c6428464 CM	191	mov pc, lr
93ed3970	192	ENDPROC(vfp_save_state)
c6428464 CM	193	#endif
c6428464 CM	194
1da177e4 LT	195	last_VFP_context_address:
	196	.word last_VFP_context
	197
93ed3970	198	ENTRY(vfp_get_float)
1da177e4 LT	199	add pc, pc, r0, lsl #3
	200	mov r0, r0
	201	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
	202	mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
	203	mov pc, lr
	204	mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
	205	mov pc, lr
	206	.endr
93ed3970	207	ENDPROC(vfp_get_float)
1da177e4	208
93ed3970	209	ENTRY(vfp_put_float)
0355b3e0	210	add pc, pc, r1, lsl #3
1da177e4 LT	211	mov r0, r0
1da177e4 LT	212	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
0355b3e0	213	mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0
1da177e4	214	mov pc, lr
0355b3e0	215	mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
1da177e4 LT	216	mov pc, lr
1da177e4 LT	217	.endr
93ed3970	218	ENDPROC(vfp_put_float)
1da177e4	219
93ed3970	220	ENTRY(vfp_get_double)
1da177e4 LT	221	add pc, pc, r0, lsl #3
	222	mov r0, r0
	223	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1a6be26d	224	fmrrd r0, r1, d\dr
1da177e4 LT	225	mov pc, lr
1da177e4 LT	226	.endr
25ebee02 CM	227	#ifdef CONFIG_VFPv3
	228	@ d16 - d31 registers
	229	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
	230	mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
	231	mov pc, lr
	232	.endr
	233	#endif
1da177e4	234
25ebee02	235	@ virtual register 16 (or 32 if VFPv3) for compare with zero
1da177e4 LT	236	mov r0, #0
	237	mov r1, #0
	238	mov pc, lr
93ed3970	239	ENDPROC(vfp_get_double)
1da177e4	240
93ed3970	241	ENTRY(vfp_put_double)
0355b3e0	242	add pc, pc, r2, lsl #3
1da177e4 LT	243	mov r0, r0
1da177e4 LT	244	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
0355b3e0	245	fmdrr d\dr, r0, r1
1da177e4 LT	246	mov pc, lr
1da177e4 LT	247	.endr
25ebee02 CM	248	#ifdef CONFIG_VFPv3
	249	@ d16 - d31 registers
	250	.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
	251	mcrr p11, 3, r1, r2, c\dr @ fmdrr r1, r2, d\dr
	252	mov pc, lr
	253	.endr
	254	#endif
93ed3970	255	ENDPROC(vfp_put_double)