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Commit | Line | Data |
---|---|---|
8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
b6197b93 | 3 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 4 | select ACPI_GENERIC_GSI if ACPI |
5f1ae4eb | 5 | select ACPI_GTDT if ACPI |
c6bb8f89 | 6 | select ACPI_IORT if ACPI |
6933de0c | 7 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
0cb0786b | 8 | select ACPI_MCFG if ACPI |
888125a7 | 9 | select ACPI_SPCR_TABLE if ACPI |
40c802fe | 10 | select ACPI_PPTT if ACPI |
1d8f51d4 | 11 | select ARCH_CLOCKSOURCE_DATA |
ec6d06ef | 12 | select ARCH_HAS_DEBUG_VIRTUAL |
21266be9 | 13 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
38b04a74 | 14 | select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI |
2b68f6ca | 15 | select ARCH_HAS_ELF_RANDOMIZE |
6974f0c4 | 16 | select ARCH_HAS_FORTIFY_SOURCE |
957e3fac | 17 | select ARCH_HAS_GCOV_PROFILE_ALL |
e1073d1e | 18 | select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA |
5e4c7549 | 19 | select ARCH_HAS_KCOV |
d2852a22 | 20 | select ARCH_HAS_SET_MEMORY |
308c09f1 | 21 | select ARCH_HAS_SG_CHAIN |
ad21fc4f LA |
22 | select ARCH_HAS_STRICT_KERNEL_RWX |
23 | select ARCH_HAS_STRICT_MODULE_RWX | |
1f85008e | 24 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
396a5d4a | 25 | select ARCH_HAVE_NMI_SAFE_CMPXCHG |
087133ac WD |
26 | select ARCH_INLINE_READ_LOCK if !PREEMPT |
27 | select ARCH_INLINE_READ_LOCK_BH if !PREEMPT | |
28 | select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT | |
29 | select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT | |
30 | select ARCH_INLINE_READ_UNLOCK if !PREEMPT | |
31 | select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT | |
32 | select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT | |
33 | select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT | |
34 | select ARCH_INLINE_WRITE_LOCK if !PREEMPT | |
35 | select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT | |
36 | select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT | |
37 | select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT | |
38 | select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT | |
39 | select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT | |
40 | select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT | |
41 | select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT | |
c63c8700 | 42 | select ARCH_USE_CMPXCHG_LOCKREF |
087133ac | 43 | select ARCH_USE_QUEUED_RWLOCKS |
c484f256 | 44 | select ARCH_SUPPORTS_MEMORY_FAILURE |
4badad35 | 45 | select ARCH_SUPPORTS_ATOMIC_RMW |
56166230 | 46 | select ARCH_SUPPORTS_NUMA_BALANCING |
6212a512 | 47 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 48 | select ARCH_WANT_FRAME_POINTERS |
f0b7f8a4 | 49 | select ARCH_HAS_UBSAN_SANITIZE_ALL |
25c92a37 | 50 | select ARM_AMBA |
1aee5d7a | 51 | select ARM_ARCH_TIMER |
c4188edc | 52 | select ARM_GIC |
875cbf3e | 53 | select AUDIT_ARCH_COMPAT_GENERIC |
3ee80364 | 54 | select ARM_GIC_V2M if PCI |
021f6537 | 55 | select ARM_GIC_V3 |
3ee80364 | 56 | select ARM_GIC_V3_ITS if PCI |
bff60792 | 57 | select ARM_PSCI_FW |
adace895 | 58 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 59 | select CLONE_BACKWARDS |
7ca2ef33 | 60 | select COMMON_CLK |
166936ba | 61 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 62 | select DCACHE_WORD_ACCESS |
ef37566c | 63 | select EDAC_SUPPORT |
2f34f173 | 64 | select FRAME_POINTER |
d4932f9e | 65 | select GENERIC_ALLOCATOR |
2ef7a295 | 66 | select GENERIC_ARCH_TOPOLOGY |
8c2c3df3 | 67 | select GENERIC_CLOCKEVENTS |
4b3dc967 | 68 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 69 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 70 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 71 | select GENERIC_IDLE_POLL_SETUP |
8c2c3df3 CM |
72 | select GENERIC_IRQ_PROBE |
73 | select GENERIC_IRQ_SHOW | |
6544e67b | 74 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 75 | select GENERIC_PCI_IOMAP |
65cd4f6c | 76 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 77 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
78 | select GENERIC_STRNCPY_FROM_USER |
79 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 80 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 81 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 82 | select HARDIRQS_SW_RESEND |
9f9a35a7 | 83 | select HAVE_ACPI_APEI if (ACPI && EFI) |
5284e1b4 | 84 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 85 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 86 | select HAVE_ARCH_BITREVERSE |
324420bf | 87 | select HAVE_ARCH_HUGE_VMAP |
9732cafd | 88 | select HAVE_ARCH_JUMP_LABEL |
e17d8025 | 89 | select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) |
9529247d | 90 | select HAVE_ARCH_KGDB |
8f0d3aa9 DC |
91 | select HAVE_ARCH_MMAP_RND_BITS |
92 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT | |
a1ae65b2 | 93 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 94 | select HAVE_ARCH_TRACEHOOK |
8ee70879 | 95 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE |
e3067861 | 96 | select HAVE_ARCH_VMAP_STACK |
8ee70879 | 97 | select HAVE_ARM_SMCCC |
6077776b | 98 | select HAVE_EBPF_JIT |
af64d2aa | 99 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 100 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 101 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 102 | select HAVE_CMPXCHG_LOCAL |
8ee70879 | 103 | select HAVE_CONTEXT_TRACKING |
9b2a60c4 | 104 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 105 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 | 106 | select HAVE_DMA_API_DEBUG |
6ac2104d | 107 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 108 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 109 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 110 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
111 | select HAVE_FUNCTION_TRACER |
112 | select HAVE_FUNCTION_GRAPH_TRACER | |
6b90bd4b | 113 | select HAVE_GCC_PLUGINS |
8c2c3df3 | 114 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 115 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
24da208d | 116 | select HAVE_IRQ_TIME_ACCOUNTING |
8c2c3df3 | 117 | select HAVE_MEMBLOCK |
1a2db300 | 118 | select HAVE_MEMBLOCK_NODE_MAP if NUMA |
396a5d4a | 119 | select HAVE_NMI |
55834a77 | 120 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 121 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
122 | select HAVE_PERF_REGS |
123 | select HAVE_PERF_USER_STACK_DUMP | |
0a8ea52c | 124 | select HAVE_REGS_AND_STACK_ACCESS_API |
5e5f6dc1 | 125 | select HAVE_RCU_TABLE_FREE |
055b1212 | 126 | select HAVE_SYSCALL_TRACEPOINTS |
2dd0e8d2 | 127 | select HAVE_KPROBES |
cd1ee3b1 | 128 | select HAVE_KRETPROBES |
876945db | 129 | select IOMMU_DMA if IOMMU_SUPPORT |
8c2c3df3 | 130 | select IRQ_DOMAIN |
e8557d1f | 131 | select IRQ_FORCED_THREADING |
fea2acaa | 132 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
133 | select NO_BOOTMEM |
134 | select OF | |
135 | select OF_EARLY_FLATTREE | |
9bf14b7c | 136 | select OF_RESERVED_MEM |
0cb0786b | 137 | select PCI_ECAM if ACPI |
aa1e8ec1 CM |
138 | select POWER_RESET |
139 | select POWER_SUPPLY | |
4adcec11 | 140 | select REFCOUNT_FULL |
8c2c3df3 | 141 | select SPARSE_IRQ |
7ac57a89 | 142 | select SYSCTL_EXCEPTION_TRACE |
c02433dd | 143 | select THREAD_INFO_IN_TASK |
8c2c3df3 CM |
144 | help |
145 | ARM 64-bit (AArch64) Linux support. | |
146 | ||
147 | config 64BIT | |
148 | def_bool y | |
149 | ||
150 | config ARCH_PHYS_ADDR_T_64BIT | |
151 | def_bool y | |
152 | ||
153 | config MMU | |
154 | def_bool y | |
155 | ||
030c4d24 MR |
156 | config ARM64_PAGE_SHIFT |
157 | int | |
158 | default 16 if ARM64_64K_PAGES | |
159 | default 14 if ARM64_16K_PAGES | |
160 | default 12 | |
161 | ||
162 | config ARM64_CONT_SHIFT | |
163 | int | |
164 | default 5 if ARM64_64K_PAGES | |
165 | default 7 if ARM64_16K_PAGES | |
166 | default 4 | |
167 | ||
8f0d3aa9 DC |
168 | config ARCH_MMAP_RND_BITS_MIN |
169 | default 14 if ARM64_64K_PAGES | |
170 | default 16 if ARM64_16K_PAGES | |
171 | default 18 | |
172 | ||
173 | # max bits determined by the following formula: | |
174 | # VA_BITS - PAGE_SHIFT - 3 | |
175 | config ARCH_MMAP_RND_BITS_MAX | |
176 | default 19 if ARM64_VA_BITS=36 | |
177 | default 24 if ARM64_VA_BITS=39 | |
178 | default 27 if ARM64_VA_BITS=42 | |
179 | default 30 if ARM64_VA_BITS=47 | |
180 | default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES | |
181 | default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES | |
182 | default 33 if ARM64_VA_BITS=48 | |
183 | default 14 if ARM64_64K_PAGES | |
184 | default 16 if ARM64_16K_PAGES | |
185 | default 18 | |
186 | ||
187 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
188 | default 7 if ARM64_64K_PAGES | |
189 | default 9 if ARM64_16K_PAGES | |
190 | default 11 | |
191 | ||
192 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
193 | default 16 | |
194 | ||
ce816fa8 | 195 | config NO_IOPORT_MAP |
d1e6dc91 | 196 | def_bool y if !PCI |
8c2c3df3 CM |
197 | |
198 | config STACKTRACE_SUPPORT | |
199 | def_bool y | |
200 | ||
bf0c4e04 JVS |
201 | config ILLEGAL_POINTER_VALUE |
202 | hex | |
203 | default 0xdead000000000000 | |
204 | ||
8c2c3df3 CM |
205 | config LOCKDEP_SUPPORT |
206 | def_bool y | |
207 | ||
208 | config TRACE_IRQFLAGS_SUPPORT | |
209 | def_bool y | |
210 | ||
c209f799 | 211 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
212 | def_bool y |
213 | ||
9fb7410f DM |
214 | config GENERIC_BUG |
215 | def_bool y | |
216 | depends on BUG | |
217 | ||
218 | config GENERIC_BUG_RELATIVE_POINTERS | |
219 | def_bool y | |
220 | depends on GENERIC_BUG | |
221 | ||
8c2c3df3 CM |
222 | config GENERIC_HWEIGHT |
223 | def_bool y | |
224 | ||
225 | config GENERIC_CSUM | |
226 | def_bool y | |
227 | ||
228 | config GENERIC_CALIBRATE_DELAY | |
229 | def_bool y | |
230 | ||
19e7640d | 231 | config ZONE_DMA |
8c2c3df3 CM |
232 | def_bool y |
233 | ||
e585513b | 234 | config HAVE_GENERIC_GUP |
29e56940 SC |
235 | def_bool y |
236 | ||
8c2c3df3 CM |
237 | config ARCH_DMA_ADDR_T_64BIT |
238 | def_bool y | |
239 | ||
240 | config NEED_DMA_MAP_STATE | |
241 | def_bool y | |
242 | ||
243 | config NEED_SG_DMA_LENGTH | |
244 | def_bool y | |
245 | ||
4b3dc967 WD |
246 | config SMP |
247 | def_bool y | |
248 | ||
8c2c3df3 CM |
249 | config SWIOTLB |
250 | def_bool y | |
251 | ||
252 | config IOMMU_HELPER | |
253 | def_bool SWIOTLB | |
254 | ||
4cfb3613 AB |
255 | config KERNEL_MODE_NEON |
256 | def_bool y | |
257 | ||
92cc15fc RH |
258 | config FIX_EARLYCON_MEM |
259 | def_bool y | |
260 | ||
9f25e6ad KS |
261 | config PGTABLE_LEVELS |
262 | int | |
21539939 | 263 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad KS |
264 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
265 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
266 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
44eaacf1 SP |
267 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
268 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 269 | |
9842ceae PA |
270 | config ARCH_SUPPORTS_UPROBES |
271 | def_bool y | |
272 | ||
8f360948 AB |
273 | config ARCH_PROC_KCORE_TEXT |
274 | def_bool y | |
275 | ||
8c2c3df3 CM |
276 | source "init/Kconfig" |
277 | ||
278 | source "kernel/Kconfig.freezer" | |
279 | ||
6a377491 | 280 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 CM |
281 | |
282 | menu "Bus support" | |
283 | ||
d1e6dc91 LD |
284 | config PCI |
285 | bool "PCI support" | |
286 | help | |
287 | This feature enables support for PCI bus system. If you say Y | |
288 | here, the kernel will include drivers and infrastructure code | |
289 | to support PCI bus devices. | |
290 | ||
291 | config PCI_DOMAINS | |
292 | def_bool PCI | |
293 | ||
294 | config PCI_DOMAINS_GENERIC | |
295 | def_bool PCI | |
296 | ||
297 | config PCI_SYSCALL | |
298 | def_bool PCI | |
299 | ||
300 | source "drivers/pci/Kconfig" | |
d1e6dc91 | 301 | |
8c2c3df3 CM |
302 | endmenu |
303 | ||
304 | menu "Kernel Features" | |
305 | ||
c0a01b84 AP |
306 | menu "ARM errata workarounds via the alternatives framework" |
307 | ||
308 | config ARM64_ERRATUM_826319 | |
309 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
310 | default y | |
311 | help | |
312 | This option adds an alternative code sequence to work around ARM | |
313 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
314 | AXI master interface and an L2 cache. | |
315 | ||
316 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
317 | and is unable to accept a certain write via this interface, it will | |
318 | not progress on read data presented on the read data channel and the | |
319 | system can deadlock. | |
320 | ||
321 | The workaround promotes data cache clean instructions to | |
322 | data cache clean-and-invalidate. | |
323 | Please note that this does not necessarily enable the workaround, | |
324 | as it depends on the alternative framework, which will only patch | |
325 | the kernel if an affected CPU is detected. | |
326 | ||
327 | If unsure, say Y. | |
328 | ||
329 | config ARM64_ERRATUM_827319 | |
330 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
331 | default y | |
332 | help | |
333 | This option adds an alternative code sequence to work around ARM | |
334 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
335 | master interface and an L2 cache. | |
336 | ||
337 | Under certain conditions this erratum can cause a clean line eviction | |
338 | to occur at the same time as another transaction to the same address | |
339 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
340 | interconnect reorders the two transactions. | |
341 | ||
342 | The workaround promotes data cache clean instructions to | |
343 | data cache clean-and-invalidate. | |
344 | Please note that this does not necessarily enable the workaround, | |
345 | as it depends on the alternative framework, which will only patch | |
346 | the kernel if an affected CPU is detected. | |
347 | ||
348 | If unsure, say Y. | |
349 | ||
350 | config ARM64_ERRATUM_824069 | |
351 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
352 | default y | |
353 | help | |
354 | This option adds an alternative code sequence to work around ARM | |
355 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
356 | to a coherent interconnect. | |
357 | ||
358 | If a Cortex-A53 processor is executing a store or prefetch for | |
359 | write instruction at the same time as a processor in another | |
360 | cluster is executing a cache maintenance operation to the same | |
361 | address, then this erratum might cause a clean cache line to be | |
362 | incorrectly marked as dirty. | |
363 | ||
364 | The workaround promotes data cache clean instructions to | |
365 | data cache clean-and-invalidate. | |
366 | Please note that this option does not necessarily enable the | |
367 | workaround, as it depends on the alternative framework, which will | |
368 | only patch the kernel if an affected CPU is detected. | |
369 | ||
370 | If unsure, say Y. | |
371 | ||
372 | config ARM64_ERRATUM_819472 | |
373 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
374 | default y | |
375 | help | |
376 | This option adds an alternative code sequence to work around ARM | |
377 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
378 | present when it is connected to a coherent interconnect. | |
379 | ||
380 | If the processor is executing a load and store exclusive sequence at | |
381 | the same time as a processor in another cluster is executing a cache | |
382 | maintenance operation to the same address, then this erratum might | |
383 | cause data corruption. | |
384 | ||
385 | The workaround promotes data cache clean instructions to | |
386 | data cache clean-and-invalidate. | |
387 | Please note that this does not necessarily enable the workaround, | |
388 | as it depends on the alternative framework, which will only patch | |
389 | the kernel if an affected CPU is detected. | |
390 | ||
391 | If unsure, say Y. | |
392 | ||
393 | config ARM64_ERRATUM_832075 | |
394 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
395 | default y | |
396 | help | |
397 | This option adds an alternative code sequence to work around ARM | |
398 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
399 | ||
400 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
401 | instructions to Write-Back memory are mixed with Device loads. | |
402 | ||
403 | The workaround is to promote device loads to use Load-Acquire | |
404 | semantics. | |
405 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
406 | as it depends on the alternative framework, which will only patch |
407 | the kernel if an affected CPU is detected. | |
408 | ||
409 | If unsure, say Y. | |
410 | ||
411 | config ARM64_ERRATUM_834220 | |
412 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" | |
413 | depends on KVM | |
414 | default y | |
415 | help | |
416 | This option adds an alternative code sequence to work around ARM | |
417 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
418 | ||
419 | Affected Cortex-A57 parts might report a Stage 2 translation | |
420 | fault as the result of a Stage 1 fault for load crossing a | |
421 | page boundary when there is a permission or device memory | |
422 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
423 | ||
424 | The workaround is to verify that the Stage 1 translation | |
425 | doesn't generate a fault before handling the Stage 2 fault. | |
426 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
427 | as it depends on the alternative framework, which will only patch |
428 | the kernel if an affected CPU is detected. | |
429 | ||
430 | If unsure, say Y. | |
431 | ||
905e8c5d WD |
432 | config ARM64_ERRATUM_845719 |
433 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
434 | depends on COMPAT | |
435 | default y | |
436 | help | |
437 | This option adds an alternative code sequence to work around ARM | |
438 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
439 | ||
440 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
441 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
442 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
443 | might return incorrect data. | |
444 | ||
445 | The workaround is to write the contextidr_el1 register on exception | |
446 | return to a 32-bit task. | |
447 | Please note that this does not necessarily enable the workaround, | |
448 | as it depends on the alternative framework, which will only patch | |
449 | the kernel if an affected CPU is detected. | |
450 | ||
451 | If unsure, say Y. | |
452 | ||
df057cc7 WD |
453 | config ARM64_ERRATUM_843419 |
454 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
df057cc7 | 455 | default y |
6ffe9923 | 456 | select ARM64_MODULE_CMODEL_LARGE if MODULES |
df057cc7 | 457 | help |
6ffe9923 WD |
458 | This option links the kernel with '--fix-cortex-a53-843419' and |
459 | builds modules using the large memory model in order to avoid the use | |
460 | of the ADRP instruction, which can cause a subsequent memory access | |
461 | to use an incorrect address on Cortex-A53 parts up to r0p4. | |
df057cc7 WD |
462 | |
463 | If unsure, say Y. | |
ca6ce2bd TT |
464 | |
465 | config ARM64_ERRATUM_1024718 | |
466 | bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" | |
467 | default y | |
468 | help | |
469 | This option adds work around for Arm Cortex-A55 Erratum 1024718. | |
470 | ||
471 | Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect | |
472 | update of the hardware dirty bit when the DBM/AP bits are updated | |
473 | without a break-before-make. The work around is to disable the usage | |
474 | of hardware DBM locally on the affected cores. CPUs not affected by | |
475 | erratum will continue to use the feature. | |
476 | ||
477 | If unsure, say Y. | |
df057cc7 | 478 | |
9b0f46dd SP |
479 | config ARM64_ERRATUM_1024718 |
480 | bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" | |
481 | default y | |
482 | help | |
483 | This option adds work around for Arm Cortex-A55 Erratum 1024718. | |
484 | ||
485 | Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect | |
486 | update of the hardware dirty bit when the DBM/AP bits are updated | |
487 | without a break-before-make. The work around is to disable the usage | |
488 | of hardware DBM locally on the affected cores. CPUs not affected by | |
489 | erratum will continue to use the feature. | |
490 | ||
491 | If unsure, say Y. | |
492 | ||
94100970 RR |
493 | config CAVIUM_ERRATUM_22375 |
494 | bool "Cavium erratum 22375, 24313" | |
495 | default y | |
496 | help | |
497 | Enable workaround for erratum 22375, 24313. | |
498 | ||
499 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
500 | with small impact affecting only ITS table allocation. | |
501 | ||
502 | erratum 22375: only alloc 8MB table size | |
503 | erratum 24313: ignore memory access type | |
504 | ||
505 | The fixes are in ITS initialization and basically ignore memory access | |
506 | type and table size provided by the TYPER and BASER registers. | |
507 | ||
508 | If unsure, say Y. | |
509 | ||
fbf8f40e GK |
510 | config CAVIUM_ERRATUM_23144 |
511 | bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" | |
512 | depends on NUMA | |
513 | default y | |
514 | help | |
515 | ITS SYNC command hang for cross node io and collections/cpu mapping. | |
516 | ||
517 | If unsure, say Y. | |
518 | ||
6d4e11c5 RR |
519 | config CAVIUM_ERRATUM_23154 |
520 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" | |
521 | default y | |
522 | help | |
523 | The gicv3 of ThunderX requires a modified version for | |
524 | reading the IAR status to ensure data synchronization | |
525 | (access to icc_iar1_el1 is not sync'ed before and after). | |
526 | ||
527 | If unsure, say Y. | |
528 | ||
104a0c02 AP |
529 | config CAVIUM_ERRATUM_27456 |
530 | bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" | |
531 | default y | |
532 | help | |
533 | On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI | |
534 | instructions may cause the icache to become corrupted if it | |
535 | contains data for a non-current ASID. The fix is to | |
536 | invalidate the icache when changing the mm context. | |
537 | ||
538 | If unsure, say Y. | |
539 | ||
690a3415 DD |
540 | config CAVIUM_ERRATUM_30115 |
541 | bool "Cavium erratum 30115: Guest may disable interrupts in host" | |
542 | default y | |
543 | help | |
544 | On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through | |
545 | 1.2, and T83 Pass 1.0, KVM guest execution may disable | |
546 | interrupts in host. Trapping both GICv3 group-0 and group-1 | |
547 | accesses sidesteps the issue. | |
548 | ||
549 | If unsure, say Y. | |
550 | ||
38fd94b0 CC |
551 | config QCOM_FALKOR_ERRATUM_1003 |
552 | bool "Falkor E1003: Incorrect translation due to ASID change" | |
553 | default y | |
38fd94b0 CC |
554 | help |
555 | On Falkor v1, an incorrect ASID may be cached in the TLB when ASID | |
715faa31 WD |
556 | and BADDR are changed together in TTBRx_EL1. Since we keep the ASID |
557 | in TTBR1_EL1, this situation only occurs in the entry trampoline and | |
558 | then only for entries in the walk cache, since the leaf translation | |
559 | is unchanged. Work around the erratum by invalidating the walk cache | |
560 | entries for the trampoline before entering the kernel proper. | |
38fd94b0 | 561 | |
d9ff80f8 CC |
562 | config QCOM_FALKOR_ERRATUM_1009 |
563 | bool "Falkor E1009: Prematurely complete a DSB after a TLBI" | |
564 | default y | |
565 | help | |
566 | On Falkor v1, the CPU may prematurely complete a DSB following a | |
567 | TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation | |
568 | one more time to fix the issue. | |
569 | ||
570 | If unsure, say Y. | |
571 | ||
90922a2d SD |
572 | config QCOM_QDF2400_ERRATUM_0065 |
573 | bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" | |
574 | default y | |
575 | help | |
576 | On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports | |
577 | ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have | |
578 | been indicated as 16Bytes (0xf), not 8Bytes (0x7). | |
579 | ||
580 | If unsure, say Y. | |
581 | ||
558b0165 AB |
582 | config SOCIONEXT_SYNQUACER_PREITS |
583 | bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" | |
584 | default y | |
585 | help | |
586 | Socionext Synquacer SoCs implement a separate h/w block to generate | |
587 | MSI doorbell writes with non-zero values for the device ID. | |
588 | ||
5c9a882e MZ |
589 | If unsure, say Y. |
590 | ||
591 | config HISILICON_ERRATUM_161600802 | |
592 | bool "Hip07 161600802: Erroneous redistributor VLPI base" | |
593 | default y | |
594 | help | |
595 | The HiSilicon Hip07 SoC usees the wrong redistributor base | |
596 | when issued ITS commands such as VMOVP and VMAPP, and requires | |
597 | a 128kB offset to be applied to the target address in this commands. | |
598 | ||
558b0165 | 599 | If unsure, say Y. |
932b50c7 SD |
600 | |
601 | config QCOM_FALKOR_ERRATUM_E1041 | |
602 | bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" | |
603 | default y | |
604 | help | |
605 | Falkor CPU may speculatively fetch instructions from an improper | |
606 | memory location when MMU translation is changed from SCTLR_ELn[M]=1 | |
607 | to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. | |
608 | ||
609 | If unsure, say Y. | |
610 | ||
c0a01b84 AP |
611 | endmenu |
612 | ||
613 | ||
e41ceed0 JL |
614 | choice |
615 | prompt "Page size" | |
616 | default ARM64_4K_PAGES | |
617 | help | |
618 | Page size (translation granule) configuration. | |
619 | ||
620 | config ARM64_4K_PAGES | |
621 | bool "4KB" | |
622 | help | |
623 | This feature enables 4KB pages support. | |
624 | ||
44eaacf1 SP |
625 | config ARM64_16K_PAGES |
626 | bool "16KB" | |
627 | help | |
628 | The system will use 16KB pages support. AArch32 emulation | |
629 | requires applications compiled with 16K (or a multiple of 16K) | |
630 | aligned segments. | |
631 | ||
8c2c3df3 | 632 | config ARM64_64K_PAGES |
e41ceed0 | 633 | bool "64KB" |
8c2c3df3 CM |
634 | help |
635 | This feature enables 64KB pages support (4KB by default) | |
636 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
637 | look-up. AArch32 emulation requires applications compiled |
638 | with 64K aligned segments. | |
8c2c3df3 | 639 | |
e41ceed0 JL |
640 | endchoice |
641 | ||
642 | choice | |
643 | prompt "Virtual address space size" | |
644 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 645 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
646 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
647 | help | |
648 | Allows choosing one of multiple possible virtual address | |
649 | space sizes. The level of translation table is determined by | |
650 | a combination of page size and virtual address space size. | |
651 | ||
21539939 | 652 | config ARM64_VA_BITS_36 |
56a3f30e | 653 | bool "36-bit" if EXPERT |
21539939 SP |
654 | depends on ARM64_16K_PAGES |
655 | ||
e41ceed0 JL |
656 | config ARM64_VA_BITS_39 |
657 | bool "39-bit" | |
658 | depends on ARM64_4K_PAGES | |
659 | ||
660 | config ARM64_VA_BITS_42 | |
661 | bool "42-bit" | |
662 | depends on ARM64_64K_PAGES | |
663 | ||
44eaacf1 SP |
664 | config ARM64_VA_BITS_47 |
665 | bool "47-bit" | |
666 | depends on ARM64_16K_PAGES | |
667 | ||
c79b954b JL |
668 | config ARM64_VA_BITS_48 |
669 | bool "48-bit" | |
c79b954b | 670 | |
e41ceed0 JL |
671 | endchoice |
672 | ||
673 | config ARM64_VA_BITS | |
674 | int | |
21539939 | 675 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
676 | default 39 if ARM64_VA_BITS_39 |
677 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 678 | default 47 if ARM64_VA_BITS_47 |
c79b954b | 679 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 680 | |
a872013d WD |
681 | config CPU_BIG_ENDIAN |
682 | bool "Build big-endian kernel" | |
683 | help | |
684 | Say Y if you plan on running a kernel in big-endian mode. | |
685 | ||
f6e763b9 MB |
686 | config SCHED_MC |
687 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
688 | help |
689 | Multi-core scheduler support improves the CPU scheduler's decision | |
690 | making when dealing with multi-core CPU chips at a cost of slightly | |
691 | increased overhead in some places. If unsure say N here. | |
692 | ||
693 | config SCHED_SMT | |
694 | bool "SMT scheduler support" | |
f6e763b9 MB |
695 | help |
696 | Improves the CPU scheduler's decision making when dealing with | |
697 | MultiThreading at a cost of slightly increased overhead in some | |
698 | places. If unsure say N here. | |
699 | ||
8c2c3df3 | 700 | config NR_CPUS |
62aa9655 GK |
701 | int "Maximum number of CPUs (2-4096)" |
702 | range 2 4096 | |
15942853 | 703 | # These have to remain sorted largest to smallest |
e3672649 | 704 | default "64" |
8c2c3df3 | 705 | |
9327e2c6 MR |
706 | config HOTPLUG_CPU |
707 | bool "Support for hot-pluggable CPUs" | |
217d453d | 708 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
709 | help |
710 | Say Y here to experiment with turning CPUs off and on. CPUs | |
711 | can be controlled through /sys/devices/system/cpu. | |
712 | ||
1a2db300 GK |
713 | # Common NUMA Features |
714 | config NUMA | |
715 | bool "Numa Memory Allocation and Scheduler Support" | |
0c2a6cce KW |
716 | select ACPI_NUMA if ACPI |
717 | select OF_NUMA | |
1a2db300 GK |
718 | help |
719 | Enable NUMA (Non Uniform Memory Access) support. | |
720 | ||
721 | The kernel will try to allocate memory used by a CPU on the | |
722 | local memory of the CPU and add some more | |
723 | NUMA awareness to the kernel. | |
724 | ||
725 | config NODES_SHIFT | |
726 | int "Maximum NUMA Nodes (as a power of 2)" | |
727 | range 1 10 | |
728 | default "2" | |
729 | depends on NEED_MULTIPLE_NODES | |
730 | help | |
731 | Specify the maximum number of NUMA Nodes available on the target | |
732 | system. Increases memory reserved to accommodate various tables. | |
733 | ||
734 | config USE_PERCPU_NUMA_NODE_ID | |
735 | def_bool y | |
736 | depends on NUMA | |
737 | ||
7af3a0a9 ZL |
738 | config HAVE_SETUP_PER_CPU_AREA |
739 | def_bool y | |
740 | depends on NUMA | |
741 | ||
742 | config NEED_PER_CPU_EMBED_FIRST_CHUNK | |
743 | def_bool y | |
744 | depends on NUMA | |
745 | ||
6d526ee2 AB |
746 | config HOLES_IN_ZONE |
747 | def_bool y | |
748 | depends on NUMA | |
749 | ||
8c2c3df3 | 750 | source kernel/Kconfig.preempt |
f90df5e2 | 751 | source kernel/Kconfig.hz |
8c2c3df3 | 752 | |
83863f25 LA |
753 | config ARCH_SUPPORTS_DEBUG_PAGEALLOC |
754 | def_bool y | |
755 | ||
8c2c3df3 CM |
756 | config ARCH_HAS_HOLES_MEMORYMODEL |
757 | def_bool y if SPARSEMEM | |
758 | ||
759 | config ARCH_SPARSEMEM_ENABLE | |
760 | def_bool y | |
761 | select SPARSEMEM_VMEMMAP_ENABLE | |
762 | ||
763 | config ARCH_SPARSEMEM_DEFAULT | |
764 | def_bool ARCH_SPARSEMEM_ENABLE | |
765 | ||
766 | config ARCH_SELECT_MEMORY_MODEL | |
767 | def_bool ARCH_SPARSEMEM_ENABLE | |
768 | ||
769 | config HAVE_ARCH_PFN_VALID | |
770 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
771 | ||
772 | config HW_PERF_EVENTS | |
6475b2d8 MR |
773 | def_bool y |
774 | depends on ARM_PMU | |
8c2c3df3 | 775 | |
084bd298 SC |
776 | config SYS_SUPPORTS_HUGETLBFS |
777 | def_bool y | |
778 | ||
084bd298 | 779 | config ARCH_WANT_HUGE_PMD_SHARE |
21539939 | 780 | def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
084bd298 | 781 | |
a41dc0e8 CM |
782 | config ARCH_HAS_CACHE_LINE_SIZE |
783 | def_bool y | |
784 | ||
8c2c3df3 CM |
785 | source "mm/Kconfig" |
786 | ||
a1ae65b2 AT |
787 | config SECCOMP |
788 | bool "Enable seccomp to safely compute untrusted bytecode" | |
789 | ---help--- | |
790 | This kernel feature is useful for number crunching applications | |
791 | that may need to compute untrusted bytecode during their | |
792 | execution. By using pipes or other transports made available to | |
793 | the process as file descriptors supporting the read/write | |
794 | syscalls, it's possible to isolate those applications in | |
795 | their own address space using seccomp. Once seccomp is | |
796 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
797 | and the task is only allowed to execute a few safe syscalls | |
798 | defined by each seccomp mode. | |
799 | ||
dfd57bc3 SS |
800 | config PARAVIRT |
801 | bool "Enable paravirtualization code" | |
802 | help | |
803 | This changes the kernel so it can modify itself when it is run | |
804 | under a hypervisor, potentially improving performance significantly | |
805 | over full virtualization. | |
806 | ||
807 | config PARAVIRT_TIME_ACCOUNTING | |
808 | bool "Paravirtual steal time accounting" | |
809 | select PARAVIRT | |
810 | default n | |
811 | help | |
812 | Select this option to enable fine granularity task steal time | |
813 | accounting. Time spent executing other tasks in parallel with | |
814 | the current vCPU is discounted from the vCPU power. To account for | |
815 | that, there can be a small performance impact. | |
816 | ||
817 | If in doubt, say N here. | |
818 | ||
d28f6df1 GL |
819 | config KEXEC |
820 | depends on PM_SLEEP_SMP | |
821 | select KEXEC_CORE | |
822 | bool "kexec system call" | |
823 | ---help--- | |
824 | kexec is a system call that implements the ability to shutdown your | |
825 | current kernel, and to start another kernel. It is like a reboot | |
826 | but it is independent of the system firmware. And like a reboot | |
827 | you can start any kernel with it, not just Linux. | |
828 | ||
e62aaeac AT |
829 | config CRASH_DUMP |
830 | bool "Build kdump crash kernel" | |
831 | help | |
832 | Generate crash dump after being started by kexec. This should | |
833 | be normally only set in special crash dump kernels which are | |
834 | loaded in the main kernel with kexec-tools into a specially | |
835 | reserved region and then later executed after a crash by | |
836 | kdump/kexec. | |
837 | ||
838 | For more details see Documentation/kdump/kdump.txt | |
839 | ||
aa42aa13 SS |
840 | config XEN_DOM0 |
841 | def_bool y | |
842 | depends on XEN | |
843 | ||
844 | config XEN | |
c2ba1f7d | 845 | bool "Xen guest support on ARM64" |
aa42aa13 | 846 | depends on ARM64 && OF |
83862ccf | 847 | select SWIOTLB_XEN |
dfd57bc3 | 848 | select PARAVIRT |
aa42aa13 SS |
849 | help |
850 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
851 | ||
d03bb145 SC |
852 | config FORCE_MAX_ZONEORDER |
853 | int | |
854 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
b09cbbb8 | 855 | default "13" if (ARCH_THUNDER && ARM64_4K_PAGES) |
44eaacf1 | 856 | default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) |
d03bb145 | 857 | default "11" |
44eaacf1 SP |
858 | help |
859 | The kernel memory allocator divides physically contiguous memory | |
860 | blocks into "zones", where each zone is a power of two number of | |
861 | pages. This option selects the largest power of two that the kernel | |
862 | keeps in the memory allocator. If you need to allocate very large | |
863 | blocks of physically contiguous memory, then you may need to | |
864 | increase this value. | |
865 | ||
866 | This config option is actually maximum order plus one. For example, | |
867 | a value of 11 means that the largest free memory block is 2^10 pages. | |
868 | ||
869 | We make sure that we can allocate upto a HugePage size for each configuration. | |
870 | Hence we have : | |
871 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 | |
872 | ||
873 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us | |
874 | 4M allocations matching the default size used by generic code. | |
d03bb145 | 875 | |
f86e734f | 876 | config UNMAP_KERNEL_AT_EL0 |
4225a53b | 877 | bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT |
f86e734f WD |
878 | default y |
879 | help | |
4225a53b WD |
880 | Speculation attacks against some high-performance processors can |
881 | be used to bypass MMU permission checks and leak kernel data to | |
882 | userspace. This can be defended against by unmapping the kernel | |
883 | when running in userspace, mapping it back in on exception entry | |
884 | via a trampoline page in the vector table. | |
f86e734f WD |
885 | |
886 | If unsure, say Y. | |
887 | ||
9a5fa750 WD |
888 | config HARDEN_BRANCH_PREDICTOR |
889 | bool "Harden the branch predictor against aliasing attacks" if EXPERT | |
890 | default y | |
891 | help | |
892 | Speculation attacks against some high-performance processors rely on | |
893 | being able to manipulate the branch predictor for a victim context by | |
894 | executing aliasing branches in the attacker context. Such attacks | |
895 | can be partially mitigated against by clearing internal branch | |
896 | predictor state and limiting the prediction logic in some situations. | |
897 | ||
898 | This config option will take CPU-specific actions to harden the | |
899 | branch predictor against aliasing attacks and may rely on specific | |
900 | instruction sequences or control bits being set by the system | |
901 | firmware. | |
902 | ||
903 | If unsure, say Y. | |
904 | ||
a174f422 MZ |
905 | config ARM64_SSBD |
906 | bool "Speculative Store Bypass Disable" if EXPERT | |
907 | default y | |
908 | help | |
909 | This enables mitigation of the bypassing of previous stores | |
910 | by speculative loads. | |
911 | ||
912 | If unsure, say Y. | |
913 | ||
1b907f46 WD |
914 | menuconfig ARMV8_DEPRECATED |
915 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
916 | depends on COMPAT | |
6cfa7cc4 | 917 | depends on SYSCTL |
1b907f46 WD |
918 | help |
919 | Legacy software support may require certain instructions | |
920 | that have been deprecated or obsoleted in the architecture. | |
921 | ||
922 | Enable this config to enable selective emulation of these | |
923 | features. | |
924 | ||
925 | If unsure, say Y | |
926 | ||
927 | if ARMV8_DEPRECATED | |
928 | ||
929 | config SWP_EMULATION | |
930 | bool "Emulate SWP/SWPB instructions" | |
931 | help | |
932 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
933 | they are always undefined. Say Y here to enable software | |
934 | emulation of these instructions for userspace using LDXR/STXR. | |
935 | ||
936 | In some older versions of glibc [<=2.8] SWP is used during futex | |
937 | trylock() operations with the assumption that the code will not | |
938 | be preempted. This invalid assumption may be more likely to fail | |
939 | with SWP emulation enabled, leading to deadlock of the user | |
940 | application. | |
941 | ||
942 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
943 | on an external transaction monitoring block called a global | |
944 | monitor to maintain update atomicity. If your system does not | |
945 | implement a global monitor, this option can cause programs that | |
946 | perform SWP operations to uncached memory to deadlock. | |
947 | ||
948 | If unsure, say Y | |
949 | ||
950 | config CP15_BARRIER_EMULATION | |
951 | bool "Emulate CP15 Barrier instructions" | |
952 | help | |
953 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
954 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
955 | strongly recommended to use the ISB, DSB, and DMB | |
956 | instructions instead. | |
957 | ||
958 | Say Y here to enable software emulation of these | |
959 | instructions for AArch32 userspace code. When this option is | |
960 | enabled, CP15 barrier usage is traced which can help | |
961 | identify software that needs updating. | |
962 | ||
963 | If unsure, say Y | |
964 | ||
2d888f48 SP |
965 | config SETEND_EMULATION |
966 | bool "Emulate SETEND instruction" | |
967 | help | |
968 | The SETEND instruction alters the data-endianness of the | |
969 | AArch32 EL0, and is deprecated in ARMv8. | |
970 | ||
971 | Say Y here to enable software emulation of the instruction | |
972 | for AArch32 userspace code. | |
973 | ||
974 | Note: All the cpus on the system must have mixed endian support at EL0 | |
975 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
976 | endian - is hotplugged in after this feature has been enabled, there could | |
977 | be unexpected results in the applications. | |
978 | ||
979 | If unsure, say Y | |
1b907f46 WD |
980 | endif |
981 | ||
ba42822a CM |
982 | config ARM64_SW_TTBR0_PAN |
983 | bool "Emulate Privileged Access Never using TTBR0_EL1 switching" | |
984 | help | |
985 | Enabling this option prevents the kernel from accessing | |
986 | user-space memory directly by pointing TTBR0_EL1 to a reserved | |
987 | zeroed area and reserved ASID. The user access routines | |
988 | restore the valid TTBR0_EL1 temporarily. | |
989 | ||
0e4a0709 WD |
990 | menu "ARMv8.1 architectural features" |
991 | ||
992 | config ARM64_HW_AFDBM | |
993 | bool "Support for hardware updates of the Access and Dirty page flags" | |
994 | default y | |
995 | help | |
996 | The ARMv8.1 architecture extensions introduce support for | |
997 | hardware updates of the access and dirty information in page | |
998 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
999 | capable processors, accesses to pages with PTE_AF cleared will | |
1000 | set this bit instead of raising an access flag fault. | |
1001 | Similarly, writes to read-only pages with the DBM bit set will | |
1002 | clear the read-only bit (AP[2]) instead of raising a | |
1003 | permission fault. | |
1004 | ||
1005 | Kernels built with this configuration option enabled continue | |
1006 | to work on pre-ARMv8.1 hardware and the performance impact is | |
1007 | minimal. If unsure, say Y. | |
1008 | ||
1009 | config ARM64_PAN | |
1010 | bool "Enable support for Privileged Access Never (PAN)" | |
1011 | default y | |
1012 | help | |
1013 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
1014 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
1015 | memory directly. | |
1016 | ||
1017 | Choosing this option will cause any unprotected (not using | |
1018 | copy_to_user et al) memory access to fail with a permission fault. | |
1019 | ||
1020 | The feature is detected at runtime, and will remain as a 'nop' | |
1021 | instruction if the cpu does not implement the feature. | |
1022 | ||
1023 | config ARM64_LSE_ATOMICS | |
1024 | bool "Atomic instructions" | |
1025 | help | |
1026 | As part of the Large System Extensions, ARMv8.1 introduces new | |
1027 | atomic instructions that are designed specifically to scale in | |
1028 | very large systems. | |
1029 | ||
1030 | Say Y here to make use of these instructions for the in-kernel | |
1031 | atomic routines. This incurs a small overhead on CPUs that do | |
1032 | not support these instructions and requires the kernel to be | |
1033 | built with binutils >= 2.25. | |
1034 | ||
1f364c8c MZ |
1035 | config ARM64_VHE |
1036 | bool "Enable support for Virtualization Host Extensions (VHE)" | |
1037 | default y | |
1038 | help | |
1039 | Virtualization Host Extensions (VHE) allow the kernel to run | |
1040 | directly at EL2 (instead of EL1) on processors that support | |
1041 | it. This leads to better performance for KVM, as they reduce | |
1042 | the cost of the world switch. | |
1043 | ||
1044 | Selecting this option allows the VHE feature to be detected | |
1045 | at runtime, and does not affect processors that do not | |
1046 | implement this feature. | |
1047 | ||
0e4a0709 WD |
1048 | endmenu |
1049 | ||
f993318b WD |
1050 | menu "ARMv8.2 architectural features" |
1051 | ||
57f4959b JM |
1052 | config ARM64_UAO |
1053 | bool "Enable support for User Access Override (UAO)" | |
1054 | default y | |
1055 | help | |
1056 | User Access Override (UAO; part of the ARMv8.2 Extensions) | |
1057 | causes the 'unprivileged' variant of the load/store instructions to | |
83fc61a5 | 1058 | be overridden to be privileged. |
57f4959b JM |
1059 | |
1060 | This option changes get_user() and friends to use the 'unprivileged' | |
1061 | variant of the load/store instructions. This ensures that user-space | |
1062 | really did have access to the supplied memory. When addr_limit is | |
1063 | set to kernel memory the UAO bit will be set, allowing privileged | |
1064 | access to kernel memory. | |
1065 | ||
1066 | Choosing this option will cause copy_to_user() et al to use user-space | |
1067 | memory permissions. | |
1068 | ||
1069 | The feature is detected at runtime, the kernel will use the | |
1070 | regular load/store instructions if the cpu does not implement the | |
1071 | feature. | |
1072 | ||
d50e071f RM |
1073 | config ARM64_PMEM |
1074 | bool "Enable support for persistent memory" | |
1075 | select ARCH_HAS_PMEM_API | |
5d7bdeb1 | 1076 | select ARCH_HAS_UACCESS_FLUSHCACHE |
d50e071f RM |
1077 | help |
1078 | Say Y to enable support for the persistent memory API based on the | |
1079 | ARMv8.2 DCPoP feature. | |
1080 | ||
1081 | The feature is detected at runtime, and the kernel will use DC CVAC | |
1082 | operations if DC CVAP is not supported (following the behaviour of | |
1083 | DC CVAP itself if the system does not define a point of persistence). | |
1084 | ||
9207a173 XX |
1085 | config ARM64_RAS_EXTN |
1086 | bool "Enable support for RAS CPU Extensions" | |
1087 | default y | |
1088 | help | |
1089 | CPUs that support the Reliability, Availability and Serviceability | |
1090 | (RAS) Extensions, part of ARMv8.2 are able to track faults and | |
1091 | errors, classify them and report them to software. | |
1092 | ||
1093 | On CPUs with these extensions system software can use additional | |
1094 | barriers to determine if faults are pending and read the | |
1095 | classification from a new set of registers. | |
1096 | ||
1097 | Selecting this feature will allow the kernel to use these barriers | |
1098 | and access the new registers if the system supports the extension. | |
1099 | Platform RAS features may additionally depend on firmware support. | |
1100 | ||
f993318b WD |
1101 | endmenu |
1102 | ||
ddd25ad1 DM |
1103 | config ARM64_SVE |
1104 | bool "ARM Scalable Vector Extension support" | |
1105 | default y | |
1106 | help | |
1107 | The Scalable Vector Extension (SVE) is an extension to the AArch64 | |
1108 | execution state which complements and extends the SIMD functionality | |
1109 | of the base architecture to support much larger vectors and to enable | |
1110 | additional vectorisation opportunities. | |
1111 | ||
1112 | To enable use of this extension on CPUs that implement it, say Y. | |
1113 | ||
fd045f6c AB |
1114 | config ARM64_MODULE_CMODEL_LARGE |
1115 | bool | |
1116 | ||
1117 | config ARM64_MODULE_PLTS | |
1118 | bool | |
1119 | select ARM64_MODULE_CMODEL_LARGE | |
1120 | select HAVE_MOD_ARCH_SPECIFIC | |
1121 | ||
1e48ef7f AB |
1122 | config RELOCATABLE |
1123 | bool | |
1124 | help | |
1125 | This builds the kernel as a Position Independent Executable (PIE), | |
1126 | which retains all relocation metadata required to relocate the | |
1127 | kernel binary at runtime to a different virtual address than the | |
1128 | address it was linked at. | |
1129 | Since AArch64 uses the RELA relocation format, this requires a | |
1130 | relocation pass at runtime even if the kernel is loaded at the | |
1131 | same address it was linked at. | |
1132 | ||
f80fb3a3 AB |
1133 | config RANDOMIZE_BASE |
1134 | bool "Randomize the address of the kernel image" | |
b9c220b5 | 1135 | select ARM64_MODULE_PLTS if MODULES |
f80fb3a3 AB |
1136 | select RELOCATABLE |
1137 | help | |
1138 | Randomizes the virtual address at which the kernel image is | |
1139 | loaded, as a security feature that deters exploit attempts | |
1140 | relying on knowledge of the location of kernel internals. | |
1141 | ||
1142 | It is the bootloader's job to provide entropy, by passing a | |
1143 | random u64 value in /chosen/kaslr-seed at kernel entry. | |
1144 | ||
2b5fe07a AB |
1145 | When booting via the UEFI stub, it will invoke the firmware's |
1146 | EFI_RNG_PROTOCOL implementation (if available) to supply entropy | |
1147 | to the kernel proper. In addition, it will randomise the physical | |
1148 | location of the kernel Image as well. | |
1149 | ||
f80fb3a3 AB |
1150 | If unsure, say N. |
1151 | ||
1152 | config RANDOMIZE_MODULE_REGION_FULL | |
1153 | bool "Randomize the module region independently from the core kernel" | |
e71a4e1b | 1154 | depends on RANDOMIZE_BASE |
f80fb3a3 AB |
1155 | default y |
1156 | help | |
1157 | Randomizes the location of the module region without considering the | |
1158 | location of the core kernel. This way, it is impossible for modules | |
1159 | to leak information about the location of core kernel data structures | |
1160 | but it does imply that function calls between modules and the core | |
1161 | kernel will need to be resolved via veneers in the module PLT. | |
1162 | ||
1163 | When this option is not set, the module region will be randomized over | |
1164 | a limited range that contains the [_stext, _etext] interval of the | |
1165 | core kernel, so branch relocations are always in range. | |
1166 | ||
8c2c3df3 CM |
1167 | endmenu |
1168 | ||
1169 | menu "Boot options" | |
1170 | ||
5e89c55e LP |
1171 | config ARM64_ACPI_PARKING_PROTOCOL |
1172 | bool "Enable support for the ARM64 ACPI parking protocol" | |
1173 | depends on ACPI | |
1174 | help | |
1175 | Enable support for the ARM64 ACPI parking protocol. If disabled | |
1176 | the kernel will not allow booting through the ARM64 ACPI parking | |
1177 | protocol even if the corresponding data is present in the ACPI | |
1178 | MADT table. | |
1179 | ||
8c2c3df3 CM |
1180 | config CMDLINE |
1181 | string "Default kernel command string" | |
1182 | default "" | |
1183 | help | |
1184 | Provide a set of default command-line options at build time by | |
1185 | entering them here. As a minimum, you should specify the the | |
1186 | root device (e.g. root=/dev/nfs). | |
1187 | ||
1188 | config CMDLINE_FORCE | |
1189 | bool "Always use the default kernel command string" | |
1190 | help | |
1191 | Always use the default kernel command string, even if the boot | |
1192 | loader passes other arguments to the kernel. | |
1193 | This is useful if you cannot or don't want to change the | |
1194 | command-line options your boot loader passes to the kernel. | |
1195 | ||
f4f75ad5 AB |
1196 | config EFI_STUB |
1197 | bool | |
1198 | ||
f84d0275 MS |
1199 | config EFI |
1200 | bool "UEFI runtime support" | |
1201 | depends on OF && !CPU_BIG_ENDIAN | |
b472db6c | 1202 | depends on KERNEL_MODE_NEON |
0d3b8171 | 1203 | select ARCH_SUPPORTS_ACPI |
f84d0275 MS |
1204 | select LIBFDT |
1205 | select UCS2_STRING | |
1206 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 1207 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
1208 | select EFI_STUB |
1209 | select EFI_ARMSTUB | |
f84d0275 MS |
1210 | default y |
1211 | help | |
1212 | This option provides support for runtime services provided | |
1213 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
1214 | clock, and platform reset). A UEFI stub is also provided to |
1215 | allow the kernel to be booted as an EFI application. This | |
1216 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 1217 | |
d1ae8c00 YL |
1218 | config DMI |
1219 | bool "Enable support for SMBIOS (DMI) tables" | |
1220 | depends on EFI | |
1221 | default y | |
1222 | help | |
1223 | This enables SMBIOS/DMI feature for systems. | |
1224 | ||
1225 | This option is only useful on systems that have UEFI firmware. | |
1226 | However, even with this option, the resultant kernel should | |
1227 | continue to boot on existing non-UEFI platforms. | |
1228 | ||
8c2c3df3 CM |
1229 | endmenu |
1230 | ||
1231 | menu "Userspace binary formats" | |
1232 | ||
1233 | source "fs/Kconfig.binfmt" | |
1234 | ||
1235 | config COMPAT | |
1236 | bool "Kernel support for 32-bit EL0" | |
755e70b7 | 1237 | depends on ARM64_4K_PAGES || EXPERT |
2e449048 | 1238 | select COMPAT_BINFMT_ELF if BINFMT_ELF |
af1839eb | 1239 | select HAVE_UID16 |
84b9e9b4 | 1240 | select OLD_SIGSUSPEND3 |
51682036 | 1241 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
1242 | help |
1243 | This option enables support for a 32-bit EL0 running under a 64-bit | |
1244 | kernel at EL1. AArch32-specific components such as system calls, | |
1245 | the user helper functions, VFP support and the ptrace interface are | |
1246 | handled appropriately by the kernel. | |
1247 | ||
44eaacf1 SP |
1248 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware |
1249 | that you will only be able to execute AArch32 binaries that were compiled | |
1250 | with page size aligned segments. | |
a8fcd8b1 | 1251 | |
8c2c3df3 CM |
1252 | If you want to execute 32-bit userspace applications, say Y. |
1253 | ||
1254 | config SYSVIPC_COMPAT | |
1255 | def_bool y | |
1256 | depends on COMPAT && SYSVIPC | |
1257 | ||
1258 | endmenu | |
1259 | ||
166936ba LP |
1260 | menu "Power management options" |
1261 | ||
1262 | source "kernel/power/Kconfig" | |
1263 | ||
82869ac5 JM |
1264 | config ARCH_HIBERNATION_POSSIBLE |
1265 | def_bool y | |
1266 | depends on CPU_PM | |
1267 | ||
1268 | config ARCH_HIBERNATION_HEADER | |
1269 | def_bool y | |
1270 | depends on HIBERNATION | |
1271 | ||
166936ba LP |
1272 | config ARCH_SUSPEND_POSSIBLE |
1273 | def_bool y | |
1274 | ||
166936ba LP |
1275 | endmenu |
1276 | ||
1307220d LP |
1277 | menu "CPU Power Management" |
1278 | ||
1279 | source "drivers/cpuidle/Kconfig" | |
1280 | ||
52e7e816 RH |
1281 | source "drivers/cpufreq/Kconfig" |
1282 | ||
1283 | endmenu | |
1284 | ||
8c2c3df3 CM |
1285 | source "net/Kconfig" |
1286 | ||
1287 | source "drivers/Kconfig" | |
1288 | ||
0d34a427 LO |
1289 | source "ubuntu/Kconfig" |
1290 | ||
f84d0275 MS |
1291 | source "drivers/firmware/Kconfig" |
1292 | ||
b6a02173 GG |
1293 | source "drivers/acpi/Kconfig" |
1294 | ||
8c2c3df3 CM |
1295 | source "fs/Kconfig" |
1296 | ||
c3eb5b14 MZ |
1297 | source "arch/arm64/kvm/Kconfig" |
1298 | ||
8c2c3df3 CM |
1299 | source "arch/arm64/Kconfig.debug" |
1300 | ||
1301 | source "security/Kconfig" | |
1302 | ||
1303 | source "crypto/Kconfig" | |
2c98833a AB |
1304 | if CRYPTO |
1305 | source "arch/arm64/crypto/Kconfig" | |
1306 | endif | |
8c2c3df3 CM |
1307 | |
1308 | source "lib/Kconfig" |