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Commit | Line | Data |
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ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
8c2c3df3 CM |
2 | config ARM64 |
3 | def_bool y | |
b6197b93 | 4 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 5 | select ACPI_GENERIC_GSI if ACPI |
5f1ae4eb | 6 | select ACPI_GTDT if ACPI |
c6bb8f89 | 7 | select ACPI_IORT if ACPI |
6933de0c | 8 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
52146173 | 9 | select ACPI_MCFG if (ACPI && PCI) |
888125a7 | 10 | select ACPI_SPCR_TABLE if ACPI |
0ce82232 | 11 | select ACPI_PPTT if ACPI |
09587a09 | 12 | select ARCH_HAS_DEBUG_WX |
ab7876a9 | 13 | select ARCH_BINFMT_ELF_STATE |
1e866974 | 14 | select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION |
91024b3c AK |
15 | select ARCH_ENABLE_MEMORY_HOTPLUG |
16 | select ARCH_ENABLE_MEMORY_HOTREMOVE | |
66f24fa7 | 17 | select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 |
1e866974 | 18 | select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE |
c2280be8 | 19 | select ARCH_HAS_CACHE_LINE_SIZE |
ec6d06ef | 20 | select ARCH_HAS_DEBUG_VIRTUAL |
399145f9 | 21 | select ARCH_HAS_DEBUG_VM_PGTABLE |
13bf5ced | 22 | select ARCH_HAS_DMA_PREP_COHERENT |
38b04a74 | 23 | select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI |
e75bef2a | 24 | select ARCH_HAS_FAST_MULTIPLIER |
6974f0c4 | 25 | select ARCH_HAS_FORTIFY_SOURCE |
957e3fac | 26 | select ARCH_HAS_GCOV_PROFILE_ALL |
4eb0716e | 27 | select ARCH_HAS_GIGANTIC_PAGE |
5e4c7549 | 28 | select ARCH_HAS_KCOV |
d8ae8a37 | 29 | select ARCH_HAS_KEEPINITRD |
f1e3a12b | 30 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
0ebeea8c | 31 | select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE |
73b20c84 | 32 | select ARCH_HAS_PTE_DEVMAP |
3010a5ea | 33 | select ARCH_HAS_PTE_SPECIAL |
347cb6af | 34 | select ARCH_HAS_SETUP_DMA_OPS |
4739d53f | 35 | select ARCH_HAS_SET_DIRECT_MAP |
d2852a22 | 36 | select ARCH_HAS_SET_MEMORY |
5fc57df2 | 37 | select ARCH_STACKWALK |
ad21fc4f LA |
38 | select ARCH_HAS_STRICT_KERNEL_RWX |
39 | select ARCH_HAS_STRICT_MODULE_RWX | |
886643b7 CH |
40 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
41 | select ARCH_HAS_SYNC_DMA_FOR_CPU | |
4378a7d4 | 42 | select ARCH_HAS_SYSCALL_WRAPPER |
dc2acded | 43 | select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT |
1f85008e | 44 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
ab7876a9 | 45 | select ARCH_HAVE_ELF_PROT |
396a5d4a | 46 | select ARCH_HAVE_NMI_SAFE_CMPXCHG |
7ef858da TG |
47 | select ARCH_INLINE_READ_LOCK if !PREEMPTION |
48 | select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION | |
49 | select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION | |
50 | select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION | |
51 | select ARCH_INLINE_READ_UNLOCK if !PREEMPTION | |
52 | select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION | |
53 | select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION | |
54 | select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION | |
55 | select ARCH_INLINE_WRITE_LOCK if !PREEMPTION | |
56 | select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION | |
57 | select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION | |
58 | select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION | |
59 | select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION | |
60 | select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION | |
61 | select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION | |
62 | select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION | |
63 | select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION | |
64 | select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION | |
65 | select ARCH_INLINE_SPIN_LOCK if !PREEMPTION | |
66 | select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION | |
67 | select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION | |
68 | select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION | |
69 | select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION | |
70 | select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION | |
71 | select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION | |
72 | select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION | |
350e88ba | 73 | select ARCH_KEEP_MEMBLOCK |
c63c8700 | 74 | select ARCH_USE_CMPXCHG_LOCKREF |
bf7f15c5 | 75 | select ARCH_USE_GNU_PROPERTY |
dce44566 | 76 | select ARCH_USE_MEMTEST |
087133ac | 77 | select ARCH_USE_QUEUED_RWLOCKS |
c1109047 | 78 | select ARCH_USE_QUEUED_SPINLOCKS |
50479d58 | 79 | select ARCH_USE_SYM_ANNOTATIONS |
5d6ad668 | 80 | select ARCH_SUPPORTS_DEBUG_PAGEALLOC |
855f9a8e | 81 | select ARCH_SUPPORTS_HUGETLBFS |
c484f256 | 82 | select ARCH_SUPPORTS_MEMORY_FAILURE |
5287569a | 83 | select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK |
112b6a8e ST |
84 | select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN |
85 | select ARCH_SUPPORTS_LTO_CLANG_THIN | |
9186ad8e | 86 | select ARCH_SUPPORTS_CFI_CLANG |
4badad35 | 87 | select ARCH_SUPPORTS_ATOMIC_RMW |
c12d3362 | 88 | select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG) |
56166230 | 89 | select ARCH_SUPPORTS_NUMA_BALANCING |
84c187af | 90 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT |
81c22041 | 91 | select ARCH_WANT_DEFAULT_BPF_JIT |
67f3977f | 92 | select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT |
b6f35981 | 93 | select ARCH_WANT_FRAME_POINTERS |
3876d4a3 | 94 | select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
59612b24 | 95 | select ARCH_WANT_LD_ORPHAN_WARN |
f0b7f8a4 | 96 | select ARCH_HAS_UBSAN_SANITIZE_ALL |
25c92a37 | 97 | select ARM_AMBA |
1aee5d7a | 98 | select ARM_ARCH_TIMER |
c4188edc | 99 | select ARM_GIC |
875cbf3e | 100 | select AUDIT_ARCH_COMPAT_GENERIC |
3ee80364 | 101 | select ARM_GIC_V2M if PCI |
021f6537 | 102 | select ARM_GIC_V3 |
3ee80364 | 103 | select ARM_GIC_V3_ITS if PCI |
bff60792 | 104 | select ARM_PSCI_FW |
10916706 | 105 | select BUILDTIME_TABLE_SORT |
db2789b5 | 106 | select CLONE_BACKWARDS |
7ca2ef33 | 107 | select COMMON_CLK |
166936ba | 108 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7481cddf | 109 | select CRC32 |
7bc13fd3 | 110 | select DCACHE_WORD_ACCESS |
0c3b3171 | 111 | select DMA_DIRECT_REMAP |
ef37566c | 112 | select EDAC_SUPPORT |
2f34f173 | 113 | select FRAME_POINTER |
d4932f9e | 114 | select GENERIC_ALLOCATOR |
2ef7a295 | 115 | select GENERIC_ARCH_TOPOLOGY |
4b3dc967 | 116 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 117 | select GENERIC_CPU_AUTOPROBE |
61ae1321 | 118 | select GENERIC_CPU_VULNERABILITIES |
bf4b558e | 119 | select GENERIC_EARLY_IOREMAP |
98c5ec77 | 120 | select GENERIC_FIND_FIRST_BIT |
2314ee4d | 121 | select GENERIC_IDLE_POLL_SETUP |
d3afc7f1 | 122 | select GENERIC_IRQ_IPI |
8c2c3df3 CM |
123 | select GENERIC_IRQ_PROBE |
124 | select GENERIC_IRQ_SHOW | |
6544e67b | 125 | select GENERIC_IRQ_SHOW_LEVEL |
6585bd82 | 126 | select GENERIC_LIB_DEVMEM_IS_ALLOWED |
cb61f676 | 127 | select GENERIC_PCI_IOMAP |
102f45fd | 128 | select GENERIC_PTDUMP |
65cd4f6c | 129 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 130 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
131 | select GENERIC_STRNCPY_FROM_USER |
132 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 133 | select GENERIC_TIME_VSYSCALL |
28b1a824 | 134 | select GENERIC_GETTIMEOFDAY |
9614cc57 | 135 | select GENERIC_VDSO_TIME_NS |
a1ddc74a | 136 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 137 | select HARDIRQS_SW_RESEND |
45544eee | 138 | select HAVE_MOVE_PMD |
f5308c89 | 139 | select HAVE_MOVE_PUD |
eb01d42a | 140 | select HAVE_PCI |
9f9a35a7 | 141 | select HAVE_ACPI_APEI if (ACPI && EFI) |
5284e1b4 | 142 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 143 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 144 | select HAVE_ARCH_BITREVERSE |
689eae42 | 145 | select HAVE_ARCH_COMPILER_H |
324420bf | 146 | select HAVE_ARCH_HUGE_VMAP |
9732cafd | 147 | select HAVE_ARCH_JUMP_LABEL |
c296146c | 148 | select HAVE_ARCH_JUMP_LABEL_RELATIVE |
e17d8025 | 149 | select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) |
71b613fc | 150 | select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN |
2d4acb90 | 151 | select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN |
94ab5b61 | 152 | select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) |
840b2398 | 153 | select HAVE_ARCH_KFENCE |
9529247d | 154 | select HAVE_ARCH_KGDB |
8f0d3aa9 DC |
155 | select HAVE_ARCH_MMAP_RND_BITS |
156 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT | |
4f5b0c17 | 157 | select HAVE_ARCH_PFN_VALID |
271ca788 | 158 | select HAVE_ARCH_PREL32_RELOCATIONS |
70918779 | 159 | select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET |
a1ae65b2 | 160 | select HAVE_ARCH_SECCOMP_FILTER |
0b3e3366 | 161 | select HAVE_ARCH_STACKLEAK |
9e8084d3 | 162 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
8c2c3df3 | 163 | select HAVE_ARCH_TRACEHOOK |
8ee70879 | 164 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE |
e3067861 | 165 | select HAVE_ARCH_VMAP_STACK |
8ee70879 | 166 | select HAVE_ARM_SMCCC |
2ff2b7ec | 167 | select HAVE_ASM_MODVERSIONS |
6077776b | 168 | select HAVE_EBPF_JIT |
af64d2aa | 169 | select HAVE_C_RECORDMCOUNT |
5284e1b4 | 170 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 171 | select HAVE_CMPXCHG_LOCAL |
8ee70879 | 172 | select HAVE_CONTEXT_TRACKING |
b69ec42b | 173 | select HAVE_DEBUG_KMEMLEAK |
6ac2104d | 174 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 175 | select HAVE_DYNAMIC_FTRACE |
3b23e499 TD |
176 | select HAVE_DYNAMIC_FTRACE_WITH_REGS \ |
177 | if $(cc-option,-fpatchable-function-entry=2) | |
a31d793d ST |
178 | select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ |
179 | if DYNAMIC_FTRACE_WITH_REGS | |
50afc33a | 180 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
67a929e0 | 181 | select HAVE_FAST_GUP |
af64d2aa | 182 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 | 183 | select HAVE_FUNCTION_TRACER |
42d038c4 | 184 | select HAVE_FUNCTION_ERROR_INJECTION |
819e50e2 | 185 | select HAVE_FUNCTION_GRAPH_TRACER |
6b90bd4b | 186 | select HAVE_GCC_PLUGINS |
8c2c3df3 | 187 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
24da208d | 188 | select HAVE_IRQ_TIME_ACCOUNTING |
396a5d4a | 189 | select HAVE_NMI |
55834a77 | 190 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 191 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
192 | select HAVE_PERF_REGS |
193 | select HAVE_PERF_USER_STACK_DUMP | |
0a8ea52c | 194 | select HAVE_REGS_AND_STACK_ACCESS_API |
a823c35f | 195 | select HAVE_FUNCTION_ARG_ACCESS_API |
98346023 | 196 | select HAVE_FUTEX_CMPXCHG if FUTEX |
ff2e6d72 | 197 | select MMU_GATHER_RCU_TABLE_FREE |
409d5db4 | 198 | select HAVE_RSEQ |
d148eac0 | 199 | select HAVE_STACKPROTECTOR |
055b1212 | 200 | select HAVE_SYSCALL_TRACEPOINTS |
2dd0e8d2 | 201 | select HAVE_KPROBES |
cd1ee3b1 | 202 | select HAVE_KRETPROBES |
28b1a824 | 203 | select HAVE_GENERIC_VDSO |
876945db | 204 | select IOMMU_DMA if IOMMU_SUPPORT |
8c2c3df3 | 205 | select IRQ_DOMAIN |
e8557d1f | 206 | select IRQ_FORCED_THREADING |
acc3042d | 207 | select KASAN_VMALLOC if KASAN_GENERIC |
fea2acaa | 208 | select MODULES_USE_ELF_RELA |
f616ab59 | 209 | select NEED_DMA_MAP_STATE |
86596f0a | 210 | select NEED_SG_DMA_LENGTH |
8c2c3df3 CM |
211 | select OF |
212 | select OF_EARLY_FLATTREE | |
2eac9c2d | 213 | select PCI_DOMAINS_GENERIC if PCI |
52146173 | 214 | select PCI_ECAM if (ACPI && PCI) |
20f1b79d | 215 | select PCI_SYSCALL if PCI |
aa1e8ec1 CM |
216 | select POWER_RESET |
217 | select POWER_SUPPLY | |
8c2c3df3 | 218 | select SPARSE_IRQ |
09230cbc | 219 | select SWIOTLB |
7ac57a89 | 220 | select SYSCTL_EXCEPTION_TRACE |
c02433dd | 221 | select THREAD_INFO_IN_TASK |
7677f7fd | 222 | select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD |
8c2c3df3 CM |
223 | help |
224 | ARM 64-bit (AArch64) Linux support. | |
225 | ||
226 | config 64BIT | |
227 | def_bool y | |
228 | ||
8c2c3df3 CM |
229 | config MMU |
230 | def_bool y | |
231 | ||
030c4d24 MR |
232 | config ARM64_PAGE_SHIFT |
233 | int | |
234 | default 16 if ARM64_64K_PAGES | |
235 | default 14 if ARM64_16K_PAGES | |
236 | default 12 | |
237 | ||
c0d6de32 | 238 | config ARM64_CONT_PTE_SHIFT |
030c4d24 MR |
239 | int |
240 | default 5 if ARM64_64K_PAGES | |
241 | default 7 if ARM64_16K_PAGES | |
242 | default 4 | |
243 | ||
e6765941 GS |
244 | config ARM64_CONT_PMD_SHIFT |
245 | int | |
246 | default 5 if ARM64_64K_PAGES | |
247 | default 5 if ARM64_16K_PAGES | |
248 | default 4 | |
249 | ||
8f0d3aa9 DC |
250 | config ARCH_MMAP_RND_BITS_MIN |
251 | default 14 if ARM64_64K_PAGES | |
252 | default 16 if ARM64_16K_PAGES | |
253 | default 18 | |
254 | ||
255 | # max bits determined by the following formula: | |
256 | # VA_BITS - PAGE_SHIFT - 3 | |
257 | config ARCH_MMAP_RND_BITS_MAX | |
258 | default 19 if ARM64_VA_BITS=36 | |
259 | default 24 if ARM64_VA_BITS=39 | |
260 | default 27 if ARM64_VA_BITS=42 | |
261 | default 30 if ARM64_VA_BITS=47 | |
262 | default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES | |
263 | default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES | |
264 | default 33 if ARM64_VA_BITS=48 | |
265 | default 14 if ARM64_64K_PAGES | |
266 | default 16 if ARM64_16K_PAGES | |
267 | default 18 | |
268 | ||
269 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
270 | default 7 if ARM64_64K_PAGES | |
271 | default 9 if ARM64_16K_PAGES | |
272 | default 11 | |
273 | ||
274 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
275 | default 16 | |
276 | ||
ce816fa8 | 277 | config NO_IOPORT_MAP |
d1e6dc91 | 278 | def_bool y if !PCI |
8c2c3df3 CM |
279 | |
280 | config STACKTRACE_SUPPORT | |
281 | def_bool y | |
282 | ||
bf0c4e04 JVS |
283 | config ILLEGAL_POINTER_VALUE |
284 | hex | |
285 | default 0xdead000000000000 | |
286 | ||
8c2c3df3 CM |
287 | config LOCKDEP_SUPPORT |
288 | def_bool y | |
289 | ||
290 | config TRACE_IRQFLAGS_SUPPORT | |
291 | def_bool y | |
292 | ||
9fb7410f DM |
293 | config GENERIC_BUG |
294 | def_bool y | |
295 | depends on BUG | |
296 | ||
297 | config GENERIC_BUG_RELATIVE_POINTERS | |
298 | def_bool y | |
299 | depends on GENERIC_BUG | |
300 | ||
8c2c3df3 CM |
301 | config GENERIC_HWEIGHT |
302 | def_bool y | |
303 | ||
304 | config GENERIC_CSUM | |
305 | def_bool y | |
306 | ||
307 | config GENERIC_CALIBRATE_DELAY | |
308 | def_bool y | |
309 | ||
1a8e1cef NSJ |
310 | config ZONE_DMA |
311 | bool "Support DMA zone" if EXPERT | |
312 | default y | |
313 | ||
ad67f5a6 | 314 | config ZONE_DMA32 |
0c1f14ed MC |
315 | bool "Support DMA32 zone" if EXPERT |
316 | default y | |
8c2c3df3 | 317 | |
ca6e51d5 OS |
318 | config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE |
319 | def_bool y | |
320 | ||
4b3dc967 WD |
321 | config SMP |
322 | def_bool y | |
323 | ||
4cfb3613 AB |
324 | config KERNEL_MODE_NEON |
325 | def_bool y | |
326 | ||
92cc15fc RH |
327 | config FIX_EARLYCON_MEM |
328 | def_bool y | |
329 | ||
9f25e6ad KS |
330 | config PGTABLE_LEVELS |
331 | int | |
21539939 | 332 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad | 333 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
b6d00d47 | 334 | default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) |
9f25e6ad | 335 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 |
44eaacf1 SP |
336 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
337 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 338 | |
9842ceae PA |
339 | config ARCH_SUPPORTS_UPROBES |
340 | def_bool y | |
341 | ||
8f360948 AB |
342 | config ARCH_PROC_KCORE_TEXT |
343 | def_bool y | |
344 | ||
8bf9284d VM |
345 | config BROKEN_GAS_INST |
346 | def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) | |
347 | ||
6bd1d0be SC |
348 | config KASAN_SHADOW_OFFSET |
349 | hex | |
0fea6e9a | 350 | depends on KASAN_GENERIC || KASAN_SW_TAGS |
f4693c27 AB |
351 | default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS |
352 | default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS | |
353 | default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS | |
354 | default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS | |
355 | default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS | |
356 | default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS | |
357 | default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS | |
358 | default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS | |
359 | default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS | |
360 | default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS | |
6bd1d0be SC |
361 | default 0xffffffffffffffff |
362 | ||
6a377491 | 363 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 | 364 | |
8c2c3df3 CM |
365 | menu "Kernel Features" |
366 | ||
c0a01b84 AP |
367 | menu "ARM errata workarounds via the alternatives framework" |
368 | ||
c9460dcb | 369 | config ARM64_WORKAROUND_CLEAN_CACHE |
bc15cf70 | 370 | bool |
c9460dcb | 371 | |
c0a01b84 AP |
372 | config ARM64_ERRATUM_826319 |
373 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
374 | default y | |
c9460dcb | 375 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
376 | help |
377 | This option adds an alternative code sequence to work around ARM | |
378 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
379 | AXI master interface and an L2 cache. | |
380 | ||
381 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
382 | and is unable to accept a certain write via this interface, it will | |
383 | not progress on read data presented on the read data channel and the | |
384 | system can deadlock. | |
385 | ||
386 | The workaround promotes data cache clean instructions to | |
387 | data cache clean-and-invalidate. | |
388 | Please note that this does not necessarily enable the workaround, | |
389 | as it depends on the alternative framework, which will only patch | |
390 | the kernel if an affected CPU is detected. | |
391 | ||
392 | If unsure, say Y. | |
393 | ||
394 | config ARM64_ERRATUM_827319 | |
395 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
396 | default y | |
c9460dcb | 397 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
398 | help |
399 | This option adds an alternative code sequence to work around ARM | |
400 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
401 | master interface and an L2 cache. | |
402 | ||
403 | Under certain conditions this erratum can cause a clean line eviction | |
404 | to occur at the same time as another transaction to the same address | |
405 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
406 | interconnect reorders the two transactions. | |
407 | ||
408 | The workaround promotes data cache clean instructions to | |
409 | data cache clean-and-invalidate. | |
410 | Please note that this does not necessarily enable the workaround, | |
411 | as it depends on the alternative framework, which will only patch | |
412 | the kernel if an affected CPU is detected. | |
413 | ||
414 | If unsure, say Y. | |
415 | ||
416 | config ARM64_ERRATUM_824069 | |
417 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
418 | default y | |
c9460dcb | 419 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
420 | help |
421 | This option adds an alternative code sequence to work around ARM | |
422 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
423 | to a coherent interconnect. | |
424 | ||
425 | If a Cortex-A53 processor is executing a store or prefetch for | |
426 | write instruction at the same time as a processor in another | |
427 | cluster is executing a cache maintenance operation to the same | |
428 | address, then this erratum might cause a clean cache line to be | |
429 | incorrectly marked as dirty. | |
430 | ||
431 | The workaround promotes data cache clean instructions to | |
432 | data cache clean-and-invalidate. | |
433 | Please note that this option does not necessarily enable the | |
434 | workaround, as it depends on the alternative framework, which will | |
435 | only patch the kernel if an affected CPU is detected. | |
436 | ||
437 | If unsure, say Y. | |
438 | ||
439 | config ARM64_ERRATUM_819472 | |
440 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
441 | default y | |
c9460dcb | 442 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
443 | help |
444 | This option adds an alternative code sequence to work around ARM | |
445 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
446 | present when it is connected to a coherent interconnect. | |
447 | ||
448 | If the processor is executing a load and store exclusive sequence at | |
449 | the same time as a processor in another cluster is executing a cache | |
450 | maintenance operation to the same address, then this erratum might | |
451 | cause data corruption. | |
452 | ||
453 | The workaround promotes data cache clean instructions to | |
454 | data cache clean-and-invalidate. | |
455 | Please note that this does not necessarily enable the workaround, | |
456 | as it depends on the alternative framework, which will only patch | |
457 | the kernel if an affected CPU is detected. | |
458 | ||
459 | If unsure, say Y. | |
460 | ||
461 | config ARM64_ERRATUM_832075 | |
462 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
463 | default y | |
464 | help | |
465 | This option adds an alternative code sequence to work around ARM | |
466 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
467 | ||
468 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
469 | instructions to Write-Back memory are mixed with Device loads. | |
470 | ||
471 | The workaround is to promote device loads to use Load-Acquire | |
472 | semantics. | |
473 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
474 | as it depends on the alternative framework, which will only patch |
475 | the kernel if an affected CPU is detected. | |
476 | ||
477 | If unsure, say Y. | |
478 | ||
479 | config ARM64_ERRATUM_834220 | |
480 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" | |
481 | depends on KVM | |
482 | default y | |
483 | help | |
484 | This option adds an alternative code sequence to work around ARM | |
485 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
486 | ||
487 | Affected Cortex-A57 parts might report a Stage 2 translation | |
488 | fault as the result of a Stage 1 fault for load crossing a | |
489 | page boundary when there is a permission or device memory | |
490 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
491 | ||
492 | The workaround is to verify that the Stage 1 translation | |
493 | doesn't generate a fault before handling the Stage 2 fault. | |
494 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
495 | as it depends on the alternative framework, which will only patch |
496 | the kernel if an affected CPU is detected. | |
497 | ||
498 | If unsure, say Y. | |
499 | ||
905e8c5d WD |
500 | config ARM64_ERRATUM_845719 |
501 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
502 | depends on COMPAT | |
503 | default y | |
504 | help | |
505 | This option adds an alternative code sequence to work around ARM | |
506 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
507 | ||
508 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
509 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
510 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
511 | might return incorrect data. | |
512 | ||
513 | The workaround is to write the contextidr_el1 register on exception | |
514 | return to a 32-bit task. | |
515 | Please note that this does not necessarily enable the workaround, | |
516 | as it depends on the alternative framework, which will only patch | |
517 | the kernel if an affected CPU is detected. | |
518 | ||
519 | If unsure, say Y. | |
520 | ||
df057cc7 WD |
521 | config ARM64_ERRATUM_843419 |
522 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
df057cc7 | 523 | default y |
a257e025 | 524 | select ARM64_MODULE_PLTS if MODULES |
df057cc7 | 525 | help |
6ffe9923 | 526 | This option links the kernel with '--fix-cortex-a53-843419' and |
a257e025 AB |
527 | enables PLT support to replace certain ADRP instructions, which can |
528 | cause subsequent memory accesses to use an incorrect address on | |
529 | Cortex-A53 parts up to r0p4. | |
df057cc7 WD |
530 | |
531 | If unsure, say Y. | |
532 | ||
987fdfec MY |
533 | config ARM64_LD_HAS_FIX_ERRATUM_843419 |
534 | def_bool $(ld-option,--fix-cortex-a53-843419) | |
535 | ||
ece1397c SP |
536 | config ARM64_ERRATUM_1024718 |
537 | bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" | |
538 | default y | |
539 | help | |
bc15cf70 | 540 | This option adds a workaround for ARM Cortex-A55 Erratum 1024718. |
ece1397c | 541 | |
c0b15c25 | 542 | Affected Cortex-A55 cores (all revisions) could cause incorrect |
ece1397c | 543 | update of the hardware dirty bit when the DBM/AP bits are updated |
bc15cf70 | 544 | without a break-before-make. The workaround is to disable the usage |
ece1397c | 545 | of hardware DBM locally on the affected cores. CPUs not affected by |
bc15cf70 | 546 | this erratum will continue to use the feature. |
df057cc7 WD |
547 | |
548 | If unsure, say Y. | |
549 | ||
a5325089 | 550 | config ARM64_ERRATUM_1418040 |
6989303a | 551 | bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" |
95b861a4 | 552 | default y |
c2b5bba3 | 553 | depends on COMPAT |
95b861a4 | 554 | help |
24cf262d | 555 | This option adds a workaround for ARM Cortex-A76/Neoverse-N1 |
a5325089 | 556 | errata 1188873 and 1418040. |
95b861a4 | 557 | |
a5325089 | 558 | Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could |
6989303a MZ |
559 | cause register corruption when accessing the timer registers |
560 | from AArch32 userspace. | |
95b861a4 MZ |
561 | |
562 | If unsure, say Y. | |
563 | ||
02ab1f50 | 564 | config ARM64_WORKAROUND_SPECULATIVE_AT |
e85d68fa SP |
565 | bool |
566 | ||
a457b0f7 | 567 | config ARM64_ERRATUM_1165522 |
02ab1f50 | 568 | bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" |
a457b0f7 | 569 | default y |
02ab1f50 | 570 | select ARM64_WORKAROUND_SPECULATIVE_AT |
a457b0f7 | 571 | help |
bc15cf70 | 572 | This option adds a workaround for ARM Cortex-A76 erratum 1165522. |
a457b0f7 MZ |
573 | |
574 | Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with | |
575 | corrupted TLBs by speculating an AT instruction during a guest | |
576 | context switch. | |
577 | ||
578 | If unsure, say Y. | |
579 | ||
02ab1f50 AS |
580 | config ARM64_ERRATUM_1319367 |
581 | bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" | |
582 | default y | |
583 | select ARM64_WORKAROUND_SPECULATIVE_AT | |
584 | help | |
585 | This option adds work arounds for ARM Cortex-A57 erratum 1319537 | |
586 | and A72 erratum 1319367 | |
587 | ||
588 | Cortex-A57 and A72 cores could end-up with corrupted TLBs by | |
589 | speculating an AT instruction during a guest context switch. | |
590 | ||
591 | If unsure, say Y. | |
592 | ||
275fa0ea | 593 | config ARM64_ERRATUM_1530923 |
02ab1f50 | 594 | bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" |
275fa0ea | 595 | default y |
02ab1f50 | 596 | select ARM64_WORKAROUND_SPECULATIVE_AT |
275fa0ea SP |
597 | help |
598 | This option adds a workaround for ARM Cortex-A55 erratum 1530923. | |
599 | ||
600 | Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with | |
601 | corrupted TLBs by speculating an AT instruction during a guest | |
602 | context switch. | |
603 | ||
604 | If unsure, say Y. | |
a457b0f7 | 605 | |
ebcea694 GU |
606 | config ARM64_WORKAROUND_REPEAT_TLBI |
607 | bool | |
608 | ||
ce8c80c5 CM |
609 | config ARM64_ERRATUM_1286807 |
610 | bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" | |
611 | default y | |
612 | select ARM64_WORKAROUND_REPEAT_TLBI | |
613 | help | |
bc15cf70 | 614 | This option adds a workaround for ARM Cortex-A76 erratum 1286807. |
ce8c80c5 CM |
615 | |
616 | On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual | |
617 | address for a cacheable mapping of a location is being | |
618 | accessed by a core while another core is remapping the virtual | |
619 | address to a new physical page using the recommended | |
620 | break-before-make sequence, then under very rare circumstances | |
621 | TLBI+DSB completes before a read using the translation being | |
622 | invalidated has been observed by other observers. The | |
623 | workaround repeats the TLBI+DSB operation. | |
624 | ||
969f5ea6 WD |
625 | config ARM64_ERRATUM_1463225 |
626 | bool "Cortex-A76: Software Step might prevent interrupt recognition" | |
627 | default y | |
628 | help | |
629 | This option adds a workaround for Arm Cortex-A76 erratum 1463225. | |
630 | ||
631 | On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping | |
632 | of a system call instruction (SVC) can prevent recognition of | |
633 | subsequent interrupts when software stepping is disabled in the | |
634 | exception handler of the system call and either kernel debugging | |
635 | is enabled or VHE is in use. | |
636 | ||
637 | Work around the erratum by triggering a dummy step exception | |
638 | when handling a system call from a task that is being stepped | |
639 | in a VHE configuration of the kernel. | |
640 | ||
641 | If unsure, say Y. | |
642 | ||
05460849 JM |
643 | config ARM64_ERRATUM_1542419 |
644 | bool "Neoverse-N1: workaround mis-ordering of instruction fetches" | |
645 | default y | |
646 | help | |
647 | This option adds a workaround for ARM Neoverse-N1 erratum | |
648 | 1542419. | |
649 | ||
650 | Affected Neoverse-N1 cores could execute a stale instruction when | |
651 | modified by another CPU. The workaround depends on a firmware | |
652 | counterpart. | |
653 | ||
654 | Workaround the issue by hiding the DIC feature from EL0. This | |
655 | forces user-space to perform cache maintenance. | |
656 | ||
657 | If unsure, say Y. | |
658 | ||
96d389ca RH |
659 | config ARM64_ERRATUM_1508412 |
660 | bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" | |
661 | default y | |
662 | help | |
663 | This option adds a workaround for Arm Cortex-A77 erratum 1508412. | |
664 | ||
665 | Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence | |
666 | of a store-exclusive or read of PAR_EL1 and a load with device or | |
667 | non-cacheable memory attributes. The workaround depends on a firmware | |
668 | counterpart. | |
669 | ||
670 | KVM guests must also have the workaround implemented or they can | |
671 | deadlock the system. | |
672 | ||
673 | Work around the issue by inserting DMB SY barriers around PAR_EL1 | |
674 | register reads and warning KVM users. The DMB barrier is sufficient | |
675 | to prevent a speculative PAR_EL1 read. | |
676 | ||
677 | If unsure, say Y. | |
678 | ||
94100970 RR |
679 | config CAVIUM_ERRATUM_22375 |
680 | bool "Cavium erratum 22375, 24313" | |
681 | default y | |
682 | help | |
bc15cf70 | 683 | Enable workaround for errata 22375 and 24313. |
94100970 RR |
684 | |
685 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
bc15cf70 | 686 | with a small impact affecting only ITS table allocation. |
94100970 RR |
687 | |
688 | erratum 22375: only alloc 8MB table size | |
689 | erratum 24313: ignore memory access type | |
690 | ||
691 | The fixes are in ITS initialization and basically ignore memory access | |
692 | type and table size provided by the TYPER and BASER registers. | |
693 | ||
694 | If unsure, say Y. | |
695 | ||
fbf8f40e GK |
696 | config CAVIUM_ERRATUM_23144 |
697 | bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" | |
698 | depends on NUMA | |
699 | default y | |
700 | help | |
701 | ITS SYNC command hang for cross node io and collections/cpu mapping. | |
702 | ||
703 | If unsure, say Y. | |
704 | ||
6d4e11c5 RR |
705 | config CAVIUM_ERRATUM_23154 |
706 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" | |
707 | default y | |
708 | help | |
709 | The gicv3 of ThunderX requires a modified version for | |
710 | reading the IAR status to ensure data synchronization | |
711 | (access to icc_iar1_el1 is not sync'ed before and after). | |
712 | ||
713 | If unsure, say Y. | |
714 | ||
104a0c02 AP |
715 | config CAVIUM_ERRATUM_27456 |
716 | bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" | |
717 | default y | |
718 | help | |
719 | On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI | |
720 | instructions may cause the icache to become corrupted if it | |
721 | contains data for a non-current ASID. The fix is to | |
722 | invalidate the icache when changing the mm context. | |
723 | ||
724 | If unsure, say Y. | |
725 | ||
690a3415 DD |
726 | config CAVIUM_ERRATUM_30115 |
727 | bool "Cavium erratum 30115: Guest may disable interrupts in host" | |
728 | default y | |
729 | help | |
730 | On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through | |
731 | 1.2, and T83 Pass 1.0, KVM guest execution may disable | |
732 | interrupts in host. Trapping both GICv3 group-0 and group-1 | |
733 | accesses sidesteps the issue. | |
734 | ||
735 | If unsure, say Y. | |
736 | ||
603afdc9 MZ |
737 | config CAVIUM_TX2_ERRATUM_219 |
738 | bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" | |
739 | default y | |
740 | help | |
741 | On Cavium ThunderX2, a load, store or prefetch instruction between a | |
742 | TTBR update and the corresponding context synchronizing operation can | |
743 | cause a spurious Data Abort to be delivered to any hardware thread in | |
744 | the CPU core. | |
745 | ||
746 | Work around the issue by avoiding the problematic code sequence and | |
747 | trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The | |
748 | trap handler performs the corresponding register access, skips the | |
749 | instruction and ensures context synchronization by virtue of the | |
750 | exception return. | |
751 | ||
752 | If unsure, say Y. | |
753 | ||
ebcea694 GU |
754 | config FUJITSU_ERRATUM_010001 |
755 | bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" | |
756 | default y | |
757 | help | |
758 | This option adds a workaround for Fujitsu-A64FX erratum E#010001. | |
759 | On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory | |
760 | accesses may cause undefined fault (Data abort, DFSC=0b111111). | |
761 | This fault occurs under a specific hardware condition when a | |
762 | load/store instruction performs an address translation using: | |
763 | case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. | |
764 | case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. | |
765 | case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. | |
766 | case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. | |
767 | ||
768 | The workaround is to ensure these bits are clear in TCR_ELx. | |
769 | The workaround only affects the Fujitsu-A64FX. | |
770 | ||
771 | If unsure, say Y. | |
772 | ||
773 | config HISILICON_ERRATUM_161600802 | |
774 | bool "Hip07 161600802: Erroneous redistributor VLPI base" | |
775 | default y | |
776 | help | |
777 | The HiSilicon Hip07 SoC uses the wrong redistributor base | |
778 | when issued ITS commands such as VMOVP and VMAPP, and requires | |
779 | a 128kB offset to be applied to the target address in this commands. | |
780 | ||
781 | If unsure, say Y. | |
782 | ||
38fd94b0 CC |
783 | config QCOM_FALKOR_ERRATUM_1003 |
784 | bool "Falkor E1003: Incorrect translation due to ASID change" | |
785 | default y | |
38fd94b0 CC |
786 | help |
787 | On Falkor v1, an incorrect ASID may be cached in the TLB when ASID | |
d1777e68 WD |
788 | and BADDR are changed together in TTBRx_EL1. Since we keep the ASID |
789 | in TTBR1_EL1, this situation only occurs in the entry trampoline and | |
790 | then only for entries in the walk cache, since the leaf translation | |
791 | is unchanged. Work around the erratum by invalidating the walk cache | |
792 | entries for the trampoline before entering the kernel proper. | |
38fd94b0 | 793 | |
d9ff80f8 CC |
794 | config QCOM_FALKOR_ERRATUM_1009 |
795 | bool "Falkor E1009: Prematurely complete a DSB after a TLBI" | |
796 | default y | |
ce8c80c5 | 797 | select ARM64_WORKAROUND_REPEAT_TLBI |
d9ff80f8 CC |
798 | help |
799 | On Falkor v1, the CPU may prematurely complete a DSB following a | |
800 | TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation | |
801 | one more time to fix the issue. | |
802 | ||
803 | If unsure, say Y. | |
804 | ||
90922a2d SD |
805 | config QCOM_QDF2400_ERRATUM_0065 |
806 | bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" | |
807 | default y | |
808 | help | |
809 | On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports | |
810 | ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have | |
811 | been indicated as 16Bytes (0xf), not 8Bytes (0x7). | |
812 | ||
813 | If unsure, say Y. | |
814 | ||
932b50c7 SD |
815 | config QCOM_FALKOR_ERRATUM_E1041 |
816 | bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" | |
817 | default y | |
818 | help | |
819 | Falkor CPU may speculatively fetch instructions from an improper | |
820 | memory location when MMU translation is changed from SCTLR_ELn[M]=1 | |
821 | to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. | |
822 | ||
823 | If unsure, say Y. | |
824 | ||
20109a85 RW |
825 | config NVIDIA_CARMEL_CNP_ERRATUM |
826 | bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" | |
827 | default y | |
828 | help | |
829 | If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not | |
830 | invalidate shared TLB entries installed by a different core, as it would | |
831 | on standard ARM cores. | |
832 | ||
833 | If unsure, say Y. | |
834 | ||
ebcea694 GU |
835 | config SOCIONEXT_SYNQUACER_PREITS |
836 | bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" | |
3e32131a ZL |
837 | default y |
838 | help | |
ebcea694 GU |
839 | Socionext Synquacer SoCs implement a separate h/w block to generate |
840 | MSI doorbell writes with non-zero values for the device ID. | |
3e32131a ZL |
841 | |
842 | If unsure, say Y. | |
843 | ||
c0a01b84 AP |
844 | endmenu |
845 | ||
846 | ||
e41ceed0 JL |
847 | choice |
848 | prompt "Page size" | |
849 | default ARM64_4K_PAGES | |
850 | help | |
851 | Page size (translation granule) configuration. | |
852 | ||
853 | config ARM64_4K_PAGES | |
854 | bool "4KB" | |
855 | help | |
856 | This feature enables 4KB pages support. | |
857 | ||
44eaacf1 SP |
858 | config ARM64_16K_PAGES |
859 | bool "16KB" | |
860 | help | |
861 | The system will use 16KB pages support. AArch32 emulation | |
862 | requires applications compiled with 16K (or a multiple of 16K) | |
863 | aligned segments. | |
864 | ||
8c2c3df3 | 865 | config ARM64_64K_PAGES |
e41ceed0 | 866 | bool "64KB" |
8c2c3df3 CM |
867 | help |
868 | This feature enables 64KB pages support (4KB by default) | |
869 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
870 | look-up. AArch32 emulation requires applications compiled |
871 | with 64K aligned segments. | |
8c2c3df3 | 872 | |
e41ceed0 JL |
873 | endchoice |
874 | ||
875 | choice | |
876 | prompt "Virtual address space size" | |
877 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 878 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
879 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
880 | help | |
881 | Allows choosing one of multiple possible virtual address | |
882 | space sizes. The level of translation table is determined by | |
883 | a combination of page size and virtual address space size. | |
884 | ||
21539939 | 885 | config ARM64_VA_BITS_36 |
56a3f30e | 886 | bool "36-bit" if EXPERT |
21539939 SP |
887 | depends on ARM64_16K_PAGES |
888 | ||
e41ceed0 JL |
889 | config ARM64_VA_BITS_39 |
890 | bool "39-bit" | |
891 | depends on ARM64_4K_PAGES | |
892 | ||
893 | config ARM64_VA_BITS_42 | |
894 | bool "42-bit" | |
895 | depends on ARM64_64K_PAGES | |
896 | ||
44eaacf1 SP |
897 | config ARM64_VA_BITS_47 |
898 | bool "47-bit" | |
899 | depends on ARM64_16K_PAGES | |
900 | ||
c79b954b JL |
901 | config ARM64_VA_BITS_48 |
902 | bool "48-bit" | |
c79b954b | 903 | |
b6d00d47 SC |
904 | config ARM64_VA_BITS_52 |
905 | bool "52-bit" | |
68d23da4 WD |
906 | depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) |
907 | help | |
908 | Enable 52-bit virtual addressing for userspace when explicitly | |
b6d00d47 SC |
909 | requested via a hint to mmap(). The kernel will also use 52-bit |
910 | virtual addresses for its own mappings (provided HW support for | |
911 | this feature is available, otherwise it reverts to 48-bit). | |
68d23da4 WD |
912 | |
913 | NOTE: Enabling 52-bit virtual addressing in conjunction with | |
914 | ARMv8.3 Pointer Authentication will result in the PAC being | |
915 | reduced from 7 bits to 3 bits, which may have a significant | |
916 | impact on its susceptibility to brute-force attacks. | |
917 | ||
918 | If unsure, select 48-bit virtual addressing instead. | |
919 | ||
e41ceed0 JL |
920 | endchoice |
921 | ||
68d23da4 WD |
922 | config ARM64_FORCE_52BIT |
923 | bool "Force 52-bit virtual addresses for userspace" | |
b6d00d47 | 924 | depends on ARM64_VA_BITS_52 && EXPERT |
68d23da4 WD |
925 | help |
926 | For systems with 52-bit userspace VAs enabled, the kernel will attempt | |
927 | to maintain compatibility with older software by providing 48-bit VAs | |
928 | unless a hint is supplied to mmap. | |
929 | ||
930 | This configuration option disables the 48-bit compatibility logic, and | |
931 | forces all userspace addresses to be 52-bit on HW that supports it. One | |
932 | should only enable this configuration option for stress testing userspace | |
933 | memory management code. If unsure say N here. | |
934 | ||
e41ceed0 JL |
935 | config ARM64_VA_BITS |
936 | int | |
21539939 | 937 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
938 | default 39 if ARM64_VA_BITS_39 |
939 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 940 | default 47 if ARM64_VA_BITS_47 |
b6d00d47 SC |
941 | default 48 if ARM64_VA_BITS_48 |
942 | default 52 if ARM64_VA_BITS_52 | |
e41ceed0 | 943 | |
982aa7c5 KM |
944 | choice |
945 | prompt "Physical address space size" | |
946 | default ARM64_PA_BITS_48 | |
947 | help | |
948 | Choose the maximum physical address range that the kernel will | |
949 | support. | |
950 | ||
951 | config ARM64_PA_BITS_48 | |
952 | bool "48-bit" | |
953 | ||
f77d2817 KM |
954 | config ARM64_PA_BITS_52 |
955 | bool "52-bit (ARMv8.2)" | |
956 | depends on ARM64_64K_PAGES | |
957 | depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN | |
958 | help | |
959 | Enable support for a 52-bit physical address space, introduced as | |
960 | part of the ARMv8.2-LPA extension. | |
961 | ||
962 | With this enabled, the kernel will also continue to work on CPUs that | |
963 | do not support ARMv8.2-LPA, but with some added memory overhead (and | |
964 | minor performance overhead). | |
965 | ||
982aa7c5 KM |
966 | endchoice |
967 | ||
968 | config ARM64_PA_BITS | |
969 | int | |
970 | default 48 if ARM64_PA_BITS_48 | |
f77d2817 | 971 | default 52 if ARM64_PA_BITS_52 |
982aa7c5 | 972 | |
d8e85e14 AR |
973 | choice |
974 | prompt "Endianness" | |
975 | default CPU_LITTLE_ENDIAN | |
976 | help | |
977 | Select the endianness of data accesses performed by the CPU. Userspace | |
978 | applications will need to be compiled and linked for the endianness | |
979 | that is selected here. | |
980 | ||
a872013d | 981 | config CPU_BIG_ENDIAN |
e9c6deee NC |
982 | bool "Build big-endian kernel" |
983 | depends on !LD_IS_LLD || LLD_VERSION >= 130000 | |
984 | help | |
d8e85e14 AR |
985 | Say Y if you plan on running a kernel with a big-endian userspace. |
986 | ||
987 | config CPU_LITTLE_ENDIAN | |
988 | bool "Build little-endian kernel" | |
989 | help | |
990 | Say Y if you plan on running a kernel with a little-endian userspace. | |
991 | This is usually the case for distributions targeting arm64. | |
992 | ||
993 | endchoice | |
a872013d | 994 | |
f6e763b9 MB |
995 | config SCHED_MC |
996 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
997 | help |
998 | Multi-core scheduler support improves the CPU scheduler's decision | |
999 | making when dealing with multi-core CPU chips at a cost of slightly | |
1000 | increased overhead in some places. If unsure say N here. | |
1001 | ||
1002 | config SCHED_SMT | |
1003 | bool "SMT scheduler support" | |
f6e763b9 MB |
1004 | help |
1005 | Improves the CPU scheduler's decision making when dealing with | |
1006 | MultiThreading at a cost of slightly increased overhead in some | |
1007 | places. If unsure say N here. | |
1008 | ||
8c2c3df3 | 1009 | config NR_CPUS |
62aa9655 GK |
1010 | int "Maximum number of CPUs (2-4096)" |
1011 | range 2 4096 | |
846a415b | 1012 | default "256" |
8c2c3df3 | 1013 | |
9327e2c6 MR |
1014 | config HOTPLUG_CPU |
1015 | bool "Support for hot-pluggable CPUs" | |
217d453d | 1016 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
1017 | help |
1018 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1019 | can be controlled through /sys/devices/system/cpu. | |
1020 | ||
1a2db300 GK |
1021 | # Common NUMA Features |
1022 | config NUMA | |
4399e6cd | 1023 | bool "NUMA Memory Allocation and Scheduler Support" |
ae3c107c | 1024 | select GENERIC_ARCH_NUMA |
0c2a6cce KW |
1025 | select ACPI_NUMA if ACPI |
1026 | select OF_NUMA | |
1a2db300 | 1027 | help |
4399e6cd | 1028 | Enable NUMA (Non-Uniform Memory Access) support. |
1a2db300 GK |
1029 | |
1030 | The kernel will try to allocate memory used by a CPU on the | |
1031 | local memory of the CPU and add some more | |
1032 | NUMA awareness to the kernel. | |
1033 | ||
1034 | config NODES_SHIFT | |
1035 | int "Maximum NUMA Nodes (as a power of 2)" | |
1036 | range 1 10 | |
2a13c13b | 1037 | default "4" |
1a2db300 GK |
1038 | depends on NEED_MULTIPLE_NODES |
1039 | help | |
1040 | Specify the maximum number of NUMA Nodes available on the target | |
1041 | system. Increases memory reserved to accommodate various tables. | |
1042 | ||
1043 | config USE_PERCPU_NUMA_NODE_ID | |
1044 | def_bool y | |
1045 | depends on NUMA | |
1046 | ||
7af3a0a9 ZL |
1047 | config HAVE_SETUP_PER_CPU_AREA |
1048 | def_bool y | |
1049 | depends on NUMA | |
1050 | ||
1051 | config NEED_PER_CPU_EMBED_FIRST_CHUNK | |
1052 | def_bool y | |
1053 | depends on NUMA | |
1054 | ||
6d526ee2 AB |
1055 | config HOLES_IN_ZONE |
1056 | def_bool y | |
6d526ee2 | 1057 | |
8636a1f9 | 1058 | source "kernel/Kconfig.hz" |
8c2c3df3 | 1059 | |
8c2c3df3 CM |
1060 | config ARCH_SPARSEMEM_ENABLE |
1061 | def_bool y | |
1062 | select SPARSEMEM_VMEMMAP_ENABLE | |
782276b4 | 1063 | select SPARSEMEM_VMEMMAP |
e7d4bac4 | 1064 | |
8c2c3df3 | 1065 | config HW_PERF_EVENTS |
6475b2d8 MR |
1066 | def_bool y |
1067 | depends on ARM_PMU | |
8c2c3df3 | 1068 | |
18107f8a VM |
1069 | config ARCH_HAS_FILTER_PGPROT |
1070 | def_bool y | |
1071 | ||
5287569a ST |
1072 | # Supported by clang >= 7.0 |
1073 | config CC_HAVE_SHADOW_CALL_STACK | |
1074 | def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) | |
1075 | ||
dfd57bc3 SS |
1076 | config PARAVIRT |
1077 | bool "Enable paravirtualization code" | |
1078 | help | |
1079 | This changes the kernel so it can modify itself when it is run | |
1080 | under a hypervisor, potentially improving performance significantly | |
1081 | over full virtualization. | |
1082 | ||
1083 | config PARAVIRT_TIME_ACCOUNTING | |
1084 | bool "Paravirtual steal time accounting" | |
1085 | select PARAVIRT | |
dfd57bc3 SS |
1086 | help |
1087 | Select this option to enable fine granularity task steal time | |
1088 | accounting. Time spent executing other tasks in parallel with | |
1089 | the current vCPU is discounted from the vCPU power. To account for | |
1090 | that, there can be a small performance impact. | |
1091 | ||
1092 | If in doubt, say N here. | |
1093 | ||
d28f6df1 GL |
1094 | config KEXEC |
1095 | depends on PM_SLEEP_SMP | |
1096 | select KEXEC_CORE | |
1097 | bool "kexec system call" | |
a7f7f624 | 1098 | help |
d28f6df1 GL |
1099 | kexec is a system call that implements the ability to shutdown your |
1100 | current kernel, and to start another kernel. It is like a reboot | |
1101 | but it is independent of the system firmware. And like a reboot | |
1102 | you can start any kernel with it, not just Linux. | |
1103 | ||
3ddd9992 AT |
1104 | config KEXEC_FILE |
1105 | bool "kexec file based system call" | |
1106 | select KEXEC_CORE | |
dce92f6b | 1107 | select HAVE_IMA_KEXEC if IMA |
3ddd9992 AT |
1108 | help |
1109 | This is new version of kexec system call. This system call is | |
1110 | file based and takes file descriptors as system call argument | |
1111 | for kernel and initramfs as opposed to list of segments as | |
1112 | accepted by previous system call. | |
1113 | ||
99d5cadf | 1114 | config KEXEC_SIG |
732b7b93 AT |
1115 | bool "Verify kernel signature during kexec_file_load() syscall" |
1116 | depends on KEXEC_FILE | |
1117 | help | |
1118 | Select this option to verify a signature with loaded kernel | |
1119 | image. If configured, any attempt of loading a image without | |
1120 | valid signature will fail. | |
1121 | ||
1122 | In addition to that option, you need to enable signature | |
1123 | verification for the corresponding kernel image type being | |
1124 | loaded in order for this to work. | |
1125 | ||
1126 | config KEXEC_IMAGE_VERIFY_SIG | |
1127 | bool "Enable Image signature verification support" | |
1128 | default y | |
99d5cadf | 1129 | depends on KEXEC_SIG |
732b7b93 AT |
1130 | depends on EFI && SIGNED_PE_FILE_VERIFICATION |
1131 | help | |
1132 | Enable Image signature verification support. | |
1133 | ||
1134 | comment "Support for PE file signature verification disabled" | |
99d5cadf | 1135 | depends on KEXEC_SIG |
732b7b93 AT |
1136 | depends on !EFI || !SIGNED_PE_FILE_VERIFICATION |
1137 | ||
e62aaeac AT |
1138 | config CRASH_DUMP |
1139 | bool "Build kdump crash kernel" | |
1140 | help | |
1141 | Generate crash dump after being started by kexec. This should | |
1142 | be normally only set in special crash dump kernels which are | |
1143 | loaded in the main kernel with kexec-tools into a specially | |
1144 | reserved region and then later executed after a crash by | |
1145 | kdump/kexec. | |
1146 | ||
330d4810 | 1147 | For more details see Documentation/admin-guide/kdump/kdump.rst |
e62aaeac | 1148 | |
072e3d96 PT |
1149 | config TRANS_TABLE |
1150 | def_bool y | |
1151 | depends on HIBERNATION | |
1152 | ||
aa42aa13 SS |
1153 | config XEN_DOM0 |
1154 | def_bool y | |
1155 | depends on XEN | |
1156 | ||
1157 | config XEN | |
c2ba1f7d | 1158 | bool "Xen guest support on ARM64" |
aa42aa13 | 1159 | depends on ARM64 && OF |
83862ccf | 1160 | select SWIOTLB_XEN |
dfd57bc3 | 1161 | select PARAVIRT |
aa42aa13 SS |
1162 | help |
1163 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
1164 | ||
d03bb145 SC |
1165 | config FORCE_MAX_ZONEORDER |
1166 | int | |
79cc2ed5 AK |
1167 | default "14" if ARM64_64K_PAGES |
1168 | default "12" if ARM64_16K_PAGES | |
d03bb145 | 1169 | default "11" |
44eaacf1 SP |
1170 | help |
1171 | The kernel memory allocator divides physically contiguous memory | |
1172 | blocks into "zones", where each zone is a power of two number of | |
1173 | pages. This option selects the largest power of two that the kernel | |
1174 | keeps in the memory allocator. If you need to allocate very large | |
1175 | blocks of physically contiguous memory, then you may need to | |
1176 | increase this value. | |
1177 | ||
1178 | This config option is actually maximum order plus one. For example, | |
1179 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1180 | ||
1181 | We make sure that we can allocate upto a HugePage size for each configuration. | |
1182 | Hence we have : | |
1183 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 | |
1184 | ||
1185 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us | |
1186 | 4M allocations matching the default size used by generic code. | |
d03bb145 | 1187 | |
084eb77c | 1188 | config UNMAP_KERNEL_AT_EL0 |
0617052d | 1189 | bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT |
084eb77c WD |
1190 | default y |
1191 | help | |
0617052d WD |
1192 | Speculation attacks against some high-performance processors can |
1193 | be used to bypass MMU permission checks and leak kernel data to | |
1194 | userspace. This can be defended against by unmapping the kernel | |
1195 | when running in userspace, mapping it back in on exception entry | |
1196 | via a trampoline page in the vector table. | |
084eb77c WD |
1197 | |
1198 | If unsure, say Y. | |
1199 | ||
c55191e9 AB |
1200 | config RODATA_FULL_DEFAULT_ENABLED |
1201 | bool "Apply r/o permissions of VM areas also to their linear aliases" | |
1202 | default y | |
1203 | help | |
1204 | Apply read-only attributes of VM areas to the linear alias of | |
1205 | the backing pages as well. This prevents code or read-only data | |
1206 | from being modified (inadvertently or intentionally) via another | |
1207 | mapping of the same memory page. This additional enhancement can | |
1208 | be turned off at runtime by passing rodata=[off|on] (and turned on | |
1209 | with rodata=full if this option is set to 'n') | |
1210 | ||
1211 | This requires the linear region to be mapped down to pages, | |
1212 | which may adversely affect performance in some cases. | |
1213 | ||
dd523791 WD |
1214 | config ARM64_SW_TTBR0_PAN |
1215 | bool "Emulate Privileged Access Never using TTBR0_EL1 switching" | |
1216 | help | |
1217 | Enabling this option prevents the kernel from accessing | |
1218 | user-space memory directly by pointing TTBR0_EL1 to a reserved | |
1219 | zeroed area and reserved ASID. The user access routines | |
1220 | restore the valid TTBR0_EL1 temporarily. | |
1221 | ||
63f0c603 CM |
1222 | config ARM64_TAGGED_ADDR_ABI |
1223 | bool "Enable the tagged user addresses syscall ABI" | |
1224 | default y | |
1225 | help | |
1226 | When this option is enabled, user applications can opt in to a | |
1227 | relaxed ABI via prctl() allowing tagged addresses to be passed | |
1228 | to system calls as pointer arguments. For details, see | |
799c8510 | 1229 | Documentation/arm64/tagged-address-abi.rst. |
63f0c603 | 1230 | |
dd523791 WD |
1231 | menuconfig COMPAT |
1232 | bool "Kernel support for 32-bit EL0" | |
1233 | depends on ARM64_4K_PAGES || EXPERT | |
dd523791 WD |
1234 | select HAVE_UID16 |
1235 | select OLD_SIGSUSPEND3 | |
1236 | select COMPAT_OLD_SIGACTION | |
1237 | help | |
1238 | This option enables support for a 32-bit EL0 running under a 64-bit | |
1239 | kernel at EL1. AArch32-specific components such as system calls, | |
1240 | the user helper functions, VFP support and the ptrace interface are | |
1241 | handled appropriately by the kernel. | |
1242 | ||
1243 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware | |
1244 | that you will only be able to execute AArch32 binaries that were compiled | |
1245 | with page size aligned segments. | |
1246 | ||
1247 | If you want to execute 32-bit userspace applications, say Y. | |
1248 | ||
1249 | if COMPAT | |
1250 | ||
1251 | config KUSER_HELPERS | |
7c4791c9 | 1252 | bool "Enable kuser helpers page for 32-bit applications" |
dd523791 WD |
1253 | default y |
1254 | help | |
1255 | Warning: disabling this option may break 32-bit user programs. | |
1256 | ||
1257 | Provide kuser helpers to compat tasks. The kernel provides | |
1258 | helper code to userspace in read only form at a fixed location | |
1259 | to allow userspace to be independent of the CPU type fitted to | |
1260 | the system. This permits binaries to be run on ARMv4 through | |
1261 | to ARMv8 without modification. | |
1262 | ||
dc7a12bd | 1263 | See Documentation/arm/kernel_user_helpers.rst for details. |
dd523791 WD |
1264 | |
1265 | However, the fixed address nature of these helpers can be used | |
1266 | by ROP (return orientated programming) authors when creating | |
1267 | exploits. | |
1268 | ||
1269 | If all of the binaries and libraries which run on your platform | |
1270 | are built specifically for your platform, and make no use of | |
1271 | these helpers, then you can turn this option off to hinder | |
1272 | such exploits. However, in that case, if a binary or library | |
1273 | relying on those helpers is run, it will not function correctly. | |
1274 | ||
1275 | Say N here only if you are absolutely certain that you do not | |
1276 | need these helpers; otherwise, the safe option is to say Y. | |
1277 | ||
7c4791c9 WD |
1278 | config COMPAT_VDSO |
1279 | bool "Enable vDSO for 32-bit applications" | |
1280 | depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != "" | |
1281 | select GENERIC_COMPAT_VDSO | |
1282 | default y | |
1283 | help | |
1284 | Place in the process address space of 32-bit applications an | |
1285 | ELF shared object providing fast implementations of gettimeofday | |
1286 | and clock_gettime. | |
1287 | ||
1288 | You must have a 32-bit build of glibc 2.22 or later for programs | |
1289 | to seamlessly take advantage of this. | |
dd523791 | 1290 | |
625412c2 ND |
1291 | config THUMB2_COMPAT_VDSO |
1292 | bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT | |
1293 | depends on COMPAT_VDSO | |
1294 | default y | |
1295 | help | |
1296 | Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, | |
1297 | otherwise with '-marm'. | |
1298 | ||
1b907f46 WD |
1299 | menuconfig ARMV8_DEPRECATED |
1300 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
6cfa7cc4 | 1301 | depends on SYSCTL |
1b907f46 WD |
1302 | help |
1303 | Legacy software support may require certain instructions | |
1304 | that have been deprecated or obsoleted in the architecture. | |
1305 | ||
1306 | Enable this config to enable selective emulation of these | |
1307 | features. | |
1308 | ||
1309 | If unsure, say Y | |
1310 | ||
1311 | if ARMV8_DEPRECATED | |
1312 | ||
1313 | config SWP_EMULATION | |
1314 | bool "Emulate SWP/SWPB instructions" | |
1315 | help | |
1316 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
1317 | they are always undefined. Say Y here to enable software | |
1318 | emulation of these instructions for userspace using LDXR/STXR. | |
dd720784 MB |
1319 | This feature can be controlled at runtime with the abi.swp |
1320 | sysctl which is disabled by default. | |
1b907f46 WD |
1321 | |
1322 | In some older versions of glibc [<=2.8] SWP is used during futex | |
1323 | trylock() operations with the assumption that the code will not | |
1324 | be preempted. This invalid assumption may be more likely to fail | |
1325 | with SWP emulation enabled, leading to deadlock of the user | |
1326 | application. | |
1327 | ||
1328 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
1329 | on an external transaction monitoring block called a global | |
1330 | monitor to maintain update atomicity. If your system does not | |
1331 | implement a global monitor, this option can cause programs that | |
1332 | perform SWP operations to uncached memory to deadlock. | |
1333 | ||
1334 | If unsure, say Y | |
1335 | ||
1336 | config CP15_BARRIER_EMULATION | |
1337 | bool "Emulate CP15 Barrier instructions" | |
1338 | help | |
1339 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
1340 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
1341 | strongly recommended to use the ISB, DSB, and DMB | |
1342 | instructions instead. | |
1343 | ||
1344 | Say Y here to enable software emulation of these | |
1345 | instructions for AArch32 userspace code. When this option is | |
1346 | enabled, CP15 barrier usage is traced which can help | |
dd720784 MB |
1347 | identify software that needs updating. This feature can be |
1348 | controlled at runtime with the abi.cp15_barrier sysctl. | |
1b907f46 WD |
1349 | |
1350 | If unsure, say Y | |
1351 | ||
2d888f48 SP |
1352 | config SETEND_EMULATION |
1353 | bool "Emulate SETEND instruction" | |
1354 | help | |
1355 | The SETEND instruction alters the data-endianness of the | |
1356 | AArch32 EL0, and is deprecated in ARMv8. | |
1357 | ||
1358 | Say Y here to enable software emulation of the instruction | |
dd720784 MB |
1359 | for AArch32 userspace code. This feature can be controlled |
1360 | at runtime with the abi.setend sysctl. | |
2d888f48 SP |
1361 | |
1362 | Note: All the cpus on the system must have mixed endian support at EL0 | |
1363 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
1364 | endian - is hotplugged in after this feature has been enabled, there could | |
1365 | be unexpected results in the applications. | |
1366 | ||
1367 | If unsure, say Y | |
1b907f46 WD |
1368 | endif |
1369 | ||
dd523791 | 1370 | endif |
ba42822a | 1371 | |
0e4a0709 WD |
1372 | menu "ARMv8.1 architectural features" |
1373 | ||
1374 | config ARM64_HW_AFDBM | |
1375 | bool "Support for hardware updates of the Access and Dirty page flags" | |
1376 | default y | |
1377 | help | |
1378 | The ARMv8.1 architecture extensions introduce support for | |
1379 | hardware updates of the access and dirty information in page | |
1380 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
1381 | capable processors, accesses to pages with PTE_AF cleared will | |
1382 | set this bit instead of raising an access flag fault. | |
1383 | Similarly, writes to read-only pages with the DBM bit set will | |
1384 | clear the read-only bit (AP[2]) instead of raising a | |
1385 | permission fault. | |
1386 | ||
1387 | Kernels built with this configuration option enabled continue | |
1388 | to work on pre-ARMv8.1 hardware and the performance impact is | |
1389 | minimal. If unsure, say Y. | |
1390 | ||
1391 | config ARM64_PAN | |
1392 | bool "Enable support for Privileged Access Never (PAN)" | |
1393 | default y | |
1394 | help | |
1395 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
1396 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
1397 | memory directly. | |
1398 | ||
1399 | Choosing this option will cause any unprotected (not using | |
1400 | copy_to_user et al) memory access to fail with a permission fault. | |
1401 | ||
1402 | The feature is detected at runtime, and will remain as a 'nop' | |
1403 | instruction if the cpu does not implement the feature. | |
1404 | ||
364a5a8a WD |
1405 | config AS_HAS_LDAPR |
1406 | def_bool $(as-instr,.arch_extension rcpc) | |
1407 | ||
2decad92 CM |
1408 | config AS_HAS_LSE_ATOMICS |
1409 | def_bool $(as-instr,.arch_extension lse) | |
1410 | ||
0e4a0709 | 1411 | config ARM64_LSE_ATOMICS |
395af861 CM |
1412 | bool |
1413 | default ARM64_USE_LSE_ATOMICS | |
2decad92 | 1414 | depends on AS_HAS_LSE_ATOMICS |
395af861 CM |
1415 | |
1416 | config ARM64_USE_LSE_ATOMICS | |
0e4a0709 | 1417 | bool "Atomic instructions" |
b32baf91 | 1418 | depends on JUMP_LABEL |
7bd99b40 | 1419 | default y |
0e4a0709 WD |
1420 | help |
1421 | As part of the Large System Extensions, ARMv8.1 introduces new | |
1422 | atomic instructions that are designed specifically to scale in | |
1423 | very large systems. | |
1424 | ||
1425 | Say Y here to make use of these instructions for the in-kernel | |
1426 | atomic routines. This incurs a small overhead on CPUs that do | |
1427 | not support these instructions and requires the kernel to be | |
7bd99b40 WD |
1428 | built with binutils >= 2.25 in order for the new instructions |
1429 | to be used. | |
0e4a0709 WD |
1430 | |
1431 | endmenu | |
1432 | ||
f993318b WD |
1433 | menu "ARMv8.2 architectural features" |
1434 | ||
d50e071f RM |
1435 | config ARM64_PMEM |
1436 | bool "Enable support for persistent memory" | |
1437 | select ARCH_HAS_PMEM_API | |
5d7bdeb1 | 1438 | select ARCH_HAS_UACCESS_FLUSHCACHE |
d50e071f RM |
1439 | help |
1440 | Say Y to enable support for the persistent memory API based on the | |
1441 | ARMv8.2 DCPoP feature. | |
1442 | ||
1443 | The feature is detected at runtime, and the kernel will use DC CVAC | |
1444 | operations if DC CVAP is not supported (following the behaviour of | |
1445 | DC CVAP itself if the system does not define a point of persistence). | |
1446 | ||
64c02720 XX |
1447 | config ARM64_RAS_EXTN |
1448 | bool "Enable support for RAS CPU Extensions" | |
1449 | default y | |
1450 | help | |
1451 | CPUs that support the Reliability, Availability and Serviceability | |
1452 | (RAS) Extensions, part of ARMv8.2 are able to track faults and | |
1453 | errors, classify them and report them to software. | |
1454 | ||
1455 | On CPUs with these extensions system software can use additional | |
1456 | barriers to determine if faults are pending and read the | |
1457 | classification from a new set of registers. | |
1458 | ||
1459 | Selecting this feature will allow the kernel to use these barriers | |
1460 | and access the new registers if the system supports the extension. | |
1461 | Platform RAS features may additionally depend on firmware support. | |
1462 | ||
5ffdfaed VM |
1463 | config ARM64_CNP |
1464 | bool "Enable support for Common Not Private (CNP) translations" | |
1465 | default y | |
1466 | depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN | |
1467 | help | |
1468 | Common Not Private (CNP) allows translation table entries to | |
1469 | be shared between different PEs in the same inner shareable | |
1470 | domain, so the hardware can use this fact to optimise the | |
1471 | caching of such entries in the TLB. | |
1472 | ||
1473 | Selecting this option allows the CNP feature to be detected | |
1474 | at runtime, and does not affect PEs that do not implement | |
1475 | this feature. | |
1476 | ||
f993318b WD |
1477 | endmenu |
1478 | ||
04ca3204 MR |
1479 | menu "ARMv8.3 architectural features" |
1480 | ||
1481 | config ARM64_PTR_AUTH | |
1482 | bool "Enable support for pointer authentication" | |
1483 | default y | |
74afda40 | 1484 | depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC |
4dc9b282 | 1485 | # Modern compilers insert a .note.gnu.property section note for PAC |
15cd0e67 | 1486 | # which is only understood by binutils starting with version 2.33.1. |
052c805a | 1487 | depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) |
15cd0e67 | 1488 | depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE |
74afda40 | 1489 | depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) |
04ca3204 MR |
1490 | help |
1491 | Pointer authentication (part of the ARMv8.3 Extensions) provides | |
1492 | instructions for signing and authenticating pointers against secret | |
1493 | keys, which can be used to mitigate Return Oriented Programming (ROP) | |
1494 | and other attacks. | |
1495 | ||
1496 | This option enables these instructions at EL0 (i.e. for userspace). | |
04ca3204 MR |
1497 | Choosing this option will cause the kernel to initialise secret keys |
1498 | for each process at exec() time, with these keys being | |
1499 | context-switched along with the process. | |
1500 | ||
74afda40 KM |
1501 | If the compiler supports the -mbranch-protection or |
1502 | -msign-return-address flag (e.g. GCC 7 or later), then this option | |
1503 | will also cause the kernel itself to be compiled with return address | |
1504 | protection. In this case, and if the target hardware is known to | |
1505 | support pointer authentication, then CONFIG_STACKPROTECTOR can be | |
1506 | disabled with minimal loss of protection. | |
1507 | ||
04ca3204 | 1508 | The feature is detected at runtime. If the feature is not present in |
384b40ca | 1509 | hardware it will not be advertised to userspace/KVM guest nor will it |
dfb0589c | 1510 | be enabled. |
04ca3204 | 1511 | |
6982934e KM |
1512 | If the feature is present on the boot CPU but not on a late CPU, then |
1513 | the late CPU will be parked. Also, if the boot CPU does not have | |
1514 | address auth and the late CPU has then the late CPU will still boot | |
1515 | but with the feature disabled. On such a system, this option should | |
1516 | not be selected. | |
1517 | ||
74afda40 KM |
1518 | This feature works with FUNCTION_GRAPH_TRACER option only if |
1519 | DYNAMIC_FTRACE_WITH_REGS is enabled. | |
1520 | ||
1521 | config CC_HAS_BRANCH_PROT_PAC_RET | |
1522 | # GCC 9 or later, clang 8 or later | |
1523 | def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) | |
1524 | ||
1525 | config CC_HAS_SIGN_RETURN_ADDRESS | |
1526 | # GCC 7, 8 | |
1527 | def_bool $(cc-option,-msign-return-address=all) | |
1528 | ||
1529 | config AS_HAS_PAC | |
4d0831e8 | 1530 | def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) |
74afda40 | 1531 | |
3b446c7d ND |
1532 | config AS_HAS_CFI_NEGATE_RA_STATE |
1533 | def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) | |
1534 | ||
04ca3204 MR |
1535 | endmenu |
1536 | ||
2c9d45b4 IV |
1537 | menu "ARMv8.4 architectural features" |
1538 | ||
1539 | config ARM64_AMU_EXTN | |
1540 | bool "Enable support for the Activity Monitors Unit CPU extension" | |
1541 | default y | |
1542 | help | |
1543 | The activity monitors extension is an optional extension introduced | |
1544 | by the ARMv8.4 CPU architecture. This enables support for version 1 | |
1545 | of the activity monitors architecture, AMUv1. | |
1546 | ||
1547 | To enable the use of this extension on CPUs that implement it, say Y. | |
1548 | ||
1549 | Note that for architectural reasons, firmware _must_ implement AMU | |
1550 | support when running on CPUs that present the activity monitors | |
1551 | extension. The required support is present in: | |
1552 | * Version 1.5 and later of the ARM Trusted Firmware | |
1553 | ||
1554 | For kernels that have this configuration enabled but boot with broken | |
1555 | firmware, you may need to say N here until the firmware is fixed. | |
1556 | Otherwise you may experience firmware panics or lockups when | |
1557 | accessing the counter registers. Even if you are not observing these | |
1558 | symptoms, the values returned by the register reads might not | |
1559 | correctly reflect reality. Most commonly, the value read will be 0, | |
1560 | indicating that the counter is not enabled. | |
1561 | ||
7c78f67e ZY |
1562 | config AS_HAS_ARMV8_4 |
1563 | def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) | |
1564 | ||
1565 | config ARM64_TLB_RANGE | |
1566 | bool "Enable support for tlbi range feature" | |
1567 | default y | |
1568 | depends on AS_HAS_ARMV8_4 | |
1569 | help | |
1570 | ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a | |
1571 | range of input addresses. | |
1572 | ||
1573 | The feature introduces new assembly instructions, and they were | |
1574 | support when binutils >= 2.30. | |
1575 | ||
04ca3204 MR |
1576 | endmenu |
1577 | ||
3e6c69a0 MB |
1578 | menu "ARMv8.5 architectural features" |
1579 | ||
f469c032 VF |
1580 | config AS_HAS_ARMV8_5 |
1581 | def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) | |
1582 | ||
383499f8 DM |
1583 | config ARM64_BTI |
1584 | bool "Branch Target Identification support" | |
1585 | default y | |
1586 | help | |
1587 | Branch Target Identification (part of the ARMv8.5 Extensions) | |
1588 | provides a mechanism to limit the set of locations to which computed | |
1589 | branch instructions such as BR or BLR can jump. | |
1590 | ||
1591 | To make use of BTI on CPUs that support it, say Y. | |
1592 | ||
1593 | BTI is intended to provide complementary protection to other control | |
1594 | flow integrity protection mechanisms, such as the Pointer | |
1595 | authentication mechanism provided as part of the ARMv8.3 Extensions. | |
1596 | For this reason, it does not make sense to enable this option without | |
1597 | also enabling support for pointer authentication. Thus, when | |
1598 | enabling this option you should also select ARM64_PTR_AUTH=y. | |
1599 | ||
1600 | Userspace binaries must also be specifically compiled to make use of | |
1601 | this mechanism. If you say N here or the hardware does not support | |
1602 | BTI, such binaries can still run, but you get no additional | |
1603 | enforcement of branch destinations. | |
1604 | ||
97fed779 MB |
1605 | config ARM64_BTI_KERNEL |
1606 | bool "Use Branch Target Identification for kernel" | |
1607 | default y | |
1608 | depends on ARM64_BTI | |
1609 | depends on ARM64_PTR_AUTH | |
1610 | depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI | |
3a88d7c5 WD |
1611 | # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 |
1612 | depends on !CC_IS_GCC || GCC_VERSION >= 100100 | |
97fed779 MB |
1613 | depends on !(CC_IS_CLANG && GCOV_KERNEL) |
1614 | depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) | |
1615 | help | |
1616 | Build the kernel with Branch Target Identification annotations | |
1617 | and enable enforcement of this for kernel code. When this option | |
1618 | is enabled and the system supports BTI all kernel code including | |
1619 | modular code must have BTI enabled. | |
1620 | ||
1621 | config CC_HAS_BRANCH_PROT_PAC_RET_BTI | |
1622 | # GCC 9 or later, clang 8 or later | |
1623 | def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) | |
1624 | ||
3e6c69a0 MB |
1625 | config ARM64_E0PD |
1626 | bool "Enable support for E0PD" | |
1627 | default y | |
1628 | help | |
e717d93b WD |
1629 | E0PD (part of the ARMv8.5 extensions) allows us to ensure |
1630 | that EL0 accesses made via TTBR1 always fault in constant time, | |
1631 | providing similar benefits to KASLR as those provided by KPTI, but | |
1632 | with lower overhead and without disrupting legitimate access to | |
1633 | kernel memory such as SPE. | |
3e6c69a0 | 1634 | |
e717d93b | 1635 | This option enables E0PD for TTBR1 where available. |
3e6c69a0 | 1636 | |
1a50ec0b RH |
1637 | config ARCH_RANDOM |
1638 | bool "Enable support for random number generation" | |
1639 | default y | |
1640 | help | |
1641 | Random number generation (part of the ARMv8.5 Extensions) | |
1642 | provides a high bandwidth, cryptographically secure | |
1643 | hardware random number generator. | |
1644 | ||
89b94df9 VF |
1645 | config ARM64_AS_HAS_MTE |
1646 | # Initial support for MTE went in binutils 2.32.0, checked with | |
1647 | # ".arch armv8.5-a+memtag" below. However, this was incomplete | |
1648 | # as a late addition to the final architecture spec (LDGM/STGM) | |
1649 | # is only supported in the newer 2.32.x and 2.33 binutils | |
1650 | # versions, hence the extra "stgm" instruction check below. | |
1651 | def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) | |
1652 | ||
1653 | config ARM64_MTE | |
1654 | bool "Memory Tagging Extension support" | |
1655 | default y | |
1656 | depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI | |
f469c032 | 1657 | depends on AS_HAS_ARMV8_5 |
2decad92 | 1658 | depends on AS_HAS_LSE_ATOMICS |
98c970da VF |
1659 | # Required for tag checking in the uaccess routines |
1660 | depends on ARM64_PAN | |
89b94df9 VF |
1661 | select ARCH_USES_HIGH_VMA_FLAGS |
1662 | help | |
1663 | Memory Tagging (part of the ARMv8.5 Extensions) provides | |
1664 | architectural support for run-time, always-on detection of | |
1665 | various classes of memory error to aid with software debugging | |
1666 | to eliminate vulnerabilities arising from memory-unsafe | |
1667 | languages. | |
1668 | ||
1669 | This option enables the support for the Memory Tagging | |
1670 | Extension at EL0 (i.e. for userspace). | |
1671 | ||
1672 | Selecting this option allows the feature to be detected at | |
1673 | runtime. Any secondary CPU not implementing this feature will | |
1674 | not be allowed a late bring-up. | |
1675 | ||
1676 | Userspace binaries that want to use this feature must | |
1677 | explicitly opt in. The mechanism for the userspace is | |
1678 | described in: | |
1679 | ||
1680 | Documentation/arm64/memory-tagging-extension.rst. | |
1681 | ||
3e6c69a0 MB |
1682 | endmenu |
1683 | ||
18107f8a VM |
1684 | menu "ARMv8.7 architectural features" |
1685 | ||
1686 | config ARM64_EPAN | |
1687 | bool "Enable support for Enhanced Privileged Access Never (EPAN)" | |
1688 | default y | |
1689 | depends on ARM64_PAN | |
1690 | help | |
1691 | Enhanced Privileged Access Never (EPAN) allows Privileged | |
1692 | Access Never to be used with Execute-only mappings. | |
1693 | ||
1694 | The feature is detected at runtime, and will remain disabled | |
1695 | if the cpu does not implement the feature. | |
1696 | endmenu | |
1697 | ||
ddd25ad1 DM |
1698 | config ARM64_SVE |
1699 | bool "ARM Scalable Vector Extension support" | |
1700 | default y | |
1701 | help | |
1702 | The Scalable Vector Extension (SVE) is an extension to the AArch64 | |
1703 | execution state which complements and extends the SIMD functionality | |
1704 | of the base architecture to support much larger vectors and to enable | |
1705 | additional vectorisation opportunities. | |
1706 | ||
1707 | To enable use of this extension on CPUs that implement it, say Y. | |
1708 | ||
06a916fe DM |
1709 | On CPUs that support the SVE2 extensions, this option will enable |
1710 | those too. | |
1711 | ||
5043694e DM |
1712 | Note that for architectural reasons, firmware _must_ implement SVE |
1713 | support when running on SVE capable hardware. The required support | |
1714 | is present in: | |
1715 | ||
1716 | * version 1.5 and later of the ARM Trusted Firmware | |
1717 | * the AArch64 boot wrapper since commit 5e1261e08abf | |
1718 | ("bootwrapper: SVE: Enable SVE for EL2 and below"). | |
1719 | ||
1720 | For other firmware implementations, consult the firmware documentation | |
1721 | or vendor. | |
1722 | ||
1723 | If you need the kernel to boot on SVE-capable hardware with broken | |
1724 | firmware, you may need to say N here until you get your firmware | |
1725 | fixed. Otherwise, you may experience firmware panics or lockups when | |
1726 | booting the kernel. If unsure and you are not observing these | |
1727 | symptoms, you should assume that it is safe to say Y. | |
fd045f6c AB |
1728 | |
1729 | config ARM64_MODULE_PLTS | |
58557e48 | 1730 | bool "Use PLTs to allow module memory to spill over into vmalloc area" |
faaa73bc | 1731 | depends on MODULES |
fd045f6c | 1732 | select HAVE_MOD_ARCH_SPECIFIC |
58557e48 FF |
1733 | help |
1734 | Allocate PLTs when loading modules so that jumps and calls whose | |
1735 | targets are too far away for their relative offsets to be encoded | |
1736 | in the instructions themselves can be bounced via veneers in the | |
1737 | module's PLT. This allows modules to be allocated in the generic | |
1738 | vmalloc area after the dedicated module memory area has been | |
1739 | exhausted. | |
1740 | ||
1741 | When running with address space randomization (KASLR), the module | |
1742 | region itself may be too far away for ordinary relative jumps and | |
1743 | calls, and so in that case, module PLTs are required and cannot be | |
1744 | disabled. | |
1745 | ||
1746 | Specific errata workaround(s) might also force module PLTs to be | |
1747 | enabled (ARM64_ERRATUM_843419). | |
fd045f6c | 1748 | |
bc3c03cc JT |
1749 | config ARM64_PSEUDO_NMI |
1750 | bool "Support for NMI-like interrupts" | |
3c9c1dcd | 1751 | select ARM_GIC_V3 |
bc3c03cc JT |
1752 | help |
1753 | Adds support for mimicking Non-Maskable Interrupts through the use of | |
1754 | GIC interrupt priority. This support requires version 3 or later of | |
bc15cf70 | 1755 | ARM GIC. |
bc3c03cc JT |
1756 | |
1757 | This high priority configuration for interrupts needs to be | |
1758 | explicitly enabled by setting the kernel parameter | |
1759 | "irqchip.gicv3_pseudo_nmi" to 1. | |
1760 | ||
1761 | If unsure, say N | |
1762 | ||
48ce8f80 JT |
1763 | if ARM64_PSEUDO_NMI |
1764 | config ARM64_DEBUG_PRIORITY_MASKING | |
1765 | bool "Debug interrupt priority masking" | |
1766 | help | |
1767 | This adds runtime checks to functions enabling/disabling | |
1768 | interrupts when using priority masking. The additional checks verify | |
1769 | the validity of ICC_PMR_EL1 when calling concerned functions. | |
1770 | ||
1771 | If unsure, say N | |
1772 | endif | |
1773 | ||
1e48ef7f | 1774 | config RELOCATABLE |
dd4bc607 | 1775 | bool "Build a relocatable kernel image" if EXPERT |
5cf896fb | 1776 | select ARCH_HAS_RELR |
dd4bc607 | 1777 | default y |
1e48ef7f AB |
1778 | help |
1779 | This builds the kernel as a Position Independent Executable (PIE), | |
1780 | which retains all relocation metadata required to relocate the | |
1781 | kernel binary at runtime to a different virtual address than the | |
1782 | address it was linked at. | |
1783 | Since AArch64 uses the RELA relocation format, this requires a | |
1784 | relocation pass at runtime even if the kernel is loaded at the | |
1785 | same address it was linked at. | |
1786 | ||
f80fb3a3 AB |
1787 | config RANDOMIZE_BASE |
1788 | bool "Randomize the address of the kernel image" | |
b9c220b5 | 1789 | select ARM64_MODULE_PLTS if MODULES |
f80fb3a3 AB |
1790 | select RELOCATABLE |
1791 | help | |
1792 | Randomizes the virtual address at which the kernel image is | |
1793 | loaded, as a security feature that deters exploit attempts | |
1794 | relying on knowledge of the location of kernel internals. | |
1795 | ||
1796 | It is the bootloader's job to provide entropy, by passing a | |
1797 | random u64 value in /chosen/kaslr-seed at kernel entry. | |
1798 | ||
2b5fe07a AB |
1799 | When booting via the UEFI stub, it will invoke the firmware's |
1800 | EFI_RNG_PROTOCOL implementation (if available) to supply entropy | |
1801 | to the kernel proper. In addition, it will randomise the physical | |
1802 | location of the kernel Image as well. | |
1803 | ||
f80fb3a3 AB |
1804 | If unsure, say N. |
1805 | ||
1806 | config RANDOMIZE_MODULE_REGION_FULL | |
f2b9ba87 | 1807 | bool "Randomize the module region over a 4 GB range" |
e71a4e1b | 1808 | depends on RANDOMIZE_BASE |
f80fb3a3 AB |
1809 | default y |
1810 | help | |
f2b9ba87 AB |
1811 | Randomizes the location of the module region inside a 4 GB window |
1812 | covering the core kernel. This way, it is less likely for modules | |
f80fb3a3 AB |
1813 | to leak information about the location of core kernel data structures |
1814 | but it does imply that function calls between modules and the core | |
1815 | kernel will need to be resolved via veneers in the module PLT. | |
1816 | ||
1817 | When this option is not set, the module region will be randomized over | |
1818 | a limited range that contains the [_stext, _etext] interval of the | |
1819 | core kernel, so branch relocations are always in range. | |
1820 | ||
0a1213fa AB |
1821 | config CC_HAVE_STACKPROTECTOR_SYSREG |
1822 | def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) | |
1823 | ||
1824 | config STACKPROTECTOR_PER_TASK | |
1825 | def_bool y | |
1826 | depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG | |
1827 | ||
8c2c3df3 CM |
1828 | endmenu |
1829 | ||
1830 | menu "Boot options" | |
1831 | ||
5e89c55e LP |
1832 | config ARM64_ACPI_PARKING_PROTOCOL |
1833 | bool "Enable support for the ARM64 ACPI parking protocol" | |
1834 | depends on ACPI | |
1835 | help | |
1836 | Enable support for the ARM64 ACPI parking protocol. If disabled | |
1837 | the kernel will not allow booting through the ARM64 ACPI parking | |
1838 | protocol even if the corresponding data is present in the ACPI | |
1839 | MADT table. | |
1840 | ||
8c2c3df3 CM |
1841 | config CMDLINE |
1842 | string "Default kernel command string" | |
1843 | default "" | |
1844 | help | |
1845 | Provide a set of default command-line options at build time by | |
1846 | entering them here. As a minimum, you should specify the the | |
1847 | root device (e.g. root=/dev/nfs). | |
1848 | ||
1e40d105 TH |
1849 | choice |
1850 | prompt "Kernel command line type" if CMDLINE != "" | |
1851 | default CMDLINE_FROM_BOOTLOADER | |
1852 | help | |
1853 | Choose how the kernel will handle the provided default kernel | |
1854 | command line string. | |
1855 | ||
1856 | config CMDLINE_FROM_BOOTLOADER | |
1857 | bool "Use bootloader kernel arguments if available" | |
1858 | help | |
1859 | Uses the command-line options passed by the boot loader. If | |
1860 | the boot loader doesn't provide any, the default kernel command | |
1861 | string provided in CMDLINE will be used. | |
1862 | ||
8c2c3df3 CM |
1863 | config CMDLINE_FORCE |
1864 | bool "Always use the default kernel command string" | |
1865 | help | |
1866 | Always use the default kernel command string, even if the boot | |
1867 | loader passes other arguments to the kernel. | |
1868 | This is useful if you cannot or don't want to change the | |
1869 | command-line options your boot loader passes to the kernel. | |
1870 | ||
1e40d105 TH |
1871 | endchoice |
1872 | ||
f4f75ad5 AB |
1873 | config EFI_STUB |
1874 | bool | |
1875 | ||
f84d0275 MS |
1876 | config EFI |
1877 | bool "UEFI runtime support" | |
1878 | depends on OF && !CPU_BIG_ENDIAN | |
b472db6c | 1879 | depends on KERNEL_MODE_NEON |
2c870e61 | 1880 | select ARCH_SUPPORTS_ACPI |
f84d0275 MS |
1881 | select LIBFDT |
1882 | select UCS2_STRING | |
1883 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 1884 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 | 1885 | select EFI_STUB |
2e0eb483 | 1886 | select EFI_GENERIC_STUB |
8d39cee0 | 1887 | imply IMA_SECURE_AND_OR_TRUSTED_BOOT |
f84d0275 MS |
1888 | default y |
1889 | help | |
1890 | This option provides support for runtime services provided | |
1891 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
1892 | clock, and platform reset). A UEFI stub is also provided to |
1893 | allow the kernel to be booted as an EFI application. This | |
1894 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 1895 | |
d1ae8c00 YL |
1896 | config DMI |
1897 | bool "Enable support for SMBIOS (DMI) tables" | |
1898 | depends on EFI | |
1899 | default y | |
1900 | help | |
1901 | This enables SMBIOS/DMI feature for systems. | |
1902 | ||
1903 | This option is only useful on systems that have UEFI firmware. | |
1904 | However, even with this option, the resultant kernel should | |
1905 | continue to boot on existing non-UEFI platforms. | |
1906 | ||
8c2c3df3 CM |
1907 | endmenu |
1908 | ||
8c2c3df3 CM |
1909 | config SYSVIPC_COMPAT |
1910 | def_bool y | |
1911 | depends on COMPAT && SYSVIPC | |
1912 | ||
166936ba LP |
1913 | menu "Power management options" |
1914 | ||
1915 | source "kernel/power/Kconfig" | |
1916 | ||
82869ac5 JM |
1917 | config ARCH_HIBERNATION_POSSIBLE |
1918 | def_bool y | |
1919 | depends on CPU_PM | |
1920 | ||
1921 | config ARCH_HIBERNATION_HEADER | |
1922 | def_bool y | |
1923 | depends on HIBERNATION | |
1924 | ||
166936ba LP |
1925 | config ARCH_SUSPEND_POSSIBLE |
1926 | def_bool y | |
1927 | ||
166936ba LP |
1928 | endmenu |
1929 | ||
1307220d LP |
1930 | menu "CPU Power Management" |
1931 | ||
1932 | source "drivers/cpuidle/Kconfig" | |
1933 | ||
52e7e816 RH |
1934 | source "drivers/cpufreq/Kconfig" |
1935 | ||
1936 | endmenu | |
1937 | ||
f84d0275 MS |
1938 | source "drivers/firmware/Kconfig" |
1939 | ||
b6a02173 GG |
1940 | source "drivers/acpi/Kconfig" |
1941 | ||
c3eb5b14 MZ |
1942 | source "arch/arm64/kvm/Kconfig" |
1943 | ||
2c98833a AB |
1944 | if CRYPTO |
1945 | source "arch/arm64/crypto/Kconfig" | |
1946 | endif |