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Commit | Line | Data |
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8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
d8f4f161 | 3 | select ACPI_GENERIC_GSI if ACPI |
6933de0c | 4 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
8c2c3df3 | 5 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE |
2b68f6ca | 6 | select ARCH_HAS_ELF_RANDOMIZE |
957e3fac | 7 | select ARCH_HAS_GCOV_PROFILE_ALL |
308c09f1 | 8 | select ARCH_HAS_SG_CHAIN |
1f85008e | 9 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
c63c8700 | 10 | select ARCH_USE_CMPXCHG_LOCKREF |
4badad35 | 11 | select ARCH_SUPPORTS_ATOMIC_RMW |
9170100e | 12 | select ARCH_WANT_OPTIONAL_GPIOLIB |
6212a512 | 13 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 14 | select ARCH_WANT_FRAME_POINTERS |
25c92a37 | 15 | select ARM_AMBA |
1aee5d7a | 16 | select ARM_ARCH_TIMER |
c4188edc | 17 | select ARM_GIC |
875cbf3e | 18 | select AUDIT_ARCH_COMPAT_GENERIC |
853a33ce | 19 | select ARM_GIC_V2M if PCI_MSI |
021f6537 | 20 | select ARM_GIC_V3 |
19812729 | 21 | select ARM_GIC_V3_ITS if PCI_MSI |
adace895 | 22 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 23 | select CLONE_BACKWARDS |
7ca2ef33 | 24 | select COMMON_CLK |
166936ba | 25 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 26 | select DCACHE_WORD_ACCESS |
d4932f9e | 27 | select GENERIC_ALLOCATOR |
8c2c3df3 | 28 | select GENERIC_CLOCKEVENTS |
1f85008e | 29 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
3be1a5c4 | 30 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 31 | select GENERIC_EARLY_IOREMAP |
8c2c3df3 CM |
32 | select GENERIC_IRQ_PROBE |
33 | select GENERIC_IRQ_SHOW | |
6544e67b | 34 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 35 | select GENERIC_PCI_IOMAP |
65cd4f6c | 36 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 37 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
38 | select GENERIC_STRNCPY_FROM_USER |
39 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 40 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 41 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 42 | select HARDIRQS_SW_RESEND |
5284e1b4 | 43 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 44 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 45 | select HAVE_ARCH_BITREVERSE |
9732cafd | 46 | select HAVE_ARCH_JUMP_LABEL |
9529247d | 47 | select HAVE_ARCH_KGDB |
a1ae65b2 | 48 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 49 | select HAVE_ARCH_TRACEHOOK |
e54bcde3 | 50 | select HAVE_BPF_JIT |
af64d2aa | 51 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 52 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 53 | select HAVE_CMPXCHG_DOUBLE |
9b2a60c4 | 54 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 55 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 CM |
56 | select HAVE_DMA_API_DEBUG |
57 | select HAVE_DMA_ATTRS | |
6ac2104d | 58 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 59 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 60 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 61 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
62 | select HAVE_FUNCTION_TRACER |
63 | select HAVE_FUNCTION_GRAPH_TRACER | |
8c2c3df3 | 64 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 65 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
8c2c3df3 | 66 | select HAVE_MEMBLOCK |
55834a77 | 67 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 68 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
69 | select HAVE_PERF_REGS |
70 | select HAVE_PERF_USER_STACK_DUMP | |
5e5f6dc1 | 71 | select HAVE_RCU_TABLE_FREE |
055b1212 | 72 | select HAVE_SYSCALL_TRACEPOINTS |
8c2c3df3 | 73 | select IRQ_DOMAIN |
fea2acaa | 74 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
75 | select NO_BOOTMEM |
76 | select OF | |
77 | select OF_EARLY_FLATTREE | |
9bf14b7c | 78 | select OF_RESERVED_MEM |
8c2c3df3 | 79 | select PERF_USE_VMALLOC |
aa1e8ec1 CM |
80 | select POWER_RESET |
81 | select POWER_SUPPLY | |
8c2c3df3 CM |
82 | select RTC_LIB |
83 | select SPARSE_IRQ | |
7ac57a89 | 84 | select SYSCTL_EXCEPTION_TRACE |
6c81fe79 | 85 | select HAVE_CONTEXT_TRACKING |
8c2c3df3 CM |
86 | help |
87 | ARM 64-bit (AArch64) Linux support. | |
88 | ||
89 | config 64BIT | |
90 | def_bool y | |
91 | ||
92 | config ARCH_PHYS_ADDR_T_64BIT | |
93 | def_bool y | |
94 | ||
95 | config MMU | |
96 | def_bool y | |
97 | ||
ce816fa8 | 98 | config NO_IOPORT_MAP |
d1e6dc91 | 99 | def_bool y if !PCI |
8c2c3df3 CM |
100 | |
101 | config STACKTRACE_SUPPORT | |
102 | def_bool y | |
103 | ||
104 | config LOCKDEP_SUPPORT | |
105 | def_bool y | |
106 | ||
107 | config TRACE_IRQFLAGS_SUPPORT | |
108 | def_bool y | |
109 | ||
c209f799 | 110 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
111 | def_bool y |
112 | ||
113 | config GENERIC_HWEIGHT | |
114 | def_bool y | |
115 | ||
116 | config GENERIC_CSUM | |
117 | def_bool y | |
118 | ||
119 | config GENERIC_CALIBRATE_DELAY | |
120 | def_bool y | |
121 | ||
19e7640d | 122 | config ZONE_DMA |
8c2c3df3 CM |
123 | def_bool y |
124 | ||
29e56940 SC |
125 | config HAVE_GENERIC_RCU_GUP |
126 | def_bool y | |
127 | ||
8c2c3df3 CM |
128 | config ARCH_DMA_ADDR_T_64BIT |
129 | def_bool y | |
130 | ||
131 | config NEED_DMA_MAP_STATE | |
132 | def_bool y | |
133 | ||
134 | config NEED_SG_DMA_LENGTH | |
135 | def_bool y | |
136 | ||
137 | config SWIOTLB | |
138 | def_bool y | |
139 | ||
140 | config IOMMU_HELPER | |
141 | def_bool SWIOTLB | |
142 | ||
4cfb3613 AB |
143 | config KERNEL_MODE_NEON |
144 | def_bool y | |
145 | ||
92cc15fc RH |
146 | config FIX_EARLYCON_MEM |
147 | def_bool y | |
148 | ||
9f25e6ad KS |
149 | config PGTABLE_LEVELS |
150 | int | |
151 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 | |
152 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
153 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
154 | default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48 | |
155 | ||
8c2c3df3 CM |
156 | source "init/Kconfig" |
157 | ||
158 | source "kernel/Kconfig.freezer" | |
159 | ||
1ae90e79 CM |
160 | menu "Platform selection" |
161 | ||
6f56eef1 AA |
162 | config ARCH_EXYNOS |
163 | bool | |
164 | help | |
165 | This enables support for Samsung Exynos SoC family | |
166 | ||
167 | config ARCH_EXYNOS7 | |
168 | bool "ARMv8 based Samsung Exynos7" | |
169 | select ARCH_EXYNOS | |
170 | select COMMON_CLK_SAMSUNG | |
171 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
172 | select HAVE_S3C_RTC if RTC_CLASS | |
173 | select PINCTRL | |
174 | select PINCTRL_EXYNOS | |
175 | ||
176 | help | |
177 | This enables support for Samsung Exynos7 SoC family | |
178 | ||
5118a6a3 OJ |
179 | config ARCH_FSL_LS2085A |
180 | bool "Freescale LS2085A SOC" | |
181 | help | |
182 | This enables support for Freescale LS2085A SOC. | |
183 | ||
85fe946e BW |
184 | config ARCH_HISI |
185 | bool "Hisilicon SoC Family" | |
186 | help | |
187 | This enables support for Hisilicon ARMv8 SoC family | |
188 | ||
4727a6f6 EH |
189 | config ARCH_MEDIATEK |
190 | bool "Mediatek MT65xx & MT81xx ARMv8 SoC" | |
191 | select ARM_GIC | |
0a233cdf | 192 | select PINCTRL |
4727a6f6 EH |
193 | help |
194 | Support for Mediatek MT65xx & MT81xx ARMv8 SoCs | |
195 | ||
d7f64a44 AK |
196 | config ARCH_QCOM |
197 | bool "Qualcomm Platforms" | |
198 | select PINCTRL | |
199 | help | |
200 | This enables support for the ARMv8 based Qualcomm chipsets. | |
201 | ||
41904360 SS |
202 | config ARCH_SEATTLE |
203 | bool "AMD Seattle SoC Family" | |
204 | help | |
205 | This enables support for AMD Seattle SOC Family | |
206 | ||
d035fdfa PW |
207 | config ARCH_TEGRA |
208 | bool "NVIDIA Tegra SoC Family" | |
209 | select ARCH_HAS_RESET_CONTROLLER | |
210 | select ARCH_REQUIRE_GPIOLIB | |
211 | select CLKDEV_LOOKUP | |
212 | select CLKSRC_MMIO | |
213 | select CLKSRC_OF | |
214 | select GENERIC_CLOCKEVENTS | |
215 | select HAVE_CLK | |
d035fdfa PW |
216 | select PINCTRL |
217 | select RESET_CONTROLLER | |
218 | help | |
219 | This enables support for the NVIDIA Tegra SoC family. | |
220 | ||
221 | config ARCH_TEGRA_132_SOC | |
222 | bool "NVIDIA Tegra132 SoC" | |
223 | depends on ARCH_TEGRA | |
224 | select PINCTRL_TEGRA124 | |
d035fdfa PW |
225 | select USB_ULPI if USB_PHY |
226 | select USB_ULPI_VIEWPORT if USB_PHY | |
227 | help | |
228 | Enable support for NVIDIA Tegra132 SoC, based on the Denver | |
229 | ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, | |
230 | but contains an NVIDIA Denver CPU complex in place of | |
231 | Tegra124's "4+1" Cortex-A15 CPU complex. | |
232 | ||
c4bb7995 ZZ |
233 | config ARCH_SPRD |
234 | bool "Spreadtrum SoC platform" | |
235 | help | |
236 | Support for Spreadtrum ARM based SoCs | |
237 | ||
28f7420d RMC |
238 | config ARCH_THUNDER |
239 | bool "Cavium Inc. Thunder SoC Family" | |
240 | help | |
241 | This enables support for Cavium's Thunder Family of SoCs. | |
242 | ||
1ae90e79 CM |
243 | config ARCH_VEXPRESS |
244 | bool "ARMv8 software model (Versatile Express)" | |
245 | select ARCH_REQUIRE_GPIOLIB | |
246 | select COMMON_CLK_VERSATILE | |
aa1e8ec1 | 247 | select POWER_RESET_VEXPRESS |
1ae90e79 CM |
248 | select VEXPRESS_CONFIG |
249 | help | |
250 | This enables support for the ARMv8 software model (Versatile | |
251 | Express). | |
8c2c3df3 | 252 | |
15942853 VK |
253 | config ARCH_XGENE |
254 | bool "AppliedMicro X-Gene SOC Family" | |
255 | help | |
256 | This enables support for AppliedMicro X-Gene SOC Family | |
257 | ||
5d1b79d2 MS |
258 | config ARCH_ZYNQMP |
259 | bool "Xilinx ZynqMP Family" | |
260 | help | |
261 | This enables support for Xilinx ZynqMP Family | |
262 | ||
8c2c3df3 CM |
263 | endmenu |
264 | ||
265 | menu "Bus support" | |
266 | ||
d1e6dc91 LD |
267 | config PCI |
268 | bool "PCI support" | |
269 | help | |
270 | This feature enables support for PCI bus system. If you say Y | |
271 | here, the kernel will include drivers and infrastructure code | |
272 | to support PCI bus devices. | |
273 | ||
274 | config PCI_DOMAINS | |
275 | def_bool PCI | |
276 | ||
277 | config PCI_DOMAINS_GENERIC | |
278 | def_bool PCI | |
279 | ||
280 | config PCI_SYSCALL | |
281 | def_bool PCI | |
282 | ||
283 | source "drivers/pci/Kconfig" | |
284 | source "drivers/pci/pcie/Kconfig" | |
285 | source "drivers/pci/hotplug/Kconfig" | |
286 | ||
8c2c3df3 CM |
287 | endmenu |
288 | ||
289 | menu "Kernel Features" | |
290 | ||
c0a01b84 AP |
291 | menu "ARM errata workarounds via the alternatives framework" |
292 | ||
293 | config ARM64_ERRATUM_826319 | |
294 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
295 | default y | |
296 | help | |
297 | This option adds an alternative code sequence to work around ARM | |
298 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
299 | AXI master interface and an L2 cache. | |
300 | ||
301 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
302 | and is unable to accept a certain write via this interface, it will | |
303 | not progress on read data presented on the read data channel and the | |
304 | system can deadlock. | |
305 | ||
306 | The workaround promotes data cache clean instructions to | |
307 | data cache clean-and-invalidate. | |
308 | Please note that this does not necessarily enable the workaround, | |
309 | as it depends on the alternative framework, which will only patch | |
310 | the kernel if an affected CPU is detected. | |
311 | ||
312 | If unsure, say Y. | |
313 | ||
314 | config ARM64_ERRATUM_827319 | |
315 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
316 | default y | |
317 | help | |
318 | This option adds an alternative code sequence to work around ARM | |
319 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
320 | master interface and an L2 cache. | |
321 | ||
322 | Under certain conditions this erratum can cause a clean line eviction | |
323 | to occur at the same time as another transaction to the same address | |
324 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
325 | interconnect reorders the two transactions. | |
326 | ||
327 | The workaround promotes data cache clean instructions to | |
328 | data cache clean-and-invalidate. | |
329 | Please note that this does not necessarily enable the workaround, | |
330 | as it depends on the alternative framework, which will only patch | |
331 | the kernel if an affected CPU is detected. | |
332 | ||
333 | If unsure, say Y. | |
334 | ||
335 | config ARM64_ERRATUM_824069 | |
336 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
337 | default y | |
338 | help | |
339 | This option adds an alternative code sequence to work around ARM | |
340 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
341 | to a coherent interconnect. | |
342 | ||
343 | If a Cortex-A53 processor is executing a store or prefetch for | |
344 | write instruction at the same time as a processor in another | |
345 | cluster is executing a cache maintenance operation to the same | |
346 | address, then this erratum might cause a clean cache line to be | |
347 | incorrectly marked as dirty. | |
348 | ||
349 | The workaround promotes data cache clean instructions to | |
350 | data cache clean-and-invalidate. | |
351 | Please note that this option does not necessarily enable the | |
352 | workaround, as it depends on the alternative framework, which will | |
353 | only patch the kernel if an affected CPU is detected. | |
354 | ||
355 | If unsure, say Y. | |
356 | ||
357 | config ARM64_ERRATUM_819472 | |
358 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
359 | default y | |
360 | help | |
361 | This option adds an alternative code sequence to work around ARM | |
362 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
363 | present when it is connected to a coherent interconnect. | |
364 | ||
365 | If the processor is executing a load and store exclusive sequence at | |
366 | the same time as a processor in another cluster is executing a cache | |
367 | maintenance operation to the same address, then this erratum might | |
368 | cause data corruption. | |
369 | ||
370 | The workaround promotes data cache clean instructions to | |
371 | data cache clean-and-invalidate. | |
372 | Please note that this does not necessarily enable the workaround, | |
373 | as it depends on the alternative framework, which will only patch | |
374 | the kernel if an affected CPU is detected. | |
375 | ||
376 | If unsure, say Y. | |
377 | ||
378 | config ARM64_ERRATUM_832075 | |
379 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
380 | default y | |
381 | help | |
382 | This option adds an alternative code sequence to work around ARM | |
383 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
384 | ||
385 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
386 | instructions to Write-Back memory are mixed with Device loads. | |
387 | ||
388 | The workaround is to promote device loads to use Load-Acquire | |
389 | semantics. | |
390 | Please note that this does not necessarily enable the workaround, | |
391 | as it depends on the alternative framework, which will only patch | |
392 | the kernel if an affected CPU is detected. | |
393 | ||
394 | If unsure, say Y. | |
395 | ||
905e8c5d WD |
396 | config ARM64_ERRATUM_845719 |
397 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
398 | depends on COMPAT | |
399 | default y | |
400 | help | |
401 | This option adds an alternative code sequence to work around ARM | |
402 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
403 | ||
404 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
405 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
406 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
407 | might return incorrect data. | |
408 | ||
409 | The workaround is to write the contextidr_el1 register on exception | |
410 | return to a 32-bit task. | |
411 | Please note that this does not necessarily enable the workaround, | |
412 | as it depends on the alternative framework, which will only patch | |
413 | the kernel if an affected CPU is detected. | |
414 | ||
415 | If unsure, say Y. | |
416 | ||
c0a01b84 AP |
417 | endmenu |
418 | ||
419 | ||
e41ceed0 JL |
420 | choice |
421 | prompt "Page size" | |
422 | default ARM64_4K_PAGES | |
423 | help | |
424 | Page size (translation granule) configuration. | |
425 | ||
426 | config ARM64_4K_PAGES | |
427 | bool "4KB" | |
428 | help | |
429 | This feature enables 4KB pages support. | |
430 | ||
8c2c3df3 | 431 | config ARM64_64K_PAGES |
e41ceed0 | 432 | bool "64KB" |
8c2c3df3 CM |
433 | help |
434 | This feature enables 64KB pages support (4KB by default) | |
435 | allowing only two levels of page tables and faster TLB | |
436 | look-up. AArch32 emulation is not available when this feature | |
437 | is enabled. | |
438 | ||
e41ceed0 JL |
439 | endchoice |
440 | ||
441 | choice | |
442 | prompt "Virtual address space size" | |
443 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
444 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES | |
445 | help | |
446 | Allows choosing one of multiple possible virtual address | |
447 | space sizes. The level of translation table is determined by | |
448 | a combination of page size and virtual address space size. | |
449 | ||
450 | config ARM64_VA_BITS_39 | |
451 | bool "39-bit" | |
452 | depends on ARM64_4K_PAGES | |
453 | ||
454 | config ARM64_VA_BITS_42 | |
455 | bool "42-bit" | |
456 | depends on ARM64_64K_PAGES | |
457 | ||
c79b954b JL |
458 | config ARM64_VA_BITS_48 |
459 | bool "48-bit" | |
c79b954b | 460 | |
e41ceed0 JL |
461 | endchoice |
462 | ||
463 | config ARM64_VA_BITS | |
464 | int | |
465 | default 39 if ARM64_VA_BITS_39 | |
466 | default 42 if ARM64_VA_BITS_42 | |
c79b954b | 467 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 468 | |
a872013d WD |
469 | config CPU_BIG_ENDIAN |
470 | bool "Build big-endian kernel" | |
471 | help | |
472 | Say Y if you plan on running a kernel in big-endian mode. | |
473 | ||
8c2c3df3 CM |
474 | config SMP |
475 | bool "Symmetric Multi-Processing" | |
8c2c3df3 CM |
476 | help |
477 | This enables support for systems with more than one CPU. If | |
478 | you say N here, the kernel will run on single and | |
479 | multiprocessor machines, but will use only one CPU of a | |
480 | multiprocessor machine. If you say Y here, the kernel will run | |
481 | on many, but not all, single processor machines. On a single | |
482 | processor machine, the kernel will run faster if you say N | |
483 | here. | |
484 | ||
485 | If you don't know what to do here, say N. | |
486 | ||
f6e763b9 MB |
487 | config SCHED_MC |
488 | bool "Multi-core scheduler support" | |
489 | depends on SMP | |
490 | help | |
491 | Multi-core scheduler support improves the CPU scheduler's decision | |
492 | making when dealing with multi-core CPU chips at a cost of slightly | |
493 | increased overhead in some places. If unsure say N here. | |
494 | ||
495 | config SCHED_SMT | |
496 | bool "SMT scheduler support" | |
497 | depends on SMP | |
498 | help | |
499 | Improves the CPU scheduler's decision making when dealing with | |
500 | MultiThreading at a cost of slightly increased overhead in some | |
501 | places. If unsure say N here. | |
502 | ||
8c2c3df3 | 503 | config NR_CPUS |
62aa9655 GK |
504 | int "Maximum number of CPUs (2-4096)" |
505 | range 2 4096 | |
8c2c3df3 | 506 | depends on SMP |
15942853 | 507 | # These have to remain sorted largest to smallest |
e3672649 | 508 | default "64" |
8c2c3df3 | 509 | |
9327e2c6 MR |
510 | config HOTPLUG_CPU |
511 | bool "Support for hot-pluggable CPUs" | |
512 | depends on SMP | |
513 | help | |
514 | Say Y here to experiment with turning CPUs off and on. CPUs | |
515 | can be controlled through /sys/devices/system/cpu. | |
516 | ||
8c2c3df3 CM |
517 | source kernel/Kconfig.preempt |
518 | ||
137650aa MR |
519 | config UP_LATE_INIT |
520 | def_bool y | |
521 | depends on !SMP | |
522 | ||
8c2c3df3 CM |
523 | config HZ |
524 | int | |
525 | default 100 | |
526 | ||
527 | config ARCH_HAS_HOLES_MEMORYMODEL | |
528 | def_bool y if SPARSEMEM | |
529 | ||
530 | config ARCH_SPARSEMEM_ENABLE | |
531 | def_bool y | |
532 | select SPARSEMEM_VMEMMAP_ENABLE | |
533 | ||
534 | config ARCH_SPARSEMEM_DEFAULT | |
535 | def_bool ARCH_SPARSEMEM_ENABLE | |
536 | ||
537 | config ARCH_SELECT_MEMORY_MODEL | |
538 | def_bool ARCH_SPARSEMEM_ENABLE | |
539 | ||
540 | config HAVE_ARCH_PFN_VALID | |
541 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
542 | ||
543 | config HW_PERF_EVENTS | |
544 | bool "Enable hardware performance counter support for perf events" | |
545 | depends on PERF_EVENTS | |
546 | default y | |
547 | help | |
548 | Enable hardware performance counter support for perf events. If | |
549 | disabled, perf events will use software events only. | |
550 | ||
084bd298 SC |
551 | config SYS_SUPPORTS_HUGETLBFS |
552 | def_bool y | |
553 | ||
554 | config ARCH_WANT_GENERAL_HUGETLB | |
555 | def_bool y | |
556 | ||
557 | config ARCH_WANT_HUGE_PMD_SHARE | |
558 | def_bool y if !ARM64_64K_PAGES | |
559 | ||
af074848 SC |
560 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
561 | def_bool y | |
562 | ||
a41dc0e8 CM |
563 | config ARCH_HAS_CACHE_LINE_SIZE |
564 | def_bool y | |
565 | ||
8c2c3df3 CM |
566 | source "mm/Kconfig" |
567 | ||
a1ae65b2 AT |
568 | config SECCOMP |
569 | bool "Enable seccomp to safely compute untrusted bytecode" | |
570 | ---help--- | |
571 | This kernel feature is useful for number crunching applications | |
572 | that may need to compute untrusted bytecode during their | |
573 | execution. By using pipes or other transports made available to | |
574 | the process as file descriptors supporting the read/write | |
575 | syscalls, it's possible to isolate those applications in | |
576 | their own address space using seccomp. Once seccomp is | |
577 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
578 | and the task is only allowed to execute a few safe syscalls | |
579 | defined by each seccomp mode. | |
580 | ||
aa42aa13 SS |
581 | config XEN_DOM0 |
582 | def_bool y | |
583 | depends on XEN | |
584 | ||
585 | config XEN | |
c2ba1f7d | 586 | bool "Xen guest support on ARM64" |
aa42aa13 | 587 | depends on ARM64 && OF |
83862ccf | 588 | select SWIOTLB_XEN |
aa42aa13 SS |
589 | help |
590 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
591 | ||
d03bb145 SC |
592 | config FORCE_MAX_ZONEORDER |
593 | int | |
594 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
595 | default "11" | |
596 | ||
1b907f46 WD |
597 | menuconfig ARMV8_DEPRECATED |
598 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
599 | depends on COMPAT | |
600 | help | |
601 | Legacy software support may require certain instructions | |
602 | that have been deprecated or obsoleted in the architecture. | |
603 | ||
604 | Enable this config to enable selective emulation of these | |
605 | features. | |
606 | ||
607 | If unsure, say Y | |
608 | ||
609 | if ARMV8_DEPRECATED | |
610 | ||
611 | config SWP_EMULATION | |
612 | bool "Emulate SWP/SWPB instructions" | |
613 | help | |
614 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
615 | they are always undefined. Say Y here to enable software | |
616 | emulation of these instructions for userspace using LDXR/STXR. | |
617 | ||
618 | In some older versions of glibc [<=2.8] SWP is used during futex | |
619 | trylock() operations with the assumption that the code will not | |
620 | be preempted. This invalid assumption may be more likely to fail | |
621 | with SWP emulation enabled, leading to deadlock of the user | |
622 | application. | |
623 | ||
624 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
625 | on an external transaction monitoring block called a global | |
626 | monitor to maintain update atomicity. If your system does not | |
627 | implement a global monitor, this option can cause programs that | |
628 | perform SWP operations to uncached memory to deadlock. | |
629 | ||
630 | If unsure, say Y | |
631 | ||
632 | config CP15_BARRIER_EMULATION | |
633 | bool "Emulate CP15 Barrier instructions" | |
634 | help | |
635 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
636 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
637 | strongly recommended to use the ISB, DSB, and DMB | |
638 | instructions instead. | |
639 | ||
640 | Say Y here to enable software emulation of these | |
641 | instructions for AArch32 userspace code. When this option is | |
642 | enabled, CP15 barrier usage is traced which can help | |
643 | identify software that needs updating. | |
644 | ||
645 | If unsure, say Y | |
646 | ||
2d888f48 SP |
647 | config SETEND_EMULATION |
648 | bool "Emulate SETEND instruction" | |
649 | help | |
650 | The SETEND instruction alters the data-endianness of the | |
651 | AArch32 EL0, and is deprecated in ARMv8. | |
652 | ||
653 | Say Y here to enable software emulation of the instruction | |
654 | for AArch32 userspace code. | |
655 | ||
656 | Note: All the cpus on the system must have mixed endian support at EL0 | |
657 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
658 | endian - is hotplugged in after this feature has been enabled, there could | |
659 | be unexpected results in the applications. | |
660 | ||
661 | If unsure, say Y | |
1b907f46 WD |
662 | endif |
663 | ||
8c2c3df3 CM |
664 | endmenu |
665 | ||
666 | menu "Boot options" | |
667 | ||
668 | config CMDLINE | |
669 | string "Default kernel command string" | |
670 | default "" | |
671 | help | |
672 | Provide a set of default command-line options at build time by | |
673 | entering them here. As a minimum, you should specify the the | |
674 | root device (e.g. root=/dev/nfs). | |
675 | ||
676 | config CMDLINE_FORCE | |
677 | bool "Always use the default kernel command string" | |
678 | help | |
679 | Always use the default kernel command string, even if the boot | |
680 | loader passes other arguments to the kernel. | |
681 | This is useful if you cannot or don't want to change the | |
682 | command-line options your boot loader passes to the kernel. | |
683 | ||
f4f75ad5 AB |
684 | config EFI_STUB |
685 | bool | |
686 | ||
f84d0275 MS |
687 | config EFI |
688 | bool "UEFI runtime support" | |
689 | depends on OF && !CPU_BIG_ENDIAN | |
690 | select LIBFDT | |
691 | select UCS2_STRING | |
692 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 693 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
694 | select EFI_STUB |
695 | select EFI_ARMSTUB | |
f84d0275 MS |
696 | default y |
697 | help | |
698 | This option provides support for runtime services provided | |
699 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
700 | clock, and platform reset). A UEFI stub is also provided to |
701 | allow the kernel to be booted as an EFI application. This | |
702 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 703 | |
d1ae8c00 YL |
704 | config DMI |
705 | bool "Enable support for SMBIOS (DMI) tables" | |
706 | depends on EFI | |
707 | default y | |
708 | help | |
709 | This enables SMBIOS/DMI feature for systems. | |
710 | ||
711 | This option is only useful on systems that have UEFI firmware. | |
712 | However, even with this option, the resultant kernel should | |
713 | continue to boot on existing non-UEFI platforms. | |
714 | ||
8c2c3df3 CM |
715 | endmenu |
716 | ||
717 | menu "Userspace binary formats" | |
718 | ||
719 | source "fs/Kconfig.binfmt" | |
720 | ||
721 | config COMPAT | |
722 | bool "Kernel support for 32-bit EL0" | |
a8fcd8b1 | 723 | depends on !ARM64_64K_PAGES || EXPERT |
8c2c3df3 | 724 | select COMPAT_BINFMT_ELF |
af1839eb | 725 | select HAVE_UID16 |
84b9e9b4 | 726 | select OLD_SIGSUSPEND3 |
51682036 | 727 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
728 | help |
729 | This option enables support for a 32-bit EL0 running under a 64-bit | |
730 | kernel at EL1. AArch32-specific components such as system calls, | |
731 | the user helper functions, VFP support and the ptrace interface are | |
732 | handled appropriately by the kernel. | |
733 | ||
a8fcd8b1 AG |
734 | If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you |
735 | will only be able to execute AArch32 binaries that were compiled with | |
736 | 64k aligned segments. | |
737 | ||
8c2c3df3 CM |
738 | If you want to execute 32-bit userspace applications, say Y. |
739 | ||
740 | config SYSVIPC_COMPAT | |
741 | def_bool y | |
742 | depends on COMPAT && SYSVIPC | |
743 | ||
744 | endmenu | |
745 | ||
166936ba LP |
746 | menu "Power management options" |
747 | ||
748 | source "kernel/power/Kconfig" | |
749 | ||
750 | config ARCH_SUSPEND_POSSIBLE | |
751 | def_bool y | |
752 | ||
166936ba LP |
753 | endmenu |
754 | ||
1307220d LP |
755 | menu "CPU Power Management" |
756 | ||
757 | source "drivers/cpuidle/Kconfig" | |
758 | ||
52e7e816 RH |
759 | source "drivers/cpufreq/Kconfig" |
760 | ||
761 | endmenu | |
762 | ||
8c2c3df3 CM |
763 | source "net/Kconfig" |
764 | ||
765 | source "drivers/Kconfig" | |
766 | ||
f84d0275 MS |
767 | source "drivers/firmware/Kconfig" |
768 | ||
b6a02173 GG |
769 | source "drivers/acpi/Kconfig" |
770 | ||
8c2c3df3 CM |
771 | source "fs/Kconfig" |
772 | ||
c3eb5b14 MZ |
773 | source "arch/arm64/kvm/Kconfig" |
774 | ||
8c2c3df3 CM |
775 | source "arch/arm64/Kconfig.debug" |
776 | ||
777 | source "security/Kconfig" | |
778 | ||
779 | source "crypto/Kconfig" | |
2c98833a AB |
780 | if CRYPTO |
781 | source "arch/arm64/crypto/Kconfig" | |
782 | endif | |
8c2c3df3 CM |
783 | |
784 | source "lib/Kconfig" |