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arm64: fix implementation of mmap2 compat syscall
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8c2c3df3
CM
1config ARM64
2 def_bool y
92980405 3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
8c2c3df3 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
957e3fac 5 select ARCH_HAS_GCOV_PROFILE_ALL
308c09f1 6 select ARCH_HAS_SG_CHAIN
1f85008e 7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
c63c8700 8 select ARCH_USE_CMPXCHG_LOCKREF
4badad35 9 select ARCH_SUPPORTS_ATOMIC_RMW
9170100e 10 select ARCH_WANT_OPTIONAL_GPIOLIB
6212a512 11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
b6f35981 12 select ARCH_WANT_FRAME_POINTERS
25c92a37 13 select ARM_AMBA
1aee5d7a 14 select ARM_ARCH_TIMER
c4188edc 15 select ARM_GIC
875cbf3e 16 select AUDIT_ARCH_COMPAT_GENERIC
853a33ce 17 select ARM_GIC_V2M if PCI_MSI
021f6537 18 select ARM_GIC_V3
19812729 19 select ARM_GIC_V3_ITS if PCI_MSI
adace895 20 select BUILDTIME_EXTABLE_SORT
db2789b5 21 select CLONE_BACKWARDS
7ca2ef33 22 select COMMON_CLK
166936ba 23 select CPU_PM if (SUSPEND || CPU_IDLE)
7bc13fd3 24 select DCACHE_WORD_ACCESS
d4932f9e 25 select GENERIC_ALLOCATOR
8c2c3df3 26 select GENERIC_CLOCKEVENTS
1f85008e 27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
3be1a5c4 28 select GENERIC_CPU_AUTOPROBE
bf4b558e 29 select GENERIC_EARLY_IOREMAP
8c2c3df3
CM
30 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
cb61f676 32 select GENERIC_PCI_IOMAP
65cd4f6c 33 select GENERIC_SCHED_CLOCK
8c2c3df3 34 select GENERIC_SMP_IDLE_THREAD
12a0ef7b
WD
35 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
8c2c3df3 37 select GENERIC_TIME_VSYSCALL
a1ddc74a 38 select HANDLE_DOMAIN_IRQ
8c2c3df3 39 select HARDIRQS_SW_RESEND
5284e1b4 40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
875cbf3e 41 select HAVE_ARCH_AUDITSYSCALL
8e7a4cef 42 select HAVE_ARCH_BITREVERSE
9732cafd 43 select HAVE_ARCH_JUMP_LABEL
9529247d 44 select HAVE_ARCH_KGDB
a1ae65b2 45 select HAVE_ARCH_SECCOMP_FILTER
8c2c3df3 46 select HAVE_ARCH_TRACEHOOK
e54bcde3 47 select HAVE_BPF_JIT
af64d2aa 48 select HAVE_C_RECORDMCOUNT
c0c264ae 49 select HAVE_CC_STACKPROTECTOR
5284e1b4 50 select HAVE_CMPXCHG_DOUBLE
9b2a60c4 51 select HAVE_DEBUG_BUGVERBOSE
b69ec42b 52 select HAVE_DEBUG_KMEMLEAK
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53 select HAVE_DMA_API_DEBUG
54 select HAVE_DMA_ATTRS
6ac2104d 55 select HAVE_DMA_CONTIGUOUS
bd7d38db 56 select HAVE_DYNAMIC_FTRACE
50afc33a 57 select HAVE_EFFICIENT_UNALIGNED_ACCESS
af64d2aa 58 select HAVE_FTRACE_MCOUNT_RECORD
819e50e2
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59 select HAVE_FUNCTION_TRACER
60 select HAVE_FUNCTION_GRAPH_TRACER
8c2c3df3 61 select HAVE_GENERIC_DMA_COHERENT
8c2c3df3 62 select HAVE_HW_BREAKPOINT if PERF_EVENTS
8c2c3df3 63 select HAVE_MEMBLOCK
55834a77 64 select HAVE_PATA_PLATFORM
8c2c3df3 65 select HAVE_PERF_EVENTS
2ee0d7fd
JP
66 select HAVE_PERF_REGS
67 select HAVE_PERF_USER_STACK_DUMP
5e5f6dc1 68 select HAVE_RCU_TABLE_FREE
055b1212 69 select HAVE_SYSCALL_TRACEPOINTS
8c2c3df3 70 select IRQ_DOMAIN
fea2acaa 71 select MODULES_USE_ELF_RELA
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CM
72 select NO_BOOTMEM
73 select OF
74 select OF_EARLY_FLATTREE
9bf14b7c 75 select OF_RESERVED_MEM
8c2c3df3 76 select PERF_USE_VMALLOC
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77 select POWER_RESET
78 select POWER_SUPPLY
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79 select RTC_LIB
80 select SPARSE_IRQ
7ac57a89 81 select SYSCTL_EXCEPTION_TRACE
6c81fe79 82 select HAVE_CONTEXT_TRACKING
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CM
83 help
84 ARM 64-bit (AArch64) Linux support.
85
86config 64BIT
87 def_bool y
88
89config ARCH_PHYS_ADDR_T_64BIT
90 def_bool y
91
92config MMU
93 def_bool y
94
ce816fa8 95config NO_IOPORT_MAP
d1e6dc91 96 def_bool y if !PCI
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97
98config STACKTRACE_SUPPORT
99 def_bool y
100
101config LOCKDEP_SUPPORT
102 def_bool y
103
104config TRACE_IRQFLAGS_SUPPORT
105 def_bool y
106
c209f799 107config RWSEM_XCHGADD_ALGORITHM
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108 def_bool y
109
110config GENERIC_HWEIGHT
111 def_bool y
112
113config GENERIC_CSUM
114 def_bool y
115
116config GENERIC_CALIBRATE_DELAY
117 def_bool y
118
19e7640d 119config ZONE_DMA
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120 def_bool y
121
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122config HAVE_GENERIC_RCU_GUP
123 def_bool y
124
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125config ARCH_DMA_ADDR_T_64BIT
126 def_bool y
127
128config NEED_DMA_MAP_STATE
129 def_bool y
130
131config NEED_SG_DMA_LENGTH
132 def_bool y
133
134config SWIOTLB
135 def_bool y
136
137config IOMMU_HELPER
138 def_bool SWIOTLB
139
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140config KERNEL_MODE_NEON
141 def_bool y
142
92cc15fc
RH
143config FIX_EARLYCON_MEM
144 def_bool y
145
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146source "init/Kconfig"
147
148source "kernel/Kconfig.freezer"
149
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150menu "Platform selection"
151
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152config ARCH_EXYNOS
153 bool
154 help
155 This enables support for Samsung Exynos SoC family
156
157config ARCH_EXYNOS7
158 bool "ARMv8 based Samsung Exynos7"
159 select ARCH_EXYNOS
160 select COMMON_CLK_SAMSUNG
161 select HAVE_S3C2410_WATCHDOG if WATCHDOG
162 select HAVE_S3C_RTC if RTC_CLASS
163 select PINCTRL
164 select PINCTRL_EXYNOS
165
166 help
167 This enables support for Samsung Exynos7 SoC family
168
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OJ
169config ARCH_FSL_LS2085A
170 bool "Freescale LS2085A SOC"
171 help
172 This enables support for Freescale LS2085A SOC.
173
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174config ARCH_MEDIATEK
175 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
176 select ARM_GIC
177 help
178 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
179
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180config ARCH_SEATTLE
181 bool "AMD Seattle SoC Family"
182 help
183 This enables support for AMD Seattle SOC Family
184
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185config ARCH_TEGRA
186 bool "NVIDIA Tegra SoC Family"
187 select ARCH_HAS_RESET_CONTROLLER
188 select ARCH_REQUIRE_GPIOLIB
189 select CLKDEV_LOOKUP
190 select CLKSRC_MMIO
191 select CLKSRC_OF
192 select GENERIC_CLOCKEVENTS
193 select HAVE_CLK
d035fdfa
PW
194 select PINCTRL
195 select RESET_CONTROLLER
196 help
197 This enables support for the NVIDIA Tegra SoC family.
198
199config ARCH_TEGRA_132_SOC
200 bool "NVIDIA Tegra132 SoC"
201 depends on ARCH_TEGRA
202 select PINCTRL_TEGRA124
d035fdfa
PW
203 select USB_ULPI if USB_PHY
204 select USB_ULPI_VIEWPORT if USB_PHY
205 help
206 Enable support for NVIDIA Tegra132 SoC, based on the Denver
207 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
208 but contains an NVIDIA Denver CPU complex in place of
209 Tegra124's "4+1" Cortex-A15 CPU complex.
210
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211config ARCH_THUNDER
212 bool "Cavium Inc. Thunder SoC Family"
213 help
214 This enables support for Cavium's Thunder Family of SoCs.
215
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CM
216config ARCH_VEXPRESS
217 bool "ARMv8 software model (Versatile Express)"
218 select ARCH_REQUIRE_GPIOLIB
219 select COMMON_CLK_VERSATILE
aa1e8ec1 220 select POWER_RESET_VEXPRESS
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221 select VEXPRESS_CONFIG
222 help
223 This enables support for the ARMv8 software model (Versatile
224 Express).
8c2c3df3 225
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226config ARCH_XGENE
227 bool "AppliedMicro X-Gene SOC Family"
228 help
229 This enables support for AppliedMicro X-Gene SOC Family
230
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231endmenu
232
233menu "Bus support"
234
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235config PCI
236 bool "PCI support"
237 help
238 This feature enables support for PCI bus system. If you say Y
239 here, the kernel will include drivers and infrastructure code
240 to support PCI bus devices.
241
242config PCI_DOMAINS
243 def_bool PCI
244
245config PCI_DOMAINS_GENERIC
246 def_bool PCI
247
248config PCI_SYSCALL
249 def_bool PCI
250
251source "drivers/pci/Kconfig"
252source "drivers/pci/pcie/Kconfig"
253source "drivers/pci/hotplug/Kconfig"
254
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255endmenu
256
257menu "Kernel Features"
258
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259menu "ARM errata workarounds via the alternatives framework"
260
261config ARM64_ERRATUM_826319
262 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
263 default y
264 help
265 This option adds an alternative code sequence to work around ARM
266 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
267 AXI master interface and an L2 cache.
268
269 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
270 and is unable to accept a certain write via this interface, it will
271 not progress on read data presented on the read data channel and the
272 system can deadlock.
273
274 The workaround promotes data cache clean instructions to
275 data cache clean-and-invalidate.
276 Please note that this does not necessarily enable the workaround,
277 as it depends on the alternative framework, which will only patch
278 the kernel if an affected CPU is detected.
279
280 If unsure, say Y.
281
282config ARM64_ERRATUM_827319
283 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
284 default y
285 help
286 This option adds an alternative code sequence to work around ARM
287 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
288 master interface and an L2 cache.
289
290 Under certain conditions this erratum can cause a clean line eviction
291 to occur at the same time as another transaction to the same address
292 on the AMBA 5 CHI interface, which can cause data corruption if the
293 interconnect reorders the two transactions.
294
295 The workaround promotes data cache clean instructions to
296 data cache clean-and-invalidate.
297 Please note that this does not necessarily enable the workaround,
298 as it depends on the alternative framework, which will only patch
299 the kernel if an affected CPU is detected.
300
301 If unsure, say Y.
302
303config ARM64_ERRATUM_824069
304 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
305 default y
306 help
307 This option adds an alternative code sequence to work around ARM
308 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
309 to a coherent interconnect.
310
311 If a Cortex-A53 processor is executing a store or prefetch for
312 write instruction at the same time as a processor in another
313 cluster is executing a cache maintenance operation to the same
314 address, then this erratum might cause a clean cache line to be
315 incorrectly marked as dirty.
316
317 The workaround promotes data cache clean instructions to
318 data cache clean-and-invalidate.
319 Please note that this option does not necessarily enable the
320 workaround, as it depends on the alternative framework, which will
321 only patch the kernel if an affected CPU is detected.
322
323 If unsure, say Y.
324
325config ARM64_ERRATUM_819472
326 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
327 default y
328 help
329 This option adds an alternative code sequence to work around ARM
330 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
331 present when it is connected to a coherent interconnect.
332
333 If the processor is executing a load and store exclusive sequence at
334 the same time as a processor in another cluster is executing a cache
335 maintenance operation to the same address, then this erratum might
336 cause data corruption.
337
338 The workaround promotes data cache clean instructions to
339 data cache clean-and-invalidate.
340 Please note that this does not necessarily enable the workaround,
341 as it depends on the alternative framework, which will only patch
342 the kernel if an affected CPU is detected.
343
344 If unsure, say Y.
345
346config ARM64_ERRATUM_832075
347 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
348 default y
349 help
350 This option adds an alternative code sequence to work around ARM
351 erratum 832075 on Cortex-A57 parts up to r1p2.
352
353 Affected Cortex-A57 parts might deadlock when exclusive load/store
354 instructions to Write-Back memory are mixed with Device loads.
355
356 The workaround is to promote device loads to use Load-Acquire
357 semantics.
358 Please note that this does not necessarily enable the workaround,
359 as it depends on the alternative framework, which will only patch
360 the kernel if an affected CPU is detected.
361
362 If unsure, say Y.
363
364endmenu
365
366
e41ceed0
JL
367choice
368 prompt "Page size"
369 default ARM64_4K_PAGES
370 help
371 Page size (translation granule) configuration.
372
373config ARM64_4K_PAGES
374 bool "4KB"
375 help
376 This feature enables 4KB pages support.
377
8c2c3df3 378config ARM64_64K_PAGES
e41ceed0 379 bool "64KB"
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380 help
381 This feature enables 64KB pages support (4KB by default)
382 allowing only two levels of page tables and faster TLB
383 look-up. AArch32 emulation is not available when this feature
384 is enabled.
385
e41ceed0
JL
386endchoice
387
388choice
389 prompt "Virtual address space size"
390 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
391 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
392 help
393 Allows choosing one of multiple possible virtual address
394 space sizes. The level of translation table is determined by
395 a combination of page size and virtual address space size.
396
397config ARM64_VA_BITS_39
398 bool "39-bit"
399 depends on ARM64_4K_PAGES
400
401config ARM64_VA_BITS_42
402 bool "42-bit"
403 depends on ARM64_64K_PAGES
404
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405config ARM64_VA_BITS_48
406 bool "48-bit"
c79b954b 407
e41ceed0
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408endchoice
409
410config ARM64_VA_BITS
411 int
412 default 39 if ARM64_VA_BITS_39
413 default 42 if ARM64_VA_BITS_42
c79b954b 414 default 48 if ARM64_VA_BITS_48
e41ceed0 415
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CM
416config ARM64_PGTABLE_LEVELS
417 int
418 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
383c2799 419 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
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420 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
421 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
c79b954b 422
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WD
423config CPU_BIG_ENDIAN
424 bool "Build big-endian kernel"
425 help
426 Say Y if you plan on running a kernel in big-endian mode.
427
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428config SMP
429 bool "Symmetric Multi-Processing"
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CM
430 help
431 This enables support for systems with more than one CPU. If
432 you say N here, the kernel will run on single and
433 multiprocessor machines, but will use only one CPU of a
434 multiprocessor machine. If you say Y here, the kernel will run
435 on many, but not all, single processor machines. On a single
436 processor machine, the kernel will run faster if you say N
437 here.
438
439 If you don't know what to do here, say N.
440
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441config SCHED_MC
442 bool "Multi-core scheduler support"
443 depends on SMP
444 help
445 Multi-core scheduler support improves the CPU scheduler's decision
446 making when dealing with multi-core CPU chips at a cost of slightly
447 increased overhead in some places. If unsure say N here.
448
449config SCHED_SMT
450 bool "SMT scheduler support"
451 depends on SMP
452 help
453 Improves the CPU scheduler's decision making when dealing with
454 MultiThreading at a cost of slightly increased overhead in some
455 places. If unsure say N here.
456
8c2c3df3 457config NR_CPUS
e3672649
RR
458 int "Maximum number of CPUs (2-64)"
459 range 2 64
8c2c3df3 460 depends on SMP
15942853 461 # These have to remain sorted largest to smallest
e3672649 462 default "64"
8c2c3df3 463
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MR
464config HOTPLUG_CPU
465 bool "Support for hot-pluggable CPUs"
466 depends on SMP
467 help
468 Say Y here to experiment with turning CPUs off and on. CPUs
469 can be controlled through /sys/devices/system/cpu.
470
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471source kernel/Kconfig.preempt
472
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MR
473config UP_LATE_INIT
474 def_bool y
475 depends on !SMP
476
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477config HZ
478 int
479 default 100
480
481config ARCH_HAS_HOLES_MEMORYMODEL
482 def_bool y if SPARSEMEM
483
484config ARCH_SPARSEMEM_ENABLE
485 def_bool y
486 select SPARSEMEM_VMEMMAP_ENABLE
487
488config ARCH_SPARSEMEM_DEFAULT
489 def_bool ARCH_SPARSEMEM_ENABLE
490
491config ARCH_SELECT_MEMORY_MODEL
492 def_bool ARCH_SPARSEMEM_ENABLE
493
494config HAVE_ARCH_PFN_VALID
495 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
496
497config HW_PERF_EVENTS
498 bool "Enable hardware performance counter support for perf events"
499 depends on PERF_EVENTS
500 default y
501 help
502 Enable hardware performance counter support for perf events. If
503 disabled, perf events will use software events only.
504
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SC
505config SYS_SUPPORTS_HUGETLBFS
506 def_bool y
507
508config ARCH_WANT_GENERAL_HUGETLB
509 def_bool y
510
511config ARCH_WANT_HUGE_PMD_SHARE
512 def_bool y if !ARM64_64K_PAGES
513
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514config HAVE_ARCH_TRANSPARENT_HUGEPAGE
515 def_bool y
516
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517config ARCH_HAS_CACHE_LINE_SIZE
518 def_bool y
519
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520source "mm/Kconfig"
521
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522config SECCOMP
523 bool "Enable seccomp to safely compute untrusted bytecode"
524 ---help---
525 This kernel feature is useful for number crunching applications
526 that may need to compute untrusted bytecode during their
527 execution. By using pipes or other transports made available to
528 the process as file descriptors supporting the read/write
529 syscalls, it's possible to isolate those applications in
530 their own address space using seccomp. Once seccomp is
531 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
532 and the task is only allowed to execute a few safe syscalls
533 defined by each seccomp mode.
534
aa42aa13
SS
535config XEN_DOM0
536 def_bool y
537 depends on XEN
538
539config XEN
c2ba1f7d 540 bool "Xen guest support on ARM64"
aa42aa13 541 depends on ARM64 && OF
83862ccf 542 select SWIOTLB_XEN
aa42aa13
SS
543 help
544 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
545
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546config FORCE_MAX_ZONEORDER
547 int
548 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
549 default "11"
550
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551menuconfig ARMV8_DEPRECATED
552 bool "Emulate deprecated/obsolete ARMv8 instructions"
553 depends on COMPAT
554 help
555 Legacy software support may require certain instructions
556 that have been deprecated or obsoleted in the architecture.
557
558 Enable this config to enable selective emulation of these
559 features.
560
561 If unsure, say Y
562
563if ARMV8_DEPRECATED
564
565config SWP_EMULATION
566 bool "Emulate SWP/SWPB instructions"
567 help
568 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
569 they are always undefined. Say Y here to enable software
570 emulation of these instructions for userspace using LDXR/STXR.
571
572 In some older versions of glibc [<=2.8] SWP is used during futex
573 trylock() operations with the assumption that the code will not
574 be preempted. This invalid assumption may be more likely to fail
575 with SWP emulation enabled, leading to deadlock of the user
576 application.
577
578 NOTE: when accessing uncached shared regions, LDXR/STXR rely
579 on an external transaction monitoring block called a global
580 monitor to maintain update atomicity. If your system does not
581 implement a global monitor, this option can cause programs that
582 perform SWP operations to uncached memory to deadlock.
583
584 If unsure, say Y
585
586config CP15_BARRIER_EMULATION
587 bool "Emulate CP15 Barrier instructions"
588 help
589 The CP15 barrier instructions - CP15ISB, CP15DSB, and
590 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
591 strongly recommended to use the ISB, DSB, and DMB
592 instructions instead.
593
594 Say Y here to enable software emulation of these
595 instructions for AArch32 userspace code. When this option is
596 enabled, CP15 barrier usage is traced which can help
597 identify software that needs updating.
598
599 If unsure, say Y
600
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SP
601config SETEND_EMULATION
602 bool "Emulate SETEND instruction"
603 help
604 The SETEND instruction alters the data-endianness of the
605 AArch32 EL0, and is deprecated in ARMv8.
606
607 Say Y here to enable software emulation of the instruction
608 for AArch32 userspace code.
609
610 Note: All the cpus on the system must have mixed endian support at EL0
611 for this feature to be enabled. If a new CPU - which doesn't support mixed
612 endian - is hotplugged in after this feature has been enabled, there could
613 be unexpected results in the applications.
614
615 If unsure, say Y
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616endif
617
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618endmenu
619
620menu "Boot options"
621
622config CMDLINE
623 string "Default kernel command string"
624 default ""
625 help
626 Provide a set of default command-line options at build time by
627 entering them here. As a minimum, you should specify the the
628 root device (e.g. root=/dev/nfs).
629
630config CMDLINE_FORCE
631 bool "Always use the default kernel command string"
632 help
633 Always use the default kernel command string, even if the boot
634 loader passes other arguments to the kernel.
635 This is useful if you cannot or don't want to change the
636 command-line options your boot loader passes to the kernel.
637
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638config EFI_STUB
639 bool
640
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MS
641config EFI
642 bool "UEFI runtime support"
643 depends on OF && !CPU_BIG_ENDIAN
644 select LIBFDT
645 select UCS2_STRING
646 select EFI_PARAMS_FROM_FDT
e15dd494 647 select EFI_RUNTIME_WRAPPERS
f4f75ad5
AB
648 select EFI_STUB
649 select EFI_ARMSTUB
f84d0275
MS
650 default y
651 help
652 This option provides support for runtime services provided
653 by UEFI firmware (such as non-volatile variables, realtime
3c7f2550
MS
654 clock, and platform reset). A UEFI stub is also provided to
655 allow the kernel to be booted as an EFI application. This
656 is only useful on systems that have UEFI firmware.
f84d0275 657
d1ae8c00
YL
658config DMI
659 bool "Enable support for SMBIOS (DMI) tables"
660 depends on EFI
661 default y
662 help
663 This enables SMBIOS/DMI feature for systems.
664
665 This option is only useful on systems that have UEFI firmware.
666 However, even with this option, the resultant kernel should
667 continue to boot on existing non-UEFI platforms.
668
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CM
669endmenu
670
671menu "Userspace binary formats"
672
673source "fs/Kconfig.binfmt"
674
675config COMPAT
676 bool "Kernel support for 32-bit EL0"
677 depends on !ARM64_64K_PAGES
678 select COMPAT_BINFMT_ELF
af1839eb 679 select HAVE_UID16
84b9e9b4 680 select OLD_SIGSUSPEND3
51682036 681 select COMPAT_OLD_SIGACTION
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682 help
683 This option enables support for a 32-bit EL0 running under a 64-bit
684 kernel at EL1. AArch32-specific components such as system calls,
685 the user helper functions, VFP support and the ptrace interface are
686 handled appropriately by the kernel.
687
688 If you want to execute 32-bit userspace applications, say Y.
689
690config SYSVIPC_COMPAT
691 def_bool y
692 depends on COMPAT && SYSVIPC
693
694endmenu
695
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696menu "Power management options"
697
698source "kernel/power/Kconfig"
699
700config ARCH_SUSPEND_POSSIBLE
701 def_bool y
702
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703endmenu
704
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705menu "CPU Power Management"
706
707source "drivers/cpuidle/Kconfig"
708
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709source "drivers/cpufreq/Kconfig"
710
711endmenu
712
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713source "net/Kconfig"
714
715source "drivers/Kconfig"
716
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717source "drivers/firmware/Kconfig"
718
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719source "fs/Kconfig"
720
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721source "arch/arm64/kvm/Kconfig"
722
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723source "arch/arm64/Kconfig.debug"
724
725source "security/Kconfig"
726
727source "crypto/Kconfig"
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728if CRYPTO
729source "arch/arm64/crypto/Kconfig"
730endif
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731
732source "lib/Kconfig"