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ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
8c2c3df3 CM |
2 | config ARM64 |
3 | def_bool y | |
b6197b93 | 4 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 5 | select ACPI_GENERIC_GSI if ACPI |
5f1ae4eb | 6 | select ACPI_GTDT if ACPI |
c6bb8f89 | 7 | select ACPI_IORT if ACPI |
6933de0c | 8 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
52146173 | 9 | select ACPI_MCFG if (ACPI && PCI) |
888125a7 | 10 | select ACPI_SPCR_TABLE if ACPI |
0ce82232 | 11 | select ACPI_PPTT if ACPI |
1d8f51d4 | 12 | select ARCH_CLOCKSOURCE_DATA |
ec6d06ef | 13 | select ARCH_HAS_DEBUG_VIRTUAL |
21266be9 | 14 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
13bf5ced | 15 | select ARCH_HAS_DMA_PREP_COHERENT |
38b04a74 | 16 | select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI |
e75bef2a | 17 | select ARCH_HAS_FAST_MULTIPLIER |
6974f0c4 | 18 | select ARCH_HAS_FORTIFY_SOURCE |
957e3fac | 19 | select ARCH_HAS_GCOV_PROFILE_ALL |
4eb0716e | 20 | select ARCH_HAS_GIGANTIC_PAGE |
5e4c7549 | 21 | select ARCH_HAS_KCOV |
d8ae8a37 | 22 | select ARCH_HAS_KEEPINITRD |
f1e3a12b | 23 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
73b20c84 | 24 | select ARCH_HAS_PTE_DEVMAP |
3010a5ea | 25 | select ARCH_HAS_PTE_SPECIAL |
347cb6af | 26 | select ARCH_HAS_SETUP_DMA_OPS |
4739d53f | 27 | select ARCH_HAS_SET_DIRECT_MAP |
d2852a22 | 28 | select ARCH_HAS_SET_MEMORY |
ad21fc4f LA |
29 | select ARCH_HAS_STRICT_KERNEL_RWX |
30 | select ARCH_HAS_STRICT_MODULE_RWX | |
886643b7 CH |
31 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
32 | select ARCH_HAS_SYNC_DMA_FOR_CPU | |
4378a7d4 | 33 | select ARCH_HAS_SYSCALL_WRAPPER |
dc2acded | 34 | select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT |
1f85008e | 35 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
396a5d4a | 36 | select ARCH_HAVE_NMI_SAFE_CMPXCHG |
087133ac WD |
37 | select ARCH_INLINE_READ_LOCK if !PREEMPT |
38 | select ARCH_INLINE_READ_LOCK_BH if !PREEMPT | |
39 | select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT | |
40 | select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT | |
41 | select ARCH_INLINE_READ_UNLOCK if !PREEMPT | |
42 | select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT | |
43 | select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT | |
44 | select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT | |
45 | select ARCH_INLINE_WRITE_LOCK if !PREEMPT | |
46 | select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT | |
47 | select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT | |
48 | select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT | |
49 | select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT | |
50 | select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT | |
51 | select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT | |
52 | select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT | |
5d168964 WD |
53 | select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT |
54 | select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT | |
55 | select ARCH_INLINE_SPIN_LOCK if !PREEMPT | |
56 | select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT | |
57 | select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT | |
58 | select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT | |
59 | select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT | |
60 | select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT | |
61 | select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT | |
62 | select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT | |
350e88ba | 63 | select ARCH_KEEP_MEMBLOCK |
c63c8700 | 64 | select ARCH_USE_CMPXCHG_LOCKREF |
087133ac | 65 | select ARCH_USE_QUEUED_RWLOCKS |
c1109047 | 66 | select ARCH_USE_QUEUED_SPINLOCKS |
c484f256 | 67 | select ARCH_SUPPORTS_MEMORY_FAILURE |
4badad35 | 68 | select ARCH_SUPPORTS_ATOMIC_RMW |
c12d3362 | 69 | select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG) |
56166230 | 70 | select ARCH_SUPPORTS_NUMA_BALANCING |
84c187af | 71 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT |
67f3977f | 72 | select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT |
b6f35981 | 73 | select ARCH_WANT_FRAME_POINTERS |
3876d4a3 | 74 | select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
f0b7f8a4 | 75 | select ARCH_HAS_UBSAN_SANITIZE_ALL |
25c92a37 | 76 | select ARM_AMBA |
1aee5d7a | 77 | select ARM_ARCH_TIMER |
c4188edc | 78 | select ARM_GIC |
875cbf3e | 79 | select AUDIT_ARCH_COMPAT_GENERIC |
3ee80364 | 80 | select ARM_GIC_V2M if PCI |
021f6537 | 81 | select ARM_GIC_V3 |
3ee80364 | 82 | select ARM_GIC_V3_ITS if PCI |
bff60792 | 83 | select ARM_PSCI_FW |
adace895 | 84 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 85 | select CLONE_BACKWARDS |
7ca2ef33 | 86 | select COMMON_CLK |
166936ba | 87 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7481cddf | 88 | select CRC32 |
7bc13fd3 | 89 | select DCACHE_WORD_ACCESS |
0c3b3171 | 90 | select DMA_DIRECT_REMAP |
ef37566c | 91 | select EDAC_SUPPORT |
2f34f173 | 92 | select FRAME_POINTER |
d4932f9e | 93 | select GENERIC_ALLOCATOR |
2ef7a295 | 94 | select GENERIC_ARCH_TOPOLOGY |
8c2c3df3 | 95 | select GENERIC_CLOCKEVENTS |
4b3dc967 | 96 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 97 | select GENERIC_CPU_AUTOPROBE |
61ae1321 | 98 | select GENERIC_CPU_VULNERABILITIES |
bf4b558e | 99 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 100 | select GENERIC_IDLE_POLL_SETUP |
78ae2e1c | 101 | select GENERIC_IRQ_MULTI_HANDLER |
8c2c3df3 CM |
102 | select GENERIC_IRQ_PROBE |
103 | select GENERIC_IRQ_SHOW | |
6544e67b | 104 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 105 | select GENERIC_PCI_IOMAP |
65cd4f6c | 106 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 107 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
108 | select GENERIC_STRNCPY_FROM_USER |
109 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 110 | select GENERIC_TIME_VSYSCALL |
28b1a824 | 111 | select GENERIC_GETTIMEOFDAY |
a1ddc74a | 112 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 113 | select HARDIRQS_SW_RESEND |
eb01d42a | 114 | select HAVE_PCI |
9f9a35a7 | 115 | select HAVE_ACPI_APEI if (ACPI && EFI) |
5284e1b4 | 116 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 117 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 118 | select HAVE_ARCH_BITREVERSE |
324420bf | 119 | select HAVE_ARCH_HUGE_VMAP |
9732cafd | 120 | select HAVE_ARCH_JUMP_LABEL |
c296146c | 121 | select HAVE_ARCH_JUMP_LABEL_RELATIVE |
e17d8025 | 122 | select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) |
2d4acb90 | 123 | select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN |
9529247d | 124 | select HAVE_ARCH_KGDB |
8f0d3aa9 DC |
125 | select HAVE_ARCH_MMAP_RND_BITS |
126 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT | |
271ca788 | 127 | select HAVE_ARCH_PREL32_RELOCATIONS |
a1ae65b2 | 128 | select HAVE_ARCH_SECCOMP_FILTER |
0b3e3366 | 129 | select HAVE_ARCH_STACKLEAK |
9e8084d3 | 130 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
8c2c3df3 | 131 | select HAVE_ARCH_TRACEHOOK |
8ee70879 | 132 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE |
e3067861 | 133 | select HAVE_ARCH_VMAP_STACK |
8ee70879 | 134 | select HAVE_ARM_SMCCC |
2ff2b7ec | 135 | select HAVE_ASM_MODVERSIONS |
6077776b | 136 | select HAVE_EBPF_JIT |
af64d2aa | 137 | select HAVE_C_RECORDMCOUNT |
5284e1b4 | 138 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 139 | select HAVE_CMPXCHG_LOCAL |
8ee70879 | 140 | select HAVE_CONTEXT_TRACKING |
9b2a60c4 | 141 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 142 | select HAVE_DEBUG_KMEMLEAK |
6ac2104d | 143 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 144 | select HAVE_DYNAMIC_FTRACE |
3b23e499 TD |
145 | select HAVE_DYNAMIC_FTRACE_WITH_REGS \ |
146 | if $(cc-option,-fpatchable-function-entry=2) | |
50afc33a | 147 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
67a929e0 | 148 | select HAVE_FAST_GUP |
af64d2aa | 149 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 | 150 | select HAVE_FUNCTION_TRACER |
42d038c4 | 151 | select HAVE_FUNCTION_ERROR_INJECTION |
819e50e2 | 152 | select HAVE_FUNCTION_GRAPH_TRACER |
6b90bd4b | 153 | select HAVE_GCC_PLUGINS |
8c2c3df3 | 154 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
24da208d | 155 | select HAVE_IRQ_TIME_ACCOUNTING |
1a2db300 | 156 | select HAVE_MEMBLOCK_NODE_MAP if NUMA |
396a5d4a | 157 | select HAVE_NMI |
55834a77 | 158 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 159 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
160 | select HAVE_PERF_REGS |
161 | select HAVE_PERF_USER_STACK_DUMP | |
0a8ea52c | 162 | select HAVE_REGS_AND_STACK_ACCESS_API |
a823c35f | 163 | select HAVE_FUNCTION_ARG_ACCESS_API |
5e5f6dc1 | 164 | select HAVE_RCU_TABLE_FREE |
409d5db4 | 165 | select HAVE_RSEQ |
d148eac0 | 166 | select HAVE_STACKPROTECTOR |
055b1212 | 167 | select HAVE_SYSCALL_TRACEPOINTS |
2dd0e8d2 | 168 | select HAVE_KPROBES |
cd1ee3b1 | 169 | select HAVE_KRETPROBES |
28b1a824 | 170 | select HAVE_GENERIC_VDSO |
876945db | 171 | select IOMMU_DMA if IOMMU_SUPPORT |
8c2c3df3 | 172 | select IRQ_DOMAIN |
e8557d1f | 173 | select IRQ_FORCED_THREADING |
fea2acaa | 174 | select MODULES_USE_ELF_RELA |
f616ab59 | 175 | select NEED_DMA_MAP_STATE |
86596f0a | 176 | select NEED_SG_DMA_LENGTH |
8c2c3df3 CM |
177 | select OF |
178 | select OF_EARLY_FLATTREE | |
2eac9c2d | 179 | select PCI_DOMAINS_GENERIC if PCI |
52146173 | 180 | select PCI_ECAM if (ACPI && PCI) |
20f1b79d | 181 | select PCI_SYSCALL if PCI |
aa1e8ec1 CM |
182 | select POWER_RESET |
183 | select POWER_SUPPLY | |
8c2c3df3 | 184 | select SPARSE_IRQ |
09230cbc | 185 | select SWIOTLB |
7ac57a89 | 186 | select SYSCTL_EXCEPTION_TRACE |
c02433dd | 187 | select THREAD_INFO_IN_TASK |
8c2c3df3 CM |
188 | help |
189 | ARM 64-bit (AArch64) Linux support. | |
190 | ||
191 | config 64BIT | |
192 | def_bool y | |
193 | ||
8c2c3df3 CM |
194 | config MMU |
195 | def_bool y | |
196 | ||
030c4d24 MR |
197 | config ARM64_PAGE_SHIFT |
198 | int | |
199 | default 16 if ARM64_64K_PAGES | |
200 | default 14 if ARM64_16K_PAGES | |
201 | default 12 | |
202 | ||
203 | config ARM64_CONT_SHIFT | |
204 | int | |
205 | default 5 if ARM64_64K_PAGES | |
206 | default 7 if ARM64_16K_PAGES | |
207 | default 4 | |
208 | ||
8f0d3aa9 DC |
209 | config ARCH_MMAP_RND_BITS_MIN |
210 | default 14 if ARM64_64K_PAGES | |
211 | default 16 if ARM64_16K_PAGES | |
212 | default 18 | |
213 | ||
214 | # max bits determined by the following formula: | |
215 | # VA_BITS - PAGE_SHIFT - 3 | |
216 | config ARCH_MMAP_RND_BITS_MAX | |
217 | default 19 if ARM64_VA_BITS=36 | |
218 | default 24 if ARM64_VA_BITS=39 | |
219 | default 27 if ARM64_VA_BITS=42 | |
220 | default 30 if ARM64_VA_BITS=47 | |
221 | default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES | |
222 | default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES | |
223 | default 33 if ARM64_VA_BITS=48 | |
224 | default 14 if ARM64_64K_PAGES | |
225 | default 16 if ARM64_16K_PAGES | |
226 | default 18 | |
227 | ||
228 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
229 | default 7 if ARM64_64K_PAGES | |
230 | default 9 if ARM64_16K_PAGES | |
231 | default 11 | |
232 | ||
233 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
234 | default 16 | |
235 | ||
ce816fa8 | 236 | config NO_IOPORT_MAP |
d1e6dc91 | 237 | def_bool y if !PCI |
8c2c3df3 CM |
238 | |
239 | config STACKTRACE_SUPPORT | |
240 | def_bool y | |
241 | ||
bf0c4e04 JVS |
242 | config ILLEGAL_POINTER_VALUE |
243 | hex | |
244 | default 0xdead000000000000 | |
245 | ||
8c2c3df3 CM |
246 | config LOCKDEP_SUPPORT |
247 | def_bool y | |
248 | ||
249 | config TRACE_IRQFLAGS_SUPPORT | |
250 | def_bool y | |
251 | ||
9fb7410f DM |
252 | config GENERIC_BUG |
253 | def_bool y | |
254 | depends on BUG | |
255 | ||
256 | config GENERIC_BUG_RELATIVE_POINTERS | |
257 | def_bool y | |
258 | depends on GENERIC_BUG | |
259 | ||
8c2c3df3 CM |
260 | config GENERIC_HWEIGHT |
261 | def_bool y | |
262 | ||
263 | config GENERIC_CSUM | |
264 | def_bool y | |
265 | ||
266 | config GENERIC_CALIBRATE_DELAY | |
267 | def_bool y | |
268 | ||
1a8e1cef NSJ |
269 | config ZONE_DMA |
270 | bool "Support DMA zone" if EXPERT | |
271 | default y | |
272 | ||
ad67f5a6 | 273 | config ZONE_DMA32 |
0c1f14ed MC |
274 | bool "Support DMA32 zone" if EXPERT |
275 | default y | |
8c2c3df3 | 276 | |
4ab21506 RM |
277 | config ARCH_ENABLE_MEMORY_HOTPLUG |
278 | def_bool y | |
279 | ||
4b3dc967 WD |
280 | config SMP |
281 | def_bool y | |
282 | ||
4cfb3613 AB |
283 | config KERNEL_MODE_NEON |
284 | def_bool y | |
285 | ||
92cc15fc RH |
286 | config FIX_EARLYCON_MEM |
287 | def_bool y | |
288 | ||
9f25e6ad KS |
289 | config PGTABLE_LEVELS |
290 | int | |
21539939 | 291 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad | 292 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
b6d00d47 | 293 | default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) |
9f25e6ad | 294 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 |
44eaacf1 SP |
295 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
296 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 297 | |
9842ceae PA |
298 | config ARCH_SUPPORTS_UPROBES |
299 | def_bool y | |
300 | ||
8f360948 AB |
301 | config ARCH_PROC_KCORE_TEXT |
302 | def_bool y | |
303 | ||
6bd1d0be SC |
304 | config KASAN_SHADOW_OFFSET |
305 | hex | |
306 | depends on KASAN | |
b6d00d47 | 307 | default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS |
6bd1d0be SC |
308 | default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS |
309 | default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS | |
310 | default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS | |
311 | default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS | |
b6d00d47 | 312 | default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS |
6bd1d0be SC |
313 | default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS |
314 | default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS | |
315 | default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS | |
316 | default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS | |
317 | default 0xffffffffffffffff | |
318 | ||
6a377491 | 319 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 | 320 | |
8c2c3df3 CM |
321 | menu "Kernel Features" |
322 | ||
c0a01b84 AP |
323 | menu "ARM errata workarounds via the alternatives framework" |
324 | ||
c9460dcb | 325 | config ARM64_WORKAROUND_CLEAN_CACHE |
bc15cf70 | 326 | bool |
c9460dcb | 327 | |
c0a01b84 AP |
328 | config ARM64_ERRATUM_826319 |
329 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
330 | default y | |
c9460dcb | 331 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
332 | help |
333 | This option adds an alternative code sequence to work around ARM | |
334 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
335 | AXI master interface and an L2 cache. | |
336 | ||
337 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
338 | and is unable to accept a certain write via this interface, it will | |
339 | not progress on read data presented on the read data channel and the | |
340 | system can deadlock. | |
341 | ||
342 | The workaround promotes data cache clean instructions to | |
343 | data cache clean-and-invalidate. | |
344 | Please note that this does not necessarily enable the workaround, | |
345 | as it depends on the alternative framework, which will only patch | |
346 | the kernel if an affected CPU is detected. | |
347 | ||
348 | If unsure, say Y. | |
349 | ||
350 | config ARM64_ERRATUM_827319 | |
351 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
352 | default y | |
c9460dcb | 353 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
354 | help |
355 | This option adds an alternative code sequence to work around ARM | |
356 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
357 | master interface and an L2 cache. | |
358 | ||
359 | Under certain conditions this erratum can cause a clean line eviction | |
360 | to occur at the same time as another transaction to the same address | |
361 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
362 | interconnect reorders the two transactions. | |
363 | ||
364 | The workaround promotes data cache clean instructions to | |
365 | data cache clean-and-invalidate. | |
366 | Please note that this does not necessarily enable the workaround, | |
367 | as it depends on the alternative framework, which will only patch | |
368 | the kernel if an affected CPU is detected. | |
369 | ||
370 | If unsure, say Y. | |
371 | ||
372 | config ARM64_ERRATUM_824069 | |
373 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
374 | default y | |
c9460dcb | 375 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
376 | help |
377 | This option adds an alternative code sequence to work around ARM | |
378 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
379 | to a coherent interconnect. | |
380 | ||
381 | If a Cortex-A53 processor is executing a store or prefetch for | |
382 | write instruction at the same time as a processor in another | |
383 | cluster is executing a cache maintenance operation to the same | |
384 | address, then this erratum might cause a clean cache line to be | |
385 | incorrectly marked as dirty. | |
386 | ||
387 | The workaround promotes data cache clean instructions to | |
388 | data cache clean-and-invalidate. | |
389 | Please note that this option does not necessarily enable the | |
390 | workaround, as it depends on the alternative framework, which will | |
391 | only patch the kernel if an affected CPU is detected. | |
392 | ||
393 | If unsure, say Y. | |
394 | ||
395 | config ARM64_ERRATUM_819472 | |
396 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
397 | default y | |
c9460dcb | 398 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
399 | help |
400 | This option adds an alternative code sequence to work around ARM | |
401 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
402 | present when it is connected to a coherent interconnect. | |
403 | ||
404 | If the processor is executing a load and store exclusive sequence at | |
405 | the same time as a processor in another cluster is executing a cache | |
406 | maintenance operation to the same address, then this erratum might | |
407 | cause data corruption. | |
408 | ||
409 | The workaround promotes data cache clean instructions to | |
410 | data cache clean-and-invalidate. | |
411 | Please note that this does not necessarily enable the workaround, | |
412 | as it depends on the alternative framework, which will only patch | |
413 | the kernel if an affected CPU is detected. | |
414 | ||
415 | If unsure, say Y. | |
416 | ||
417 | config ARM64_ERRATUM_832075 | |
418 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
419 | default y | |
420 | help | |
421 | This option adds an alternative code sequence to work around ARM | |
422 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
423 | ||
424 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
425 | instructions to Write-Back memory are mixed with Device loads. | |
426 | ||
427 | The workaround is to promote device loads to use Load-Acquire | |
428 | semantics. | |
429 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
430 | as it depends on the alternative framework, which will only patch |
431 | the kernel if an affected CPU is detected. | |
432 | ||
433 | If unsure, say Y. | |
434 | ||
435 | config ARM64_ERRATUM_834220 | |
436 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" | |
437 | depends on KVM | |
438 | default y | |
439 | help | |
440 | This option adds an alternative code sequence to work around ARM | |
441 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
442 | ||
443 | Affected Cortex-A57 parts might report a Stage 2 translation | |
444 | fault as the result of a Stage 1 fault for load crossing a | |
445 | page boundary when there is a permission or device memory | |
446 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
447 | ||
448 | The workaround is to verify that the Stage 1 translation | |
449 | doesn't generate a fault before handling the Stage 2 fault. | |
450 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
451 | as it depends on the alternative framework, which will only patch |
452 | the kernel if an affected CPU is detected. | |
453 | ||
454 | If unsure, say Y. | |
455 | ||
905e8c5d WD |
456 | config ARM64_ERRATUM_845719 |
457 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
458 | depends on COMPAT | |
459 | default y | |
460 | help | |
461 | This option adds an alternative code sequence to work around ARM | |
462 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
463 | ||
464 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
465 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
466 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
467 | might return incorrect data. | |
468 | ||
469 | The workaround is to write the contextidr_el1 register on exception | |
470 | return to a 32-bit task. | |
471 | Please note that this does not necessarily enable the workaround, | |
472 | as it depends on the alternative framework, which will only patch | |
473 | the kernel if an affected CPU is detected. | |
474 | ||
475 | If unsure, say Y. | |
476 | ||
df057cc7 WD |
477 | config ARM64_ERRATUM_843419 |
478 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
df057cc7 | 479 | default y |
a257e025 | 480 | select ARM64_MODULE_PLTS if MODULES |
df057cc7 | 481 | help |
6ffe9923 | 482 | This option links the kernel with '--fix-cortex-a53-843419' and |
a257e025 AB |
483 | enables PLT support to replace certain ADRP instructions, which can |
484 | cause subsequent memory accesses to use an incorrect address on | |
485 | Cortex-A53 parts up to r0p4. | |
df057cc7 WD |
486 | |
487 | If unsure, say Y. | |
488 | ||
ece1397c SP |
489 | config ARM64_ERRATUM_1024718 |
490 | bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" | |
491 | default y | |
492 | help | |
bc15cf70 | 493 | This option adds a workaround for ARM Cortex-A55 Erratum 1024718. |
ece1397c SP |
494 | |
495 | Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect | |
496 | update of the hardware dirty bit when the DBM/AP bits are updated | |
bc15cf70 | 497 | without a break-before-make. The workaround is to disable the usage |
ece1397c | 498 | of hardware DBM locally on the affected cores. CPUs not affected by |
bc15cf70 | 499 | this erratum will continue to use the feature. |
df057cc7 WD |
500 | |
501 | If unsure, say Y. | |
502 | ||
a5325089 | 503 | config ARM64_ERRATUM_1418040 |
6989303a | 504 | bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" |
95b861a4 | 505 | default y |
c2b5bba3 | 506 | depends on COMPAT |
95b861a4 | 507 | help |
24cf262d | 508 | This option adds a workaround for ARM Cortex-A76/Neoverse-N1 |
a5325089 | 509 | errata 1188873 and 1418040. |
95b861a4 | 510 | |
a5325089 | 511 | Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could |
6989303a MZ |
512 | cause register corruption when accessing the timer registers |
513 | from AArch32 userspace. | |
95b861a4 MZ |
514 | |
515 | If unsure, say Y. | |
516 | ||
a457b0f7 MZ |
517 | config ARM64_ERRATUM_1165522 |
518 | bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" | |
519 | default y | |
520 | help | |
bc15cf70 | 521 | This option adds a workaround for ARM Cortex-A76 erratum 1165522. |
a457b0f7 MZ |
522 | |
523 | Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with | |
524 | corrupted TLBs by speculating an AT instruction during a guest | |
525 | context switch. | |
526 | ||
527 | If unsure, say Y. | |
528 | ||
ce8c80c5 CM |
529 | config ARM64_ERRATUM_1286807 |
530 | bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" | |
531 | default y | |
532 | select ARM64_WORKAROUND_REPEAT_TLBI | |
533 | help | |
bc15cf70 | 534 | This option adds a workaround for ARM Cortex-A76 erratum 1286807. |
ce8c80c5 CM |
535 | |
536 | On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual | |
537 | address for a cacheable mapping of a location is being | |
538 | accessed by a core while another core is remapping the virtual | |
539 | address to a new physical page using the recommended | |
540 | break-before-make sequence, then under very rare circumstances | |
541 | TLBI+DSB completes before a read using the translation being | |
542 | invalidated has been observed by other observers. The | |
543 | workaround repeats the TLBI+DSB operation. | |
544 | ||
c2cc62d8 MZ |
545 | config ARM64_ERRATUM_1319367 |
546 | bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" | |
547 | default y | |
548 | help | |
549 | This option adds work arounds for ARM Cortex-A57 erratum 1319537 | |
550 | and A72 erratum 1319367 | |
551 | ||
552 | Cortex-A57 and A72 cores could end-up with corrupted TLBs by | |
553 | speculating an AT instruction during a guest context switch. | |
554 | ||
ce8c80c5 CM |
555 | If unsure, say Y. |
556 | ||
969f5ea6 WD |
557 | config ARM64_ERRATUM_1463225 |
558 | bool "Cortex-A76: Software Step might prevent interrupt recognition" | |
559 | default y | |
560 | help | |
561 | This option adds a workaround for Arm Cortex-A76 erratum 1463225. | |
562 | ||
563 | On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping | |
564 | of a system call instruction (SVC) can prevent recognition of | |
565 | subsequent interrupts when software stepping is disabled in the | |
566 | exception handler of the system call and either kernel debugging | |
567 | is enabled or VHE is in use. | |
568 | ||
569 | Work around the erratum by triggering a dummy step exception | |
570 | when handling a system call from a task that is being stepped | |
571 | in a VHE configuration of the kernel. | |
572 | ||
573 | If unsure, say Y. | |
574 | ||
05460849 JM |
575 | config ARM64_ERRATUM_1542419 |
576 | bool "Neoverse-N1: workaround mis-ordering of instruction fetches" | |
577 | default y | |
578 | help | |
579 | This option adds a workaround for ARM Neoverse-N1 erratum | |
580 | 1542419. | |
581 | ||
582 | Affected Neoverse-N1 cores could execute a stale instruction when | |
583 | modified by another CPU. The workaround depends on a firmware | |
584 | counterpart. | |
585 | ||
586 | Workaround the issue by hiding the DIC feature from EL0. This | |
587 | forces user-space to perform cache maintenance. | |
588 | ||
589 | If unsure, say Y. | |
590 | ||
94100970 RR |
591 | config CAVIUM_ERRATUM_22375 |
592 | bool "Cavium erratum 22375, 24313" | |
593 | default y | |
594 | help | |
bc15cf70 | 595 | Enable workaround for errata 22375 and 24313. |
94100970 RR |
596 | |
597 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
bc15cf70 | 598 | with a small impact affecting only ITS table allocation. |
94100970 RR |
599 | |
600 | erratum 22375: only alloc 8MB table size | |
601 | erratum 24313: ignore memory access type | |
602 | ||
603 | The fixes are in ITS initialization and basically ignore memory access | |
604 | type and table size provided by the TYPER and BASER registers. | |
605 | ||
606 | If unsure, say Y. | |
607 | ||
fbf8f40e GK |
608 | config CAVIUM_ERRATUM_23144 |
609 | bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" | |
610 | depends on NUMA | |
611 | default y | |
612 | help | |
613 | ITS SYNC command hang for cross node io and collections/cpu mapping. | |
614 | ||
615 | If unsure, say Y. | |
616 | ||
6d4e11c5 RR |
617 | config CAVIUM_ERRATUM_23154 |
618 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" | |
619 | default y | |
620 | help | |
621 | The gicv3 of ThunderX requires a modified version for | |
622 | reading the IAR status to ensure data synchronization | |
623 | (access to icc_iar1_el1 is not sync'ed before and after). | |
624 | ||
625 | If unsure, say Y. | |
626 | ||
104a0c02 AP |
627 | config CAVIUM_ERRATUM_27456 |
628 | bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" | |
629 | default y | |
630 | help | |
631 | On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI | |
632 | instructions may cause the icache to become corrupted if it | |
633 | contains data for a non-current ASID. The fix is to | |
634 | invalidate the icache when changing the mm context. | |
635 | ||
636 | If unsure, say Y. | |
637 | ||
690a3415 DD |
638 | config CAVIUM_ERRATUM_30115 |
639 | bool "Cavium erratum 30115: Guest may disable interrupts in host" | |
640 | default y | |
641 | help | |
642 | On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through | |
643 | 1.2, and T83 Pass 1.0, KVM guest execution may disable | |
644 | interrupts in host. Trapping both GICv3 group-0 and group-1 | |
645 | accesses sidesteps the issue. | |
646 | ||
647 | If unsure, say Y. | |
648 | ||
603afdc9 MZ |
649 | config CAVIUM_TX2_ERRATUM_219 |
650 | bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" | |
651 | default y | |
652 | help | |
653 | On Cavium ThunderX2, a load, store or prefetch instruction between a | |
654 | TTBR update and the corresponding context synchronizing operation can | |
655 | cause a spurious Data Abort to be delivered to any hardware thread in | |
656 | the CPU core. | |
657 | ||
658 | Work around the issue by avoiding the problematic code sequence and | |
659 | trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The | |
660 | trap handler performs the corresponding register access, skips the | |
661 | instruction and ensures context synchronization by virtue of the | |
662 | exception return. | |
663 | ||
664 | If unsure, say Y. | |
665 | ||
38fd94b0 CC |
666 | config QCOM_FALKOR_ERRATUM_1003 |
667 | bool "Falkor E1003: Incorrect translation due to ASID change" | |
668 | default y | |
38fd94b0 CC |
669 | help |
670 | On Falkor v1, an incorrect ASID may be cached in the TLB when ASID | |
d1777e68 WD |
671 | and BADDR are changed together in TTBRx_EL1. Since we keep the ASID |
672 | in TTBR1_EL1, this situation only occurs in the entry trampoline and | |
673 | then only for entries in the walk cache, since the leaf translation | |
674 | is unchanged. Work around the erratum by invalidating the walk cache | |
675 | entries for the trampoline before entering the kernel proper. | |
38fd94b0 | 676 | |
ce8c80c5 CM |
677 | config ARM64_WORKAROUND_REPEAT_TLBI |
678 | bool | |
ce8c80c5 | 679 | |
d9ff80f8 CC |
680 | config QCOM_FALKOR_ERRATUM_1009 |
681 | bool "Falkor E1009: Prematurely complete a DSB after a TLBI" | |
682 | default y | |
ce8c80c5 | 683 | select ARM64_WORKAROUND_REPEAT_TLBI |
d9ff80f8 CC |
684 | help |
685 | On Falkor v1, the CPU may prematurely complete a DSB following a | |
686 | TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation | |
687 | one more time to fix the issue. | |
688 | ||
689 | If unsure, say Y. | |
690 | ||
90922a2d SD |
691 | config QCOM_QDF2400_ERRATUM_0065 |
692 | bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" | |
693 | default y | |
694 | help | |
695 | On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports | |
696 | ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have | |
697 | been indicated as 16Bytes (0xf), not 8Bytes (0x7). | |
698 | ||
699 | If unsure, say Y. | |
700 | ||
558b0165 AB |
701 | config SOCIONEXT_SYNQUACER_PREITS |
702 | bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" | |
703 | default y | |
704 | help | |
705 | Socionext Synquacer SoCs implement a separate h/w block to generate | |
706 | MSI doorbell writes with non-zero values for the device ID. | |
707 | ||
5c9a882e MZ |
708 | If unsure, say Y. |
709 | ||
710 | config HISILICON_ERRATUM_161600802 | |
711 | bool "Hip07 161600802: Erroneous redistributor VLPI base" | |
712 | default y | |
713 | help | |
bc15cf70 | 714 | The HiSilicon Hip07 SoC uses the wrong redistributor base |
5c9a882e MZ |
715 | when issued ITS commands such as VMOVP and VMAPP, and requires |
716 | a 128kB offset to be applied to the target address in this commands. | |
717 | ||
558b0165 | 718 | If unsure, say Y. |
932b50c7 SD |
719 | |
720 | config QCOM_FALKOR_ERRATUM_E1041 | |
721 | bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" | |
722 | default y | |
723 | help | |
724 | Falkor CPU may speculatively fetch instructions from an improper | |
725 | memory location when MMU translation is changed from SCTLR_ELn[M]=1 | |
726 | to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. | |
727 | ||
728 | If unsure, say Y. | |
729 | ||
3e32131a ZL |
730 | config FUJITSU_ERRATUM_010001 |
731 | bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" | |
732 | default y | |
733 | help | |
bc15cf70 | 734 | This option adds a workaround for Fujitsu-A64FX erratum E#010001. |
3e32131a ZL |
735 | On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory |
736 | accesses may cause undefined fault (Data abort, DFSC=0b111111). | |
737 | This fault occurs under a specific hardware condition when a | |
738 | load/store instruction performs an address translation using: | |
739 | case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. | |
740 | case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. | |
741 | case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. | |
742 | case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. | |
743 | ||
744 | The workaround is to ensure these bits are clear in TCR_ELx. | |
bc15cf70 | 745 | The workaround only affects the Fujitsu-A64FX. |
3e32131a ZL |
746 | |
747 | If unsure, say Y. | |
748 | ||
c0a01b84 AP |
749 | endmenu |
750 | ||
751 | ||
e41ceed0 JL |
752 | choice |
753 | prompt "Page size" | |
754 | default ARM64_4K_PAGES | |
755 | help | |
756 | Page size (translation granule) configuration. | |
757 | ||
758 | config ARM64_4K_PAGES | |
759 | bool "4KB" | |
760 | help | |
761 | This feature enables 4KB pages support. | |
762 | ||
44eaacf1 SP |
763 | config ARM64_16K_PAGES |
764 | bool "16KB" | |
765 | help | |
766 | The system will use 16KB pages support. AArch32 emulation | |
767 | requires applications compiled with 16K (or a multiple of 16K) | |
768 | aligned segments. | |
769 | ||
8c2c3df3 | 770 | config ARM64_64K_PAGES |
e41ceed0 | 771 | bool "64KB" |
8c2c3df3 CM |
772 | help |
773 | This feature enables 64KB pages support (4KB by default) | |
774 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
775 | look-up. AArch32 emulation requires applications compiled |
776 | with 64K aligned segments. | |
8c2c3df3 | 777 | |
e41ceed0 JL |
778 | endchoice |
779 | ||
780 | choice | |
781 | prompt "Virtual address space size" | |
782 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 783 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
784 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
785 | help | |
786 | Allows choosing one of multiple possible virtual address | |
787 | space sizes. The level of translation table is determined by | |
788 | a combination of page size and virtual address space size. | |
789 | ||
21539939 | 790 | config ARM64_VA_BITS_36 |
56a3f30e | 791 | bool "36-bit" if EXPERT |
21539939 SP |
792 | depends on ARM64_16K_PAGES |
793 | ||
e41ceed0 JL |
794 | config ARM64_VA_BITS_39 |
795 | bool "39-bit" | |
796 | depends on ARM64_4K_PAGES | |
797 | ||
798 | config ARM64_VA_BITS_42 | |
799 | bool "42-bit" | |
800 | depends on ARM64_64K_PAGES | |
801 | ||
44eaacf1 SP |
802 | config ARM64_VA_BITS_47 |
803 | bool "47-bit" | |
804 | depends on ARM64_16K_PAGES | |
805 | ||
c79b954b JL |
806 | config ARM64_VA_BITS_48 |
807 | bool "48-bit" | |
c79b954b | 808 | |
b6d00d47 SC |
809 | config ARM64_VA_BITS_52 |
810 | bool "52-bit" | |
68d23da4 WD |
811 | depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) |
812 | help | |
813 | Enable 52-bit virtual addressing for userspace when explicitly | |
b6d00d47 SC |
814 | requested via a hint to mmap(). The kernel will also use 52-bit |
815 | virtual addresses for its own mappings (provided HW support for | |
816 | this feature is available, otherwise it reverts to 48-bit). | |
68d23da4 WD |
817 | |
818 | NOTE: Enabling 52-bit virtual addressing in conjunction with | |
819 | ARMv8.3 Pointer Authentication will result in the PAC being | |
820 | reduced from 7 bits to 3 bits, which may have a significant | |
821 | impact on its susceptibility to brute-force attacks. | |
822 | ||
823 | If unsure, select 48-bit virtual addressing instead. | |
824 | ||
e41ceed0 JL |
825 | endchoice |
826 | ||
68d23da4 WD |
827 | config ARM64_FORCE_52BIT |
828 | bool "Force 52-bit virtual addresses for userspace" | |
b6d00d47 | 829 | depends on ARM64_VA_BITS_52 && EXPERT |
68d23da4 WD |
830 | help |
831 | For systems with 52-bit userspace VAs enabled, the kernel will attempt | |
832 | to maintain compatibility with older software by providing 48-bit VAs | |
833 | unless a hint is supplied to mmap. | |
834 | ||
835 | This configuration option disables the 48-bit compatibility logic, and | |
836 | forces all userspace addresses to be 52-bit on HW that supports it. One | |
837 | should only enable this configuration option for stress testing userspace | |
838 | memory management code. If unsure say N here. | |
839 | ||
e41ceed0 JL |
840 | config ARM64_VA_BITS |
841 | int | |
21539939 | 842 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
843 | default 39 if ARM64_VA_BITS_39 |
844 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 845 | default 47 if ARM64_VA_BITS_47 |
b6d00d47 SC |
846 | default 48 if ARM64_VA_BITS_48 |
847 | default 52 if ARM64_VA_BITS_52 | |
e41ceed0 | 848 | |
982aa7c5 KM |
849 | choice |
850 | prompt "Physical address space size" | |
851 | default ARM64_PA_BITS_48 | |
852 | help | |
853 | Choose the maximum physical address range that the kernel will | |
854 | support. | |
855 | ||
856 | config ARM64_PA_BITS_48 | |
857 | bool "48-bit" | |
858 | ||
f77d2817 KM |
859 | config ARM64_PA_BITS_52 |
860 | bool "52-bit (ARMv8.2)" | |
861 | depends on ARM64_64K_PAGES | |
862 | depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN | |
863 | help | |
864 | Enable support for a 52-bit physical address space, introduced as | |
865 | part of the ARMv8.2-LPA extension. | |
866 | ||
867 | With this enabled, the kernel will also continue to work on CPUs that | |
868 | do not support ARMv8.2-LPA, but with some added memory overhead (and | |
869 | minor performance overhead). | |
870 | ||
982aa7c5 KM |
871 | endchoice |
872 | ||
873 | config ARM64_PA_BITS | |
874 | int | |
875 | default 48 if ARM64_PA_BITS_48 | |
f77d2817 | 876 | default 52 if ARM64_PA_BITS_52 |
982aa7c5 | 877 | |
d8e85e14 AR |
878 | choice |
879 | prompt "Endianness" | |
880 | default CPU_LITTLE_ENDIAN | |
881 | help | |
882 | Select the endianness of data accesses performed by the CPU. Userspace | |
883 | applications will need to be compiled and linked for the endianness | |
884 | that is selected here. | |
885 | ||
a872013d WD |
886 | config CPU_BIG_ENDIAN |
887 | bool "Build big-endian kernel" | |
888 | help | |
d8e85e14 AR |
889 | Say Y if you plan on running a kernel with a big-endian userspace. |
890 | ||
891 | config CPU_LITTLE_ENDIAN | |
892 | bool "Build little-endian kernel" | |
893 | help | |
894 | Say Y if you plan on running a kernel with a little-endian userspace. | |
895 | This is usually the case for distributions targeting arm64. | |
896 | ||
897 | endchoice | |
a872013d | 898 | |
f6e763b9 MB |
899 | config SCHED_MC |
900 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
901 | help |
902 | Multi-core scheduler support improves the CPU scheduler's decision | |
903 | making when dealing with multi-core CPU chips at a cost of slightly | |
904 | increased overhead in some places. If unsure say N here. | |
905 | ||
906 | config SCHED_SMT | |
907 | bool "SMT scheduler support" | |
f6e763b9 MB |
908 | help |
909 | Improves the CPU scheduler's decision making when dealing with | |
910 | MultiThreading at a cost of slightly increased overhead in some | |
911 | places. If unsure say N here. | |
912 | ||
8c2c3df3 | 913 | config NR_CPUS |
62aa9655 GK |
914 | int "Maximum number of CPUs (2-4096)" |
915 | range 2 4096 | |
846a415b | 916 | default "256" |
8c2c3df3 | 917 | |
9327e2c6 MR |
918 | config HOTPLUG_CPU |
919 | bool "Support for hot-pluggable CPUs" | |
217d453d | 920 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
921 | help |
922 | Say Y here to experiment with turning CPUs off and on. CPUs | |
923 | can be controlled through /sys/devices/system/cpu. | |
924 | ||
1a2db300 GK |
925 | # Common NUMA Features |
926 | config NUMA | |
927 | bool "Numa Memory Allocation and Scheduler Support" | |
0c2a6cce KW |
928 | select ACPI_NUMA if ACPI |
929 | select OF_NUMA | |
1a2db300 GK |
930 | help |
931 | Enable NUMA (Non Uniform Memory Access) support. | |
932 | ||
933 | The kernel will try to allocate memory used by a CPU on the | |
934 | local memory of the CPU and add some more | |
935 | NUMA awareness to the kernel. | |
936 | ||
937 | config NODES_SHIFT | |
938 | int "Maximum NUMA Nodes (as a power of 2)" | |
939 | range 1 10 | |
940 | default "2" | |
941 | depends on NEED_MULTIPLE_NODES | |
942 | help | |
943 | Specify the maximum number of NUMA Nodes available on the target | |
944 | system. Increases memory reserved to accommodate various tables. | |
945 | ||
946 | config USE_PERCPU_NUMA_NODE_ID | |
947 | def_bool y | |
948 | depends on NUMA | |
949 | ||
7af3a0a9 ZL |
950 | config HAVE_SETUP_PER_CPU_AREA |
951 | def_bool y | |
952 | depends on NUMA | |
953 | ||
954 | config NEED_PER_CPU_EMBED_FIRST_CHUNK | |
955 | def_bool y | |
956 | depends on NUMA | |
957 | ||
6d526ee2 AB |
958 | config HOLES_IN_ZONE |
959 | def_bool y | |
6d526ee2 | 960 | |
8636a1f9 | 961 | source "kernel/Kconfig.hz" |
8c2c3df3 | 962 | |
83863f25 LA |
963 | config ARCH_SUPPORTS_DEBUG_PAGEALLOC |
964 | def_bool y | |
965 | ||
8c2c3df3 CM |
966 | config ARCH_SPARSEMEM_ENABLE |
967 | def_bool y | |
968 | select SPARSEMEM_VMEMMAP_ENABLE | |
969 | ||
970 | config ARCH_SPARSEMEM_DEFAULT | |
971 | def_bool ARCH_SPARSEMEM_ENABLE | |
972 | ||
973 | config ARCH_SELECT_MEMORY_MODEL | |
974 | def_bool ARCH_SPARSEMEM_ENABLE | |
975 | ||
e7d4bac4 | 976 | config ARCH_FLATMEM_ENABLE |
54501ac1 | 977 | def_bool !NUMA |
e7d4bac4 | 978 | |
8c2c3df3 | 979 | config HAVE_ARCH_PFN_VALID |
8a695a58 | 980 | def_bool y |
8c2c3df3 CM |
981 | |
982 | config HW_PERF_EVENTS | |
6475b2d8 MR |
983 | def_bool y |
984 | depends on ARM_PMU | |
8c2c3df3 | 985 | |
084bd298 SC |
986 | config SYS_SUPPORTS_HUGETLBFS |
987 | def_bool y | |
988 | ||
084bd298 | 989 | config ARCH_WANT_HUGE_PMD_SHARE |
084bd298 | 990 | |
a41dc0e8 CM |
991 | config ARCH_HAS_CACHE_LINE_SIZE |
992 | def_bool y | |
993 | ||
54c8d911 YZ |
994 | config ARCH_ENABLE_SPLIT_PMD_PTLOCK |
995 | def_bool y if PGTABLE_LEVELS > 2 | |
996 | ||
a1ae65b2 AT |
997 | config SECCOMP |
998 | bool "Enable seccomp to safely compute untrusted bytecode" | |
999 | ---help--- | |
1000 | This kernel feature is useful for number crunching applications | |
1001 | that may need to compute untrusted bytecode during their | |
1002 | execution. By using pipes or other transports made available to | |
1003 | the process as file descriptors supporting the read/write | |
1004 | syscalls, it's possible to isolate those applications in | |
1005 | their own address space using seccomp. Once seccomp is | |
1006 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1007 | and the task is only allowed to execute a few safe syscalls | |
1008 | defined by each seccomp mode. | |
1009 | ||
dfd57bc3 SS |
1010 | config PARAVIRT |
1011 | bool "Enable paravirtualization code" | |
1012 | help | |
1013 | This changes the kernel so it can modify itself when it is run | |
1014 | under a hypervisor, potentially improving performance significantly | |
1015 | over full virtualization. | |
1016 | ||
1017 | config PARAVIRT_TIME_ACCOUNTING | |
1018 | bool "Paravirtual steal time accounting" | |
1019 | select PARAVIRT | |
dfd57bc3 SS |
1020 | help |
1021 | Select this option to enable fine granularity task steal time | |
1022 | accounting. Time spent executing other tasks in parallel with | |
1023 | the current vCPU is discounted from the vCPU power. To account for | |
1024 | that, there can be a small performance impact. | |
1025 | ||
1026 | If in doubt, say N here. | |
1027 | ||
d28f6df1 GL |
1028 | config KEXEC |
1029 | depends on PM_SLEEP_SMP | |
1030 | select KEXEC_CORE | |
1031 | bool "kexec system call" | |
1032 | ---help--- | |
1033 | kexec is a system call that implements the ability to shutdown your | |
1034 | current kernel, and to start another kernel. It is like a reboot | |
1035 | but it is independent of the system firmware. And like a reboot | |
1036 | you can start any kernel with it, not just Linux. | |
1037 | ||
3ddd9992 AT |
1038 | config KEXEC_FILE |
1039 | bool "kexec file based system call" | |
1040 | select KEXEC_CORE | |
1041 | help | |
1042 | This is new version of kexec system call. This system call is | |
1043 | file based and takes file descriptors as system call argument | |
1044 | for kernel and initramfs as opposed to list of segments as | |
1045 | accepted by previous system call. | |
1046 | ||
99d5cadf | 1047 | config KEXEC_SIG |
732b7b93 AT |
1048 | bool "Verify kernel signature during kexec_file_load() syscall" |
1049 | depends on KEXEC_FILE | |
1050 | help | |
1051 | Select this option to verify a signature with loaded kernel | |
1052 | image. If configured, any attempt of loading a image without | |
1053 | valid signature will fail. | |
1054 | ||
1055 | In addition to that option, you need to enable signature | |
1056 | verification for the corresponding kernel image type being | |
1057 | loaded in order for this to work. | |
1058 | ||
1059 | config KEXEC_IMAGE_VERIFY_SIG | |
1060 | bool "Enable Image signature verification support" | |
1061 | default y | |
99d5cadf | 1062 | depends on KEXEC_SIG |
732b7b93 AT |
1063 | depends on EFI && SIGNED_PE_FILE_VERIFICATION |
1064 | help | |
1065 | Enable Image signature verification support. | |
1066 | ||
1067 | comment "Support for PE file signature verification disabled" | |
99d5cadf | 1068 | depends on KEXEC_SIG |
732b7b93 AT |
1069 | depends on !EFI || !SIGNED_PE_FILE_VERIFICATION |
1070 | ||
e62aaeac AT |
1071 | config CRASH_DUMP |
1072 | bool "Build kdump crash kernel" | |
1073 | help | |
1074 | Generate crash dump after being started by kexec. This should | |
1075 | be normally only set in special crash dump kernels which are | |
1076 | loaded in the main kernel with kexec-tools into a specially | |
1077 | reserved region and then later executed after a crash by | |
1078 | kdump/kexec. | |
1079 | ||
330d4810 | 1080 | For more details see Documentation/admin-guide/kdump/kdump.rst |
e62aaeac | 1081 | |
aa42aa13 SS |
1082 | config XEN_DOM0 |
1083 | def_bool y | |
1084 | depends on XEN | |
1085 | ||
1086 | config XEN | |
c2ba1f7d | 1087 | bool "Xen guest support on ARM64" |
aa42aa13 | 1088 | depends on ARM64 && OF |
83862ccf | 1089 | select SWIOTLB_XEN |
dfd57bc3 | 1090 | select PARAVIRT |
aa42aa13 SS |
1091 | help |
1092 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
1093 | ||
d03bb145 SC |
1094 | config FORCE_MAX_ZONEORDER |
1095 | int | |
1096 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
44eaacf1 | 1097 | default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) |
d03bb145 | 1098 | default "11" |
44eaacf1 SP |
1099 | help |
1100 | The kernel memory allocator divides physically contiguous memory | |
1101 | blocks into "zones", where each zone is a power of two number of | |
1102 | pages. This option selects the largest power of two that the kernel | |
1103 | keeps in the memory allocator. If you need to allocate very large | |
1104 | blocks of physically contiguous memory, then you may need to | |
1105 | increase this value. | |
1106 | ||
1107 | This config option is actually maximum order plus one. For example, | |
1108 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1109 | ||
1110 | We make sure that we can allocate upto a HugePage size for each configuration. | |
1111 | Hence we have : | |
1112 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 | |
1113 | ||
1114 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us | |
1115 | 4M allocations matching the default size used by generic code. | |
d03bb145 | 1116 | |
084eb77c | 1117 | config UNMAP_KERNEL_AT_EL0 |
0617052d | 1118 | bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT |
084eb77c WD |
1119 | default y |
1120 | help | |
0617052d WD |
1121 | Speculation attacks against some high-performance processors can |
1122 | be used to bypass MMU permission checks and leak kernel data to | |
1123 | userspace. This can be defended against by unmapping the kernel | |
1124 | when running in userspace, mapping it back in on exception entry | |
1125 | via a trampoline page in the vector table. | |
084eb77c WD |
1126 | |
1127 | If unsure, say Y. | |
1128 | ||
0f15adbb WD |
1129 | config HARDEN_BRANCH_PREDICTOR |
1130 | bool "Harden the branch predictor against aliasing attacks" if EXPERT | |
1131 | default y | |
1132 | help | |
1133 | Speculation attacks against some high-performance processors rely on | |
1134 | being able to manipulate the branch predictor for a victim context by | |
1135 | executing aliasing branches in the attacker context. Such attacks | |
1136 | can be partially mitigated against by clearing internal branch | |
1137 | predictor state and limiting the prediction logic in some situations. | |
1138 | ||
1139 | This config option will take CPU-specific actions to harden the | |
1140 | branch predictor against aliasing attacks and may rely on specific | |
1141 | instruction sequences or control bits being set by the system | |
1142 | firmware. | |
1143 | ||
1144 | If unsure, say Y. | |
1145 | ||
dee39247 MZ |
1146 | config HARDEN_EL2_VECTORS |
1147 | bool "Harden EL2 vector mapping against system register leak" if EXPERT | |
1148 | default y | |
1149 | help | |
1150 | Speculation attacks against some high-performance processors can | |
1151 | be used to leak privileged information such as the vector base | |
1152 | register, resulting in a potential defeat of the EL2 layout | |
1153 | randomization. | |
1154 | ||
1155 | This config option will map the vectors to a fixed location, | |
1156 | independent of the EL2 code mapping, so that revealing VBAR_EL2 | |
1157 | to an attacker does not give away any extra information. This | |
1158 | only gets enabled on affected CPUs. | |
1159 | ||
1160 | If unsure, say Y. | |
1161 | ||
a725e3dd MZ |
1162 | config ARM64_SSBD |
1163 | bool "Speculative Store Bypass Disable" if EXPERT | |
1164 | default y | |
1165 | help | |
1166 | This enables mitigation of the bypassing of previous stores | |
1167 | by speculative loads. | |
1168 | ||
1169 | If unsure, say Y. | |
1170 | ||
c55191e9 AB |
1171 | config RODATA_FULL_DEFAULT_ENABLED |
1172 | bool "Apply r/o permissions of VM areas also to their linear aliases" | |
1173 | default y | |
1174 | help | |
1175 | Apply read-only attributes of VM areas to the linear alias of | |
1176 | the backing pages as well. This prevents code or read-only data | |
1177 | from being modified (inadvertently or intentionally) via another | |
1178 | mapping of the same memory page. This additional enhancement can | |
1179 | be turned off at runtime by passing rodata=[off|on] (and turned on | |
1180 | with rodata=full if this option is set to 'n') | |
1181 | ||
1182 | This requires the linear region to be mapped down to pages, | |
1183 | which may adversely affect performance in some cases. | |
1184 | ||
dd523791 WD |
1185 | config ARM64_SW_TTBR0_PAN |
1186 | bool "Emulate Privileged Access Never using TTBR0_EL1 switching" | |
1187 | help | |
1188 | Enabling this option prevents the kernel from accessing | |
1189 | user-space memory directly by pointing TTBR0_EL1 to a reserved | |
1190 | zeroed area and reserved ASID. The user access routines | |
1191 | restore the valid TTBR0_EL1 temporarily. | |
1192 | ||
63f0c603 CM |
1193 | config ARM64_TAGGED_ADDR_ABI |
1194 | bool "Enable the tagged user addresses syscall ABI" | |
1195 | default y | |
1196 | help | |
1197 | When this option is enabled, user applications can opt in to a | |
1198 | relaxed ABI via prctl() allowing tagged addresses to be passed | |
1199 | to system calls as pointer arguments. For details, see | |
799c8510 | 1200 | Documentation/arm64/tagged-address-abi.rst. |
63f0c603 | 1201 | |
dd523791 WD |
1202 | menuconfig COMPAT |
1203 | bool "Kernel support for 32-bit EL0" | |
1204 | depends on ARM64_4K_PAGES || EXPERT | |
1205 | select COMPAT_BINFMT_ELF if BINFMT_ELF | |
1206 | select HAVE_UID16 | |
1207 | select OLD_SIGSUSPEND3 | |
1208 | select COMPAT_OLD_SIGACTION | |
1209 | help | |
1210 | This option enables support for a 32-bit EL0 running under a 64-bit | |
1211 | kernel at EL1. AArch32-specific components such as system calls, | |
1212 | the user helper functions, VFP support and the ptrace interface are | |
1213 | handled appropriately by the kernel. | |
1214 | ||
1215 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware | |
1216 | that you will only be able to execute AArch32 binaries that were compiled | |
1217 | with page size aligned segments. | |
1218 | ||
1219 | If you want to execute 32-bit userspace applications, say Y. | |
1220 | ||
1221 | if COMPAT | |
1222 | ||
1223 | config KUSER_HELPERS | |
7c4791c9 | 1224 | bool "Enable kuser helpers page for 32-bit applications" |
dd523791 WD |
1225 | default y |
1226 | help | |
1227 | Warning: disabling this option may break 32-bit user programs. | |
1228 | ||
1229 | Provide kuser helpers to compat tasks. The kernel provides | |
1230 | helper code to userspace in read only form at a fixed location | |
1231 | to allow userspace to be independent of the CPU type fitted to | |
1232 | the system. This permits binaries to be run on ARMv4 through | |
1233 | to ARMv8 without modification. | |
1234 | ||
dc7a12bd | 1235 | See Documentation/arm/kernel_user_helpers.rst for details. |
dd523791 WD |
1236 | |
1237 | However, the fixed address nature of these helpers can be used | |
1238 | by ROP (return orientated programming) authors when creating | |
1239 | exploits. | |
1240 | ||
1241 | If all of the binaries and libraries which run on your platform | |
1242 | are built specifically for your platform, and make no use of | |
1243 | these helpers, then you can turn this option off to hinder | |
1244 | such exploits. However, in that case, if a binary or library | |
1245 | relying on those helpers is run, it will not function correctly. | |
1246 | ||
1247 | Say N here only if you are absolutely certain that you do not | |
1248 | need these helpers; otherwise, the safe option is to say Y. | |
1249 | ||
7c4791c9 WD |
1250 | config COMPAT_VDSO |
1251 | bool "Enable vDSO for 32-bit applications" | |
1252 | depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != "" | |
1253 | select GENERIC_COMPAT_VDSO | |
1254 | default y | |
1255 | help | |
1256 | Place in the process address space of 32-bit applications an | |
1257 | ELF shared object providing fast implementations of gettimeofday | |
1258 | and clock_gettime. | |
1259 | ||
1260 | You must have a 32-bit build of glibc 2.22 or later for programs | |
1261 | to seamlessly take advantage of this. | |
dd523791 | 1262 | |
1b907f46 WD |
1263 | menuconfig ARMV8_DEPRECATED |
1264 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
6cfa7cc4 | 1265 | depends on SYSCTL |
1b907f46 WD |
1266 | help |
1267 | Legacy software support may require certain instructions | |
1268 | that have been deprecated or obsoleted in the architecture. | |
1269 | ||
1270 | Enable this config to enable selective emulation of these | |
1271 | features. | |
1272 | ||
1273 | If unsure, say Y | |
1274 | ||
1275 | if ARMV8_DEPRECATED | |
1276 | ||
1277 | config SWP_EMULATION | |
1278 | bool "Emulate SWP/SWPB instructions" | |
1279 | help | |
1280 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
1281 | they are always undefined. Say Y here to enable software | |
1282 | emulation of these instructions for userspace using LDXR/STXR. | |
1283 | ||
1284 | In some older versions of glibc [<=2.8] SWP is used during futex | |
1285 | trylock() operations with the assumption that the code will not | |
1286 | be preempted. This invalid assumption may be more likely to fail | |
1287 | with SWP emulation enabled, leading to deadlock of the user | |
1288 | application. | |
1289 | ||
1290 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
1291 | on an external transaction monitoring block called a global | |
1292 | monitor to maintain update atomicity. If your system does not | |
1293 | implement a global monitor, this option can cause programs that | |
1294 | perform SWP operations to uncached memory to deadlock. | |
1295 | ||
1296 | If unsure, say Y | |
1297 | ||
1298 | config CP15_BARRIER_EMULATION | |
1299 | bool "Emulate CP15 Barrier instructions" | |
1300 | help | |
1301 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
1302 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
1303 | strongly recommended to use the ISB, DSB, and DMB | |
1304 | instructions instead. | |
1305 | ||
1306 | Say Y here to enable software emulation of these | |
1307 | instructions for AArch32 userspace code. When this option is | |
1308 | enabled, CP15 barrier usage is traced which can help | |
1309 | identify software that needs updating. | |
1310 | ||
1311 | If unsure, say Y | |
1312 | ||
2d888f48 SP |
1313 | config SETEND_EMULATION |
1314 | bool "Emulate SETEND instruction" | |
1315 | help | |
1316 | The SETEND instruction alters the data-endianness of the | |
1317 | AArch32 EL0, and is deprecated in ARMv8. | |
1318 | ||
1319 | Say Y here to enable software emulation of the instruction | |
1320 | for AArch32 userspace code. | |
1321 | ||
1322 | Note: All the cpus on the system must have mixed endian support at EL0 | |
1323 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
1324 | endian - is hotplugged in after this feature has been enabled, there could | |
1325 | be unexpected results in the applications. | |
1326 | ||
1327 | If unsure, say Y | |
1b907f46 WD |
1328 | endif |
1329 | ||
dd523791 | 1330 | endif |
ba42822a | 1331 | |
0e4a0709 WD |
1332 | menu "ARMv8.1 architectural features" |
1333 | ||
1334 | config ARM64_HW_AFDBM | |
1335 | bool "Support for hardware updates of the Access and Dirty page flags" | |
1336 | default y | |
1337 | help | |
1338 | The ARMv8.1 architecture extensions introduce support for | |
1339 | hardware updates of the access and dirty information in page | |
1340 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
1341 | capable processors, accesses to pages with PTE_AF cleared will | |
1342 | set this bit instead of raising an access flag fault. | |
1343 | Similarly, writes to read-only pages with the DBM bit set will | |
1344 | clear the read-only bit (AP[2]) instead of raising a | |
1345 | permission fault. | |
1346 | ||
1347 | Kernels built with this configuration option enabled continue | |
1348 | to work on pre-ARMv8.1 hardware and the performance impact is | |
1349 | minimal. If unsure, say Y. | |
1350 | ||
1351 | config ARM64_PAN | |
1352 | bool "Enable support for Privileged Access Never (PAN)" | |
1353 | default y | |
1354 | help | |
1355 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
1356 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
1357 | memory directly. | |
1358 | ||
1359 | Choosing this option will cause any unprotected (not using | |
1360 | copy_to_user et al) memory access to fail with a permission fault. | |
1361 | ||
1362 | The feature is detected at runtime, and will remain as a 'nop' | |
1363 | instruction if the cpu does not implement the feature. | |
1364 | ||
1365 | config ARM64_LSE_ATOMICS | |
1366 | bool "Atomic instructions" | |
b32baf91 | 1367 | depends on JUMP_LABEL |
7bd99b40 | 1368 | default y |
0e4a0709 WD |
1369 | help |
1370 | As part of the Large System Extensions, ARMv8.1 introduces new | |
1371 | atomic instructions that are designed specifically to scale in | |
1372 | very large systems. | |
1373 | ||
1374 | Say Y here to make use of these instructions for the in-kernel | |
1375 | atomic routines. This incurs a small overhead on CPUs that do | |
1376 | not support these instructions and requires the kernel to be | |
7bd99b40 WD |
1377 | built with binutils >= 2.25 in order for the new instructions |
1378 | to be used. | |
0e4a0709 | 1379 | |
1f364c8c MZ |
1380 | config ARM64_VHE |
1381 | bool "Enable support for Virtualization Host Extensions (VHE)" | |
1382 | default y | |
1383 | help | |
1384 | Virtualization Host Extensions (VHE) allow the kernel to run | |
1385 | directly at EL2 (instead of EL1) on processors that support | |
1386 | it. This leads to better performance for KVM, as they reduce | |
1387 | the cost of the world switch. | |
1388 | ||
1389 | Selecting this option allows the VHE feature to be detected | |
1390 | at runtime, and does not affect processors that do not | |
1391 | implement this feature. | |
1392 | ||
0e4a0709 WD |
1393 | endmenu |
1394 | ||
f993318b WD |
1395 | menu "ARMv8.2 architectural features" |
1396 | ||
57f4959b JM |
1397 | config ARM64_UAO |
1398 | bool "Enable support for User Access Override (UAO)" | |
1399 | default y | |
1400 | help | |
1401 | User Access Override (UAO; part of the ARMv8.2 Extensions) | |
1402 | causes the 'unprivileged' variant of the load/store instructions to | |
83fc61a5 | 1403 | be overridden to be privileged. |
57f4959b JM |
1404 | |
1405 | This option changes get_user() and friends to use the 'unprivileged' | |
1406 | variant of the load/store instructions. This ensures that user-space | |
1407 | really did have access to the supplied memory. When addr_limit is | |
1408 | set to kernel memory the UAO bit will be set, allowing privileged | |
1409 | access to kernel memory. | |
1410 | ||
1411 | Choosing this option will cause copy_to_user() et al to use user-space | |
1412 | memory permissions. | |
1413 | ||
1414 | The feature is detected at runtime, the kernel will use the | |
1415 | regular load/store instructions if the cpu does not implement the | |
1416 | feature. | |
1417 | ||
d50e071f RM |
1418 | config ARM64_PMEM |
1419 | bool "Enable support for persistent memory" | |
1420 | select ARCH_HAS_PMEM_API | |
5d7bdeb1 | 1421 | select ARCH_HAS_UACCESS_FLUSHCACHE |
d50e071f RM |
1422 | help |
1423 | Say Y to enable support for the persistent memory API based on the | |
1424 | ARMv8.2 DCPoP feature. | |
1425 | ||
1426 | The feature is detected at runtime, and the kernel will use DC CVAC | |
1427 | operations if DC CVAP is not supported (following the behaviour of | |
1428 | DC CVAP itself if the system does not define a point of persistence). | |
1429 | ||
64c02720 XX |
1430 | config ARM64_RAS_EXTN |
1431 | bool "Enable support for RAS CPU Extensions" | |
1432 | default y | |
1433 | help | |
1434 | CPUs that support the Reliability, Availability and Serviceability | |
1435 | (RAS) Extensions, part of ARMv8.2 are able to track faults and | |
1436 | errors, classify them and report them to software. | |
1437 | ||
1438 | On CPUs with these extensions system software can use additional | |
1439 | barriers to determine if faults are pending and read the | |
1440 | classification from a new set of registers. | |
1441 | ||
1442 | Selecting this feature will allow the kernel to use these barriers | |
1443 | and access the new registers if the system supports the extension. | |
1444 | Platform RAS features may additionally depend on firmware support. | |
1445 | ||
5ffdfaed VM |
1446 | config ARM64_CNP |
1447 | bool "Enable support for Common Not Private (CNP) translations" | |
1448 | default y | |
1449 | depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN | |
1450 | help | |
1451 | Common Not Private (CNP) allows translation table entries to | |
1452 | be shared between different PEs in the same inner shareable | |
1453 | domain, so the hardware can use this fact to optimise the | |
1454 | caching of such entries in the TLB. | |
1455 | ||
1456 | Selecting this option allows the CNP feature to be detected | |
1457 | at runtime, and does not affect PEs that do not implement | |
1458 | this feature. | |
1459 | ||
f993318b WD |
1460 | endmenu |
1461 | ||
04ca3204 MR |
1462 | menu "ARMv8.3 architectural features" |
1463 | ||
1464 | config ARM64_PTR_AUTH | |
1465 | bool "Enable support for pointer authentication" | |
1466 | default y | |
384b40ca | 1467 | depends on !KVM || ARM64_VHE |
04ca3204 MR |
1468 | help |
1469 | Pointer authentication (part of the ARMv8.3 Extensions) provides | |
1470 | instructions for signing and authenticating pointers against secret | |
1471 | keys, which can be used to mitigate Return Oriented Programming (ROP) | |
1472 | and other attacks. | |
1473 | ||
1474 | This option enables these instructions at EL0 (i.e. for userspace). | |
1475 | ||
1476 | Choosing this option will cause the kernel to initialise secret keys | |
1477 | for each process at exec() time, with these keys being | |
1478 | context-switched along with the process. | |
1479 | ||
1480 | The feature is detected at runtime. If the feature is not present in | |
384b40ca MR |
1481 | hardware it will not be advertised to userspace/KVM guest nor will it |
1482 | be enabled. However, KVM guest also require VHE mode and hence | |
1483 | CONFIG_ARM64_VHE=y option to use this feature. | |
04ca3204 MR |
1484 | |
1485 | endmenu | |
1486 | ||
ddd25ad1 DM |
1487 | config ARM64_SVE |
1488 | bool "ARM Scalable Vector Extension support" | |
1489 | default y | |
85acda3b | 1490 | depends on !KVM || ARM64_VHE |
ddd25ad1 DM |
1491 | help |
1492 | The Scalable Vector Extension (SVE) is an extension to the AArch64 | |
1493 | execution state which complements and extends the SIMD functionality | |
1494 | of the base architecture to support much larger vectors and to enable | |
1495 | additional vectorisation opportunities. | |
1496 | ||
1497 | To enable use of this extension on CPUs that implement it, say Y. | |
1498 | ||
06a916fe DM |
1499 | On CPUs that support the SVE2 extensions, this option will enable |
1500 | those too. | |
1501 | ||
5043694e DM |
1502 | Note that for architectural reasons, firmware _must_ implement SVE |
1503 | support when running on SVE capable hardware. The required support | |
1504 | is present in: | |
1505 | ||
1506 | * version 1.5 and later of the ARM Trusted Firmware | |
1507 | * the AArch64 boot wrapper since commit 5e1261e08abf | |
1508 | ("bootwrapper: SVE: Enable SVE for EL2 and below"). | |
1509 | ||
1510 | For other firmware implementations, consult the firmware documentation | |
1511 | or vendor. | |
1512 | ||
1513 | If you need the kernel to boot on SVE-capable hardware with broken | |
1514 | firmware, you may need to say N here until you get your firmware | |
1515 | fixed. Otherwise, you may experience firmware panics or lockups when | |
1516 | booting the kernel. If unsure and you are not observing these | |
1517 | symptoms, you should assume that it is safe to say Y. | |
fd045f6c | 1518 | |
85acda3b DM |
1519 | CPUs that support SVE are architecturally required to support the |
1520 | Virtualization Host Extensions (VHE), so the kernel makes no | |
1521 | provision for supporting SVE alongside KVM without VHE enabled. | |
1522 | Thus, you will need to enable CONFIG_ARM64_VHE if you want to support | |
1523 | KVM in the same kernel image. | |
1524 | ||
fd045f6c | 1525 | config ARM64_MODULE_PLTS |
58557e48 | 1526 | bool "Use PLTs to allow module memory to spill over into vmalloc area" |
faaa73bc | 1527 | depends on MODULES |
fd045f6c | 1528 | select HAVE_MOD_ARCH_SPECIFIC |
58557e48 FF |
1529 | help |
1530 | Allocate PLTs when loading modules so that jumps and calls whose | |
1531 | targets are too far away for their relative offsets to be encoded | |
1532 | in the instructions themselves can be bounced via veneers in the | |
1533 | module's PLT. This allows modules to be allocated in the generic | |
1534 | vmalloc area after the dedicated module memory area has been | |
1535 | exhausted. | |
1536 | ||
1537 | When running with address space randomization (KASLR), the module | |
1538 | region itself may be too far away for ordinary relative jumps and | |
1539 | calls, and so in that case, module PLTs are required and cannot be | |
1540 | disabled. | |
1541 | ||
1542 | Specific errata workaround(s) might also force module PLTs to be | |
1543 | enabled (ARM64_ERRATUM_843419). | |
fd045f6c | 1544 | |
bc3c03cc JT |
1545 | config ARM64_PSEUDO_NMI |
1546 | bool "Support for NMI-like interrupts" | |
1547 | select CONFIG_ARM_GIC_V3 | |
1548 | help | |
1549 | Adds support for mimicking Non-Maskable Interrupts through the use of | |
1550 | GIC interrupt priority. This support requires version 3 or later of | |
bc15cf70 | 1551 | ARM GIC. |
bc3c03cc JT |
1552 | |
1553 | This high priority configuration for interrupts needs to be | |
1554 | explicitly enabled by setting the kernel parameter | |
1555 | "irqchip.gicv3_pseudo_nmi" to 1. | |
1556 | ||
1557 | If unsure, say N | |
1558 | ||
48ce8f80 JT |
1559 | if ARM64_PSEUDO_NMI |
1560 | config ARM64_DEBUG_PRIORITY_MASKING | |
1561 | bool "Debug interrupt priority masking" | |
1562 | help | |
1563 | This adds runtime checks to functions enabling/disabling | |
1564 | interrupts when using priority masking. The additional checks verify | |
1565 | the validity of ICC_PMR_EL1 when calling concerned functions. | |
1566 | ||
1567 | If unsure, say N | |
1568 | endif | |
1569 | ||
1e48ef7f AB |
1570 | config RELOCATABLE |
1571 | bool | |
5cf896fb | 1572 | select ARCH_HAS_RELR |
1e48ef7f AB |
1573 | help |
1574 | This builds the kernel as a Position Independent Executable (PIE), | |
1575 | which retains all relocation metadata required to relocate the | |
1576 | kernel binary at runtime to a different virtual address than the | |
1577 | address it was linked at. | |
1578 | Since AArch64 uses the RELA relocation format, this requires a | |
1579 | relocation pass at runtime even if the kernel is loaded at the | |
1580 | same address it was linked at. | |
1581 | ||
f80fb3a3 AB |
1582 | config RANDOMIZE_BASE |
1583 | bool "Randomize the address of the kernel image" | |
b9c220b5 | 1584 | select ARM64_MODULE_PLTS if MODULES |
f80fb3a3 AB |
1585 | select RELOCATABLE |
1586 | help | |
1587 | Randomizes the virtual address at which the kernel image is | |
1588 | loaded, as a security feature that deters exploit attempts | |
1589 | relying on knowledge of the location of kernel internals. | |
1590 | ||
1591 | It is the bootloader's job to provide entropy, by passing a | |
1592 | random u64 value in /chosen/kaslr-seed at kernel entry. | |
1593 | ||
2b5fe07a AB |
1594 | When booting via the UEFI stub, it will invoke the firmware's |
1595 | EFI_RNG_PROTOCOL implementation (if available) to supply entropy | |
1596 | to the kernel proper. In addition, it will randomise the physical | |
1597 | location of the kernel Image as well. | |
1598 | ||
f80fb3a3 AB |
1599 | If unsure, say N. |
1600 | ||
1601 | config RANDOMIZE_MODULE_REGION_FULL | |
f2b9ba87 | 1602 | bool "Randomize the module region over a 4 GB range" |
e71a4e1b | 1603 | depends on RANDOMIZE_BASE |
f80fb3a3 AB |
1604 | default y |
1605 | help | |
f2b9ba87 AB |
1606 | Randomizes the location of the module region inside a 4 GB window |
1607 | covering the core kernel. This way, it is less likely for modules | |
f80fb3a3 AB |
1608 | to leak information about the location of core kernel data structures |
1609 | but it does imply that function calls between modules and the core | |
1610 | kernel will need to be resolved via veneers in the module PLT. | |
1611 | ||
1612 | When this option is not set, the module region will be randomized over | |
1613 | a limited range that contains the [_stext, _etext] interval of the | |
1614 | core kernel, so branch relocations are always in range. | |
1615 | ||
0a1213fa AB |
1616 | config CC_HAVE_STACKPROTECTOR_SYSREG |
1617 | def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) | |
1618 | ||
1619 | config STACKPROTECTOR_PER_TASK | |
1620 | def_bool y | |
1621 | depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG | |
1622 | ||
8c2c3df3 CM |
1623 | endmenu |
1624 | ||
1625 | menu "Boot options" | |
1626 | ||
5e89c55e LP |
1627 | config ARM64_ACPI_PARKING_PROTOCOL |
1628 | bool "Enable support for the ARM64 ACPI parking protocol" | |
1629 | depends on ACPI | |
1630 | help | |
1631 | Enable support for the ARM64 ACPI parking protocol. If disabled | |
1632 | the kernel will not allow booting through the ARM64 ACPI parking | |
1633 | protocol even if the corresponding data is present in the ACPI | |
1634 | MADT table. | |
1635 | ||
8c2c3df3 CM |
1636 | config CMDLINE |
1637 | string "Default kernel command string" | |
1638 | default "" | |
1639 | help | |
1640 | Provide a set of default command-line options at build time by | |
1641 | entering them here. As a minimum, you should specify the the | |
1642 | root device (e.g. root=/dev/nfs). | |
1643 | ||
1644 | config CMDLINE_FORCE | |
1645 | bool "Always use the default kernel command string" | |
f70c08e4 | 1646 | depends on CMDLINE != "" |
8c2c3df3 CM |
1647 | help |
1648 | Always use the default kernel command string, even if the boot | |
1649 | loader passes other arguments to the kernel. | |
1650 | This is useful if you cannot or don't want to change the | |
1651 | command-line options your boot loader passes to the kernel. | |
1652 | ||
f4f75ad5 AB |
1653 | config EFI_STUB |
1654 | bool | |
1655 | ||
f84d0275 MS |
1656 | config EFI |
1657 | bool "UEFI runtime support" | |
1658 | depends on OF && !CPU_BIG_ENDIAN | |
b472db6c | 1659 | depends on KERNEL_MODE_NEON |
2c870e61 | 1660 | select ARCH_SUPPORTS_ACPI |
f84d0275 MS |
1661 | select LIBFDT |
1662 | select UCS2_STRING | |
1663 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 1664 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
1665 | select EFI_STUB |
1666 | select EFI_ARMSTUB | |
f84d0275 MS |
1667 | default y |
1668 | help | |
1669 | This option provides support for runtime services provided | |
1670 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
1671 | clock, and platform reset). A UEFI stub is also provided to |
1672 | allow the kernel to be booted as an EFI application. This | |
1673 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 1674 | |
d1ae8c00 YL |
1675 | config DMI |
1676 | bool "Enable support for SMBIOS (DMI) tables" | |
1677 | depends on EFI | |
1678 | default y | |
1679 | help | |
1680 | This enables SMBIOS/DMI feature for systems. | |
1681 | ||
1682 | This option is only useful on systems that have UEFI firmware. | |
1683 | However, even with this option, the resultant kernel should | |
1684 | continue to boot on existing non-UEFI platforms. | |
1685 | ||
8c2c3df3 CM |
1686 | endmenu |
1687 | ||
8c2c3df3 CM |
1688 | config SYSVIPC_COMPAT |
1689 | def_bool y | |
1690 | depends on COMPAT && SYSVIPC | |
1691 | ||
4a03a058 AK |
1692 | config ARCH_ENABLE_HUGEPAGE_MIGRATION |
1693 | def_bool y | |
1694 | depends on HUGETLB_PAGE && MIGRATION | |
1695 | ||
166936ba LP |
1696 | menu "Power management options" |
1697 | ||
1698 | source "kernel/power/Kconfig" | |
1699 | ||
82869ac5 JM |
1700 | config ARCH_HIBERNATION_POSSIBLE |
1701 | def_bool y | |
1702 | depends on CPU_PM | |
1703 | ||
1704 | config ARCH_HIBERNATION_HEADER | |
1705 | def_bool y | |
1706 | depends on HIBERNATION | |
1707 | ||
166936ba LP |
1708 | config ARCH_SUSPEND_POSSIBLE |
1709 | def_bool y | |
1710 | ||
166936ba LP |
1711 | endmenu |
1712 | ||
1307220d LP |
1713 | menu "CPU Power Management" |
1714 | ||
1715 | source "drivers/cpuidle/Kconfig" | |
1716 | ||
52e7e816 RH |
1717 | source "drivers/cpufreq/Kconfig" |
1718 | ||
1719 | endmenu | |
1720 | ||
f84d0275 MS |
1721 | source "drivers/firmware/Kconfig" |
1722 | ||
b6a02173 GG |
1723 | source "drivers/acpi/Kconfig" |
1724 | ||
c3eb5b14 MZ |
1725 | source "arch/arm64/kvm/Kconfig" |
1726 | ||
2c98833a AB |
1727 | if CRYPTO |
1728 | source "arch/arm64/crypto/Kconfig" | |
1729 | endif |