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Commit | Line | Data |
---|---|---|
8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
b6197b93 | 3 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 4 | select ACPI_GENERIC_GSI if ACPI |
5f1ae4eb | 5 | select ACPI_GTDT if ACPI |
c6bb8f89 | 6 | select ACPI_IORT if ACPI |
6933de0c | 7 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
0cb0786b | 8 | select ACPI_MCFG if ACPI |
888125a7 | 9 | select ACPI_SPCR_TABLE if ACPI |
0ce82232 | 10 | select ACPI_PPTT if ACPI |
1d8f51d4 | 11 | select ARCH_CLOCKSOURCE_DATA |
ec6d06ef | 12 | select ARCH_HAS_DEBUG_VIRTUAL |
21266be9 | 13 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
886643b7 CH |
14 | select ARCH_HAS_DMA_COHERENT_TO_PFN |
15 | select ARCH_HAS_DMA_MMAP_PGPROT | |
38b04a74 | 16 | select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI |
2b68f6ca | 17 | select ARCH_HAS_ELF_RANDOMIZE |
e75bef2a | 18 | select ARCH_HAS_FAST_MULTIPLIER |
6974f0c4 | 19 | select ARCH_HAS_FORTIFY_SOURCE |
957e3fac | 20 | select ARCH_HAS_GCOV_PROFILE_ALL |
e1073d1e | 21 | select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA |
5e4c7549 | 22 | select ARCH_HAS_KCOV |
f1e3a12b | 23 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
3010a5ea | 24 | select ARCH_HAS_PTE_SPECIAL |
d2852a22 | 25 | select ARCH_HAS_SET_MEMORY |
308c09f1 | 26 | select ARCH_HAS_SG_CHAIN |
ad21fc4f LA |
27 | select ARCH_HAS_STRICT_KERNEL_RWX |
28 | select ARCH_HAS_STRICT_MODULE_RWX | |
886643b7 CH |
29 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
30 | select ARCH_HAS_SYNC_DMA_FOR_CPU | |
4378a7d4 | 31 | select ARCH_HAS_SYSCALL_WRAPPER |
1f85008e | 32 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
396a5d4a | 33 | select ARCH_HAVE_NMI_SAFE_CMPXCHG |
087133ac WD |
34 | select ARCH_INLINE_READ_LOCK if !PREEMPT |
35 | select ARCH_INLINE_READ_LOCK_BH if !PREEMPT | |
36 | select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT | |
37 | select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT | |
38 | select ARCH_INLINE_READ_UNLOCK if !PREEMPT | |
39 | select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT | |
40 | select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT | |
41 | select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT | |
42 | select ARCH_INLINE_WRITE_LOCK if !PREEMPT | |
43 | select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT | |
44 | select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT | |
45 | select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT | |
46 | select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT | |
47 | select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT | |
48 | select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT | |
49 | select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT | |
5d168964 WD |
50 | select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT |
51 | select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT | |
52 | select ARCH_INLINE_SPIN_LOCK if !PREEMPT | |
53 | select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT | |
54 | select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT | |
55 | select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT | |
56 | select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT | |
57 | select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT | |
58 | select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT | |
59 | select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT | |
c63c8700 | 60 | select ARCH_USE_CMPXCHG_LOCKREF |
087133ac | 61 | select ARCH_USE_QUEUED_RWLOCKS |
c1109047 | 62 | select ARCH_USE_QUEUED_SPINLOCKS |
c484f256 | 63 | select ARCH_SUPPORTS_MEMORY_FAILURE |
4badad35 | 64 | select ARCH_SUPPORTS_ATOMIC_RMW |
f3a53f7b | 65 | select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG |
56166230 | 66 | select ARCH_SUPPORTS_NUMA_BALANCING |
6212a512 | 67 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 68 | select ARCH_WANT_FRAME_POINTERS |
f0b7f8a4 | 69 | select ARCH_HAS_UBSAN_SANITIZE_ALL |
25c92a37 | 70 | select ARM_AMBA |
1aee5d7a | 71 | select ARM_ARCH_TIMER |
c4188edc | 72 | select ARM_GIC |
875cbf3e | 73 | select AUDIT_ARCH_COMPAT_GENERIC |
3ee80364 | 74 | select ARM_GIC_V2M if PCI |
021f6537 | 75 | select ARM_GIC_V3 |
3ee80364 | 76 | select ARM_GIC_V3_ITS if PCI |
bff60792 | 77 | select ARM_PSCI_FW |
adace895 | 78 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 79 | select CLONE_BACKWARDS |
7ca2ef33 | 80 | select COMMON_CLK |
166936ba | 81 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7481cddf | 82 | select CRC32 |
7bc13fd3 | 83 | select DCACHE_WORD_ACCESS |
0d8488ac | 84 | select DMA_DIRECT_OPS |
ef37566c | 85 | select EDAC_SUPPORT |
2f34f173 | 86 | select FRAME_POINTER |
d4932f9e | 87 | select GENERIC_ALLOCATOR |
2ef7a295 | 88 | select GENERIC_ARCH_TOPOLOGY |
8c2c3df3 | 89 | select GENERIC_CLOCKEVENTS |
4b3dc967 | 90 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 91 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 92 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 93 | select GENERIC_IDLE_POLL_SETUP |
78ae2e1c | 94 | select GENERIC_IRQ_MULTI_HANDLER |
8c2c3df3 CM |
95 | select GENERIC_IRQ_PROBE |
96 | select GENERIC_IRQ_SHOW | |
6544e67b | 97 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 98 | select GENERIC_PCI_IOMAP |
65cd4f6c | 99 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 100 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
101 | select GENERIC_STRNCPY_FROM_USER |
102 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 103 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 104 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 105 | select HARDIRQS_SW_RESEND |
9f9a35a7 | 106 | select HAVE_ACPI_APEI if (ACPI && EFI) |
5284e1b4 | 107 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 108 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 109 | select HAVE_ARCH_BITREVERSE |
324420bf | 110 | select HAVE_ARCH_HUGE_VMAP |
9732cafd | 111 | select HAVE_ARCH_JUMP_LABEL |
c296146c | 112 | select HAVE_ARCH_JUMP_LABEL_RELATIVE |
e17d8025 | 113 | select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) |
9529247d | 114 | select HAVE_ARCH_KGDB |
8f0d3aa9 DC |
115 | select HAVE_ARCH_MMAP_RND_BITS |
116 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT | |
271ca788 | 117 | select HAVE_ARCH_PREL32_RELOCATIONS |
a1ae65b2 | 118 | select HAVE_ARCH_SECCOMP_FILTER |
0b3e3366 | 119 | select HAVE_ARCH_STACKLEAK |
9e8084d3 | 120 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
8c2c3df3 | 121 | select HAVE_ARCH_TRACEHOOK |
8ee70879 | 122 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE |
e3067861 | 123 | select HAVE_ARCH_VMAP_STACK |
8ee70879 | 124 | select HAVE_ARM_SMCCC |
6077776b | 125 | select HAVE_EBPF_JIT |
af64d2aa | 126 | select HAVE_C_RECORDMCOUNT |
5284e1b4 | 127 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 128 | select HAVE_CMPXCHG_LOCAL |
8ee70879 | 129 | select HAVE_CONTEXT_TRACKING |
9b2a60c4 | 130 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 131 | select HAVE_DEBUG_KMEMLEAK |
6ac2104d | 132 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 133 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 134 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 135 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
136 | select HAVE_FUNCTION_TRACER |
137 | select HAVE_FUNCTION_GRAPH_TRACER | |
6b90bd4b | 138 | select HAVE_GCC_PLUGINS |
8c2c3df3 | 139 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 140 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
24da208d | 141 | select HAVE_IRQ_TIME_ACCOUNTING |
1a2db300 | 142 | select HAVE_MEMBLOCK_NODE_MAP if NUMA |
396a5d4a | 143 | select HAVE_NMI |
55834a77 | 144 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 145 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
146 | select HAVE_PERF_REGS |
147 | select HAVE_PERF_USER_STACK_DUMP | |
0a8ea52c | 148 | select HAVE_REGS_AND_STACK_ACCESS_API |
5e5f6dc1 | 149 | select HAVE_RCU_TABLE_FREE |
ace8cb75 | 150 | select HAVE_RCU_TABLE_INVALIDATE |
409d5db4 | 151 | select HAVE_RSEQ |
d148eac0 | 152 | select HAVE_STACKPROTECTOR |
055b1212 | 153 | select HAVE_SYSCALL_TRACEPOINTS |
2dd0e8d2 | 154 | select HAVE_KPROBES |
cd1ee3b1 | 155 | select HAVE_KRETPROBES |
876945db | 156 | select IOMMU_DMA if IOMMU_SUPPORT |
8c2c3df3 | 157 | select IRQ_DOMAIN |
e8557d1f | 158 | select IRQ_FORCED_THREADING |
fea2acaa | 159 | select MODULES_USE_ELF_RELA |
667b24d0 | 160 | select MULTI_IRQ_HANDLER |
f616ab59 | 161 | select NEED_DMA_MAP_STATE |
86596f0a | 162 | select NEED_SG_DMA_LENGTH |
8c2c3df3 CM |
163 | select OF |
164 | select OF_EARLY_FLATTREE | |
9bf14b7c | 165 | select OF_RESERVED_MEM |
0cb0786b | 166 | select PCI_ECAM if ACPI |
aa1e8ec1 CM |
167 | select POWER_RESET |
168 | select POWER_SUPPLY | |
4adcec11 | 169 | select REFCOUNT_FULL |
8c2c3df3 | 170 | select SPARSE_IRQ |
09230cbc | 171 | select SWIOTLB |
7ac57a89 | 172 | select SYSCTL_EXCEPTION_TRACE |
c02433dd | 173 | select THREAD_INFO_IN_TASK |
8c2c3df3 CM |
174 | help |
175 | ARM 64-bit (AArch64) Linux support. | |
176 | ||
177 | config 64BIT | |
178 | def_bool y | |
179 | ||
8c2c3df3 CM |
180 | config MMU |
181 | def_bool y | |
182 | ||
030c4d24 MR |
183 | config ARM64_PAGE_SHIFT |
184 | int | |
185 | default 16 if ARM64_64K_PAGES | |
186 | default 14 if ARM64_16K_PAGES | |
187 | default 12 | |
188 | ||
189 | config ARM64_CONT_SHIFT | |
190 | int | |
191 | default 5 if ARM64_64K_PAGES | |
192 | default 7 if ARM64_16K_PAGES | |
193 | default 4 | |
194 | ||
8f0d3aa9 DC |
195 | config ARCH_MMAP_RND_BITS_MIN |
196 | default 14 if ARM64_64K_PAGES | |
197 | default 16 if ARM64_16K_PAGES | |
198 | default 18 | |
199 | ||
200 | # max bits determined by the following formula: | |
201 | # VA_BITS - PAGE_SHIFT - 3 | |
202 | config ARCH_MMAP_RND_BITS_MAX | |
203 | default 19 if ARM64_VA_BITS=36 | |
204 | default 24 if ARM64_VA_BITS=39 | |
205 | default 27 if ARM64_VA_BITS=42 | |
206 | default 30 if ARM64_VA_BITS=47 | |
207 | default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES | |
208 | default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES | |
209 | default 33 if ARM64_VA_BITS=48 | |
210 | default 14 if ARM64_64K_PAGES | |
211 | default 16 if ARM64_16K_PAGES | |
212 | default 18 | |
213 | ||
214 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
215 | default 7 if ARM64_64K_PAGES | |
216 | default 9 if ARM64_16K_PAGES | |
217 | default 11 | |
218 | ||
219 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
220 | default 16 | |
221 | ||
ce816fa8 | 222 | config NO_IOPORT_MAP |
d1e6dc91 | 223 | def_bool y if !PCI |
8c2c3df3 CM |
224 | |
225 | config STACKTRACE_SUPPORT | |
226 | def_bool y | |
227 | ||
bf0c4e04 JVS |
228 | config ILLEGAL_POINTER_VALUE |
229 | hex | |
230 | default 0xdead000000000000 | |
231 | ||
8c2c3df3 CM |
232 | config LOCKDEP_SUPPORT |
233 | def_bool y | |
234 | ||
235 | config TRACE_IRQFLAGS_SUPPORT | |
236 | def_bool y | |
237 | ||
c209f799 | 238 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
239 | def_bool y |
240 | ||
9fb7410f DM |
241 | config GENERIC_BUG |
242 | def_bool y | |
243 | depends on BUG | |
244 | ||
245 | config GENERIC_BUG_RELATIVE_POINTERS | |
246 | def_bool y | |
247 | depends on GENERIC_BUG | |
248 | ||
8c2c3df3 CM |
249 | config GENERIC_HWEIGHT |
250 | def_bool y | |
251 | ||
252 | config GENERIC_CSUM | |
253 | def_bool y | |
254 | ||
255 | config GENERIC_CALIBRATE_DELAY | |
256 | def_bool y | |
257 | ||
ad67f5a6 | 258 | config ZONE_DMA32 |
8c2c3df3 CM |
259 | def_bool y |
260 | ||
e585513b | 261 | config HAVE_GENERIC_GUP |
29e56940 SC |
262 | def_bool y |
263 | ||
4b3dc967 WD |
264 | config SMP |
265 | def_bool y | |
266 | ||
4cfb3613 AB |
267 | config KERNEL_MODE_NEON |
268 | def_bool y | |
269 | ||
92cc15fc RH |
270 | config FIX_EARLYCON_MEM |
271 | def_bool y | |
272 | ||
9f25e6ad KS |
273 | config PGTABLE_LEVELS |
274 | int | |
21539939 | 275 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad KS |
276 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
277 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
278 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
44eaacf1 SP |
279 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
280 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 281 | |
9842ceae PA |
282 | config ARCH_SUPPORTS_UPROBES |
283 | def_bool y | |
284 | ||
8f360948 AB |
285 | config ARCH_PROC_KCORE_TEXT |
286 | def_bool y | |
287 | ||
6a377491 | 288 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 CM |
289 | |
290 | menu "Bus support" | |
291 | ||
d1e6dc91 LD |
292 | config PCI |
293 | bool "PCI support" | |
294 | help | |
295 | This feature enables support for PCI bus system. If you say Y | |
296 | here, the kernel will include drivers and infrastructure code | |
297 | to support PCI bus devices. | |
298 | ||
299 | config PCI_DOMAINS | |
300 | def_bool PCI | |
301 | ||
302 | config PCI_DOMAINS_GENERIC | |
303 | def_bool PCI | |
304 | ||
305 | config PCI_SYSCALL | |
306 | def_bool PCI | |
307 | ||
308 | source "drivers/pci/Kconfig" | |
d1e6dc91 | 309 | |
8c2c3df3 CM |
310 | endmenu |
311 | ||
312 | menu "Kernel Features" | |
313 | ||
c0a01b84 AP |
314 | menu "ARM errata workarounds via the alternatives framework" |
315 | ||
316 | config ARM64_ERRATUM_826319 | |
317 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
318 | default y | |
319 | help | |
320 | This option adds an alternative code sequence to work around ARM | |
321 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
322 | AXI master interface and an L2 cache. | |
323 | ||
324 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
325 | and is unable to accept a certain write via this interface, it will | |
326 | not progress on read data presented on the read data channel and the | |
327 | system can deadlock. | |
328 | ||
329 | The workaround promotes data cache clean instructions to | |
330 | data cache clean-and-invalidate. | |
331 | Please note that this does not necessarily enable the workaround, | |
332 | as it depends on the alternative framework, which will only patch | |
333 | the kernel if an affected CPU is detected. | |
334 | ||
335 | If unsure, say Y. | |
336 | ||
337 | config ARM64_ERRATUM_827319 | |
338 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
339 | default y | |
340 | help | |
341 | This option adds an alternative code sequence to work around ARM | |
342 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
343 | master interface and an L2 cache. | |
344 | ||
345 | Under certain conditions this erratum can cause a clean line eviction | |
346 | to occur at the same time as another transaction to the same address | |
347 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
348 | interconnect reorders the two transactions. | |
349 | ||
350 | The workaround promotes data cache clean instructions to | |
351 | data cache clean-and-invalidate. | |
352 | Please note that this does not necessarily enable the workaround, | |
353 | as it depends on the alternative framework, which will only patch | |
354 | the kernel if an affected CPU is detected. | |
355 | ||
356 | If unsure, say Y. | |
357 | ||
358 | config ARM64_ERRATUM_824069 | |
359 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
360 | default y | |
361 | help | |
362 | This option adds an alternative code sequence to work around ARM | |
363 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
364 | to a coherent interconnect. | |
365 | ||
366 | If a Cortex-A53 processor is executing a store or prefetch for | |
367 | write instruction at the same time as a processor in another | |
368 | cluster is executing a cache maintenance operation to the same | |
369 | address, then this erratum might cause a clean cache line to be | |
370 | incorrectly marked as dirty. | |
371 | ||
372 | The workaround promotes data cache clean instructions to | |
373 | data cache clean-and-invalidate. | |
374 | Please note that this option does not necessarily enable the | |
375 | workaround, as it depends on the alternative framework, which will | |
376 | only patch the kernel if an affected CPU is detected. | |
377 | ||
378 | If unsure, say Y. | |
379 | ||
380 | config ARM64_ERRATUM_819472 | |
381 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
382 | default y | |
383 | help | |
384 | This option adds an alternative code sequence to work around ARM | |
385 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
386 | present when it is connected to a coherent interconnect. | |
387 | ||
388 | If the processor is executing a load and store exclusive sequence at | |
389 | the same time as a processor in another cluster is executing a cache | |
390 | maintenance operation to the same address, then this erratum might | |
391 | cause data corruption. | |
392 | ||
393 | The workaround promotes data cache clean instructions to | |
394 | data cache clean-and-invalidate. | |
395 | Please note that this does not necessarily enable the workaround, | |
396 | as it depends on the alternative framework, which will only patch | |
397 | the kernel if an affected CPU is detected. | |
398 | ||
399 | If unsure, say Y. | |
400 | ||
401 | config ARM64_ERRATUM_832075 | |
402 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
403 | default y | |
404 | help | |
405 | This option adds an alternative code sequence to work around ARM | |
406 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
407 | ||
408 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
409 | instructions to Write-Back memory are mixed with Device loads. | |
410 | ||
411 | The workaround is to promote device loads to use Load-Acquire | |
412 | semantics. | |
413 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
414 | as it depends on the alternative framework, which will only patch |
415 | the kernel if an affected CPU is detected. | |
416 | ||
417 | If unsure, say Y. | |
418 | ||
419 | config ARM64_ERRATUM_834220 | |
420 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" | |
421 | depends on KVM | |
422 | default y | |
423 | help | |
424 | This option adds an alternative code sequence to work around ARM | |
425 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
426 | ||
427 | Affected Cortex-A57 parts might report a Stage 2 translation | |
428 | fault as the result of a Stage 1 fault for load crossing a | |
429 | page boundary when there is a permission or device memory | |
430 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
431 | ||
432 | The workaround is to verify that the Stage 1 translation | |
433 | doesn't generate a fault before handling the Stage 2 fault. | |
434 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
435 | as it depends on the alternative framework, which will only patch |
436 | the kernel if an affected CPU is detected. | |
437 | ||
438 | If unsure, say Y. | |
439 | ||
905e8c5d WD |
440 | config ARM64_ERRATUM_845719 |
441 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
442 | depends on COMPAT | |
443 | default y | |
444 | help | |
445 | This option adds an alternative code sequence to work around ARM | |
446 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
447 | ||
448 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
449 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
450 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
451 | might return incorrect data. | |
452 | ||
453 | The workaround is to write the contextidr_el1 register on exception | |
454 | return to a 32-bit task. | |
455 | Please note that this does not necessarily enable the workaround, | |
456 | as it depends on the alternative framework, which will only patch | |
457 | the kernel if an affected CPU is detected. | |
458 | ||
459 | If unsure, say Y. | |
460 | ||
df057cc7 WD |
461 | config ARM64_ERRATUM_843419 |
462 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
df057cc7 | 463 | default y |
a257e025 | 464 | select ARM64_MODULE_PLTS if MODULES |
df057cc7 | 465 | help |
6ffe9923 | 466 | This option links the kernel with '--fix-cortex-a53-843419' and |
a257e025 AB |
467 | enables PLT support to replace certain ADRP instructions, which can |
468 | cause subsequent memory accesses to use an incorrect address on | |
469 | Cortex-A53 parts up to r0p4. | |
df057cc7 WD |
470 | |
471 | If unsure, say Y. | |
472 | ||
ece1397c SP |
473 | config ARM64_ERRATUM_1024718 |
474 | bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" | |
475 | default y | |
476 | help | |
477 | This option adds work around for Arm Cortex-A55 Erratum 1024718. | |
478 | ||
479 | Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect | |
480 | update of the hardware dirty bit when the DBM/AP bits are updated | |
481 | without a break-before-make. The work around is to disable the usage | |
482 | of hardware DBM locally on the affected cores. CPUs not affected by | |
483 | erratum will continue to use the feature. | |
df057cc7 WD |
484 | |
485 | If unsure, say Y. | |
486 | ||
95b861a4 MZ |
487 | config ARM64_ERRATUM_1188873 |
488 | bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" | |
489 | default y | |
040f3401 | 490 | select ARM_ARCH_TIMER_OOL_WORKAROUND |
95b861a4 MZ |
491 | help |
492 | This option adds work arounds for ARM Cortex-A76 erratum 1188873 | |
493 | ||
494 | Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause | |
495 | register corruption when accessing the timer registers from | |
496 | AArch32 userspace. | |
497 | ||
498 | If unsure, say Y. | |
499 | ||
94100970 RR |
500 | config CAVIUM_ERRATUM_22375 |
501 | bool "Cavium erratum 22375, 24313" | |
502 | default y | |
503 | help | |
504 | Enable workaround for erratum 22375, 24313. | |
505 | ||
506 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
507 | with small impact affecting only ITS table allocation. | |
508 | ||
509 | erratum 22375: only alloc 8MB table size | |
510 | erratum 24313: ignore memory access type | |
511 | ||
512 | The fixes are in ITS initialization and basically ignore memory access | |
513 | type and table size provided by the TYPER and BASER registers. | |
514 | ||
515 | If unsure, say Y. | |
516 | ||
fbf8f40e GK |
517 | config CAVIUM_ERRATUM_23144 |
518 | bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" | |
519 | depends on NUMA | |
520 | default y | |
521 | help | |
522 | ITS SYNC command hang for cross node io and collections/cpu mapping. | |
523 | ||
524 | If unsure, say Y. | |
525 | ||
6d4e11c5 RR |
526 | config CAVIUM_ERRATUM_23154 |
527 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" | |
528 | default y | |
529 | help | |
530 | The gicv3 of ThunderX requires a modified version for | |
531 | reading the IAR status to ensure data synchronization | |
532 | (access to icc_iar1_el1 is not sync'ed before and after). | |
533 | ||
534 | If unsure, say Y. | |
535 | ||
104a0c02 AP |
536 | config CAVIUM_ERRATUM_27456 |
537 | bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" | |
538 | default y | |
539 | help | |
540 | On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI | |
541 | instructions may cause the icache to become corrupted if it | |
542 | contains data for a non-current ASID. The fix is to | |
543 | invalidate the icache when changing the mm context. | |
544 | ||
545 | If unsure, say Y. | |
546 | ||
690a3415 DD |
547 | config CAVIUM_ERRATUM_30115 |
548 | bool "Cavium erratum 30115: Guest may disable interrupts in host" | |
549 | default y | |
550 | help | |
551 | On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through | |
552 | 1.2, and T83 Pass 1.0, KVM guest execution may disable | |
553 | interrupts in host. Trapping both GICv3 group-0 and group-1 | |
554 | accesses sidesteps the issue. | |
555 | ||
556 | If unsure, say Y. | |
557 | ||
38fd94b0 CC |
558 | config QCOM_FALKOR_ERRATUM_1003 |
559 | bool "Falkor E1003: Incorrect translation due to ASID change" | |
560 | default y | |
38fd94b0 CC |
561 | help |
562 | On Falkor v1, an incorrect ASID may be cached in the TLB when ASID | |
d1777e68 WD |
563 | and BADDR are changed together in TTBRx_EL1. Since we keep the ASID |
564 | in TTBR1_EL1, this situation only occurs in the entry trampoline and | |
565 | then only for entries in the walk cache, since the leaf translation | |
566 | is unchanged. Work around the erratum by invalidating the walk cache | |
567 | entries for the trampoline before entering the kernel proper. | |
38fd94b0 | 568 | |
d9ff80f8 CC |
569 | config QCOM_FALKOR_ERRATUM_1009 |
570 | bool "Falkor E1009: Prematurely complete a DSB after a TLBI" | |
571 | default y | |
572 | help | |
573 | On Falkor v1, the CPU may prematurely complete a DSB following a | |
574 | TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation | |
575 | one more time to fix the issue. | |
576 | ||
577 | If unsure, say Y. | |
578 | ||
90922a2d SD |
579 | config QCOM_QDF2400_ERRATUM_0065 |
580 | bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" | |
581 | default y | |
582 | help | |
583 | On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports | |
584 | ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have | |
585 | been indicated as 16Bytes (0xf), not 8Bytes (0x7). | |
586 | ||
587 | If unsure, say Y. | |
588 | ||
558b0165 AB |
589 | config SOCIONEXT_SYNQUACER_PREITS |
590 | bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" | |
591 | default y | |
592 | help | |
593 | Socionext Synquacer SoCs implement a separate h/w block to generate | |
594 | MSI doorbell writes with non-zero values for the device ID. | |
595 | ||
5c9a882e MZ |
596 | If unsure, say Y. |
597 | ||
598 | config HISILICON_ERRATUM_161600802 | |
599 | bool "Hip07 161600802: Erroneous redistributor VLPI base" | |
600 | default y | |
601 | help | |
602 | The HiSilicon Hip07 SoC usees the wrong redistributor base | |
603 | when issued ITS commands such as VMOVP and VMAPP, and requires | |
604 | a 128kB offset to be applied to the target address in this commands. | |
605 | ||
558b0165 | 606 | If unsure, say Y. |
932b50c7 SD |
607 | |
608 | config QCOM_FALKOR_ERRATUM_E1041 | |
609 | bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" | |
610 | default y | |
611 | help | |
612 | Falkor CPU may speculatively fetch instructions from an improper | |
613 | memory location when MMU translation is changed from SCTLR_ELn[M]=1 | |
614 | to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. | |
615 | ||
616 | If unsure, say Y. | |
617 | ||
c0a01b84 AP |
618 | endmenu |
619 | ||
620 | ||
e41ceed0 JL |
621 | choice |
622 | prompt "Page size" | |
623 | default ARM64_4K_PAGES | |
624 | help | |
625 | Page size (translation granule) configuration. | |
626 | ||
627 | config ARM64_4K_PAGES | |
628 | bool "4KB" | |
629 | help | |
630 | This feature enables 4KB pages support. | |
631 | ||
44eaacf1 SP |
632 | config ARM64_16K_PAGES |
633 | bool "16KB" | |
634 | help | |
635 | The system will use 16KB pages support. AArch32 emulation | |
636 | requires applications compiled with 16K (or a multiple of 16K) | |
637 | aligned segments. | |
638 | ||
8c2c3df3 | 639 | config ARM64_64K_PAGES |
e41ceed0 | 640 | bool "64KB" |
8c2c3df3 CM |
641 | help |
642 | This feature enables 64KB pages support (4KB by default) | |
643 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
644 | look-up. AArch32 emulation requires applications compiled |
645 | with 64K aligned segments. | |
8c2c3df3 | 646 | |
e41ceed0 JL |
647 | endchoice |
648 | ||
649 | choice | |
650 | prompt "Virtual address space size" | |
651 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 652 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
653 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
654 | help | |
655 | Allows choosing one of multiple possible virtual address | |
656 | space sizes. The level of translation table is determined by | |
657 | a combination of page size and virtual address space size. | |
658 | ||
21539939 | 659 | config ARM64_VA_BITS_36 |
56a3f30e | 660 | bool "36-bit" if EXPERT |
21539939 SP |
661 | depends on ARM64_16K_PAGES |
662 | ||
e41ceed0 JL |
663 | config ARM64_VA_BITS_39 |
664 | bool "39-bit" | |
665 | depends on ARM64_4K_PAGES | |
666 | ||
667 | config ARM64_VA_BITS_42 | |
668 | bool "42-bit" | |
669 | depends on ARM64_64K_PAGES | |
670 | ||
44eaacf1 SP |
671 | config ARM64_VA_BITS_47 |
672 | bool "47-bit" | |
673 | depends on ARM64_16K_PAGES | |
674 | ||
c79b954b JL |
675 | config ARM64_VA_BITS_48 |
676 | bool "48-bit" | |
c79b954b | 677 | |
e41ceed0 JL |
678 | endchoice |
679 | ||
680 | config ARM64_VA_BITS | |
681 | int | |
21539939 | 682 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
683 | default 39 if ARM64_VA_BITS_39 |
684 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 685 | default 47 if ARM64_VA_BITS_47 |
c79b954b | 686 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 687 | |
982aa7c5 KM |
688 | choice |
689 | prompt "Physical address space size" | |
690 | default ARM64_PA_BITS_48 | |
691 | help | |
692 | Choose the maximum physical address range that the kernel will | |
693 | support. | |
694 | ||
695 | config ARM64_PA_BITS_48 | |
696 | bool "48-bit" | |
697 | ||
f77d2817 KM |
698 | config ARM64_PA_BITS_52 |
699 | bool "52-bit (ARMv8.2)" | |
700 | depends on ARM64_64K_PAGES | |
701 | depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN | |
702 | help | |
703 | Enable support for a 52-bit physical address space, introduced as | |
704 | part of the ARMv8.2-LPA extension. | |
705 | ||
706 | With this enabled, the kernel will also continue to work on CPUs that | |
707 | do not support ARMv8.2-LPA, but with some added memory overhead (and | |
708 | minor performance overhead). | |
709 | ||
982aa7c5 KM |
710 | endchoice |
711 | ||
712 | config ARM64_PA_BITS | |
713 | int | |
714 | default 48 if ARM64_PA_BITS_48 | |
f77d2817 | 715 | default 52 if ARM64_PA_BITS_52 |
982aa7c5 | 716 | |
a872013d WD |
717 | config CPU_BIG_ENDIAN |
718 | bool "Build big-endian kernel" | |
719 | help | |
720 | Say Y if you plan on running a kernel in big-endian mode. | |
721 | ||
f6e763b9 MB |
722 | config SCHED_MC |
723 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
724 | help |
725 | Multi-core scheduler support improves the CPU scheduler's decision | |
726 | making when dealing with multi-core CPU chips at a cost of slightly | |
727 | increased overhead in some places. If unsure say N here. | |
728 | ||
729 | config SCHED_SMT | |
730 | bool "SMT scheduler support" | |
f6e763b9 MB |
731 | help |
732 | Improves the CPU scheduler's decision making when dealing with | |
733 | MultiThreading at a cost of slightly increased overhead in some | |
734 | places. If unsure say N here. | |
735 | ||
8c2c3df3 | 736 | config NR_CPUS |
62aa9655 GK |
737 | int "Maximum number of CPUs (2-4096)" |
738 | range 2 4096 | |
15942853 | 739 | # These have to remain sorted largest to smallest |
e3672649 | 740 | default "64" |
8c2c3df3 | 741 | |
9327e2c6 MR |
742 | config HOTPLUG_CPU |
743 | bool "Support for hot-pluggable CPUs" | |
217d453d | 744 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
745 | help |
746 | Say Y here to experiment with turning CPUs off and on. CPUs | |
747 | can be controlled through /sys/devices/system/cpu. | |
748 | ||
1a2db300 GK |
749 | # Common NUMA Features |
750 | config NUMA | |
751 | bool "Numa Memory Allocation and Scheduler Support" | |
0c2a6cce KW |
752 | select ACPI_NUMA if ACPI |
753 | select OF_NUMA | |
1a2db300 GK |
754 | help |
755 | Enable NUMA (Non Uniform Memory Access) support. | |
756 | ||
757 | The kernel will try to allocate memory used by a CPU on the | |
758 | local memory of the CPU and add some more | |
759 | NUMA awareness to the kernel. | |
760 | ||
761 | config NODES_SHIFT | |
762 | int "Maximum NUMA Nodes (as a power of 2)" | |
763 | range 1 10 | |
764 | default "2" | |
765 | depends on NEED_MULTIPLE_NODES | |
766 | help | |
767 | Specify the maximum number of NUMA Nodes available on the target | |
768 | system. Increases memory reserved to accommodate various tables. | |
769 | ||
770 | config USE_PERCPU_NUMA_NODE_ID | |
771 | def_bool y | |
772 | depends on NUMA | |
773 | ||
7af3a0a9 ZL |
774 | config HAVE_SETUP_PER_CPU_AREA |
775 | def_bool y | |
776 | depends on NUMA | |
777 | ||
778 | config NEED_PER_CPU_EMBED_FIRST_CHUNK | |
779 | def_bool y | |
780 | depends on NUMA | |
781 | ||
6d526ee2 AB |
782 | config HOLES_IN_ZONE |
783 | def_bool y | |
6d526ee2 | 784 | |
f90df5e2 | 785 | source kernel/Kconfig.hz |
8c2c3df3 | 786 | |
83863f25 LA |
787 | config ARCH_SUPPORTS_DEBUG_PAGEALLOC |
788 | def_bool y | |
789 | ||
8c2c3df3 CM |
790 | config ARCH_SPARSEMEM_ENABLE |
791 | def_bool y | |
792 | select SPARSEMEM_VMEMMAP_ENABLE | |
793 | ||
794 | config ARCH_SPARSEMEM_DEFAULT | |
795 | def_bool ARCH_SPARSEMEM_ENABLE | |
796 | ||
797 | config ARCH_SELECT_MEMORY_MODEL | |
798 | def_bool ARCH_SPARSEMEM_ENABLE | |
799 | ||
e7d4bac4 | 800 | config ARCH_FLATMEM_ENABLE |
54501ac1 | 801 | def_bool !NUMA |
e7d4bac4 | 802 | |
8c2c3df3 | 803 | config HAVE_ARCH_PFN_VALID |
8a695a58 | 804 | def_bool y |
8c2c3df3 CM |
805 | |
806 | config HW_PERF_EVENTS | |
6475b2d8 MR |
807 | def_bool y |
808 | depends on ARM_PMU | |
8c2c3df3 | 809 | |
084bd298 SC |
810 | config SYS_SUPPORTS_HUGETLBFS |
811 | def_bool y | |
812 | ||
084bd298 | 813 | config ARCH_WANT_HUGE_PMD_SHARE |
21539939 | 814 | def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
084bd298 | 815 | |
a41dc0e8 CM |
816 | config ARCH_HAS_CACHE_LINE_SIZE |
817 | def_bool y | |
818 | ||
a1ae65b2 AT |
819 | config SECCOMP |
820 | bool "Enable seccomp to safely compute untrusted bytecode" | |
821 | ---help--- | |
822 | This kernel feature is useful for number crunching applications | |
823 | that may need to compute untrusted bytecode during their | |
824 | execution. By using pipes or other transports made available to | |
825 | the process as file descriptors supporting the read/write | |
826 | syscalls, it's possible to isolate those applications in | |
827 | their own address space using seccomp. Once seccomp is | |
828 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
829 | and the task is only allowed to execute a few safe syscalls | |
830 | defined by each seccomp mode. | |
831 | ||
dfd57bc3 SS |
832 | config PARAVIRT |
833 | bool "Enable paravirtualization code" | |
834 | help | |
835 | This changes the kernel so it can modify itself when it is run | |
836 | under a hypervisor, potentially improving performance significantly | |
837 | over full virtualization. | |
838 | ||
839 | config PARAVIRT_TIME_ACCOUNTING | |
840 | bool "Paravirtual steal time accounting" | |
841 | select PARAVIRT | |
842 | default n | |
843 | help | |
844 | Select this option to enable fine granularity task steal time | |
845 | accounting. Time spent executing other tasks in parallel with | |
846 | the current vCPU is discounted from the vCPU power. To account for | |
847 | that, there can be a small performance impact. | |
848 | ||
849 | If in doubt, say N here. | |
850 | ||
d28f6df1 GL |
851 | config KEXEC |
852 | depends on PM_SLEEP_SMP | |
853 | select KEXEC_CORE | |
854 | bool "kexec system call" | |
855 | ---help--- | |
856 | kexec is a system call that implements the ability to shutdown your | |
857 | current kernel, and to start another kernel. It is like a reboot | |
858 | but it is independent of the system firmware. And like a reboot | |
859 | you can start any kernel with it, not just Linux. | |
860 | ||
3ddd9992 AT |
861 | config KEXEC_FILE |
862 | bool "kexec file based system call" | |
863 | select KEXEC_CORE | |
864 | help | |
865 | This is new version of kexec system call. This system call is | |
866 | file based and takes file descriptors as system call argument | |
867 | for kernel and initramfs as opposed to list of segments as | |
868 | accepted by previous system call. | |
869 | ||
e62aaeac AT |
870 | config CRASH_DUMP |
871 | bool "Build kdump crash kernel" | |
872 | help | |
873 | Generate crash dump after being started by kexec. This should | |
874 | be normally only set in special crash dump kernels which are | |
875 | loaded in the main kernel with kexec-tools into a specially | |
876 | reserved region and then later executed after a crash by | |
877 | kdump/kexec. | |
878 | ||
879 | For more details see Documentation/kdump/kdump.txt | |
880 | ||
aa42aa13 SS |
881 | config XEN_DOM0 |
882 | def_bool y | |
883 | depends on XEN | |
884 | ||
885 | config XEN | |
c2ba1f7d | 886 | bool "Xen guest support on ARM64" |
aa42aa13 | 887 | depends on ARM64 && OF |
83862ccf | 888 | select SWIOTLB_XEN |
dfd57bc3 | 889 | select PARAVIRT |
aa42aa13 SS |
890 | help |
891 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
892 | ||
d03bb145 SC |
893 | config FORCE_MAX_ZONEORDER |
894 | int | |
895 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
44eaacf1 | 896 | default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) |
d03bb145 | 897 | default "11" |
44eaacf1 SP |
898 | help |
899 | The kernel memory allocator divides physically contiguous memory | |
900 | blocks into "zones", where each zone is a power of two number of | |
901 | pages. This option selects the largest power of two that the kernel | |
902 | keeps in the memory allocator. If you need to allocate very large | |
903 | blocks of physically contiguous memory, then you may need to | |
904 | increase this value. | |
905 | ||
906 | This config option is actually maximum order plus one. For example, | |
907 | a value of 11 means that the largest free memory block is 2^10 pages. | |
908 | ||
909 | We make sure that we can allocate upto a HugePage size for each configuration. | |
910 | Hence we have : | |
911 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 | |
912 | ||
913 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us | |
914 | 4M allocations matching the default size used by generic code. | |
d03bb145 | 915 | |
084eb77c | 916 | config UNMAP_KERNEL_AT_EL0 |
0617052d | 917 | bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT |
084eb77c WD |
918 | default y |
919 | help | |
0617052d WD |
920 | Speculation attacks against some high-performance processors can |
921 | be used to bypass MMU permission checks and leak kernel data to | |
922 | userspace. This can be defended against by unmapping the kernel | |
923 | when running in userspace, mapping it back in on exception entry | |
924 | via a trampoline page in the vector table. | |
084eb77c WD |
925 | |
926 | If unsure, say Y. | |
927 | ||
0f15adbb WD |
928 | config HARDEN_BRANCH_PREDICTOR |
929 | bool "Harden the branch predictor against aliasing attacks" if EXPERT | |
930 | default y | |
931 | help | |
932 | Speculation attacks against some high-performance processors rely on | |
933 | being able to manipulate the branch predictor for a victim context by | |
934 | executing aliasing branches in the attacker context. Such attacks | |
935 | can be partially mitigated against by clearing internal branch | |
936 | predictor state and limiting the prediction logic in some situations. | |
937 | ||
938 | This config option will take CPU-specific actions to harden the | |
939 | branch predictor against aliasing attacks and may rely on specific | |
940 | instruction sequences or control bits being set by the system | |
941 | firmware. | |
942 | ||
943 | If unsure, say Y. | |
944 | ||
dee39247 MZ |
945 | config HARDEN_EL2_VECTORS |
946 | bool "Harden EL2 vector mapping against system register leak" if EXPERT | |
947 | default y | |
948 | help | |
949 | Speculation attacks against some high-performance processors can | |
950 | be used to leak privileged information such as the vector base | |
951 | register, resulting in a potential defeat of the EL2 layout | |
952 | randomization. | |
953 | ||
954 | This config option will map the vectors to a fixed location, | |
955 | independent of the EL2 code mapping, so that revealing VBAR_EL2 | |
956 | to an attacker does not give away any extra information. This | |
957 | only gets enabled on affected CPUs. | |
958 | ||
959 | If unsure, say Y. | |
960 | ||
a725e3dd MZ |
961 | config ARM64_SSBD |
962 | bool "Speculative Store Bypass Disable" if EXPERT | |
963 | default y | |
964 | help | |
965 | This enables mitigation of the bypassing of previous stores | |
966 | by speculative loads. | |
967 | ||
968 | If unsure, say Y. | |
969 | ||
1b907f46 WD |
970 | menuconfig ARMV8_DEPRECATED |
971 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
972 | depends on COMPAT | |
6cfa7cc4 | 973 | depends on SYSCTL |
1b907f46 WD |
974 | help |
975 | Legacy software support may require certain instructions | |
976 | that have been deprecated or obsoleted in the architecture. | |
977 | ||
978 | Enable this config to enable selective emulation of these | |
979 | features. | |
980 | ||
981 | If unsure, say Y | |
982 | ||
983 | if ARMV8_DEPRECATED | |
984 | ||
985 | config SWP_EMULATION | |
986 | bool "Emulate SWP/SWPB instructions" | |
987 | help | |
988 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
989 | they are always undefined. Say Y here to enable software | |
990 | emulation of these instructions for userspace using LDXR/STXR. | |
991 | ||
992 | In some older versions of glibc [<=2.8] SWP is used during futex | |
993 | trylock() operations with the assumption that the code will not | |
994 | be preempted. This invalid assumption may be more likely to fail | |
995 | with SWP emulation enabled, leading to deadlock of the user | |
996 | application. | |
997 | ||
998 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
999 | on an external transaction monitoring block called a global | |
1000 | monitor to maintain update atomicity. If your system does not | |
1001 | implement a global monitor, this option can cause programs that | |
1002 | perform SWP operations to uncached memory to deadlock. | |
1003 | ||
1004 | If unsure, say Y | |
1005 | ||
1006 | config CP15_BARRIER_EMULATION | |
1007 | bool "Emulate CP15 Barrier instructions" | |
1008 | help | |
1009 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
1010 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
1011 | strongly recommended to use the ISB, DSB, and DMB | |
1012 | instructions instead. | |
1013 | ||
1014 | Say Y here to enable software emulation of these | |
1015 | instructions for AArch32 userspace code. When this option is | |
1016 | enabled, CP15 barrier usage is traced which can help | |
1017 | identify software that needs updating. | |
1018 | ||
1019 | If unsure, say Y | |
1020 | ||
2d888f48 SP |
1021 | config SETEND_EMULATION |
1022 | bool "Emulate SETEND instruction" | |
1023 | help | |
1024 | The SETEND instruction alters the data-endianness of the | |
1025 | AArch32 EL0, and is deprecated in ARMv8. | |
1026 | ||
1027 | Say Y here to enable software emulation of the instruction | |
1028 | for AArch32 userspace code. | |
1029 | ||
1030 | Note: All the cpus on the system must have mixed endian support at EL0 | |
1031 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
1032 | endian - is hotplugged in after this feature has been enabled, there could | |
1033 | be unexpected results in the applications. | |
1034 | ||
1035 | If unsure, say Y | |
1b907f46 WD |
1036 | endif |
1037 | ||
ba42822a CM |
1038 | config ARM64_SW_TTBR0_PAN |
1039 | bool "Emulate Privileged Access Never using TTBR0_EL1 switching" | |
1040 | help | |
1041 | Enabling this option prevents the kernel from accessing | |
1042 | user-space memory directly by pointing TTBR0_EL1 to a reserved | |
1043 | zeroed area and reserved ASID. The user access routines | |
1044 | restore the valid TTBR0_EL1 temporarily. | |
1045 | ||
0e4a0709 WD |
1046 | menu "ARMv8.1 architectural features" |
1047 | ||
1048 | config ARM64_HW_AFDBM | |
1049 | bool "Support for hardware updates of the Access and Dirty page flags" | |
1050 | default y | |
1051 | help | |
1052 | The ARMv8.1 architecture extensions introduce support for | |
1053 | hardware updates of the access and dirty information in page | |
1054 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
1055 | capable processors, accesses to pages with PTE_AF cleared will | |
1056 | set this bit instead of raising an access flag fault. | |
1057 | Similarly, writes to read-only pages with the DBM bit set will | |
1058 | clear the read-only bit (AP[2]) instead of raising a | |
1059 | permission fault. | |
1060 | ||
1061 | Kernels built with this configuration option enabled continue | |
1062 | to work on pre-ARMv8.1 hardware and the performance impact is | |
1063 | minimal. If unsure, say Y. | |
1064 | ||
1065 | config ARM64_PAN | |
1066 | bool "Enable support for Privileged Access Never (PAN)" | |
1067 | default y | |
1068 | help | |
1069 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
1070 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
1071 | memory directly. | |
1072 | ||
1073 | Choosing this option will cause any unprotected (not using | |
1074 | copy_to_user et al) memory access to fail with a permission fault. | |
1075 | ||
1076 | The feature is detected at runtime, and will remain as a 'nop' | |
1077 | instruction if the cpu does not implement the feature. | |
1078 | ||
1079 | config ARM64_LSE_ATOMICS | |
1080 | bool "Atomic instructions" | |
7bd99b40 | 1081 | default y |
0e4a0709 WD |
1082 | help |
1083 | As part of the Large System Extensions, ARMv8.1 introduces new | |
1084 | atomic instructions that are designed specifically to scale in | |
1085 | very large systems. | |
1086 | ||
1087 | Say Y here to make use of these instructions for the in-kernel | |
1088 | atomic routines. This incurs a small overhead on CPUs that do | |
1089 | not support these instructions and requires the kernel to be | |
7bd99b40 WD |
1090 | built with binutils >= 2.25 in order for the new instructions |
1091 | to be used. | |
0e4a0709 | 1092 | |
1f364c8c MZ |
1093 | config ARM64_VHE |
1094 | bool "Enable support for Virtualization Host Extensions (VHE)" | |
1095 | default y | |
1096 | help | |
1097 | Virtualization Host Extensions (VHE) allow the kernel to run | |
1098 | directly at EL2 (instead of EL1) on processors that support | |
1099 | it. This leads to better performance for KVM, as they reduce | |
1100 | the cost of the world switch. | |
1101 | ||
1102 | Selecting this option allows the VHE feature to be detected | |
1103 | at runtime, and does not affect processors that do not | |
1104 | implement this feature. | |
1105 | ||
0e4a0709 WD |
1106 | endmenu |
1107 | ||
f993318b WD |
1108 | menu "ARMv8.2 architectural features" |
1109 | ||
57f4959b JM |
1110 | config ARM64_UAO |
1111 | bool "Enable support for User Access Override (UAO)" | |
1112 | default y | |
1113 | help | |
1114 | User Access Override (UAO; part of the ARMv8.2 Extensions) | |
1115 | causes the 'unprivileged' variant of the load/store instructions to | |
83fc61a5 | 1116 | be overridden to be privileged. |
57f4959b JM |
1117 | |
1118 | This option changes get_user() and friends to use the 'unprivileged' | |
1119 | variant of the load/store instructions. This ensures that user-space | |
1120 | really did have access to the supplied memory. When addr_limit is | |
1121 | set to kernel memory the UAO bit will be set, allowing privileged | |
1122 | access to kernel memory. | |
1123 | ||
1124 | Choosing this option will cause copy_to_user() et al to use user-space | |
1125 | memory permissions. | |
1126 | ||
1127 | The feature is detected at runtime, the kernel will use the | |
1128 | regular load/store instructions if the cpu does not implement the | |
1129 | feature. | |
1130 | ||
d50e071f RM |
1131 | config ARM64_PMEM |
1132 | bool "Enable support for persistent memory" | |
1133 | select ARCH_HAS_PMEM_API | |
5d7bdeb1 | 1134 | select ARCH_HAS_UACCESS_FLUSHCACHE |
d50e071f RM |
1135 | help |
1136 | Say Y to enable support for the persistent memory API based on the | |
1137 | ARMv8.2 DCPoP feature. | |
1138 | ||
1139 | The feature is detected at runtime, and the kernel will use DC CVAC | |
1140 | operations if DC CVAP is not supported (following the behaviour of | |
1141 | DC CVAP itself if the system does not define a point of persistence). | |
1142 | ||
64c02720 XX |
1143 | config ARM64_RAS_EXTN |
1144 | bool "Enable support for RAS CPU Extensions" | |
1145 | default y | |
1146 | help | |
1147 | CPUs that support the Reliability, Availability and Serviceability | |
1148 | (RAS) Extensions, part of ARMv8.2 are able to track faults and | |
1149 | errors, classify them and report them to software. | |
1150 | ||
1151 | On CPUs with these extensions system software can use additional | |
1152 | barriers to determine if faults are pending and read the | |
1153 | classification from a new set of registers. | |
1154 | ||
1155 | Selecting this feature will allow the kernel to use these barriers | |
1156 | and access the new registers if the system supports the extension. | |
1157 | Platform RAS features may additionally depend on firmware support. | |
1158 | ||
5ffdfaed VM |
1159 | config ARM64_CNP |
1160 | bool "Enable support for Common Not Private (CNP) translations" | |
1161 | default y | |
1162 | depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN | |
1163 | help | |
1164 | Common Not Private (CNP) allows translation table entries to | |
1165 | be shared between different PEs in the same inner shareable | |
1166 | domain, so the hardware can use this fact to optimise the | |
1167 | caching of such entries in the TLB. | |
1168 | ||
1169 | Selecting this option allows the CNP feature to be detected | |
1170 | at runtime, and does not affect PEs that do not implement | |
1171 | this feature. | |
1172 | ||
f993318b WD |
1173 | endmenu |
1174 | ||
ddd25ad1 DM |
1175 | config ARM64_SVE |
1176 | bool "ARM Scalable Vector Extension support" | |
1177 | default y | |
85acda3b | 1178 | depends on !KVM || ARM64_VHE |
ddd25ad1 DM |
1179 | help |
1180 | The Scalable Vector Extension (SVE) is an extension to the AArch64 | |
1181 | execution state which complements and extends the SIMD functionality | |
1182 | of the base architecture to support much larger vectors and to enable | |
1183 | additional vectorisation opportunities. | |
1184 | ||
1185 | To enable use of this extension on CPUs that implement it, say Y. | |
1186 | ||
5043694e DM |
1187 | Note that for architectural reasons, firmware _must_ implement SVE |
1188 | support when running on SVE capable hardware. The required support | |
1189 | is present in: | |
1190 | ||
1191 | * version 1.5 and later of the ARM Trusted Firmware | |
1192 | * the AArch64 boot wrapper since commit 5e1261e08abf | |
1193 | ("bootwrapper: SVE: Enable SVE for EL2 and below"). | |
1194 | ||
1195 | For other firmware implementations, consult the firmware documentation | |
1196 | or vendor. | |
1197 | ||
1198 | If you need the kernel to boot on SVE-capable hardware with broken | |
1199 | firmware, you may need to say N here until you get your firmware | |
1200 | fixed. Otherwise, you may experience firmware panics or lockups when | |
1201 | booting the kernel. If unsure and you are not observing these | |
1202 | symptoms, you should assume that it is safe to say Y. | |
fd045f6c | 1203 | |
85acda3b DM |
1204 | CPUs that support SVE are architecturally required to support the |
1205 | Virtualization Host Extensions (VHE), so the kernel makes no | |
1206 | provision for supporting SVE alongside KVM without VHE enabled. | |
1207 | Thus, you will need to enable CONFIG_ARM64_VHE if you want to support | |
1208 | KVM in the same kernel image. | |
1209 | ||
fd045f6c AB |
1210 | config ARM64_MODULE_PLTS |
1211 | bool | |
fd045f6c AB |
1212 | select HAVE_MOD_ARCH_SPECIFIC |
1213 | ||
1e48ef7f AB |
1214 | config RELOCATABLE |
1215 | bool | |
1216 | help | |
1217 | This builds the kernel as a Position Independent Executable (PIE), | |
1218 | which retains all relocation metadata required to relocate the | |
1219 | kernel binary at runtime to a different virtual address than the | |
1220 | address it was linked at. | |
1221 | Since AArch64 uses the RELA relocation format, this requires a | |
1222 | relocation pass at runtime even if the kernel is loaded at the | |
1223 | same address it was linked at. | |
1224 | ||
f80fb3a3 AB |
1225 | config RANDOMIZE_BASE |
1226 | bool "Randomize the address of the kernel image" | |
b9c220b5 | 1227 | select ARM64_MODULE_PLTS if MODULES |
f80fb3a3 AB |
1228 | select RELOCATABLE |
1229 | help | |
1230 | Randomizes the virtual address at which the kernel image is | |
1231 | loaded, as a security feature that deters exploit attempts | |
1232 | relying on knowledge of the location of kernel internals. | |
1233 | ||
1234 | It is the bootloader's job to provide entropy, by passing a | |
1235 | random u64 value in /chosen/kaslr-seed at kernel entry. | |
1236 | ||
2b5fe07a AB |
1237 | When booting via the UEFI stub, it will invoke the firmware's |
1238 | EFI_RNG_PROTOCOL implementation (if available) to supply entropy | |
1239 | to the kernel proper. In addition, it will randomise the physical | |
1240 | location of the kernel Image as well. | |
1241 | ||
f80fb3a3 AB |
1242 | If unsure, say N. |
1243 | ||
1244 | config RANDOMIZE_MODULE_REGION_FULL | |
f2b9ba87 | 1245 | bool "Randomize the module region over a 4 GB range" |
e71a4e1b | 1246 | depends on RANDOMIZE_BASE |
f80fb3a3 AB |
1247 | default y |
1248 | help | |
f2b9ba87 AB |
1249 | Randomizes the location of the module region inside a 4 GB window |
1250 | covering the core kernel. This way, it is less likely for modules | |
f80fb3a3 AB |
1251 | to leak information about the location of core kernel data structures |
1252 | but it does imply that function calls between modules and the core | |
1253 | kernel will need to be resolved via veneers in the module PLT. | |
1254 | ||
1255 | When this option is not set, the module region will be randomized over | |
1256 | a limited range that contains the [_stext, _etext] interval of the | |
1257 | core kernel, so branch relocations are always in range. | |
1258 | ||
8c2c3df3 CM |
1259 | endmenu |
1260 | ||
1261 | menu "Boot options" | |
1262 | ||
5e89c55e LP |
1263 | config ARM64_ACPI_PARKING_PROTOCOL |
1264 | bool "Enable support for the ARM64 ACPI parking protocol" | |
1265 | depends on ACPI | |
1266 | help | |
1267 | Enable support for the ARM64 ACPI parking protocol. If disabled | |
1268 | the kernel will not allow booting through the ARM64 ACPI parking | |
1269 | protocol even if the corresponding data is present in the ACPI | |
1270 | MADT table. | |
1271 | ||
8c2c3df3 CM |
1272 | config CMDLINE |
1273 | string "Default kernel command string" | |
1274 | default "" | |
1275 | help | |
1276 | Provide a set of default command-line options at build time by | |
1277 | entering them here. As a minimum, you should specify the the | |
1278 | root device (e.g. root=/dev/nfs). | |
1279 | ||
1280 | config CMDLINE_FORCE | |
1281 | bool "Always use the default kernel command string" | |
1282 | help | |
1283 | Always use the default kernel command string, even if the boot | |
1284 | loader passes other arguments to the kernel. | |
1285 | This is useful if you cannot or don't want to change the | |
1286 | command-line options your boot loader passes to the kernel. | |
1287 | ||
f4f75ad5 AB |
1288 | config EFI_STUB |
1289 | bool | |
1290 | ||
f84d0275 MS |
1291 | config EFI |
1292 | bool "UEFI runtime support" | |
1293 | depends on OF && !CPU_BIG_ENDIAN | |
b472db6c | 1294 | depends on KERNEL_MODE_NEON |
2c870e61 | 1295 | select ARCH_SUPPORTS_ACPI |
f84d0275 MS |
1296 | select LIBFDT |
1297 | select UCS2_STRING | |
1298 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 1299 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
1300 | select EFI_STUB |
1301 | select EFI_ARMSTUB | |
f84d0275 MS |
1302 | default y |
1303 | help | |
1304 | This option provides support for runtime services provided | |
1305 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
1306 | clock, and platform reset). A UEFI stub is also provided to |
1307 | allow the kernel to be booted as an EFI application. This | |
1308 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 1309 | |
d1ae8c00 YL |
1310 | config DMI |
1311 | bool "Enable support for SMBIOS (DMI) tables" | |
1312 | depends on EFI | |
1313 | default y | |
1314 | help | |
1315 | This enables SMBIOS/DMI feature for systems. | |
1316 | ||
1317 | This option is only useful on systems that have UEFI firmware. | |
1318 | However, even with this option, the resultant kernel should | |
1319 | continue to boot on existing non-UEFI platforms. | |
1320 | ||
8c2c3df3 CM |
1321 | endmenu |
1322 | ||
8c2c3df3 CM |
1323 | config COMPAT |
1324 | bool "Kernel support for 32-bit EL0" | |
755e70b7 | 1325 | depends on ARM64_4K_PAGES || EXPERT |
2e449048 | 1326 | select COMPAT_BINFMT_ELF if BINFMT_ELF |
af1839eb | 1327 | select HAVE_UID16 |
84b9e9b4 | 1328 | select OLD_SIGSUSPEND3 |
51682036 | 1329 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
1330 | help |
1331 | This option enables support for a 32-bit EL0 running under a 64-bit | |
1332 | kernel at EL1. AArch32-specific components such as system calls, | |
1333 | the user helper functions, VFP support and the ptrace interface are | |
1334 | handled appropriately by the kernel. | |
1335 | ||
44eaacf1 SP |
1336 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware |
1337 | that you will only be able to execute AArch32 binaries that were compiled | |
1338 | with page size aligned segments. | |
a8fcd8b1 | 1339 | |
8c2c3df3 CM |
1340 | If you want to execute 32-bit userspace applications, say Y. |
1341 | ||
1342 | config SYSVIPC_COMPAT | |
1343 | def_bool y | |
1344 | depends on COMPAT && SYSVIPC | |
1345 | ||
166936ba LP |
1346 | menu "Power management options" |
1347 | ||
1348 | source "kernel/power/Kconfig" | |
1349 | ||
82869ac5 JM |
1350 | config ARCH_HIBERNATION_POSSIBLE |
1351 | def_bool y | |
1352 | depends on CPU_PM | |
1353 | ||
1354 | config ARCH_HIBERNATION_HEADER | |
1355 | def_bool y | |
1356 | depends on HIBERNATION | |
1357 | ||
166936ba LP |
1358 | config ARCH_SUSPEND_POSSIBLE |
1359 | def_bool y | |
1360 | ||
166936ba LP |
1361 | endmenu |
1362 | ||
1307220d LP |
1363 | menu "CPU Power Management" |
1364 | ||
1365 | source "drivers/cpuidle/Kconfig" | |
1366 | ||
52e7e816 RH |
1367 | source "drivers/cpufreq/Kconfig" |
1368 | ||
1369 | endmenu | |
1370 | ||
f84d0275 MS |
1371 | source "drivers/firmware/Kconfig" |
1372 | ||
b6a02173 GG |
1373 | source "drivers/acpi/Kconfig" |
1374 | ||
c3eb5b14 MZ |
1375 | source "arch/arm64/kvm/Kconfig" |
1376 | ||
2c98833a AB |
1377 | if CRYPTO |
1378 | source "arch/arm64/crypto/Kconfig" | |
1379 | endif |