]>
Commit | Line | Data |
---|---|---|
8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
b6197b93 | 3 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 4 | select ACPI_GENERIC_GSI if ACPI |
5f1ae4eb | 5 | select ACPI_GTDT if ACPI |
c6bb8f89 | 6 | select ACPI_IORT if ACPI |
6933de0c | 7 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
0cb0786b | 8 | select ACPI_MCFG if ACPI |
888125a7 | 9 | select ACPI_SPCR_TABLE if ACPI |
1d8f51d4 | 10 | select ARCH_CLOCKSOURCE_DATA |
ec6d06ef | 11 | select ARCH_HAS_DEBUG_VIRTUAL |
21266be9 | 12 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
38b04a74 | 13 | select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI |
2b68f6ca | 14 | select ARCH_HAS_ELF_RANDOMIZE |
957e3fac | 15 | select ARCH_HAS_GCOV_PROFILE_ALL |
14f09910 | 16 | select ARCH_HAS_GIGANTIC_PAGE |
5e4c7549 | 17 | select ARCH_HAS_KCOV |
d2852a22 | 18 | select ARCH_HAS_SET_MEMORY |
308c09f1 | 19 | select ARCH_HAS_SG_CHAIN |
ad21fc4f LA |
20 | select ARCH_HAS_STRICT_KERNEL_RWX |
21 | select ARCH_HAS_STRICT_MODULE_RWX | |
1f85008e | 22 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
7edda088 | 23 | select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA |
c63c8700 | 24 | select ARCH_USE_CMPXCHG_LOCKREF |
c484f256 | 25 | select ARCH_SUPPORTS_MEMORY_FAILURE |
4badad35 | 26 | select ARCH_SUPPORTS_ATOMIC_RMW |
56166230 | 27 | select ARCH_SUPPORTS_NUMA_BALANCING |
6212a512 | 28 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 29 | select ARCH_WANT_FRAME_POINTERS |
f0b7f8a4 | 30 | select ARCH_HAS_UBSAN_SANITIZE_ALL |
25c92a37 | 31 | select ARM_AMBA |
1aee5d7a | 32 | select ARM_ARCH_TIMER |
c4188edc | 33 | select ARM_GIC |
875cbf3e | 34 | select AUDIT_ARCH_COMPAT_GENERIC |
3ee80364 | 35 | select ARM_GIC_V2M if PCI |
021f6537 | 36 | select ARM_GIC_V3 |
3ee80364 | 37 | select ARM_GIC_V3_ITS if PCI |
bff60792 | 38 | select ARM_PSCI_FW |
adace895 | 39 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 40 | select CLONE_BACKWARDS |
7ca2ef33 | 41 | select COMMON_CLK |
166936ba | 42 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 43 | select DCACHE_WORD_ACCESS |
ef37566c | 44 | select EDAC_SUPPORT |
2f34f173 | 45 | select FRAME_POINTER |
d4932f9e | 46 | select GENERIC_ALLOCATOR |
2ef7a295 | 47 | select GENERIC_ARCH_TOPOLOGY |
8c2c3df3 | 48 | select GENERIC_CLOCKEVENTS |
4b3dc967 | 49 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 50 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 51 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 52 | select GENERIC_IDLE_POLL_SETUP |
8c2c3df3 CM |
53 | select GENERIC_IRQ_PROBE |
54 | select GENERIC_IRQ_SHOW | |
6544e67b | 55 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 56 | select GENERIC_PCI_IOMAP |
65cd4f6c | 57 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 58 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
59 | select GENERIC_STRNCPY_FROM_USER |
60 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 61 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 62 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 63 | select HARDIRQS_SW_RESEND |
9f9a35a7 | 64 | select HAVE_ACPI_APEI if (ACPI && EFI) |
5284e1b4 | 65 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 66 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 67 | select HAVE_ARCH_BITREVERSE |
324420bf | 68 | select HAVE_ARCH_HUGE_VMAP |
9732cafd | 69 | select HAVE_ARCH_JUMP_LABEL |
f1b9032f | 70 | select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) |
9529247d | 71 | select HAVE_ARCH_KGDB |
8f0d3aa9 DC |
72 | select HAVE_ARCH_MMAP_RND_BITS |
73 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT | |
a1ae65b2 | 74 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 75 | select HAVE_ARCH_TRACEHOOK |
8ee70879 YS |
76 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE |
77 | select HAVE_ARM_SMCCC | |
6077776b | 78 | select HAVE_EBPF_JIT |
af64d2aa | 79 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 80 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 81 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 82 | select HAVE_CMPXCHG_LOCAL |
8ee70879 | 83 | select HAVE_CONTEXT_TRACKING |
9b2a60c4 | 84 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 85 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 | 86 | select HAVE_DMA_API_DEBUG |
6ac2104d | 87 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 88 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 89 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 90 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
91 | select HAVE_FUNCTION_TRACER |
92 | select HAVE_FUNCTION_GRAPH_TRACER | |
6b90bd4b | 93 | select HAVE_GCC_PLUGINS |
8c2c3df3 | 94 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 95 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
24da208d | 96 | select HAVE_IRQ_TIME_ACCOUNTING |
8c2c3df3 | 97 | select HAVE_MEMBLOCK |
1a2db300 | 98 | select HAVE_MEMBLOCK_NODE_MAP if NUMA |
7edda088 | 99 | select HAVE_NMI if ACPI_APEI_SEA |
55834a77 | 100 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 101 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
102 | select HAVE_PERF_REGS |
103 | select HAVE_PERF_USER_STACK_DUMP | |
0a8ea52c | 104 | select HAVE_REGS_AND_STACK_ACCESS_API |
5e5f6dc1 | 105 | select HAVE_RCU_TABLE_FREE |
055b1212 | 106 | select HAVE_SYSCALL_TRACEPOINTS |
2dd0e8d2 | 107 | select HAVE_KPROBES |
cd1ee3b1 | 108 | select HAVE_KRETPROBES |
876945db | 109 | select IOMMU_DMA if IOMMU_SUPPORT |
8c2c3df3 | 110 | select IRQ_DOMAIN |
e8557d1f | 111 | select IRQ_FORCED_THREADING |
fea2acaa | 112 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
113 | select NO_BOOTMEM |
114 | select OF | |
115 | select OF_EARLY_FLATTREE | |
9bf14b7c | 116 | select OF_RESERVED_MEM |
0cb0786b | 117 | select PCI_ECAM if ACPI |
aa1e8ec1 CM |
118 | select POWER_RESET |
119 | select POWER_SUPPLY | |
8c2c3df3 | 120 | select SPARSE_IRQ |
7ac57a89 | 121 | select SYSCTL_EXCEPTION_TRACE |
c02433dd | 122 | select THREAD_INFO_IN_TASK |
8c2c3df3 CM |
123 | help |
124 | ARM 64-bit (AArch64) Linux support. | |
125 | ||
126 | config 64BIT | |
127 | def_bool y | |
128 | ||
129 | config ARCH_PHYS_ADDR_T_64BIT | |
130 | def_bool y | |
131 | ||
132 | config MMU | |
133 | def_bool y | |
134 | ||
030c4d24 MR |
135 | config ARM64_PAGE_SHIFT |
136 | int | |
137 | default 16 if ARM64_64K_PAGES | |
138 | default 14 if ARM64_16K_PAGES | |
139 | default 12 | |
140 | ||
141 | config ARM64_CONT_SHIFT | |
142 | int | |
143 | default 5 if ARM64_64K_PAGES | |
144 | default 7 if ARM64_16K_PAGES | |
145 | default 4 | |
146 | ||
8f0d3aa9 DC |
147 | config ARCH_MMAP_RND_BITS_MIN |
148 | default 14 if ARM64_64K_PAGES | |
149 | default 16 if ARM64_16K_PAGES | |
150 | default 18 | |
151 | ||
152 | # max bits determined by the following formula: | |
153 | # VA_BITS - PAGE_SHIFT - 3 | |
154 | config ARCH_MMAP_RND_BITS_MAX | |
155 | default 19 if ARM64_VA_BITS=36 | |
156 | default 24 if ARM64_VA_BITS=39 | |
157 | default 27 if ARM64_VA_BITS=42 | |
158 | default 30 if ARM64_VA_BITS=47 | |
159 | default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES | |
160 | default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES | |
161 | default 33 if ARM64_VA_BITS=48 | |
162 | default 14 if ARM64_64K_PAGES | |
163 | default 16 if ARM64_16K_PAGES | |
164 | default 18 | |
165 | ||
166 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
167 | default 7 if ARM64_64K_PAGES | |
168 | default 9 if ARM64_16K_PAGES | |
169 | default 11 | |
170 | ||
171 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
172 | default 16 | |
173 | ||
ce816fa8 | 174 | config NO_IOPORT_MAP |
d1e6dc91 | 175 | def_bool y if !PCI |
8c2c3df3 CM |
176 | |
177 | config STACKTRACE_SUPPORT | |
178 | def_bool y | |
179 | ||
bf0c4e04 JVS |
180 | config ILLEGAL_POINTER_VALUE |
181 | hex | |
182 | default 0xdead000000000000 | |
183 | ||
8c2c3df3 CM |
184 | config LOCKDEP_SUPPORT |
185 | def_bool y | |
186 | ||
187 | config TRACE_IRQFLAGS_SUPPORT | |
188 | def_bool y | |
189 | ||
c209f799 | 190 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
191 | def_bool y |
192 | ||
9fb7410f DM |
193 | config GENERIC_BUG |
194 | def_bool y | |
195 | depends on BUG | |
196 | ||
197 | config GENERIC_BUG_RELATIVE_POINTERS | |
198 | def_bool y | |
199 | depends on GENERIC_BUG | |
200 | ||
8c2c3df3 CM |
201 | config GENERIC_HWEIGHT |
202 | def_bool y | |
203 | ||
204 | config GENERIC_CSUM | |
205 | def_bool y | |
206 | ||
207 | config GENERIC_CALIBRATE_DELAY | |
208 | def_bool y | |
209 | ||
19e7640d | 210 | config ZONE_DMA |
8c2c3df3 CM |
211 | def_bool y |
212 | ||
e585513b | 213 | config HAVE_GENERIC_GUP |
29e56940 SC |
214 | def_bool y |
215 | ||
8c2c3df3 CM |
216 | config ARCH_DMA_ADDR_T_64BIT |
217 | def_bool y | |
218 | ||
219 | config NEED_DMA_MAP_STATE | |
220 | def_bool y | |
221 | ||
222 | config NEED_SG_DMA_LENGTH | |
223 | def_bool y | |
224 | ||
4b3dc967 WD |
225 | config SMP |
226 | def_bool y | |
227 | ||
8c2c3df3 CM |
228 | config SWIOTLB |
229 | def_bool y | |
230 | ||
231 | config IOMMU_HELPER | |
232 | def_bool SWIOTLB | |
233 | ||
4cfb3613 AB |
234 | config KERNEL_MODE_NEON |
235 | def_bool y | |
236 | ||
92cc15fc RH |
237 | config FIX_EARLYCON_MEM |
238 | def_bool y | |
239 | ||
9f25e6ad KS |
240 | config PGTABLE_LEVELS |
241 | int | |
21539939 | 242 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad KS |
243 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
244 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
245 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
44eaacf1 SP |
246 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
247 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 248 | |
9842ceae PA |
249 | config ARCH_SUPPORTS_UPROBES |
250 | def_bool y | |
251 | ||
8f360948 AB |
252 | config ARCH_PROC_KCORE_TEXT |
253 | def_bool y | |
254 | ||
8c2c3df3 CM |
255 | source "init/Kconfig" |
256 | ||
257 | source "kernel/Kconfig.freezer" | |
258 | ||
6a377491 | 259 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 CM |
260 | |
261 | menu "Bus support" | |
262 | ||
d1e6dc91 LD |
263 | config PCI |
264 | bool "PCI support" | |
265 | help | |
266 | This feature enables support for PCI bus system. If you say Y | |
267 | here, the kernel will include drivers and infrastructure code | |
268 | to support PCI bus devices. | |
269 | ||
270 | config PCI_DOMAINS | |
271 | def_bool PCI | |
272 | ||
273 | config PCI_DOMAINS_GENERIC | |
274 | def_bool PCI | |
275 | ||
276 | config PCI_SYSCALL | |
277 | def_bool PCI | |
278 | ||
279 | source "drivers/pci/Kconfig" | |
d1e6dc91 | 280 | |
8c2c3df3 CM |
281 | endmenu |
282 | ||
283 | menu "Kernel Features" | |
284 | ||
c0a01b84 AP |
285 | menu "ARM errata workarounds via the alternatives framework" |
286 | ||
287 | config ARM64_ERRATUM_826319 | |
288 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
289 | default y | |
290 | help | |
291 | This option adds an alternative code sequence to work around ARM | |
292 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
293 | AXI master interface and an L2 cache. | |
294 | ||
295 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
296 | and is unable to accept a certain write via this interface, it will | |
297 | not progress on read data presented on the read data channel and the | |
298 | system can deadlock. | |
299 | ||
300 | The workaround promotes data cache clean instructions to | |
301 | data cache clean-and-invalidate. | |
302 | Please note that this does not necessarily enable the workaround, | |
303 | as it depends on the alternative framework, which will only patch | |
304 | the kernel if an affected CPU is detected. | |
305 | ||
306 | If unsure, say Y. | |
307 | ||
308 | config ARM64_ERRATUM_827319 | |
309 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
310 | default y | |
311 | help | |
312 | This option adds an alternative code sequence to work around ARM | |
313 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
314 | master interface and an L2 cache. | |
315 | ||
316 | Under certain conditions this erratum can cause a clean line eviction | |
317 | to occur at the same time as another transaction to the same address | |
318 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
319 | interconnect reorders the two transactions. | |
320 | ||
321 | The workaround promotes data cache clean instructions to | |
322 | data cache clean-and-invalidate. | |
323 | Please note that this does not necessarily enable the workaround, | |
324 | as it depends on the alternative framework, which will only patch | |
325 | the kernel if an affected CPU is detected. | |
326 | ||
327 | If unsure, say Y. | |
328 | ||
329 | config ARM64_ERRATUM_824069 | |
330 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
331 | default y | |
332 | help | |
333 | This option adds an alternative code sequence to work around ARM | |
334 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
335 | to a coherent interconnect. | |
336 | ||
337 | If a Cortex-A53 processor is executing a store or prefetch for | |
338 | write instruction at the same time as a processor in another | |
339 | cluster is executing a cache maintenance operation to the same | |
340 | address, then this erratum might cause a clean cache line to be | |
341 | incorrectly marked as dirty. | |
342 | ||
343 | The workaround promotes data cache clean instructions to | |
344 | data cache clean-and-invalidate. | |
345 | Please note that this option does not necessarily enable the | |
346 | workaround, as it depends on the alternative framework, which will | |
347 | only patch the kernel if an affected CPU is detected. | |
348 | ||
349 | If unsure, say Y. | |
350 | ||
351 | config ARM64_ERRATUM_819472 | |
352 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
353 | default y | |
354 | help | |
355 | This option adds an alternative code sequence to work around ARM | |
356 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
357 | present when it is connected to a coherent interconnect. | |
358 | ||
359 | If the processor is executing a load and store exclusive sequence at | |
360 | the same time as a processor in another cluster is executing a cache | |
361 | maintenance operation to the same address, then this erratum might | |
362 | cause data corruption. | |
363 | ||
364 | The workaround promotes data cache clean instructions to | |
365 | data cache clean-and-invalidate. | |
366 | Please note that this does not necessarily enable the workaround, | |
367 | as it depends on the alternative framework, which will only patch | |
368 | the kernel if an affected CPU is detected. | |
369 | ||
370 | If unsure, say Y. | |
371 | ||
372 | config ARM64_ERRATUM_832075 | |
373 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
374 | default y | |
375 | help | |
376 | This option adds an alternative code sequence to work around ARM | |
377 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
378 | ||
379 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
380 | instructions to Write-Back memory are mixed with Device loads. | |
381 | ||
382 | The workaround is to promote device loads to use Load-Acquire | |
383 | semantics. | |
384 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
385 | as it depends on the alternative framework, which will only patch |
386 | the kernel if an affected CPU is detected. | |
387 | ||
388 | If unsure, say Y. | |
389 | ||
390 | config ARM64_ERRATUM_834220 | |
391 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" | |
392 | depends on KVM | |
393 | default y | |
394 | help | |
395 | This option adds an alternative code sequence to work around ARM | |
396 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
397 | ||
398 | Affected Cortex-A57 parts might report a Stage 2 translation | |
399 | fault as the result of a Stage 1 fault for load crossing a | |
400 | page boundary when there is a permission or device memory | |
401 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
402 | ||
403 | The workaround is to verify that the Stage 1 translation | |
404 | doesn't generate a fault before handling the Stage 2 fault. | |
405 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
406 | as it depends on the alternative framework, which will only patch |
407 | the kernel if an affected CPU is detected. | |
408 | ||
409 | If unsure, say Y. | |
410 | ||
905e8c5d WD |
411 | config ARM64_ERRATUM_845719 |
412 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
413 | depends on COMPAT | |
414 | default y | |
415 | help | |
416 | This option adds an alternative code sequence to work around ARM | |
417 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
418 | ||
419 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
420 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
421 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
422 | might return incorrect data. | |
423 | ||
424 | The workaround is to write the contextidr_el1 register on exception | |
425 | return to a 32-bit task. | |
426 | Please note that this does not necessarily enable the workaround, | |
427 | as it depends on the alternative framework, which will only patch | |
428 | the kernel if an affected CPU is detected. | |
429 | ||
430 | If unsure, say Y. | |
431 | ||
df057cc7 WD |
432 | config ARM64_ERRATUM_843419 |
433 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
df057cc7 | 434 | default y |
6ffe9923 | 435 | select ARM64_MODULE_CMODEL_LARGE if MODULES |
df057cc7 | 436 | help |
6ffe9923 WD |
437 | This option links the kernel with '--fix-cortex-a53-843419' and |
438 | builds modules using the large memory model in order to avoid the use | |
439 | of the ADRP instruction, which can cause a subsequent memory access | |
440 | to use an incorrect address on Cortex-A53 parts up to r0p4. | |
df057cc7 WD |
441 | |
442 | If unsure, say Y. | |
443 | ||
94100970 RR |
444 | config CAVIUM_ERRATUM_22375 |
445 | bool "Cavium erratum 22375, 24313" | |
446 | default y | |
447 | help | |
448 | Enable workaround for erratum 22375, 24313. | |
449 | ||
450 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
451 | with small impact affecting only ITS table allocation. | |
452 | ||
453 | erratum 22375: only alloc 8MB table size | |
454 | erratum 24313: ignore memory access type | |
455 | ||
456 | The fixes are in ITS initialization and basically ignore memory access | |
457 | type and table size provided by the TYPER and BASER registers. | |
458 | ||
459 | If unsure, say Y. | |
460 | ||
fbf8f40e GK |
461 | config CAVIUM_ERRATUM_23144 |
462 | bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" | |
463 | depends on NUMA | |
464 | default y | |
465 | help | |
466 | ITS SYNC command hang for cross node io and collections/cpu mapping. | |
467 | ||
468 | If unsure, say Y. | |
469 | ||
6d4e11c5 RR |
470 | config CAVIUM_ERRATUM_23154 |
471 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" | |
472 | default y | |
473 | help | |
474 | The gicv3 of ThunderX requires a modified version for | |
475 | reading the IAR status to ensure data synchronization | |
476 | (access to icc_iar1_el1 is not sync'ed before and after). | |
477 | ||
478 | If unsure, say Y. | |
479 | ||
104a0c02 AP |
480 | config CAVIUM_ERRATUM_27456 |
481 | bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" | |
482 | default y | |
483 | help | |
484 | On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI | |
485 | instructions may cause the icache to become corrupted if it | |
486 | contains data for a non-current ASID. The fix is to | |
487 | invalidate the icache when changing the mm context. | |
488 | ||
489 | If unsure, say Y. | |
490 | ||
38fd94b0 CC |
491 | config QCOM_FALKOR_ERRATUM_1003 |
492 | bool "Falkor E1003: Incorrect translation due to ASID change" | |
493 | default y | |
494 | select ARM64_PAN if ARM64_SW_TTBR0_PAN | |
495 | help | |
496 | On Falkor v1, an incorrect ASID may be cached in the TLB when ASID | |
497 | and BADDR are changed together in TTBRx_EL1. The workaround for this | |
498 | issue is to use a reserved ASID in cpu_do_switch_mm() before | |
499 | switching to the new ASID. Saying Y here selects ARM64_PAN if | |
500 | ARM64_SW_TTBR0_PAN is selected. This is done because implementing and | |
501 | maintaining the E1003 workaround in the software PAN emulation code | |
502 | would be an unnecessary complication. The affected Falkor v1 CPU | |
503 | implements ARMv8.1 hardware PAN support and using hardware PAN | |
504 | support versus software PAN emulation is mutually exclusive at | |
505 | runtime. | |
506 | ||
507 | If unsure, say Y. | |
508 | ||
d9ff80f8 CC |
509 | config QCOM_FALKOR_ERRATUM_1009 |
510 | bool "Falkor E1009: Prematurely complete a DSB after a TLBI" | |
511 | default y | |
512 | help | |
513 | On Falkor v1, the CPU may prematurely complete a DSB following a | |
514 | TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation | |
515 | one more time to fix the issue. | |
516 | ||
517 | If unsure, say Y. | |
518 | ||
90922a2d SD |
519 | config QCOM_QDF2400_ERRATUM_0065 |
520 | bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" | |
521 | default y | |
522 | help | |
523 | On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports | |
524 | ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have | |
525 | been indicated as 16Bytes (0xf), not 8Bytes (0x7). | |
526 | ||
527 | If unsure, say Y. | |
528 | ||
c0a01b84 AP |
529 | endmenu |
530 | ||
531 | ||
e41ceed0 JL |
532 | choice |
533 | prompt "Page size" | |
534 | default ARM64_4K_PAGES | |
535 | help | |
536 | Page size (translation granule) configuration. | |
537 | ||
538 | config ARM64_4K_PAGES | |
539 | bool "4KB" | |
540 | help | |
541 | This feature enables 4KB pages support. | |
542 | ||
44eaacf1 SP |
543 | config ARM64_16K_PAGES |
544 | bool "16KB" | |
545 | help | |
546 | The system will use 16KB pages support. AArch32 emulation | |
547 | requires applications compiled with 16K (or a multiple of 16K) | |
548 | aligned segments. | |
549 | ||
8c2c3df3 | 550 | config ARM64_64K_PAGES |
e41ceed0 | 551 | bool "64KB" |
8c2c3df3 CM |
552 | help |
553 | This feature enables 64KB pages support (4KB by default) | |
554 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
555 | look-up. AArch32 emulation requires applications compiled |
556 | with 64K aligned segments. | |
8c2c3df3 | 557 | |
e41ceed0 JL |
558 | endchoice |
559 | ||
560 | choice | |
561 | prompt "Virtual address space size" | |
562 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 563 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
564 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
565 | help | |
566 | Allows choosing one of multiple possible virtual address | |
567 | space sizes. The level of translation table is determined by | |
568 | a combination of page size and virtual address space size. | |
569 | ||
21539939 | 570 | config ARM64_VA_BITS_36 |
56a3f30e | 571 | bool "36-bit" if EXPERT |
21539939 SP |
572 | depends on ARM64_16K_PAGES |
573 | ||
e41ceed0 JL |
574 | config ARM64_VA_BITS_39 |
575 | bool "39-bit" | |
576 | depends on ARM64_4K_PAGES | |
577 | ||
578 | config ARM64_VA_BITS_42 | |
579 | bool "42-bit" | |
580 | depends on ARM64_64K_PAGES | |
581 | ||
44eaacf1 SP |
582 | config ARM64_VA_BITS_47 |
583 | bool "47-bit" | |
584 | depends on ARM64_16K_PAGES | |
585 | ||
c79b954b JL |
586 | config ARM64_VA_BITS_48 |
587 | bool "48-bit" | |
c79b954b | 588 | |
e41ceed0 JL |
589 | endchoice |
590 | ||
591 | config ARM64_VA_BITS | |
592 | int | |
21539939 | 593 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
594 | default 39 if ARM64_VA_BITS_39 |
595 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 596 | default 47 if ARM64_VA_BITS_47 |
c79b954b | 597 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 598 | |
a872013d WD |
599 | config CPU_BIG_ENDIAN |
600 | bool "Build big-endian kernel" | |
601 | help | |
602 | Say Y if you plan on running a kernel in big-endian mode. | |
603 | ||
f6e763b9 MB |
604 | config SCHED_MC |
605 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
606 | help |
607 | Multi-core scheduler support improves the CPU scheduler's decision | |
608 | making when dealing with multi-core CPU chips at a cost of slightly | |
609 | increased overhead in some places. If unsure say N here. | |
610 | ||
611 | config SCHED_SMT | |
612 | bool "SMT scheduler support" | |
f6e763b9 MB |
613 | help |
614 | Improves the CPU scheduler's decision making when dealing with | |
615 | MultiThreading at a cost of slightly increased overhead in some | |
616 | places. If unsure say N here. | |
617 | ||
8c2c3df3 | 618 | config NR_CPUS |
62aa9655 GK |
619 | int "Maximum number of CPUs (2-4096)" |
620 | range 2 4096 | |
15942853 | 621 | # These have to remain sorted largest to smallest |
e3672649 | 622 | default "64" |
8c2c3df3 | 623 | |
9327e2c6 MR |
624 | config HOTPLUG_CPU |
625 | bool "Support for hot-pluggable CPUs" | |
217d453d | 626 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
627 | help |
628 | Say Y here to experiment with turning CPUs off and on. CPUs | |
629 | can be controlled through /sys/devices/system/cpu. | |
630 | ||
1a2db300 GK |
631 | # Common NUMA Features |
632 | config NUMA | |
633 | bool "Numa Memory Allocation and Scheduler Support" | |
0c2a6cce KW |
634 | select ACPI_NUMA if ACPI |
635 | select OF_NUMA | |
1a2db300 GK |
636 | help |
637 | Enable NUMA (Non Uniform Memory Access) support. | |
638 | ||
639 | The kernel will try to allocate memory used by a CPU on the | |
640 | local memory of the CPU and add some more | |
641 | NUMA awareness to the kernel. | |
642 | ||
643 | config NODES_SHIFT | |
644 | int "Maximum NUMA Nodes (as a power of 2)" | |
645 | range 1 10 | |
646 | default "2" | |
647 | depends on NEED_MULTIPLE_NODES | |
648 | help | |
649 | Specify the maximum number of NUMA Nodes available on the target | |
650 | system. Increases memory reserved to accommodate various tables. | |
651 | ||
652 | config USE_PERCPU_NUMA_NODE_ID | |
653 | def_bool y | |
654 | depends on NUMA | |
655 | ||
7af3a0a9 ZL |
656 | config HAVE_SETUP_PER_CPU_AREA |
657 | def_bool y | |
658 | depends on NUMA | |
659 | ||
660 | config NEED_PER_CPU_EMBED_FIRST_CHUNK | |
661 | def_bool y | |
662 | depends on NUMA | |
663 | ||
6d526ee2 AB |
664 | config HOLES_IN_ZONE |
665 | def_bool y | |
666 | depends on NUMA | |
667 | ||
8c2c3df3 | 668 | source kernel/Kconfig.preempt |
f90df5e2 | 669 | source kernel/Kconfig.hz |
8c2c3df3 | 670 | |
83863f25 LA |
671 | config ARCH_SUPPORTS_DEBUG_PAGEALLOC |
672 | def_bool y | |
673 | ||
8c2c3df3 CM |
674 | config ARCH_HAS_HOLES_MEMORYMODEL |
675 | def_bool y if SPARSEMEM | |
676 | ||
677 | config ARCH_SPARSEMEM_ENABLE | |
678 | def_bool y | |
679 | select SPARSEMEM_VMEMMAP_ENABLE | |
680 | ||
681 | config ARCH_SPARSEMEM_DEFAULT | |
682 | def_bool ARCH_SPARSEMEM_ENABLE | |
683 | ||
684 | config ARCH_SELECT_MEMORY_MODEL | |
685 | def_bool ARCH_SPARSEMEM_ENABLE | |
686 | ||
687 | config HAVE_ARCH_PFN_VALID | |
688 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
689 | ||
690 | config HW_PERF_EVENTS | |
6475b2d8 MR |
691 | def_bool y |
692 | depends on ARM_PMU | |
8c2c3df3 | 693 | |
084bd298 SC |
694 | config SYS_SUPPORTS_HUGETLBFS |
695 | def_bool y | |
696 | ||
084bd298 | 697 | config ARCH_WANT_HUGE_PMD_SHARE |
21539939 | 698 | def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
084bd298 | 699 | |
a41dc0e8 CM |
700 | config ARCH_HAS_CACHE_LINE_SIZE |
701 | def_bool y | |
702 | ||
8c2c3df3 CM |
703 | source "mm/Kconfig" |
704 | ||
a1ae65b2 AT |
705 | config SECCOMP |
706 | bool "Enable seccomp to safely compute untrusted bytecode" | |
707 | ---help--- | |
708 | This kernel feature is useful for number crunching applications | |
709 | that may need to compute untrusted bytecode during their | |
710 | execution. By using pipes or other transports made available to | |
711 | the process as file descriptors supporting the read/write | |
712 | syscalls, it's possible to isolate those applications in | |
713 | their own address space using seccomp. Once seccomp is | |
714 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
715 | and the task is only allowed to execute a few safe syscalls | |
716 | defined by each seccomp mode. | |
717 | ||
dfd57bc3 SS |
718 | config PARAVIRT |
719 | bool "Enable paravirtualization code" | |
720 | help | |
721 | This changes the kernel so it can modify itself when it is run | |
722 | under a hypervisor, potentially improving performance significantly | |
723 | over full virtualization. | |
724 | ||
725 | config PARAVIRT_TIME_ACCOUNTING | |
726 | bool "Paravirtual steal time accounting" | |
727 | select PARAVIRT | |
728 | default n | |
729 | help | |
730 | Select this option to enable fine granularity task steal time | |
731 | accounting. Time spent executing other tasks in parallel with | |
732 | the current vCPU is discounted from the vCPU power. To account for | |
733 | that, there can be a small performance impact. | |
734 | ||
735 | If in doubt, say N here. | |
736 | ||
d28f6df1 GL |
737 | config KEXEC |
738 | depends on PM_SLEEP_SMP | |
739 | select KEXEC_CORE | |
740 | bool "kexec system call" | |
741 | ---help--- | |
742 | kexec is a system call that implements the ability to shutdown your | |
743 | current kernel, and to start another kernel. It is like a reboot | |
744 | but it is independent of the system firmware. And like a reboot | |
745 | you can start any kernel with it, not just Linux. | |
746 | ||
e62aaeac AT |
747 | config CRASH_DUMP |
748 | bool "Build kdump crash kernel" | |
749 | help | |
750 | Generate crash dump after being started by kexec. This should | |
751 | be normally only set in special crash dump kernels which are | |
752 | loaded in the main kernel with kexec-tools into a specially | |
753 | reserved region and then later executed after a crash by | |
754 | kdump/kexec. | |
755 | ||
756 | For more details see Documentation/kdump/kdump.txt | |
757 | ||
aa42aa13 SS |
758 | config XEN_DOM0 |
759 | def_bool y | |
760 | depends on XEN | |
761 | ||
762 | config XEN | |
c2ba1f7d | 763 | bool "Xen guest support on ARM64" |
aa42aa13 | 764 | depends on ARM64 && OF |
83862ccf | 765 | select SWIOTLB_XEN |
dfd57bc3 | 766 | select PARAVIRT |
aa42aa13 SS |
767 | help |
768 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
769 | ||
d03bb145 SC |
770 | config FORCE_MAX_ZONEORDER |
771 | int | |
772 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
44eaacf1 | 773 | default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) |
d03bb145 | 774 | default "11" |
44eaacf1 SP |
775 | help |
776 | The kernel memory allocator divides physically contiguous memory | |
777 | blocks into "zones", where each zone is a power of two number of | |
778 | pages. This option selects the largest power of two that the kernel | |
779 | keeps in the memory allocator. If you need to allocate very large | |
780 | blocks of physically contiguous memory, then you may need to | |
781 | increase this value. | |
782 | ||
783 | This config option is actually maximum order plus one. For example, | |
784 | a value of 11 means that the largest free memory block is 2^10 pages. | |
785 | ||
786 | We make sure that we can allocate upto a HugePage size for each configuration. | |
787 | Hence we have : | |
788 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 | |
789 | ||
790 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us | |
791 | 4M allocations matching the default size used by generic code. | |
d03bb145 | 792 | |
1b907f46 WD |
793 | menuconfig ARMV8_DEPRECATED |
794 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
795 | depends on COMPAT | |
796 | help | |
797 | Legacy software support may require certain instructions | |
798 | that have been deprecated or obsoleted in the architecture. | |
799 | ||
800 | Enable this config to enable selective emulation of these | |
801 | features. | |
802 | ||
803 | If unsure, say Y | |
804 | ||
805 | if ARMV8_DEPRECATED | |
806 | ||
807 | config SWP_EMULATION | |
808 | bool "Emulate SWP/SWPB instructions" | |
809 | help | |
810 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
811 | they are always undefined. Say Y here to enable software | |
812 | emulation of these instructions for userspace using LDXR/STXR. | |
813 | ||
814 | In some older versions of glibc [<=2.8] SWP is used during futex | |
815 | trylock() operations with the assumption that the code will not | |
816 | be preempted. This invalid assumption may be more likely to fail | |
817 | with SWP emulation enabled, leading to deadlock of the user | |
818 | application. | |
819 | ||
820 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
821 | on an external transaction monitoring block called a global | |
822 | monitor to maintain update atomicity. If your system does not | |
823 | implement a global monitor, this option can cause programs that | |
824 | perform SWP operations to uncached memory to deadlock. | |
825 | ||
826 | If unsure, say Y | |
827 | ||
828 | config CP15_BARRIER_EMULATION | |
829 | bool "Emulate CP15 Barrier instructions" | |
830 | help | |
831 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
832 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
833 | strongly recommended to use the ISB, DSB, and DMB | |
834 | instructions instead. | |
835 | ||
836 | Say Y here to enable software emulation of these | |
837 | instructions for AArch32 userspace code. When this option is | |
838 | enabled, CP15 barrier usage is traced which can help | |
839 | identify software that needs updating. | |
840 | ||
841 | If unsure, say Y | |
842 | ||
2d888f48 SP |
843 | config SETEND_EMULATION |
844 | bool "Emulate SETEND instruction" | |
845 | help | |
846 | The SETEND instruction alters the data-endianness of the | |
847 | AArch32 EL0, and is deprecated in ARMv8. | |
848 | ||
849 | Say Y here to enable software emulation of the instruction | |
850 | for AArch32 userspace code. | |
851 | ||
852 | Note: All the cpus on the system must have mixed endian support at EL0 | |
853 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
854 | endian - is hotplugged in after this feature has been enabled, there could | |
855 | be unexpected results in the applications. | |
856 | ||
857 | If unsure, say Y | |
1b907f46 WD |
858 | endif |
859 | ||
ba42822a CM |
860 | config ARM64_SW_TTBR0_PAN |
861 | bool "Emulate Privileged Access Never using TTBR0_EL1 switching" | |
862 | help | |
863 | Enabling this option prevents the kernel from accessing | |
864 | user-space memory directly by pointing TTBR0_EL1 to a reserved | |
865 | zeroed area and reserved ASID. The user access routines | |
866 | restore the valid TTBR0_EL1 temporarily. | |
867 | ||
0e4a0709 WD |
868 | menu "ARMv8.1 architectural features" |
869 | ||
870 | config ARM64_HW_AFDBM | |
871 | bool "Support for hardware updates of the Access and Dirty page flags" | |
872 | default y | |
873 | help | |
874 | The ARMv8.1 architecture extensions introduce support for | |
875 | hardware updates of the access and dirty information in page | |
876 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
877 | capable processors, accesses to pages with PTE_AF cleared will | |
878 | set this bit instead of raising an access flag fault. | |
879 | Similarly, writes to read-only pages with the DBM bit set will | |
880 | clear the read-only bit (AP[2]) instead of raising a | |
881 | permission fault. | |
882 | ||
883 | Kernels built with this configuration option enabled continue | |
884 | to work on pre-ARMv8.1 hardware and the performance impact is | |
885 | minimal. If unsure, say Y. | |
886 | ||
887 | config ARM64_PAN | |
888 | bool "Enable support for Privileged Access Never (PAN)" | |
889 | default y | |
890 | help | |
891 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
892 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
893 | memory directly. | |
894 | ||
895 | Choosing this option will cause any unprotected (not using | |
896 | copy_to_user et al) memory access to fail with a permission fault. | |
897 | ||
898 | The feature is detected at runtime, and will remain as a 'nop' | |
899 | instruction if the cpu does not implement the feature. | |
900 | ||
901 | config ARM64_LSE_ATOMICS | |
902 | bool "Atomic instructions" | |
903 | help | |
904 | As part of the Large System Extensions, ARMv8.1 introduces new | |
905 | atomic instructions that are designed specifically to scale in | |
906 | very large systems. | |
907 | ||
908 | Say Y here to make use of these instructions for the in-kernel | |
909 | atomic routines. This incurs a small overhead on CPUs that do | |
910 | not support these instructions and requires the kernel to be | |
911 | built with binutils >= 2.25. | |
912 | ||
1f364c8c MZ |
913 | config ARM64_VHE |
914 | bool "Enable support for Virtualization Host Extensions (VHE)" | |
915 | default y | |
916 | help | |
917 | Virtualization Host Extensions (VHE) allow the kernel to run | |
918 | directly at EL2 (instead of EL1) on processors that support | |
919 | it. This leads to better performance for KVM, as they reduce | |
920 | the cost of the world switch. | |
921 | ||
922 | Selecting this option allows the VHE feature to be detected | |
923 | at runtime, and does not affect processors that do not | |
924 | implement this feature. | |
925 | ||
0e4a0709 WD |
926 | endmenu |
927 | ||
f993318b WD |
928 | menu "ARMv8.2 architectural features" |
929 | ||
57f4959b JM |
930 | config ARM64_UAO |
931 | bool "Enable support for User Access Override (UAO)" | |
932 | default y | |
933 | help | |
934 | User Access Override (UAO; part of the ARMv8.2 Extensions) | |
935 | causes the 'unprivileged' variant of the load/store instructions to | |
936 | be overriden to be privileged. | |
937 | ||
938 | This option changes get_user() and friends to use the 'unprivileged' | |
939 | variant of the load/store instructions. This ensures that user-space | |
940 | really did have access to the supplied memory. When addr_limit is | |
941 | set to kernel memory the UAO bit will be set, allowing privileged | |
942 | access to kernel memory. | |
943 | ||
944 | Choosing this option will cause copy_to_user() et al to use user-space | |
945 | memory permissions. | |
946 | ||
947 | The feature is detected at runtime, the kernel will use the | |
948 | regular load/store instructions if the cpu does not implement the | |
949 | feature. | |
950 | ||
f993318b WD |
951 | endmenu |
952 | ||
fd045f6c AB |
953 | config ARM64_MODULE_CMODEL_LARGE |
954 | bool | |
955 | ||
956 | config ARM64_MODULE_PLTS | |
957 | bool | |
958 | select ARM64_MODULE_CMODEL_LARGE | |
959 | select HAVE_MOD_ARCH_SPECIFIC | |
960 | ||
1e48ef7f AB |
961 | config RELOCATABLE |
962 | bool | |
963 | help | |
964 | This builds the kernel as a Position Independent Executable (PIE), | |
965 | which retains all relocation metadata required to relocate the | |
966 | kernel binary at runtime to a different virtual address than the | |
967 | address it was linked at. | |
968 | Since AArch64 uses the RELA relocation format, this requires a | |
969 | relocation pass at runtime even if the kernel is loaded at the | |
970 | same address it was linked at. | |
971 | ||
f80fb3a3 AB |
972 | config RANDOMIZE_BASE |
973 | bool "Randomize the address of the kernel image" | |
b9c220b5 | 974 | select ARM64_MODULE_PLTS if MODULES |
f80fb3a3 AB |
975 | select RELOCATABLE |
976 | help | |
977 | Randomizes the virtual address at which the kernel image is | |
978 | loaded, as a security feature that deters exploit attempts | |
979 | relying on knowledge of the location of kernel internals. | |
980 | ||
981 | It is the bootloader's job to provide entropy, by passing a | |
982 | random u64 value in /chosen/kaslr-seed at kernel entry. | |
983 | ||
2b5fe07a AB |
984 | When booting via the UEFI stub, it will invoke the firmware's |
985 | EFI_RNG_PROTOCOL implementation (if available) to supply entropy | |
986 | to the kernel proper. In addition, it will randomise the physical | |
987 | location of the kernel Image as well. | |
988 | ||
f80fb3a3 AB |
989 | If unsure, say N. |
990 | ||
991 | config RANDOMIZE_MODULE_REGION_FULL | |
992 | bool "Randomize the module region independently from the core kernel" | |
e71a4e1b | 993 | depends on RANDOMIZE_BASE |
f80fb3a3 AB |
994 | default y |
995 | help | |
996 | Randomizes the location of the module region without considering the | |
997 | location of the core kernel. This way, it is impossible for modules | |
998 | to leak information about the location of core kernel data structures | |
999 | but it does imply that function calls between modules and the core | |
1000 | kernel will need to be resolved via veneers in the module PLT. | |
1001 | ||
1002 | When this option is not set, the module region will be randomized over | |
1003 | a limited range that contains the [_stext, _etext] interval of the | |
1004 | core kernel, so branch relocations are always in range. | |
1005 | ||
8c2c3df3 CM |
1006 | endmenu |
1007 | ||
1008 | menu "Boot options" | |
1009 | ||
5e89c55e LP |
1010 | config ARM64_ACPI_PARKING_PROTOCOL |
1011 | bool "Enable support for the ARM64 ACPI parking protocol" | |
1012 | depends on ACPI | |
1013 | help | |
1014 | Enable support for the ARM64 ACPI parking protocol. If disabled | |
1015 | the kernel will not allow booting through the ARM64 ACPI parking | |
1016 | protocol even if the corresponding data is present in the ACPI | |
1017 | MADT table. | |
1018 | ||
8c2c3df3 CM |
1019 | config CMDLINE |
1020 | string "Default kernel command string" | |
1021 | default "" | |
1022 | help | |
1023 | Provide a set of default command-line options at build time by | |
1024 | entering them here. As a minimum, you should specify the the | |
1025 | root device (e.g. root=/dev/nfs). | |
1026 | ||
1027 | config CMDLINE_FORCE | |
1028 | bool "Always use the default kernel command string" | |
1029 | help | |
1030 | Always use the default kernel command string, even if the boot | |
1031 | loader passes other arguments to the kernel. | |
1032 | This is useful if you cannot or don't want to change the | |
1033 | command-line options your boot loader passes to the kernel. | |
1034 | ||
f4f75ad5 AB |
1035 | config EFI_STUB |
1036 | bool | |
1037 | ||
f84d0275 MS |
1038 | config EFI |
1039 | bool "UEFI runtime support" | |
1040 | depends on OF && !CPU_BIG_ENDIAN | |
1041 | select LIBFDT | |
1042 | select UCS2_STRING | |
1043 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 1044 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
1045 | select EFI_STUB |
1046 | select EFI_ARMSTUB | |
f84d0275 MS |
1047 | default y |
1048 | help | |
1049 | This option provides support for runtime services provided | |
1050 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
1051 | clock, and platform reset). A UEFI stub is also provided to |
1052 | allow the kernel to be booted as an EFI application. This | |
1053 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 1054 | |
d1ae8c00 YL |
1055 | config DMI |
1056 | bool "Enable support for SMBIOS (DMI) tables" | |
1057 | depends on EFI | |
1058 | default y | |
1059 | help | |
1060 | This enables SMBIOS/DMI feature for systems. | |
1061 | ||
1062 | This option is only useful on systems that have UEFI firmware. | |
1063 | However, even with this option, the resultant kernel should | |
1064 | continue to boot on existing non-UEFI platforms. | |
1065 | ||
8c2c3df3 CM |
1066 | endmenu |
1067 | ||
1068 | menu "Userspace binary formats" | |
1069 | ||
1070 | source "fs/Kconfig.binfmt" | |
1071 | ||
1072 | config COMPAT | |
1073 | bool "Kernel support for 32-bit EL0" | |
755e70b7 | 1074 | depends on ARM64_4K_PAGES || EXPERT |
2e449048 | 1075 | select COMPAT_BINFMT_ELF if BINFMT_ELF |
af1839eb | 1076 | select HAVE_UID16 |
84b9e9b4 | 1077 | select OLD_SIGSUSPEND3 |
51682036 | 1078 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
1079 | help |
1080 | This option enables support for a 32-bit EL0 running under a 64-bit | |
1081 | kernel at EL1. AArch32-specific components such as system calls, | |
1082 | the user helper functions, VFP support and the ptrace interface are | |
1083 | handled appropriately by the kernel. | |
1084 | ||
44eaacf1 SP |
1085 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware |
1086 | that you will only be able to execute AArch32 binaries that were compiled | |
1087 | with page size aligned segments. | |
a8fcd8b1 | 1088 | |
8c2c3df3 CM |
1089 | If you want to execute 32-bit userspace applications, say Y. |
1090 | ||
1091 | config SYSVIPC_COMPAT | |
1092 | def_bool y | |
1093 | depends on COMPAT && SYSVIPC | |
1094 | ||
1095 | endmenu | |
1096 | ||
166936ba LP |
1097 | menu "Power management options" |
1098 | ||
1099 | source "kernel/power/Kconfig" | |
1100 | ||
82869ac5 JM |
1101 | config ARCH_HIBERNATION_POSSIBLE |
1102 | def_bool y | |
1103 | depends on CPU_PM | |
1104 | ||
1105 | config ARCH_HIBERNATION_HEADER | |
1106 | def_bool y | |
1107 | depends on HIBERNATION | |
1108 | ||
166936ba LP |
1109 | config ARCH_SUSPEND_POSSIBLE |
1110 | def_bool y | |
1111 | ||
166936ba LP |
1112 | endmenu |
1113 | ||
1307220d LP |
1114 | menu "CPU Power Management" |
1115 | ||
1116 | source "drivers/cpuidle/Kconfig" | |
1117 | ||
52e7e816 RH |
1118 | source "drivers/cpufreq/Kconfig" |
1119 | ||
1120 | endmenu | |
1121 | ||
8c2c3df3 CM |
1122 | source "net/Kconfig" |
1123 | ||
1124 | source "drivers/Kconfig" | |
1125 | ||
f84d0275 MS |
1126 | source "drivers/firmware/Kconfig" |
1127 | ||
b6a02173 GG |
1128 | source "drivers/acpi/Kconfig" |
1129 | ||
8c2c3df3 CM |
1130 | source "fs/Kconfig" |
1131 | ||
c3eb5b14 MZ |
1132 | source "arch/arm64/kvm/Kconfig" |
1133 | ||
8c2c3df3 CM |
1134 | source "arch/arm64/Kconfig.debug" |
1135 | ||
1136 | source "security/Kconfig" | |
1137 | ||
1138 | source "crypto/Kconfig" | |
2c98833a AB |
1139 | if CRYPTO |
1140 | source "arch/arm64/crypto/Kconfig" | |
1141 | endif | |
8c2c3df3 CM |
1142 | |
1143 | source "lib/Kconfig" |