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gcov: enable GCOV_PROFILE_ALL from ARCH Kconfigs
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8c2c3df3
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1config ARM64
2 def_bool y
92980405 3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
8c2c3df3 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
957e3fac 5 select ARCH_HAS_GCOV_PROFILE_ALL
308c09f1 6 select ARCH_HAS_SG_CHAIN
1f85008e 7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
c63c8700 8 select ARCH_USE_CMPXCHG_LOCKREF
4badad35 9 select ARCH_SUPPORTS_ATOMIC_RMW
9170100e 10 select ARCH_WANT_OPTIONAL_GPIOLIB
6212a512 11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
b6f35981 12 select ARCH_WANT_FRAME_POINTERS
25c92a37 13 select ARM_AMBA
1aee5d7a 14 select ARM_ARCH_TIMER
c4188edc 15 select ARM_GIC
875cbf3e 16 select AUDIT_ARCH_COMPAT_GENERIC
021f6537 17 select ARM_GIC_V3
adace895 18 select BUILDTIME_EXTABLE_SORT
db2789b5 19 select CLONE_BACKWARDS
7ca2ef33 20 select COMMON_CLK
166936ba 21 select CPU_PM if (SUSPEND || CPU_IDLE)
7bc13fd3 22 select DCACHE_WORD_ACCESS
d4932f9e 23 select GENERIC_ALLOCATOR
8c2c3df3 24 select GENERIC_CLOCKEVENTS
1f85008e 25 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
3be1a5c4 26 select GENERIC_CPU_AUTOPROBE
bf4b558e 27 select GENERIC_EARLY_IOREMAP
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28 select GENERIC_IRQ_PROBE
29 select GENERIC_IRQ_SHOW
cb61f676 30 select GENERIC_PCI_IOMAP
65cd4f6c 31 select GENERIC_SCHED_CLOCK
8c2c3df3 32 select GENERIC_SMP_IDLE_THREAD
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33 select GENERIC_STRNCPY_FROM_USER
34 select GENERIC_STRNLEN_USER
8c2c3df3 35 select GENERIC_TIME_VSYSCALL
a1ddc74a 36 select HANDLE_DOMAIN_IRQ
8c2c3df3 37 select HARDIRQS_SW_RESEND
5284e1b4 38 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
875cbf3e 39 select HAVE_ARCH_AUDITSYSCALL
9732cafd 40 select HAVE_ARCH_JUMP_LABEL
9529247d 41 select HAVE_ARCH_KGDB
a1ae65b2 42 select HAVE_ARCH_SECCOMP_FILTER
8c2c3df3 43 select HAVE_ARCH_TRACEHOOK
e54bcde3 44 select HAVE_BPF_JIT
af64d2aa 45 select HAVE_C_RECORDMCOUNT
c0c264ae 46 select HAVE_CC_STACKPROTECTOR
5284e1b4 47 select HAVE_CMPXCHG_DOUBLE
9b2a60c4 48 select HAVE_DEBUG_BUGVERBOSE
b69ec42b 49 select HAVE_DEBUG_KMEMLEAK
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50 select HAVE_DMA_API_DEBUG
51 select HAVE_DMA_ATTRS
6ac2104d 52 select HAVE_DMA_CONTIGUOUS
bd7d38db 53 select HAVE_DYNAMIC_FTRACE
50afc33a 54 select HAVE_EFFICIENT_UNALIGNED_ACCESS
af64d2aa 55 select HAVE_FTRACE_MCOUNT_RECORD
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56 select HAVE_FUNCTION_TRACER
57 select HAVE_FUNCTION_GRAPH_TRACER
8c2c3df3 58 select HAVE_GENERIC_DMA_COHERENT
8c2c3df3 59 select HAVE_HW_BREAKPOINT if PERF_EVENTS
8c2c3df3 60 select HAVE_MEMBLOCK
55834a77 61 select HAVE_PATA_PLATFORM
8c2c3df3 62 select HAVE_PERF_EVENTS
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63 select HAVE_PERF_REGS
64 select HAVE_PERF_USER_STACK_DUMP
5e5f6dc1 65 select HAVE_RCU_TABLE_FREE
055b1212 66 select HAVE_SYSCALL_TRACEPOINTS
8c2c3df3 67 select IRQ_DOMAIN
fea2acaa 68 select MODULES_USE_ELF_RELA
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69 select NO_BOOTMEM
70 select OF
71 select OF_EARLY_FLATTREE
9bf14b7c 72 select OF_RESERVED_MEM
8c2c3df3 73 select PERF_USE_VMALLOC
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74 select POWER_RESET
75 select POWER_SUPPLY
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76 select RTC_LIB
77 select SPARSE_IRQ
7ac57a89 78 select SYSCTL_EXCEPTION_TRACE
6c81fe79 79 select HAVE_CONTEXT_TRACKING
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80 help
81 ARM 64-bit (AArch64) Linux support.
82
83config 64BIT
84 def_bool y
85
86config ARCH_PHYS_ADDR_T_64BIT
87 def_bool y
88
89config MMU
90 def_bool y
91
ce816fa8 92config NO_IOPORT_MAP
d1e6dc91 93 def_bool y if !PCI
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94
95config STACKTRACE_SUPPORT
96 def_bool y
97
98config LOCKDEP_SUPPORT
99 def_bool y
100
101config TRACE_IRQFLAGS_SUPPORT
102 def_bool y
103
c209f799 104config RWSEM_XCHGADD_ALGORITHM
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105 def_bool y
106
107config GENERIC_HWEIGHT
108 def_bool y
109
110config GENERIC_CSUM
111 def_bool y
112
113config GENERIC_CALIBRATE_DELAY
114 def_bool y
115
19e7640d 116config ZONE_DMA
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117 def_bool y
118
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119config HAVE_GENERIC_RCU_GUP
120 def_bool y
121
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122config ARCH_DMA_ADDR_T_64BIT
123 def_bool y
124
125config NEED_DMA_MAP_STATE
126 def_bool y
127
128config NEED_SG_DMA_LENGTH
129 def_bool y
130
131config SWIOTLB
132 def_bool y
133
134config IOMMU_HELPER
135 def_bool SWIOTLB
136
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137config KERNEL_MODE_NEON
138 def_bool y
139
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140config FIX_EARLYCON_MEM
141 def_bool y
142
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143source "init/Kconfig"
144
145source "kernel/Kconfig.freezer"
146
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147menu "Platform selection"
148
41904360
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149config ARCH_SEATTLE
150 bool "AMD Seattle SoC Family"
151 help
152 This enables support for AMD Seattle SOC Family
153
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154config ARCH_THUNDER
155 bool "Cavium Inc. Thunder SoC Family"
156 help
157 This enables support for Cavium's Thunder Family of SoCs.
158
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159config ARCH_VEXPRESS
160 bool "ARMv8 software model (Versatile Express)"
161 select ARCH_REQUIRE_GPIOLIB
162 select COMMON_CLK_VERSATILE
aa1e8ec1 163 select POWER_RESET_VEXPRESS
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164 select VEXPRESS_CONFIG
165 help
166 This enables support for the ARMv8 software model (Versatile
167 Express).
8c2c3df3 168
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169config ARCH_XGENE
170 bool "AppliedMicro X-Gene SOC Family"
171 help
172 This enables support for AppliedMicro X-Gene SOC Family
173
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174endmenu
175
176menu "Bus support"
177
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178config PCI
179 bool "PCI support"
180 help
181 This feature enables support for PCI bus system. If you say Y
182 here, the kernel will include drivers and infrastructure code
183 to support PCI bus devices.
184
185config PCI_DOMAINS
186 def_bool PCI
187
188config PCI_DOMAINS_GENERIC
189 def_bool PCI
190
191config PCI_SYSCALL
192 def_bool PCI
193
194source "drivers/pci/Kconfig"
195source "drivers/pci/pcie/Kconfig"
196source "drivers/pci/hotplug/Kconfig"
197
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198endmenu
199
200menu "Kernel Features"
201
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202menu "ARM errata workarounds via the alternatives framework"
203
204config ARM64_ERRATUM_826319
205 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
206 default y
207 help
208 This option adds an alternative code sequence to work around ARM
209 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
210 AXI master interface and an L2 cache.
211
212 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
213 and is unable to accept a certain write via this interface, it will
214 not progress on read data presented on the read data channel and the
215 system can deadlock.
216
217 The workaround promotes data cache clean instructions to
218 data cache clean-and-invalidate.
219 Please note that this does not necessarily enable the workaround,
220 as it depends on the alternative framework, which will only patch
221 the kernel if an affected CPU is detected.
222
223 If unsure, say Y.
224
225config ARM64_ERRATUM_827319
226 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
227 default y
228 help
229 This option adds an alternative code sequence to work around ARM
230 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
231 master interface and an L2 cache.
232
233 Under certain conditions this erratum can cause a clean line eviction
234 to occur at the same time as another transaction to the same address
235 on the AMBA 5 CHI interface, which can cause data corruption if the
236 interconnect reorders the two transactions.
237
238 The workaround promotes data cache clean instructions to
239 data cache clean-and-invalidate.
240 Please note that this does not necessarily enable the workaround,
241 as it depends on the alternative framework, which will only patch
242 the kernel if an affected CPU is detected.
243
244 If unsure, say Y.
245
246config ARM64_ERRATUM_824069
247 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
248 default y
249 help
250 This option adds an alternative code sequence to work around ARM
251 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
252 to a coherent interconnect.
253
254 If a Cortex-A53 processor is executing a store or prefetch for
255 write instruction at the same time as a processor in another
256 cluster is executing a cache maintenance operation to the same
257 address, then this erratum might cause a clean cache line to be
258 incorrectly marked as dirty.
259
260 The workaround promotes data cache clean instructions to
261 data cache clean-and-invalidate.
262 Please note that this option does not necessarily enable the
263 workaround, as it depends on the alternative framework, which will
264 only patch the kernel if an affected CPU is detected.
265
266 If unsure, say Y.
267
268config ARM64_ERRATUM_819472
269 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
270 default y
271 help
272 This option adds an alternative code sequence to work around ARM
273 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
274 present when it is connected to a coherent interconnect.
275
276 If the processor is executing a load and store exclusive sequence at
277 the same time as a processor in another cluster is executing a cache
278 maintenance operation to the same address, then this erratum might
279 cause data corruption.
280
281 The workaround promotes data cache clean instructions to
282 data cache clean-and-invalidate.
283 Please note that this does not necessarily enable the workaround,
284 as it depends on the alternative framework, which will only patch
285 the kernel if an affected CPU is detected.
286
287 If unsure, say Y.
288
289config ARM64_ERRATUM_832075
290 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
291 default y
292 help
293 This option adds an alternative code sequence to work around ARM
294 erratum 832075 on Cortex-A57 parts up to r1p2.
295
296 Affected Cortex-A57 parts might deadlock when exclusive load/store
297 instructions to Write-Back memory are mixed with Device loads.
298
299 The workaround is to promote device loads to use Load-Acquire
300 semantics.
301 Please note that this does not necessarily enable the workaround,
302 as it depends on the alternative framework, which will only patch
303 the kernel if an affected CPU is detected.
304
305 If unsure, say Y.
306
307endmenu
308
309
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310choice
311 prompt "Page size"
312 default ARM64_4K_PAGES
313 help
314 Page size (translation granule) configuration.
315
316config ARM64_4K_PAGES
317 bool "4KB"
318 help
319 This feature enables 4KB pages support.
320
8c2c3df3 321config ARM64_64K_PAGES
e41ceed0 322 bool "64KB"
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323 help
324 This feature enables 64KB pages support (4KB by default)
325 allowing only two levels of page tables and faster TLB
326 look-up. AArch32 emulation is not available when this feature
327 is enabled.
328
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329endchoice
330
331choice
332 prompt "Virtual address space size"
333 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
334 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
335 help
336 Allows choosing one of multiple possible virtual address
337 space sizes. The level of translation table is determined by
338 a combination of page size and virtual address space size.
339
340config ARM64_VA_BITS_39
341 bool "39-bit"
342 depends on ARM64_4K_PAGES
343
344config ARM64_VA_BITS_42
345 bool "42-bit"
346 depends on ARM64_64K_PAGES
347
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348config ARM64_VA_BITS_48
349 bool "48-bit"
04f905a9 350 depends on !ARM_SMMU
c79b954b 351
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352endchoice
353
354config ARM64_VA_BITS
355 int
356 default 39 if ARM64_VA_BITS_39
357 default 42 if ARM64_VA_BITS_42
c79b954b 358 default 48 if ARM64_VA_BITS_48
e41ceed0 359
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360config ARM64_PGTABLE_LEVELS
361 int
362 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
383c2799 363 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
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364 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
365 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
c79b954b 366
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367config CPU_BIG_ENDIAN
368 bool "Build big-endian kernel"
369 help
370 Say Y if you plan on running a kernel in big-endian mode.
371
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372config SMP
373 bool "Symmetric Multi-Processing"
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374 help
375 This enables support for systems with more than one CPU. If
376 you say N here, the kernel will run on single and
377 multiprocessor machines, but will use only one CPU of a
378 multiprocessor machine. If you say Y here, the kernel will run
379 on many, but not all, single processor machines. On a single
380 processor machine, the kernel will run faster if you say N
381 here.
382
383 If you don't know what to do here, say N.
384
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385config SCHED_MC
386 bool "Multi-core scheduler support"
387 depends on SMP
388 help
389 Multi-core scheduler support improves the CPU scheduler's decision
390 making when dealing with multi-core CPU chips at a cost of slightly
391 increased overhead in some places. If unsure say N here.
392
393config SCHED_SMT
394 bool "SMT scheduler support"
395 depends on SMP
396 help
397 Improves the CPU scheduler's decision making when dealing with
398 MultiThreading at a cost of slightly increased overhead in some
399 places. If unsure say N here.
400
8c2c3df3 401config NR_CPUS
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402 int "Maximum number of CPUs (2-64)"
403 range 2 64
8c2c3df3 404 depends on SMP
15942853 405 # These have to remain sorted largest to smallest
e3672649 406 default "64"
8c2c3df3 407
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408config HOTPLUG_CPU
409 bool "Support for hot-pluggable CPUs"
410 depends on SMP
411 help
412 Say Y here to experiment with turning CPUs off and on. CPUs
413 can be controlled through /sys/devices/system/cpu.
414
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415source kernel/Kconfig.preempt
416
417config HZ
418 int
419 default 100
420
421config ARCH_HAS_HOLES_MEMORYMODEL
422 def_bool y if SPARSEMEM
423
424config ARCH_SPARSEMEM_ENABLE
425 def_bool y
426 select SPARSEMEM_VMEMMAP_ENABLE
427
428config ARCH_SPARSEMEM_DEFAULT
429 def_bool ARCH_SPARSEMEM_ENABLE
430
431config ARCH_SELECT_MEMORY_MODEL
432 def_bool ARCH_SPARSEMEM_ENABLE
433
434config HAVE_ARCH_PFN_VALID
435 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
436
437config HW_PERF_EVENTS
438 bool "Enable hardware performance counter support for perf events"
439 depends on PERF_EVENTS
440 default y
441 help
442 Enable hardware performance counter support for perf events. If
443 disabled, perf events will use software events only.
444
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445config SYS_SUPPORTS_HUGETLBFS
446 def_bool y
447
448config ARCH_WANT_GENERAL_HUGETLB
449 def_bool y
450
451config ARCH_WANT_HUGE_PMD_SHARE
452 def_bool y if !ARM64_64K_PAGES
453
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454config HAVE_ARCH_TRANSPARENT_HUGEPAGE
455 def_bool y
456
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457config ARCH_HAS_CACHE_LINE_SIZE
458 def_bool y
459
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460source "mm/Kconfig"
461
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462config SECCOMP
463 bool "Enable seccomp to safely compute untrusted bytecode"
464 ---help---
465 This kernel feature is useful for number crunching applications
466 that may need to compute untrusted bytecode during their
467 execution. By using pipes or other transports made available to
468 the process as file descriptors supporting the read/write
469 syscalls, it's possible to isolate those applications in
470 their own address space using seccomp. Once seccomp is
471 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
472 and the task is only allowed to execute a few safe syscalls
473 defined by each seccomp mode.
474
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475config XEN_DOM0
476 def_bool y
477 depends on XEN
478
479config XEN
c2ba1f7d 480 bool "Xen guest support on ARM64"
aa42aa13 481 depends on ARM64 && OF
83862ccf 482 select SWIOTLB_XEN
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483 help
484 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
485
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486config FORCE_MAX_ZONEORDER
487 int
488 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
489 default "11"
490
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491menuconfig ARMV8_DEPRECATED
492 bool "Emulate deprecated/obsolete ARMv8 instructions"
493 depends on COMPAT
494 help
495 Legacy software support may require certain instructions
496 that have been deprecated or obsoleted in the architecture.
497
498 Enable this config to enable selective emulation of these
499 features.
500
501 If unsure, say Y
502
503if ARMV8_DEPRECATED
504
505config SWP_EMULATION
506 bool "Emulate SWP/SWPB instructions"
507 help
508 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
509 they are always undefined. Say Y here to enable software
510 emulation of these instructions for userspace using LDXR/STXR.
511
512 In some older versions of glibc [<=2.8] SWP is used during futex
513 trylock() operations with the assumption that the code will not
514 be preempted. This invalid assumption may be more likely to fail
515 with SWP emulation enabled, leading to deadlock of the user
516 application.
517
518 NOTE: when accessing uncached shared regions, LDXR/STXR rely
519 on an external transaction monitoring block called a global
520 monitor to maintain update atomicity. If your system does not
521 implement a global monitor, this option can cause programs that
522 perform SWP operations to uncached memory to deadlock.
523
524 If unsure, say Y
525
526config CP15_BARRIER_EMULATION
527 bool "Emulate CP15 Barrier instructions"
528 help
529 The CP15 barrier instructions - CP15ISB, CP15DSB, and
530 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
531 strongly recommended to use the ISB, DSB, and DMB
532 instructions instead.
533
534 Say Y here to enable software emulation of these
535 instructions for AArch32 userspace code. When this option is
536 enabled, CP15 barrier usage is traced which can help
537 identify software that needs updating.
538
539 If unsure, say Y
540
541endif
542
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543endmenu
544
545menu "Boot options"
546
547config CMDLINE
548 string "Default kernel command string"
549 default ""
550 help
551 Provide a set of default command-line options at build time by
552 entering them here. As a minimum, you should specify the the
553 root device (e.g. root=/dev/nfs).
554
555config CMDLINE_FORCE
556 bool "Always use the default kernel command string"
557 help
558 Always use the default kernel command string, even if the boot
559 loader passes other arguments to the kernel.
560 This is useful if you cannot or don't want to change the
561 command-line options your boot loader passes to the kernel.
562
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563config EFI_STUB
564 bool
565
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566config EFI
567 bool "UEFI runtime support"
568 depends on OF && !CPU_BIG_ENDIAN
569 select LIBFDT
570 select UCS2_STRING
571 select EFI_PARAMS_FROM_FDT
e15dd494 572 select EFI_RUNTIME_WRAPPERS
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573 select EFI_STUB
574 select EFI_ARMSTUB
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575 default y
576 help
577 This option provides support for runtime services provided
578 by UEFI firmware (such as non-volatile variables, realtime
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579 clock, and platform reset). A UEFI stub is also provided to
580 allow the kernel to be booted as an EFI application. This
581 is only useful on systems that have UEFI firmware.
f84d0275 582
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583config DMI
584 bool "Enable support for SMBIOS (DMI) tables"
585 depends on EFI
586 default y
587 help
588 This enables SMBIOS/DMI feature for systems.
589
590 This option is only useful on systems that have UEFI firmware.
591 However, even with this option, the resultant kernel should
592 continue to boot on existing non-UEFI platforms.
593
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594endmenu
595
596menu "Userspace binary formats"
597
598source "fs/Kconfig.binfmt"
599
600config COMPAT
601 bool "Kernel support for 32-bit EL0"
602 depends on !ARM64_64K_PAGES
603 select COMPAT_BINFMT_ELF
af1839eb 604 select HAVE_UID16
84b9e9b4 605 select OLD_SIGSUSPEND3
51682036 606 select COMPAT_OLD_SIGACTION
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607 help
608 This option enables support for a 32-bit EL0 running under a 64-bit
609 kernel at EL1. AArch32-specific components such as system calls,
610 the user helper functions, VFP support and the ptrace interface are
611 handled appropriately by the kernel.
612
613 If you want to execute 32-bit userspace applications, say Y.
614
615config SYSVIPC_COMPAT
616 def_bool y
617 depends on COMPAT && SYSVIPC
618
619endmenu
620
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621menu "Power management options"
622
623source "kernel/power/Kconfig"
624
625config ARCH_SUSPEND_POSSIBLE
626 def_bool y
627
628config ARM64_CPU_SUSPEND
629 def_bool PM_SLEEP
630
631endmenu
632
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633menu "CPU Power Management"
634
635source "drivers/cpuidle/Kconfig"
636
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637source "drivers/cpufreq/Kconfig"
638
639endmenu
640
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641source "net/Kconfig"
642
643source "drivers/Kconfig"
644
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645source "drivers/firmware/Kconfig"
646
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647source "fs/Kconfig"
648
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649source "arch/arm64/kvm/Kconfig"
650
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651source "arch/arm64/Kconfig.debug"
652
653source "security/Kconfig"
654
655source "crypto/Kconfig"
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656if CRYPTO
657source "arch/arm64/crypto/Kconfig"
658endif
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659
660source "lib/Kconfig"