]>
Commit | Line | Data |
---|---|---|
8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
92980405 | 3 | select ARCH_BINFMT_ELF_RANDOMIZE_PIE |
8c2c3df3 | 4 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE |
957e3fac | 5 | select ARCH_HAS_GCOV_PROFILE_ALL |
308c09f1 | 6 | select ARCH_HAS_SG_CHAIN |
1f85008e | 7 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
c63c8700 | 8 | select ARCH_USE_CMPXCHG_LOCKREF |
4badad35 | 9 | select ARCH_SUPPORTS_ATOMIC_RMW |
9170100e | 10 | select ARCH_WANT_OPTIONAL_GPIOLIB |
6212a512 | 11 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 12 | select ARCH_WANT_FRAME_POINTERS |
25c92a37 | 13 | select ARM_AMBA |
1aee5d7a | 14 | select ARM_ARCH_TIMER |
c4188edc | 15 | select ARM_GIC |
875cbf3e | 16 | select AUDIT_ARCH_COMPAT_GENERIC |
853a33ce | 17 | select ARM_GIC_V2M if PCI_MSI |
021f6537 | 18 | select ARM_GIC_V3 |
19812729 | 19 | select ARM_GIC_V3_ITS if PCI_MSI |
adace895 | 20 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 21 | select CLONE_BACKWARDS |
7ca2ef33 | 22 | select COMMON_CLK |
166936ba | 23 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 24 | select DCACHE_WORD_ACCESS |
d4932f9e | 25 | select GENERIC_ALLOCATOR |
8c2c3df3 | 26 | select GENERIC_CLOCKEVENTS |
1f85008e | 27 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
3be1a5c4 | 28 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 29 | select GENERIC_EARLY_IOREMAP |
8c2c3df3 CM |
30 | select GENERIC_IRQ_PROBE |
31 | select GENERIC_IRQ_SHOW | |
cb61f676 | 32 | select GENERIC_PCI_IOMAP |
65cd4f6c | 33 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 34 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
35 | select GENERIC_STRNCPY_FROM_USER |
36 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 37 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 38 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 39 | select HARDIRQS_SW_RESEND |
5284e1b4 | 40 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 41 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 42 | select HAVE_ARCH_BITREVERSE |
9732cafd | 43 | select HAVE_ARCH_JUMP_LABEL |
9529247d | 44 | select HAVE_ARCH_KGDB |
a1ae65b2 | 45 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 46 | select HAVE_ARCH_TRACEHOOK |
e54bcde3 | 47 | select HAVE_BPF_JIT |
af64d2aa | 48 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 49 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 50 | select HAVE_CMPXCHG_DOUBLE |
9b2a60c4 | 51 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 52 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 CM |
53 | select HAVE_DMA_API_DEBUG |
54 | select HAVE_DMA_ATTRS | |
6ac2104d | 55 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 56 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 57 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 58 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
59 | select HAVE_FUNCTION_TRACER |
60 | select HAVE_FUNCTION_GRAPH_TRACER | |
8c2c3df3 | 61 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 62 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
8c2c3df3 | 63 | select HAVE_MEMBLOCK |
55834a77 | 64 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 65 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
66 | select HAVE_PERF_REGS |
67 | select HAVE_PERF_USER_STACK_DUMP | |
5e5f6dc1 | 68 | select HAVE_RCU_TABLE_FREE |
055b1212 | 69 | select HAVE_SYSCALL_TRACEPOINTS |
8c2c3df3 | 70 | select IRQ_DOMAIN |
fea2acaa | 71 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
72 | select NO_BOOTMEM |
73 | select OF | |
74 | select OF_EARLY_FLATTREE | |
9bf14b7c | 75 | select OF_RESERVED_MEM |
8c2c3df3 | 76 | select PERF_USE_VMALLOC |
aa1e8ec1 CM |
77 | select POWER_RESET |
78 | select POWER_SUPPLY | |
8c2c3df3 CM |
79 | select RTC_LIB |
80 | select SPARSE_IRQ | |
7ac57a89 | 81 | select SYSCTL_EXCEPTION_TRACE |
6c81fe79 | 82 | select HAVE_CONTEXT_TRACKING |
8c2c3df3 CM |
83 | help |
84 | ARM 64-bit (AArch64) Linux support. | |
85 | ||
86 | config 64BIT | |
87 | def_bool y | |
88 | ||
89 | config ARCH_PHYS_ADDR_T_64BIT | |
90 | def_bool y | |
91 | ||
92 | config MMU | |
93 | def_bool y | |
94 | ||
ce816fa8 | 95 | config NO_IOPORT_MAP |
d1e6dc91 | 96 | def_bool y if !PCI |
8c2c3df3 CM |
97 | |
98 | config STACKTRACE_SUPPORT | |
99 | def_bool y | |
100 | ||
101 | config LOCKDEP_SUPPORT | |
102 | def_bool y | |
103 | ||
104 | config TRACE_IRQFLAGS_SUPPORT | |
105 | def_bool y | |
106 | ||
c209f799 | 107 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
108 | def_bool y |
109 | ||
110 | config GENERIC_HWEIGHT | |
111 | def_bool y | |
112 | ||
113 | config GENERIC_CSUM | |
114 | def_bool y | |
115 | ||
116 | config GENERIC_CALIBRATE_DELAY | |
117 | def_bool y | |
118 | ||
19e7640d | 119 | config ZONE_DMA |
8c2c3df3 CM |
120 | def_bool y |
121 | ||
29e56940 SC |
122 | config HAVE_GENERIC_RCU_GUP |
123 | def_bool y | |
124 | ||
8c2c3df3 CM |
125 | config ARCH_DMA_ADDR_T_64BIT |
126 | def_bool y | |
127 | ||
128 | config NEED_DMA_MAP_STATE | |
129 | def_bool y | |
130 | ||
131 | config NEED_SG_DMA_LENGTH | |
132 | def_bool y | |
133 | ||
134 | config SWIOTLB | |
135 | def_bool y | |
136 | ||
137 | config IOMMU_HELPER | |
138 | def_bool SWIOTLB | |
139 | ||
4cfb3613 AB |
140 | config KERNEL_MODE_NEON |
141 | def_bool y | |
142 | ||
92cc15fc RH |
143 | config FIX_EARLYCON_MEM |
144 | def_bool y | |
145 | ||
8c2c3df3 CM |
146 | source "init/Kconfig" |
147 | ||
148 | source "kernel/Kconfig.freezer" | |
149 | ||
1ae90e79 CM |
150 | menu "Platform selection" |
151 | ||
6f56eef1 AA |
152 | config ARCH_EXYNOS |
153 | bool | |
154 | help | |
155 | This enables support for Samsung Exynos SoC family | |
156 | ||
157 | config ARCH_EXYNOS7 | |
158 | bool "ARMv8 based Samsung Exynos7" | |
159 | select ARCH_EXYNOS | |
160 | select COMMON_CLK_SAMSUNG | |
161 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
162 | select HAVE_S3C_RTC if RTC_CLASS | |
163 | select PINCTRL | |
164 | select PINCTRL_EXYNOS | |
165 | ||
166 | help | |
167 | This enables support for Samsung Exynos7 SoC family | |
168 | ||
5118a6a3 OJ |
169 | config ARCH_FSL_LS2085A |
170 | bool "Freescale LS2085A SOC" | |
171 | help | |
172 | This enables support for Freescale LS2085A SOC. | |
173 | ||
4727a6f6 EH |
174 | config ARCH_MEDIATEK |
175 | bool "Mediatek MT65xx & MT81xx ARMv8 SoC" | |
176 | select ARM_GIC | |
177 | help | |
178 | Support for Mediatek MT65xx & MT81xx ARMv8 SoCs | |
179 | ||
41904360 SS |
180 | config ARCH_SEATTLE |
181 | bool "AMD Seattle SoC Family" | |
182 | help | |
183 | This enables support for AMD Seattle SOC Family | |
184 | ||
d035fdfa PW |
185 | config ARCH_TEGRA |
186 | bool "NVIDIA Tegra SoC Family" | |
187 | select ARCH_HAS_RESET_CONTROLLER | |
188 | select ARCH_REQUIRE_GPIOLIB | |
189 | select CLKDEV_LOOKUP | |
190 | select CLKSRC_MMIO | |
191 | select CLKSRC_OF | |
192 | select GENERIC_CLOCKEVENTS | |
193 | select HAVE_CLK | |
d035fdfa PW |
194 | select PINCTRL |
195 | select RESET_CONTROLLER | |
196 | help | |
197 | This enables support for the NVIDIA Tegra SoC family. | |
198 | ||
199 | config ARCH_TEGRA_132_SOC | |
200 | bool "NVIDIA Tegra132 SoC" | |
201 | depends on ARCH_TEGRA | |
202 | select PINCTRL_TEGRA124 | |
d035fdfa PW |
203 | select USB_ULPI if USB_PHY |
204 | select USB_ULPI_VIEWPORT if USB_PHY | |
205 | help | |
206 | Enable support for NVIDIA Tegra132 SoC, based on the Denver | |
207 | ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, | |
208 | but contains an NVIDIA Denver CPU complex in place of | |
209 | Tegra124's "4+1" Cortex-A15 CPU complex. | |
210 | ||
28f7420d RMC |
211 | config ARCH_THUNDER |
212 | bool "Cavium Inc. Thunder SoC Family" | |
213 | help | |
214 | This enables support for Cavium's Thunder Family of SoCs. | |
215 | ||
1ae90e79 CM |
216 | config ARCH_VEXPRESS |
217 | bool "ARMv8 software model (Versatile Express)" | |
218 | select ARCH_REQUIRE_GPIOLIB | |
219 | select COMMON_CLK_VERSATILE | |
aa1e8ec1 | 220 | select POWER_RESET_VEXPRESS |
1ae90e79 CM |
221 | select VEXPRESS_CONFIG |
222 | help | |
223 | This enables support for the ARMv8 software model (Versatile | |
224 | Express). | |
8c2c3df3 | 225 | |
15942853 VK |
226 | config ARCH_XGENE |
227 | bool "AppliedMicro X-Gene SOC Family" | |
228 | help | |
229 | This enables support for AppliedMicro X-Gene SOC Family | |
230 | ||
8c2c3df3 CM |
231 | endmenu |
232 | ||
233 | menu "Bus support" | |
234 | ||
d1e6dc91 LD |
235 | config PCI |
236 | bool "PCI support" | |
237 | help | |
238 | This feature enables support for PCI bus system. If you say Y | |
239 | here, the kernel will include drivers and infrastructure code | |
240 | to support PCI bus devices. | |
241 | ||
242 | config PCI_DOMAINS | |
243 | def_bool PCI | |
244 | ||
245 | config PCI_DOMAINS_GENERIC | |
246 | def_bool PCI | |
247 | ||
248 | config PCI_SYSCALL | |
249 | def_bool PCI | |
250 | ||
251 | source "drivers/pci/Kconfig" | |
252 | source "drivers/pci/pcie/Kconfig" | |
253 | source "drivers/pci/hotplug/Kconfig" | |
254 | ||
8c2c3df3 CM |
255 | endmenu |
256 | ||
257 | menu "Kernel Features" | |
258 | ||
c0a01b84 AP |
259 | menu "ARM errata workarounds via the alternatives framework" |
260 | ||
261 | config ARM64_ERRATUM_826319 | |
262 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
263 | default y | |
264 | help | |
265 | This option adds an alternative code sequence to work around ARM | |
266 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
267 | AXI master interface and an L2 cache. | |
268 | ||
269 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
270 | and is unable to accept a certain write via this interface, it will | |
271 | not progress on read data presented on the read data channel and the | |
272 | system can deadlock. | |
273 | ||
274 | The workaround promotes data cache clean instructions to | |
275 | data cache clean-and-invalidate. | |
276 | Please note that this does not necessarily enable the workaround, | |
277 | as it depends on the alternative framework, which will only patch | |
278 | the kernel if an affected CPU is detected. | |
279 | ||
280 | If unsure, say Y. | |
281 | ||
282 | config ARM64_ERRATUM_827319 | |
283 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
284 | default y | |
285 | help | |
286 | This option adds an alternative code sequence to work around ARM | |
287 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
288 | master interface and an L2 cache. | |
289 | ||
290 | Under certain conditions this erratum can cause a clean line eviction | |
291 | to occur at the same time as another transaction to the same address | |
292 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
293 | interconnect reorders the two transactions. | |
294 | ||
295 | The workaround promotes data cache clean instructions to | |
296 | data cache clean-and-invalidate. | |
297 | Please note that this does not necessarily enable the workaround, | |
298 | as it depends on the alternative framework, which will only patch | |
299 | the kernel if an affected CPU is detected. | |
300 | ||
301 | If unsure, say Y. | |
302 | ||
303 | config ARM64_ERRATUM_824069 | |
304 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
305 | default y | |
306 | help | |
307 | This option adds an alternative code sequence to work around ARM | |
308 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
309 | to a coherent interconnect. | |
310 | ||
311 | If a Cortex-A53 processor is executing a store or prefetch for | |
312 | write instruction at the same time as a processor in another | |
313 | cluster is executing a cache maintenance operation to the same | |
314 | address, then this erratum might cause a clean cache line to be | |
315 | incorrectly marked as dirty. | |
316 | ||
317 | The workaround promotes data cache clean instructions to | |
318 | data cache clean-and-invalidate. | |
319 | Please note that this option does not necessarily enable the | |
320 | workaround, as it depends on the alternative framework, which will | |
321 | only patch the kernel if an affected CPU is detected. | |
322 | ||
323 | If unsure, say Y. | |
324 | ||
325 | config ARM64_ERRATUM_819472 | |
326 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
327 | default y | |
328 | help | |
329 | This option adds an alternative code sequence to work around ARM | |
330 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
331 | present when it is connected to a coherent interconnect. | |
332 | ||
333 | If the processor is executing a load and store exclusive sequence at | |
334 | the same time as a processor in another cluster is executing a cache | |
335 | maintenance operation to the same address, then this erratum might | |
336 | cause data corruption. | |
337 | ||
338 | The workaround promotes data cache clean instructions to | |
339 | data cache clean-and-invalidate. | |
340 | Please note that this does not necessarily enable the workaround, | |
341 | as it depends on the alternative framework, which will only patch | |
342 | the kernel if an affected CPU is detected. | |
343 | ||
344 | If unsure, say Y. | |
345 | ||
346 | config ARM64_ERRATUM_832075 | |
347 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
348 | default y | |
349 | help | |
350 | This option adds an alternative code sequence to work around ARM | |
351 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
352 | ||
353 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
354 | instructions to Write-Back memory are mixed with Device loads. | |
355 | ||
356 | The workaround is to promote device loads to use Load-Acquire | |
357 | semantics. | |
358 | Please note that this does not necessarily enable the workaround, | |
359 | as it depends on the alternative framework, which will only patch | |
360 | the kernel if an affected CPU is detected. | |
361 | ||
362 | If unsure, say Y. | |
363 | ||
364 | endmenu | |
365 | ||
366 | ||
e41ceed0 JL |
367 | choice |
368 | prompt "Page size" | |
369 | default ARM64_4K_PAGES | |
370 | help | |
371 | Page size (translation granule) configuration. | |
372 | ||
373 | config ARM64_4K_PAGES | |
374 | bool "4KB" | |
375 | help | |
376 | This feature enables 4KB pages support. | |
377 | ||
8c2c3df3 | 378 | config ARM64_64K_PAGES |
e41ceed0 | 379 | bool "64KB" |
8c2c3df3 CM |
380 | help |
381 | This feature enables 64KB pages support (4KB by default) | |
382 | allowing only two levels of page tables and faster TLB | |
383 | look-up. AArch32 emulation is not available when this feature | |
384 | is enabled. | |
385 | ||
e41ceed0 JL |
386 | endchoice |
387 | ||
388 | choice | |
389 | prompt "Virtual address space size" | |
390 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
391 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES | |
392 | help | |
393 | Allows choosing one of multiple possible virtual address | |
394 | space sizes. The level of translation table is determined by | |
395 | a combination of page size and virtual address space size. | |
396 | ||
397 | config ARM64_VA_BITS_39 | |
398 | bool "39-bit" | |
399 | depends on ARM64_4K_PAGES | |
400 | ||
401 | config ARM64_VA_BITS_42 | |
402 | bool "42-bit" | |
403 | depends on ARM64_64K_PAGES | |
404 | ||
c79b954b JL |
405 | config ARM64_VA_BITS_48 |
406 | bool "48-bit" | |
c79b954b | 407 | |
e41ceed0 JL |
408 | endchoice |
409 | ||
410 | config ARM64_VA_BITS | |
411 | int | |
412 | default 39 if ARM64_VA_BITS_39 | |
413 | default 42 if ARM64_VA_BITS_42 | |
c79b954b | 414 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 415 | |
abe669d7 CM |
416 | config ARM64_PGTABLE_LEVELS |
417 | int | |
418 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 | |
383c2799 | 419 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 |
abe669d7 CM |
420 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 |
421 | default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48 | |
c79b954b | 422 | |
a872013d WD |
423 | config CPU_BIG_ENDIAN |
424 | bool "Build big-endian kernel" | |
425 | help | |
426 | Say Y if you plan on running a kernel in big-endian mode. | |
427 | ||
8c2c3df3 CM |
428 | config SMP |
429 | bool "Symmetric Multi-Processing" | |
8c2c3df3 CM |
430 | help |
431 | This enables support for systems with more than one CPU. If | |
432 | you say N here, the kernel will run on single and | |
433 | multiprocessor machines, but will use only one CPU of a | |
434 | multiprocessor machine. If you say Y here, the kernel will run | |
435 | on many, but not all, single processor machines. On a single | |
436 | processor machine, the kernel will run faster if you say N | |
437 | here. | |
438 | ||
439 | If you don't know what to do here, say N. | |
440 | ||
f6e763b9 MB |
441 | config SCHED_MC |
442 | bool "Multi-core scheduler support" | |
443 | depends on SMP | |
444 | help | |
445 | Multi-core scheduler support improves the CPU scheduler's decision | |
446 | making when dealing with multi-core CPU chips at a cost of slightly | |
447 | increased overhead in some places. If unsure say N here. | |
448 | ||
449 | config SCHED_SMT | |
450 | bool "SMT scheduler support" | |
451 | depends on SMP | |
452 | help | |
453 | Improves the CPU scheduler's decision making when dealing with | |
454 | MultiThreading at a cost of slightly increased overhead in some | |
455 | places. If unsure say N here. | |
456 | ||
8c2c3df3 | 457 | config NR_CPUS |
e3672649 RR |
458 | int "Maximum number of CPUs (2-64)" |
459 | range 2 64 | |
8c2c3df3 | 460 | depends on SMP |
15942853 | 461 | # These have to remain sorted largest to smallest |
e3672649 | 462 | default "64" |
8c2c3df3 | 463 | |
9327e2c6 MR |
464 | config HOTPLUG_CPU |
465 | bool "Support for hot-pluggable CPUs" | |
466 | depends on SMP | |
467 | help | |
468 | Say Y here to experiment with turning CPUs off and on. CPUs | |
469 | can be controlled through /sys/devices/system/cpu. | |
470 | ||
8c2c3df3 CM |
471 | source kernel/Kconfig.preempt |
472 | ||
473 | config HZ | |
474 | int | |
475 | default 100 | |
476 | ||
477 | config ARCH_HAS_HOLES_MEMORYMODEL | |
478 | def_bool y if SPARSEMEM | |
479 | ||
480 | config ARCH_SPARSEMEM_ENABLE | |
481 | def_bool y | |
482 | select SPARSEMEM_VMEMMAP_ENABLE | |
483 | ||
484 | config ARCH_SPARSEMEM_DEFAULT | |
485 | def_bool ARCH_SPARSEMEM_ENABLE | |
486 | ||
487 | config ARCH_SELECT_MEMORY_MODEL | |
488 | def_bool ARCH_SPARSEMEM_ENABLE | |
489 | ||
490 | config HAVE_ARCH_PFN_VALID | |
491 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
492 | ||
493 | config HW_PERF_EVENTS | |
494 | bool "Enable hardware performance counter support for perf events" | |
495 | depends on PERF_EVENTS | |
496 | default y | |
497 | help | |
498 | Enable hardware performance counter support for perf events. If | |
499 | disabled, perf events will use software events only. | |
500 | ||
084bd298 SC |
501 | config SYS_SUPPORTS_HUGETLBFS |
502 | def_bool y | |
503 | ||
504 | config ARCH_WANT_GENERAL_HUGETLB | |
505 | def_bool y | |
506 | ||
507 | config ARCH_WANT_HUGE_PMD_SHARE | |
508 | def_bool y if !ARM64_64K_PAGES | |
509 | ||
af074848 SC |
510 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
511 | def_bool y | |
512 | ||
a41dc0e8 CM |
513 | config ARCH_HAS_CACHE_LINE_SIZE |
514 | def_bool y | |
515 | ||
8c2c3df3 CM |
516 | source "mm/Kconfig" |
517 | ||
a1ae65b2 AT |
518 | config SECCOMP |
519 | bool "Enable seccomp to safely compute untrusted bytecode" | |
520 | ---help--- | |
521 | This kernel feature is useful for number crunching applications | |
522 | that may need to compute untrusted bytecode during their | |
523 | execution. By using pipes or other transports made available to | |
524 | the process as file descriptors supporting the read/write | |
525 | syscalls, it's possible to isolate those applications in | |
526 | their own address space using seccomp. Once seccomp is | |
527 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
528 | and the task is only allowed to execute a few safe syscalls | |
529 | defined by each seccomp mode. | |
530 | ||
aa42aa13 SS |
531 | config XEN_DOM0 |
532 | def_bool y | |
533 | depends on XEN | |
534 | ||
535 | config XEN | |
c2ba1f7d | 536 | bool "Xen guest support on ARM64" |
aa42aa13 | 537 | depends on ARM64 && OF |
83862ccf | 538 | select SWIOTLB_XEN |
aa42aa13 SS |
539 | help |
540 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
541 | ||
d03bb145 SC |
542 | config FORCE_MAX_ZONEORDER |
543 | int | |
544 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
545 | default "11" | |
546 | ||
1b907f46 WD |
547 | menuconfig ARMV8_DEPRECATED |
548 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
549 | depends on COMPAT | |
550 | help | |
551 | Legacy software support may require certain instructions | |
552 | that have been deprecated or obsoleted in the architecture. | |
553 | ||
554 | Enable this config to enable selective emulation of these | |
555 | features. | |
556 | ||
557 | If unsure, say Y | |
558 | ||
559 | if ARMV8_DEPRECATED | |
560 | ||
561 | config SWP_EMULATION | |
562 | bool "Emulate SWP/SWPB instructions" | |
563 | help | |
564 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
565 | they are always undefined. Say Y here to enable software | |
566 | emulation of these instructions for userspace using LDXR/STXR. | |
567 | ||
568 | In some older versions of glibc [<=2.8] SWP is used during futex | |
569 | trylock() operations with the assumption that the code will not | |
570 | be preempted. This invalid assumption may be more likely to fail | |
571 | with SWP emulation enabled, leading to deadlock of the user | |
572 | application. | |
573 | ||
574 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
575 | on an external transaction monitoring block called a global | |
576 | monitor to maintain update atomicity. If your system does not | |
577 | implement a global monitor, this option can cause programs that | |
578 | perform SWP operations to uncached memory to deadlock. | |
579 | ||
580 | If unsure, say Y | |
581 | ||
582 | config CP15_BARRIER_EMULATION | |
583 | bool "Emulate CP15 Barrier instructions" | |
584 | help | |
585 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
586 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
587 | strongly recommended to use the ISB, DSB, and DMB | |
588 | instructions instead. | |
589 | ||
590 | Say Y here to enable software emulation of these | |
591 | instructions for AArch32 userspace code. When this option is | |
592 | enabled, CP15 barrier usage is traced which can help | |
593 | identify software that needs updating. | |
594 | ||
595 | If unsure, say Y | |
596 | ||
2d888f48 SP |
597 | config SETEND_EMULATION |
598 | bool "Emulate SETEND instruction" | |
599 | help | |
600 | The SETEND instruction alters the data-endianness of the | |
601 | AArch32 EL0, and is deprecated in ARMv8. | |
602 | ||
603 | Say Y here to enable software emulation of the instruction | |
604 | for AArch32 userspace code. | |
605 | ||
606 | Note: All the cpus on the system must have mixed endian support at EL0 | |
607 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
608 | endian - is hotplugged in after this feature has been enabled, there could | |
609 | be unexpected results in the applications. | |
610 | ||
611 | If unsure, say Y | |
1b907f46 WD |
612 | endif |
613 | ||
8c2c3df3 CM |
614 | endmenu |
615 | ||
616 | menu "Boot options" | |
617 | ||
618 | config CMDLINE | |
619 | string "Default kernel command string" | |
620 | default "" | |
621 | help | |
622 | Provide a set of default command-line options at build time by | |
623 | entering them here. As a minimum, you should specify the the | |
624 | root device (e.g. root=/dev/nfs). | |
625 | ||
626 | config CMDLINE_FORCE | |
627 | bool "Always use the default kernel command string" | |
628 | help | |
629 | Always use the default kernel command string, even if the boot | |
630 | loader passes other arguments to the kernel. | |
631 | This is useful if you cannot or don't want to change the | |
632 | command-line options your boot loader passes to the kernel. | |
633 | ||
f4f75ad5 AB |
634 | config EFI_STUB |
635 | bool | |
636 | ||
f84d0275 MS |
637 | config EFI |
638 | bool "UEFI runtime support" | |
639 | depends on OF && !CPU_BIG_ENDIAN | |
640 | select LIBFDT | |
641 | select UCS2_STRING | |
642 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 643 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
644 | select EFI_STUB |
645 | select EFI_ARMSTUB | |
f84d0275 MS |
646 | default y |
647 | help | |
648 | This option provides support for runtime services provided | |
649 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
650 | clock, and platform reset). A UEFI stub is also provided to |
651 | allow the kernel to be booted as an EFI application. This | |
652 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 653 | |
d1ae8c00 YL |
654 | config DMI |
655 | bool "Enable support for SMBIOS (DMI) tables" | |
656 | depends on EFI | |
657 | default y | |
658 | help | |
659 | This enables SMBIOS/DMI feature for systems. | |
660 | ||
661 | This option is only useful on systems that have UEFI firmware. | |
662 | However, even with this option, the resultant kernel should | |
663 | continue to boot on existing non-UEFI platforms. | |
664 | ||
8c2c3df3 CM |
665 | endmenu |
666 | ||
667 | menu "Userspace binary formats" | |
668 | ||
669 | source "fs/Kconfig.binfmt" | |
670 | ||
671 | config COMPAT | |
672 | bool "Kernel support for 32-bit EL0" | |
673 | depends on !ARM64_64K_PAGES | |
674 | select COMPAT_BINFMT_ELF | |
af1839eb | 675 | select HAVE_UID16 |
84b9e9b4 | 676 | select OLD_SIGSUSPEND3 |
51682036 | 677 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
678 | help |
679 | This option enables support for a 32-bit EL0 running under a 64-bit | |
680 | kernel at EL1. AArch32-specific components such as system calls, | |
681 | the user helper functions, VFP support and the ptrace interface are | |
682 | handled appropriately by the kernel. | |
683 | ||
684 | If you want to execute 32-bit userspace applications, say Y. | |
685 | ||
686 | config SYSVIPC_COMPAT | |
687 | def_bool y | |
688 | depends on COMPAT && SYSVIPC | |
689 | ||
690 | endmenu | |
691 | ||
166936ba LP |
692 | menu "Power management options" |
693 | ||
694 | source "kernel/power/Kconfig" | |
695 | ||
696 | config ARCH_SUSPEND_POSSIBLE | |
697 | def_bool y | |
698 | ||
166936ba LP |
699 | endmenu |
700 | ||
1307220d LP |
701 | menu "CPU Power Management" |
702 | ||
703 | source "drivers/cpuidle/Kconfig" | |
704 | ||
52e7e816 RH |
705 | source "drivers/cpufreq/Kconfig" |
706 | ||
707 | endmenu | |
708 | ||
8c2c3df3 CM |
709 | source "net/Kconfig" |
710 | ||
711 | source "drivers/Kconfig" | |
712 | ||
f84d0275 MS |
713 | source "drivers/firmware/Kconfig" |
714 | ||
8c2c3df3 CM |
715 | source "fs/Kconfig" |
716 | ||
c3eb5b14 MZ |
717 | source "arch/arm64/kvm/Kconfig" |
718 | ||
8c2c3df3 CM |
719 | source "arch/arm64/Kconfig.debug" |
720 | ||
721 | source "security/Kconfig" | |
722 | ||
723 | source "crypto/Kconfig" | |
2c98833a AB |
724 | if CRYPTO |
725 | source "arch/arm64/crypto/Kconfig" | |
726 | endif | |
8c2c3df3 CM |
727 | |
728 | source "lib/Kconfig" |