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Commit | Line | Data |
---|---|---|
8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
b6197b93 | 3 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 4 | select ACPI_GENERIC_GSI if ACPI |
6933de0c | 5 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
0cb0786b | 6 | select ACPI_MCFG if ACPI |
888125a7 | 7 | select ACPI_SPCR_TABLE if ACPI |
1d8f51d4 | 8 | select ARCH_CLOCKSOURCE_DATA |
ec6d06ef | 9 | select ARCH_HAS_DEBUG_VIRTUAL |
21266be9 | 10 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
38b04a74 | 11 | select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI |
2b68f6ca | 12 | select ARCH_HAS_ELF_RANDOMIZE |
957e3fac | 13 | select ARCH_HAS_GCOV_PROFILE_ALL |
14f09910 | 14 | select ARCH_HAS_GIGANTIC_PAGE |
5e4c7549 | 15 | select ARCH_HAS_KCOV |
308c09f1 | 16 | select ARCH_HAS_SG_CHAIN |
1f85008e | 17 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
c63c8700 | 18 | select ARCH_USE_CMPXCHG_LOCKREF |
4badad35 | 19 | select ARCH_SUPPORTS_ATOMIC_RMW |
56166230 | 20 | select ARCH_SUPPORTS_NUMA_BALANCING |
6212a512 | 21 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 22 | select ARCH_WANT_FRAME_POINTERS |
f0b7f8a4 | 23 | select ARCH_HAS_UBSAN_SANITIZE_ALL |
25c92a37 | 24 | select ARM_AMBA |
1aee5d7a | 25 | select ARM_ARCH_TIMER |
c4188edc | 26 | select ARM_GIC |
875cbf3e | 27 | select AUDIT_ARCH_COMPAT_GENERIC |
3ee80364 | 28 | select ARM_GIC_V2M if PCI |
021f6537 | 29 | select ARM_GIC_V3 |
3ee80364 | 30 | select ARM_GIC_V3_ITS if PCI |
bff60792 | 31 | select ARM_PSCI_FW |
adace895 | 32 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 33 | select CLONE_BACKWARDS |
7ca2ef33 | 34 | select COMMON_CLK |
166936ba | 35 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 36 | select DCACHE_WORD_ACCESS |
ef37566c | 37 | select EDAC_SUPPORT |
2f34f173 | 38 | select FRAME_POINTER |
d4932f9e | 39 | select GENERIC_ALLOCATOR |
8c2c3df3 | 40 | select GENERIC_CLOCKEVENTS |
4b3dc967 | 41 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 42 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 43 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 44 | select GENERIC_IDLE_POLL_SETUP |
8c2c3df3 CM |
45 | select GENERIC_IRQ_PROBE |
46 | select GENERIC_IRQ_SHOW | |
6544e67b | 47 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 48 | select GENERIC_PCI_IOMAP |
65cd4f6c | 49 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 50 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
51 | select GENERIC_STRNCPY_FROM_USER |
52 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 53 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 54 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 55 | select HARDIRQS_SW_RESEND |
9f9a35a7 | 56 | select HAVE_ACPI_APEI if (ACPI && EFI) |
5284e1b4 | 57 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 58 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 59 | select HAVE_ARCH_BITREVERSE |
faf5b63e | 60 | select HAVE_ARCH_HARDENED_USERCOPY |
324420bf | 61 | select HAVE_ARCH_HUGE_VMAP |
9732cafd | 62 | select HAVE_ARCH_JUMP_LABEL |
f1b9032f | 63 | select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) |
9529247d | 64 | select HAVE_ARCH_KGDB |
8f0d3aa9 DC |
65 | select HAVE_ARCH_MMAP_RND_BITS |
66 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT | |
a1ae65b2 | 67 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 68 | select HAVE_ARCH_TRACEHOOK |
8ee70879 YS |
69 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE |
70 | select HAVE_ARM_SMCCC | |
6077776b | 71 | select HAVE_EBPF_JIT |
af64d2aa | 72 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 73 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 74 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 75 | select HAVE_CMPXCHG_LOCAL |
8ee70879 | 76 | select HAVE_CONTEXT_TRACKING |
9b2a60c4 | 77 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 78 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 | 79 | select HAVE_DMA_API_DEBUG |
6ac2104d | 80 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 81 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 82 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 83 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
84 | select HAVE_FUNCTION_TRACER |
85 | select HAVE_FUNCTION_GRAPH_TRACER | |
6b90bd4b | 86 | select HAVE_GCC_PLUGINS |
8c2c3df3 | 87 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 88 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
24da208d | 89 | select HAVE_IRQ_TIME_ACCOUNTING |
8c2c3df3 | 90 | select HAVE_MEMBLOCK |
1a2db300 | 91 | select HAVE_MEMBLOCK_NODE_MAP if NUMA |
55834a77 | 92 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 93 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
94 | select HAVE_PERF_REGS |
95 | select HAVE_PERF_USER_STACK_DUMP | |
0a8ea52c | 96 | select HAVE_REGS_AND_STACK_ACCESS_API |
5e5f6dc1 | 97 | select HAVE_RCU_TABLE_FREE |
055b1212 | 98 | select HAVE_SYSCALL_TRACEPOINTS |
2dd0e8d2 | 99 | select HAVE_KPROBES |
fcfd708b | 100 | select HAVE_KRETPROBES if HAVE_KPROBES |
876945db | 101 | select IOMMU_DMA if IOMMU_SUPPORT |
8c2c3df3 | 102 | select IRQ_DOMAIN |
e8557d1f | 103 | select IRQ_FORCED_THREADING |
fea2acaa | 104 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
105 | select NO_BOOTMEM |
106 | select OF | |
107 | select OF_EARLY_FLATTREE | |
9bf14b7c | 108 | select OF_RESERVED_MEM |
0cb0786b | 109 | select PCI_ECAM if ACPI |
aa1e8ec1 CM |
110 | select POWER_RESET |
111 | select POWER_SUPPLY | |
8c2c3df3 | 112 | select SPARSE_IRQ |
7ac57a89 | 113 | select SYSCTL_EXCEPTION_TRACE |
c02433dd | 114 | select THREAD_INFO_IN_TASK |
8c2c3df3 CM |
115 | help |
116 | ARM 64-bit (AArch64) Linux support. | |
117 | ||
118 | config 64BIT | |
119 | def_bool y | |
120 | ||
121 | config ARCH_PHYS_ADDR_T_64BIT | |
122 | def_bool y | |
123 | ||
124 | config MMU | |
125 | def_bool y | |
126 | ||
40982fd6 MR |
127 | config DEBUG_RODATA |
128 | def_bool y | |
129 | ||
030c4d24 MR |
130 | config ARM64_PAGE_SHIFT |
131 | int | |
132 | default 16 if ARM64_64K_PAGES | |
133 | default 14 if ARM64_16K_PAGES | |
134 | default 12 | |
135 | ||
136 | config ARM64_CONT_SHIFT | |
137 | int | |
138 | default 5 if ARM64_64K_PAGES | |
139 | default 7 if ARM64_16K_PAGES | |
140 | default 4 | |
141 | ||
8f0d3aa9 DC |
142 | config ARCH_MMAP_RND_BITS_MIN |
143 | default 14 if ARM64_64K_PAGES | |
144 | default 16 if ARM64_16K_PAGES | |
145 | default 18 | |
146 | ||
147 | # max bits determined by the following formula: | |
148 | # VA_BITS - PAGE_SHIFT - 3 | |
149 | config ARCH_MMAP_RND_BITS_MAX | |
150 | default 19 if ARM64_VA_BITS=36 | |
151 | default 24 if ARM64_VA_BITS=39 | |
152 | default 27 if ARM64_VA_BITS=42 | |
153 | default 30 if ARM64_VA_BITS=47 | |
154 | default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES | |
155 | default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES | |
156 | default 33 if ARM64_VA_BITS=48 | |
157 | default 14 if ARM64_64K_PAGES | |
158 | default 16 if ARM64_16K_PAGES | |
159 | default 18 | |
160 | ||
161 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
162 | default 7 if ARM64_64K_PAGES | |
163 | default 9 if ARM64_16K_PAGES | |
164 | default 11 | |
165 | ||
166 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
167 | default 16 | |
168 | ||
ce816fa8 | 169 | config NO_IOPORT_MAP |
d1e6dc91 | 170 | def_bool y if !PCI |
8c2c3df3 CM |
171 | |
172 | config STACKTRACE_SUPPORT | |
173 | def_bool y | |
174 | ||
bf0c4e04 JVS |
175 | config ILLEGAL_POINTER_VALUE |
176 | hex | |
177 | default 0xdead000000000000 | |
178 | ||
8c2c3df3 CM |
179 | config LOCKDEP_SUPPORT |
180 | def_bool y | |
181 | ||
182 | config TRACE_IRQFLAGS_SUPPORT | |
183 | def_bool y | |
184 | ||
c209f799 | 185 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
186 | def_bool y |
187 | ||
9fb7410f DM |
188 | config GENERIC_BUG |
189 | def_bool y | |
190 | depends on BUG | |
191 | ||
192 | config GENERIC_BUG_RELATIVE_POINTERS | |
193 | def_bool y | |
194 | depends on GENERIC_BUG | |
195 | ||
8c2c3df3 CM |
196 | config GENERIC_HWEIGHT |
197 | def_bool y | |
198 | ||
199 | config GENERIC_CSUM | |
200 | def_bool y | |
201 | ||
202 | config GENERIC_CALIBRATE_DELAY | |
203 | def_bool y | |
204 | ||
19e7640d | 205 | config ZONE_DMA |
8c2c3df3 CM |
206 | def_bool y |
207 | ||
29e56940 SC |
208 | config HAVE_GENERIC_RCU_GUP |
209 | def_bool y | |
210 | ||
8c2c3df3 CM |
211 | config ARCH_DMA_ADDR_T_64BIT |
212 | def_bool y | |
213 | ||
214 | config NEED_DMA_MAP_STATE | |
215 | def_bool y | |
216 | ||
217 | config NEED_SG_DMA_LENGTH | |
218 | def_bool y | |
219 | ||
4b3dc967 WD |
220 | config SMP |
221 | def_bool y | |
222 | ||
8c2c3df3 CM |
223 | config SWIOTLB |
224 | def_bool y | |
225 | ||
226 | config IOMMU_HELPER | |
227 | def_bool SWIOTLB | |
228 | ||
4cfb3613 AB |
229 | config KERNEL_MODE_NEON |
230 | def_bool y | |
231 | ||
92cc15fc RH |
232 | config FIX_EARLYCON_MEM |
233 | def_bool y | |
234 | ||
9f25e6ad KS |
235 | config PGTABLE_LEVELS |
236 | int | |
21539939 | 237 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad KS |
238 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
239 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
240 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
44eaacf1 SP |
241 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
242 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 243 | |
9842ceae PA |
244 | config ARCH_SUPPORTS_UPROBES |
245 | def_bool y | |
246 | ||
8c2c3df3 CM |
247 | source "init/Kconfig" |
248 | ||
249 | source "kernel/Kconfig.freezer" | |
250 | ||
6a377491 | 251 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 CM |
252 | |
253 | menu "Bus support" | |
254 | ||
d1e6dc91 LD |
255 | config PCI |
256 | bool "PCI support" | |
257 | help | |
258 | This feature enables support for PCI bus system. If you say Y | |
259 | here, the kernel will include drivers and infrastructure code | |
260 | to support PCI bus devices. | |
261 | ||
262 | config PCI_DOMAINS | |
263 | def_bool PCI | |
264 | ||
265 | config PCI_DOMAINS_GENERIC | |
266 | def_bool PCI | |
267 | ||
268 | config PCI_SYSCALL | |
269 | def_bool PCI | |
270 | ||
271 | source "drivers/pci/Kconfig" | |
d1e6dc91 | 272 | |
8c2c3df3 CM |
273 | endmenu |
274 | ||
275 | menu "Kernel Features" | |
276 | ||
c0a01b84 AP |
277 | menu "ARM errata workarounds via the alternatives framework" |
278 | ||
279 | config ARM64_ERRATUM_826319 | |
280 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
281 | default y | |
282 | help | |
283 | This option adds an alternative code sequence to work around ARM | |
284 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
285 | AXI master interface and an L2 cache. | |
286 | ||
287 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
288 | and is unable to accept a certain write via this interface, it will | |
289 | not progress on read data presented on the read data channel and the | |
290 | system can deadlock. | |
291 | ||
292 | The workaround promotes data cache clean instructions to | |
293 | data cache clean-and-invalidate. | |
294 | Please note that this does not necessarily enable the workaround, | |
295 | as it depends on the alternative framework, which will only patch | |
296 | the kernel if an affected CPU is detected. | |
297 | ||
298 | If unsure, say Y. | |
299 | ||
300 | config ARM64_ERRATUM_827319 | |
301 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
302 | default y | |
303 | help | |
304 | This option adds an alternative code sequence to work around ARM | |
305 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
306 | master interface and an L2 cache. | |
307 | ||
308 | Under certain conditions this erratum can cause a clean line eviction | |
309 | to occur at the same time as another transaction to the same address | |
310 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
311 | interconnect reorders the two transactions. | |
312 | ||
313 | The workaround promotes data cache clean instructions to | |
314 | data cache clean-and-invalidate. | |
315 | Please note that this does not necessarily enable the workaround, | |
316 | as it depends on the alternative framework, which will only patch | |
317 | the kernel if an affected CPU is detected. | |
318 | ||
319 | If unsure, say Y. | |
320 | ||
321 | config ARM64_ERRATUM_824069 | |
322 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
323 | default y | |
324 | help | |
325 | This option adds an alternative code sequence to work around ARM | |
326 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
327 | to a coherent interconnect. | |
328 | ||
329 | If a Cortex-A53 processor is executing a store or prefetch for | |
330 | write instruction at the same time as a processor in another | |
331 | cluster is executing a cache maintenance operation to the same | |
332 | address, then this erratum might cause a clean cache line to be | |
333 | incorrectly marked as dirty. | |
334 | ||
335 | The workaround promotes data cache clean instructions to | |
336 | data cache clean-and-invalidate. | |
337 | Please note that this option does not necessarily enable the | |
338 | workaround, as it depends on the alternative framework, which will | |
339 | only patch the kernel if an affected CPU is detected. | |
340 | ||
341 | If unsure, say Y. | |
342 | ||
343 | config ARM64_ERRATUM_819472 | |
344 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
345 | default y | |
346 | help | |
347 | This option adds an alternative code sequence to work around ARM | |
348 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
349 | present when it is connected to a coherent interconnect. | |
350 | ||
351 | If the processor is executing a load and store exclusive sequence at | |
352 | the same time as a processor in another cluster is executing a cache | |
353 | maintenance operation to the same address, then this erratum might | |
354 | cause data corruption. | |
355 | ||
356 | The workaround promotes data cache clean instructions to | |
357 | data cache clean-and-invalidate. | |
358 | Please note that this does not necessarily enable the workaround, | |
359 | as it depends on the alternative framework, which will only patch | |
360 | the kernel if an affected CPU is detected. | |
361 | ||
362 | If unsure, say Y. | |
363 | ||
364 | config ARM64_ERRATUM_832075 | |
365 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
366 | default y | |
367 | help | |
368 | This option adds an alternative code sequence to work around ARM | |
369 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
370 | ||
371 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
372 | instructions to Write-Back memory are mixed with Device loads. | |
373 | ||
374 | The workaround is to promote device loads to use Load-Acquire | |
375 | semantics. | |
376 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
377 | as it depends on the alternative framework, which will only patch |
378 | the kernel if an affected CPU is detected. | |
379 | ||
380 | If unsure, say Y. | |
381 | ||
382 | config ARM64_ERRATUM_834220 | |
383 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" | |
384 | depends on KVM | |
385 | default y | |
386 | help | |
387 | This option adds an alternative code sequence to work around ARM | |
388 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
389 | ||
390 | Affected Cortex-A57 parts might report a Stage 2 translation | |
391 | fault as the result of a Stage 1 fault for load crossing a | |
392 | page boundary when there is a permission or device memory | |
393 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
394 | ||
395 | The workaround is to verify that the Stage 1 translation | |
396 | doesn't generate a fault before handling the Stage 2 fault. | |
397 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
398 | as it depends on the alternative framework, which will only patch |
399 | the kernel if an affected CPU is detected. | |
400 | ||
401 | If unsure, say Y. | |
402 | ||
905e8c5d WD |
403 | config ARM64_ERRATUM_845719 |
404 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
405 | depends on COMPAT | |
406 | default y | |
407 | help | |
408 | This option adds an alternative code sequence to work around ARM | |
409 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
410 | ||
411 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
412 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
413 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
414 | might return incorrect data. | |
415 | ||
416 | The workaround is to write the contextidr_el1 register on exception | |
417 | return to a 32-bit task. | |
418 | Please note that this does not necessarily enable the workaround, | |
419 | as it depends on the alternative framework, which will only patch | |
420 | the kernel if an affected CPU is detected. | |
421 | ||
422 | If unsure, say Y. | |
423 | ||
df057cc7 WD |
424 | config ARM64_ERRATUM_843419 |
425 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
df057cc7 | 426 | default y |
6ffe9923 | 427 | select ARM64_MODULE_CMODEL_LARGE if MODULES |
df057cc7 | 428 | help |
6ffe9923 WD |
429 | This option links the kernel with '--fix-cortex-a53-843419' and |
430 | builds modules using the large memory model in order to avoid the use | |
431 | of the ADRP instruction, which can cause a subsequent memory access | |
432 | to use an incorrect address on Cortex-A53 parts up to r0p4. | |
df057cc7 WD |
433 | |
434 | If unsure, say Y. | |
435 | ||
94100970 RR |
436 | config CAVIUM_ERRATUM_22375 |
437 | bool "Cavium erratum 22375, 24313" | |
438 | default y | |
439 | help | |
440 | Enable workaround for erratum 22375, 24313. | |
441 | ||
442 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
443 | with small impact affecting only ITS table allocation. | |
444 | ||
445 | erratum 22375: only alloc 8MB table size | |
446 | erratum 24313: ignore memory access type | |
447 | ||
448 | The fixes are in ITS initialization and basically ignore memory access | |
449 | type and table size provided by the TYPER and BASER registers. | |
450 | ||
451 | If unsure, say Y. | |
452 | ||
fbf8f40e GK |
453 | config CAVIUM_ERRATUM_23144 |
454 | bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" | |
455 | depends on NUMA | |
456 | default y | |
457 | help | |
458 | ITS SYNC command hang for cross node io and collections/cpu mapping. | |
459 | ||
460 | If unsure, say Y. | |
461 | ||
6d4e11c5 RR |
462 | config CAVIUM_ERRATUM_23154 |
463 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" | |
464 | default y | |
465 | help | |
466 | The gicv3 of ThunderX requires a modified version for | |
467 | reading the IAR status to ensure data synchronization | |
468 | (access to icc_iar1_el1 is not sync'ed before and after). | |
469 | ||
470 | If unsure, say Y. | |
471 | ||
104a0c02 AP |
472 | config CAVIUM_ERRATUM_27456 |
473 | bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" | |
474 | default y | |
475 | help | |
476 | On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI | |
477 | instructions may cause the icache to become corrupted if it | |
478 | contains data for a non-current ASID. The fix is to | |
479 | invalidate the icache when changing the mm context. | |
480 | ||
481 | If unsure, say Y. | |
482 | ||
d9ff80f8 CC |
483 | config QCOM_FALKOR_ERRATUM_1009 |
484 | bool "Falkor E1009: Prematurely complete a DSB after a TLBI" | |
485 | default y | |
486 | help | |
487 | On Falkor v1, the CPU may prematurely complete a DSB following a | |
488 | TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation | |
489 | one more time to fix the issue. | |
490 | ||
491 | If unsure, say Y. | |
492 | ||
c0a01b84 AP |
493 | endmenu |
494 | ||
495 | ||
e41ceed0 JL |
496 | choice |
497 | prompt "Page size" | |
498 | default ARM64_4K_PAGES | |
499 | help | |
500 | Page size (translation granule) configuration. | |
501 | ||
502 | config ARM64_4K_PAGES | |
503 | bool "4KB" | |
504 | help | |
505 | This feature enables 4KB pages support. | |
506 | ||
44eaacf1 SP |
507 | config ARM64_16K_PAGES |
508 | bool "16KB" | |
509 | help | |
510 | The system will use 16KB pages support. AArch32 emulation | |
511 | requires applications compiled with 16K (or a multiple of 16K) | |
512 | aligned segments. | |
513 | ||
8c2c3df3 | 514 | config ARM64_64K_PAGES |
e41ceed0 | 515 | bool "64KB" |
8c2c3df3 CM |
516 | help |
517 | This feature enables 64KB pages support (4KB by default) | |
518 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
519 | look-up. AArch32 emulation requires applications compiled |
520 | with 64K aligned segments. | |
8c2c3df3 | 521 | |
e41ceed0 JL |
522 | endchoice |
523 | ||
524 | choice | |
525 | prompt "Virtual address space size" | |
526 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 527 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
528 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
529 | help | |
530 | Allows choosing one of multiple possible virtual address | |
531 | space sizes. The level of translation table is determined by | |
532 | a combination of page size and virtual address space size. | |
533 | ||
21539939 | 534 | config ARM64_VA_BITS_36 |
56a3f30e | 535 | bool "36-bit" if EXPERT |
21539939 SP |
536 | depends on ARM64_16K_PAGES |
537 | ||
e41ceed0 JL |
538 | config ARM64_VA_BITS_39 |
539 | bool "39-bit" | |
540 | depends on ARM64_4K_PAGES | |
541 | ||
542 | config ARM64_VA_BITS_42 | |
543 | bool "42-bit" | |
544 | depends on ARM64_64K_PAGES | |
545 | ||
44eaacf1 SP |
546 | config ARM64_VA_BITS_47 |
547 | bool "47-bit" | |
548 | depends on ARM64_16K_PAGES | |
549 | ||
c79b954b JL |
550 | config ARM64_VA_BITS_48 |
551 | bool "48-bit" | |
c79b954b | 552 | |
e41ceed0 JL |
553 | endchoice |
554 | ||
555 | config ARM64_VA_BITS | |
556 | int | |
21539939 | 557 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
558 | default 39 if ARM64_VA_BITS_39 |
559 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 560 | default 47 if ARM64_VA_BITS_47 |
c79b954b | 561 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 562 | |
a872013d WD |
563 | config CPU_BIG_ENDIAN |
564 | bool "Build big-endian kernel" | |
565 | help | |
566 | Say Y if you plan on running a kernel in big-endian mode. | |
567 | ||
f6e763b9 MB |
568 | config SCHED_MC |
569 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
570 | help |
571 | Multi-core scheduler support improves the CPU scheduler's decision | |
572 | making when dealing with multi-core CPU chips at a cost of slightly | |
573 | increased overhead in some places. If unsure say N here. | |
574 | ||
575 | config SCHED_SMT | |
576 | bool "SMT scheduler support" | |
f6e763b9 MB |
577 | help |
578 | Improves the CPU scheduler's decision making when dealing with | |
579 | MultiThreading at a cost of slightly increased overhead in some | |
580 | places. If unsure say N here. | |
581 | ||
8c2c3df3 | 582 | config NR_CPUS |
62aa9655 GK |
583 | int "Maximum number of CPUs (2-4096)" |
584 | range 2 4096 | |
15942853 | 585 | # These have to remain sorted largest to smallest |
e3672649 | 586 | default "64" |
8c2c3df3 | 587 | |
9327e2c6 MR |
588 | config HOTPLUG_CPU |
589 | bool "Support for hot-pluggable CPUs" | |
217d453d | 590 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
591 | help |
592 | Say Y here to experiment with turning CPUs off and on. CPUs | |
593 | can be controlled through /sys/devices/system/cpu. | |
594 | ||
1a2db300 GK |
595 | # Common NUMA Features |
596 | config NUMA | |
597 | bool "Numa Memory Allocation and Scheduler Support" | |
0c2a6cce KW |
598 | select ACPI_NUMA if ACPI |
599 | select OF_NUMA | |
1a2db300 GK |
600 | help |
601 | Enable NUMA (Non Uniform Memory Access) support. | |
602 | ||
603 | The kernel will try to allocate memory used by a CPU on the | |
604 | local memory of the CPU and add some more | |
605 | NUMA awareness to the kernel. | |
606 | ||
607 | config NODES_SHIFT | |
608 | int "Maximum NUMA Nodes (as a power of 2)" | |
609 | range 1 10 | |
610 | default "2" | |
611 | depends on NEED_MULTIPLE_NODES | |
612 | help | |
613 | Specify the maximum number of NUMA Nodes available on the target | |
614 | system. Increases memory reserved to accommodate various tables. | |
615 | ||
616 | config USE_PERCPU_NUMA_NODE_ID | |
617 | def_bool y | |
618 | depends on NUMA | |
619 | ||
7af3a0a9 ZL |
620 | config HAVE_SETUP_PER_CPU_AREA |
621 | def_bool y | |
622 | depends on NUMA | |
623 | ||
624 | config NEED_PER_CPU_EMBED_FIRST_CHUNK | |
625 | def_bool y | |
626 | depends on NUMA | |
627 | ||
8c2c3df3 | 628 | source kernel/Kconfig.preempt |
f90df5e2 | 629 | source kernel/Kconfig.hz |
8c2c3df3 | 630 | |
83863f25 LA |
631 | config ARCH_SUPPORTS_DEBUG_PAGEALLOC |
632 | def_bool y | |
633 | ||
8c2c3df3 CM |
634 | config ARCH_HAS_HOLES_MEMORYMODEL |
635 | def_bool y if SPARSEMEM | |
636 | ||
637 | config ARCH_SPARSEMEM_ENABLE | |
638 | def_bool y | |
639 | select SPARSEMEM_VMEMMAP_ENABLE | |
640 | ||
641 | config ARCH_SPARSEMEM_DEFAULT | |
642 | def_bool ARCH_SPARSEMEM_ENABLE | |
643 | ||
644 | config ARCH_SELECT_MEMORY_MODEL | |
645 | def_bool ARCH_SPARSEMEM_ENABLE | |
646 | ||
647 | config HAVE_ARCH_PFN_VALID | |
648 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
649 | ||
650 | config HW_PERF_EVENTS | |
6475b2d8 MR |
651 | def_bool y |
652 | depends on ARM_PMU | |
8c2c3df3 | 653 | |
084bd298 SC |
654 | config SYS_SUPPORTS_HUGETLBFS |
655 | def_bool y | |
656 | ||
084bd298 | 657 | config ARCH_WANT_HUGE_PMD_SHARE |
21539939 | 658 | def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
084bd298 | 659 | |
a41dc0e8 CM |
660 | config ARCH_HAS_CACHE_LINE_SIZE |
661 | def_bool y | |
662 | ||
8c2c3df3 CM |
663 | source "mm/Kconfig" |
664 | ||
a1ae65b2 AT |
665 | config SECCOMP |
666 | bool "Enable seccomp to safely compute untrusted bytecode" | |
667 | ---help--- | |
668 | This kernel feature is useful for number crunching applications | |
669 | that may need to compute untrusted bytecode during their | |
670 | execution. By using pipes or other transports made available to | |
671 | the process as file descriptors supporting the read/write | |
672 | syscalls, it's possible to isolate those applications in | |
673 | their own address space using seccomp. Once seccomp is | |
674 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
675 | and the task is only allowed to execute a few safe syscalls | |
676 | defined by each seccomp mode. | |
677 | ||
dfd57bc3 SS |
678 | config PARAVIRT |
679 | bool "Enable paravirtualization code" | |
680 | help | |
681 | This changes the kernel so it can modify itself when it is run | |
682 | under a hypervisor, potentially improving performance significantly | |
683 | over full virtualization. | |
684 | ||
685 | config PARAVIRT_TIME_ACCOUNTING | |
686 | bool "Paravirtual steal time accounting" | |
687 | select PARAVIRT | |
688 | default n | |
689 | help | |
690 | Select this option to enable fine granularity task steal time | |
691 | accounting. Time spent executing other tasks in parallel with | |
692 | the current vCPU is discounted from the vCPU power. To account for | |
693 | that, there can be a small performance impact. | |
694 | ||
695 | If in doubt, say N here. | |
696 | ||
d28f6df1 GL |
697 | config KEXEC |
698 | depends on PM_SLEEP_SMP | |
699 | select KEXEC_CORE | |
700 | bool "kexec system call" | |
701 | ---help--- | |
702 | kexec is a system call that implements the ability to shutdown your | |
703 | current kernel, and to start another kernel. It is like a reboot | |
704 | but it is independent of the system firmware. And like a reboot | |
705 | you can start any kernel with it, not just Linux. | |
706 | ||
aa42aa13 SS |
707 | config XEN_DOM0 |
708 | def_bool y | |
709 | depends on XEN | |
710 | ||
711 | config XEN | |
c2ba1f7d | 712 | bool "Xen guest support on ARM64" |
aa42aa13 | 713 | depends on ARM64 && OF |
83862ccf | 714 | select SWIOTLB_XEN |
dfd57bc3 | 715 | select PARAVIRT |
aa42aa13 SS |
716 | help |
717 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
718 | ||
d03bb145 SC |
719 | config FORCE_MAX_ZONEORDER |
720 | int | |
721 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
44eaacf1 | 722 | default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) |
d03bb145 | 723 | default "11" |
44eaacf1 SP |
724 | help |
725 | The kernel memory allocator divides physically contiguous memory | |
726 | blocks into "zones", where each zone is a power of two number of | |
727 | pages. This option selects the largest power of two that the kernel | |
728 | keeps in the memory allocator. If you need to allocate very large | |
729 | blocks of physically contiguous memory, then you may need to | |
730 | increase this value. | |
731 | ||
732 | This config option is actually maximum order plus one. For example, | |
733 | a value of 11 means that the largest free memory block is 2^10 pages. | |
734 | ||
735 | We make sure that we can allocate upto a HugePage size for each configuration. | |
736 | Hence we have : | |
737 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 | |
738 | ||
739 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us | |
740 | 4M allocations matching the default size used by generic code. | |
d03bb145 | 741 | |
1b907f46 WD |
742 | menuconfig ARMV8_DEPRECATED |
743 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
744 | depends on COMPAT | |
745 | help | |
746 | Legacy software support may require certain instructions | |
747 | that have been deprecated or obsoleted in the architecture. | |
748 | ||
749 | Enable this config to enable selective emulation of these | |
750 | features. | |
751 | ||
752 | If unsure, say Y | |
753 | ||
754 | if ARMV8_DEPRECATED | |
755 | ||
756 | config SWP_EMULATION | |
757 | bool "Emulate SWP/SWPB instructions" | |
758 | help | |
759 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
760 | they are always undefined. Say Y here to enable software | |
761 | emulation of these instructions for userspace using LDXR/STXR. | |
762 | ||
763 | In some older versions of glibc [<=2.8] SWP is used during futex | |
764 | trylock() operations with the assumption that the code will not | |
765 | be preempted. This invalid assumption may be more likely to fail | |
766 | with SWP emulation enabled, leading to deadlock of the user | |
767 | application. | |
768 | ||
769 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
770 | on an external transaction monitoring block called a global | |
771 | monitor to maintain update atomicity. If your system does not | |
772 | implement a global monitor, this option can cause programs that | |
773 | perform SWP operations to uncached memory to deadlock. | |
774 | ||
775 | If unsure, say Y | |
776 | ||
777 | config CP15_BARRIER_EMULATION | |
778 | bool "Emulate CP15 Barrier instructions" | |
779 | help | |
780 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
781 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
782 | strongly recommended to use the ISB, DSB, and DMB | |
783 | instructions instead. | |
784 | ||
785 | Say Y here to enable software emulation of these | |
786 | instructions for AArch32 userspace code. When this option is | |
787 | enabled, CP15 barrier usage is traced which can help | |
788 | identify software that needs updating. | |
789 | ||
790 | If unsure, say Y | |
791 | ||
2d888f48 SP |
792 | config SETEND_EMULATION |
793 | bool "Emulate SETEND instruction" | |
794 | help | |
795 | The SETEND instruction alters the data-endianness of the | |
796 | AArch32 EL0, and is deprecated in ARMv8. | |
797 | ||
798 | Say Y here to enable software emulation of the instruction | |
799 | for AArch32 userspace code. | |
800 | ||
801 | Note: All the cpus on the system must have mixed endian support at EL0 | |
802 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
803 | endian - is hotplugged in after this feature has been enabled, there could | |
804 | be unexpected results in the applications. | |
805 | ||
806 | If unsure, say Y | |
1b907f46 WD |
807 | endif |
808 | ||
ba42822a CM |
809 | config ARM64_SW_TTBR0_PAN |
810 | bool "Emulate Privileged Access Never using TTBR0_EL1 switching" | |
811 | help | |
812 | Enabling this option prevents the kernel from accessing | |
813 | user-space memory directly by pointing TTBR0_EL1 to a reserved | |
814 | zeroed area and reserved ASID. The user access routines | |
815 | restore the valid TTBR0_EL1 temporarily. | |
816 | ||
0e4a0709 WD |
817 | menu "ARMv8.1 architectural features" |
818 | ||
819 | config ARM64_HW_AFDBM | |
820 | bool "Support for hardware updates of the Access and Dirty page flags" | |
821 | default y | |
822 | help | |
823 | The ARMv8.1 architecture extensions introduce support for | |
824 | hardware updates of the access and dirty information in page | |
825 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
826 | capable processors, accesses to pages with PTE_AF cleared will | |
827 | set this bit instead of raising an access flag fault. | |
828 | Similarly, writes to read-only pages with the DBM bit set will | |
829 | clear the read-only bit (AP[2]) instead of raising a | |
830 | permission fault. | |
831 | ||
832 | Kernels built with this configuration option enabled continue | |
833 | to work on pre-ARMv8.1 hardware and the performance impact is | |
834 | minimal. If unsure, say Y. | |
835 | ||
836 | config ARM64_PAN | |
837 | bool "Enable support for Privileged Access Never (PAN)" | |
838 | default y | |
839 | help | |
840 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
841 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
842 | memory directly. | |
843 | ||
844 | Choosing this option will cause any unprotected (not using | |
845 | copy_to_user et al) memory access to fail with a permission fault. | |
846 | ||
847 | The feature is detected at runtime, and will remain as a 'nop' | |
848 | instruction if the cpu does not implement the feature. | |
849 | ||
850 | config ARM64_LSE_ATOMICS | |
851 | bool "Atomic instructions" | |
852 | help | |
853 | As part of the Large System Extensions, ARMv8.1 introduces new | |
854 | atomic instructions that are designed specifically to scale in | |
855 | very large systems. | |
856 | ||
857 | Say Y here to make use of these instructions for the in-kernel | |
858 | atomic routines. This incurs a small overhead on CPUs that do | |
859 | not support these instructions and requires the kernel to be | |
860 | built with binutils >= 2.25. | |
861 | ||
1f364c8c MZ |
862 | config ARM64_VHE |
863 | bool "Enable support for Virtualization Host Extensions (VHE)" | |
864 | default y | |
865 | help | |
866 | Virtualization Host Extensions (VHE) allow the kernel to run | |
867 | directly at EL2 (instead of EL1) on processors that support | |
868 | it. This leads to better performance for KVM, as they reduce | |
869 | the cost of the world switch. | |
870 | ||
871 | Selecting this option allows the VHE feature to be detected | |
872 | at runtime, and does not affect processors that do not | |
873 | implement this feature. | |
874 | ||
0e4a0709 WD |
875 | endmenu |
876 | ||
f993318b WD |
877 | menu "ARMv8.2 architectural features" |
878 | ||
57f4959b JM |
879 | config ARM64_UAO |
880 | bool "Enable support for User Access Override (UAO)" | |
881 | default y | |
882 | help | |
883 | User Access Override (UAO; part of the ARMv8.2 Extensions) | |
884 | causes the 'unprivileged' variant of the load/store instructions to | |
885 | be overriden to be privileged. | |
886 | ||
887 | This option changes get_user() and friends to use the 'unprivileged' | |
888 | variant of the load/store instructions. This ensures that user-space | |
889 | really did have access to the supplied memory. When addr_limit is | |
890 | set to kernel memory the UAO bit will be set, allowing privileged | |
891 | access to kernel memory. | |
892 | ||
893 | Choosing this option will cause copy_to_user() et al to use user-space | |
894 | memory permissions. | |
895 | ||
896 | The feature is detected at runtime, the kernel will use the | |
897 | regular load/store instructions if the cpu does not implement the | |
898 | feature. | |
899 | ||
f993318b WD |
900 | endmenu |
901 | ||
fd045f6c AB |
902 | config ARM64_MODULE_CMODEL_LARGE |
903 | bool | |
904 | ||
905 | config ARM64_MODULE_PLTS | |
906 | bool | |
907 | select ARM64_MODULE_CMODEL_LARGE | |
908 | select HAVE_MOD_ARCH_SPECIFIC | |
909 | ||
1e48ef7f AB |
910 | config RELOCATABLE |
911 | bool | |
912 | help | |
913 | This builds the kernel as a Position Independent Executable (PIE), | |
914 | which retains all relocation metadata required to relocate the | |
915 | kernel binary at runtime to a different virtual address than the | |
916 | address it was linked at. | |
917 | Since AArch64 uses the RELA relocation format, this requires a | |
918 | relocation pass at runtime even if the kernel is loaded at the | |
919 | same address it was linked at. | |
920 | ||
f80fb3a3 AB |
921 | config RANDOMIZE_BASE |
922 | bool "Randomize the address of the kernel image" | |
b9c220b5 | 923 | select ARM64_MODULE_PLTS if MODULES |
f80fb3a3 AB |
924 | select RELOCATABLE |
925 | help | |
926 | Randomizes the virtual address at which the kernel image is | |
927 | loaded, as a security feature that deters exploit attempts | |
928 | relying on knowledge of the location of kernel internals. | |
929 | ||
930 | It is the bootloader's job to provide entropy, by passing a | |
931 | random u64 value in /chosen/kaslr-seed at kernel entry. | |
932 | ||
2b5fe07a AB |
933 | When booting via the UEFI stub, it will invoke the firmware's |
934 | EFI_RNG_PROTOCOL implementation (if available) to supply entropy | |
935 | to the kernel proper. In addition, it will randomise the physical | |
936 | location of the kernel Image as well. | |
937 | ||
f80fb3a3 AB |
938 | If unsure, say N. |
939 | ||
940 | config RANDOMIZE_MODULE_REGION_FULL | |
941 | bool "Randomize the module region independently from the core kernel" | |
8fe88a41 | 942 | depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE |
f80fb3a3 AB |
943 | default y |
944 | help | |
945 | Randomizes the location of the module region without considering the | |
946 | location of the core kernel. This way, it is impossible for modules | |
947 | to leak information about the location of core kernel data structures | |
948 | but it does imply that function calls between modules and the core | |
949 | kernel will need to be resolved via veneers in the module PLT. | |
950 | ||
951 | When this option is not set, the module region will be randomized over | |
952 | a limited range that contains the [_stext, _etext] interval of the | |
953 | core kernel, so branch relocations are always in range. | |
954 | ||
8c2c3df3 CM |
955 | endmenu |
956 | ||
957 | menu "Boot options" | |
958 | ||
5e89c55e LP |
959 | config ARM64_ACPI_PARKING_PROTOCOL |
960 | bool "Enable support for the ARM64 ACPI parking protocol" | |
961 | depends on ACPI | |
962 | help | |
963 | Enable support for the ARM64 ACPI parking protocol. If disabled | |
964 | the kernel will not allow booting through the ARM64 ACPI parking | |
965 | protocol even if the corresponding data is present in the ACPI | |
966 | MADT table. | |
967 | ||
8c2c3df3 CM |
968 | config CMDLINE |
969 | string "Default kernel command string" | |
970 | default "" | |
971 | help | |
972 | Provide a set of default command-line options at build time by | |
973 | entering them here. As a minimum, you should specify the the | |
974 | root device (e.g. root=/dev/nfs). | |
975 | ||
976 | config CMDLINE_FORCE | |
977 | bool "Always use the default kernel command string" | |
978 | help | |
979 | Always use the default kernel command string, even if the boot | |
980 | loader passes other arguments to the kernel. | |
981 | This is useful if you cannot or don't want to change the | |
982 | command-line options your boot loader passes to the kernel. | |
983 | ||
f4f75ad5 AB |
984 | config EFI_STUB |
985 | bool | |
986 | ||
f84d0275 MS |
987 | config EFI |
988 | bool "UEFI runtime support" | |
989 | depends on OF && !CPU_BIG_ENDIAN | |
990 | select LIBFDT | |
991 | select UCS2_STRING | |
992 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 993 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
994 | select EFI_STUB |
995 | select EFI_ARMSTUB | |
f84d0275 MS |
996 | default y |
997 | help | |
998 | This option provides support for runtime services provided | |
999 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
1000 | clock, and platform reset). A UEFI stub is also provided to |
1001 | allow the kernel to be booted as an EFI application. This | |
1002 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 1003 | |
d1ae8c00 YL |
1004 | config DMI |
1005 | bool "Enable support for SMBIOS (DMI) tables" | |
1006 | depends on EFI | |
1007 | default y | |
1008 | help | |
1009 | This enables SMBIOS/DMI feature for systems. | |
1010 | ||
1011 | This option is only useful on systems that have UEFI firmware. | |
1012 | However, even with this option, the resultant kernel should | |
1013 | continue to boot on existing non-UEFI platforms. | |
1014 | ||
8c2c3df3 CM |
1015 | endmenu |
1016 | ||
1017 | menu "Userspace binary formats" | |
1018 | ||
1019 | source "fs/Kconfig.binfmt" | |
1020 | ||
1021 | config COMPAT | |
1022 | bool "Kernel support for 32-bit EL0" | |
755e70b7 | 1023 | depends on ARM64_4K_PAGES || EXPERT |
2e449048 | 1024 | select COMPAT_BINFMT_ELF if BINFMT_ELF |
af1839eb | 1025 | select HAVE_UID16 |
84b9e9b4 | 1026 | select OLD_SIGSUSPEND3 |
51682036 | 1027 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
1028 | help |
1029 | This option enables support for a 32-bit EL0 running under a 64-bit | |
1030 | kernel at EL1. AArch32-specific components such as system calls, | |
1031 | the user helper functions, VFP support and the ptrace interface are | |
1032 | handled appropriately by the kernel. | |
1033 | ||
44eaacf1 SP |
1034 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware |
1035 | that you will only be able to execute AArch32 binaries that were compiled | |
1036 | with page size aligned segments. | |
a8fcd8b1 | 1037 | |
8c2c3df3 CM |
1038 | If you want to execute 32-bit userspace applications, say Y. |
1039 | ||
1040 | config SYSVIPC_COMPAT | |
1041 | def_bool y | |
1042 | depends on COMPAT && SYSVIPC | |
1043 | ||
1044 | endmenu | |
1045 | ||
166936ba LP |
1046 | menu "Power management options" |
1047 | ||
1048 | source "kernel/power/Kconfig" | |
1049 | ||
82869ac5 JM |
1050 | config ARCH_HIBERNATION_POSSIBLE |
1051 | def_bool y | |
1052 | depends on CPU_PM | |
1053 | ||
1054 | config ARCH_HIBERNATION_HEADER | |
1055 | def_bool y | |
1056 | depends on HIBERNATION | |
1057 | ||
166936ba LP |
1058 | config ARCH_SUSPEND_POSSIBLE |
1059 | def_bool y | |
1060 | ||
166936ba LP |
1061 | endmenu |
1062 | ||
1307220d LP |
1063 | menu "CPU Power Management" |
1064 | ||
1065 | source "drivers/cpuidle/Kconfig" | |
1066 | ||
52e7e816 RH |
1067 | source "drivers/cpufreq/Kconfig" |
1068 | ||
1069 | endmenu | |
1070 | ||
8c2c3df3 CM |
1071 | source "net/Kconfig" |
1072 | ||
1073 | source "drivers/Kconfig" | |
1074 | ||
f84d0275 MS |
1075 | source "drivers/firmware/Kconfig" |
1076 | ||
b6a02173 GG |
1077 | source "drivers/acpi/Kconfig" |
1078 | ||
8c2c3df3 CM |
1079 | source "fs/Kconfig" |
1080 | ||
c3eb5b14 MZ |
1081 | source "arch/arm64/kvm/Kconfig" |
1082 | ||
8c2c3df3 CM |
1083 | source "arch/arm64/Kconfig.debug" |
1084 | ||
1085 | source "security/Kconfig" | |
1086 | ||
1087 | source "crypto/Kconfig" | |
2c98833a AB |
1088 | if CRYPTO |
1089 | source "arch/arm64/crypto/Kconfig" | |
1090 | endif | |
8c2c3df3 CM |
1091 | |
1092 | source "lib/Kconfig" |