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Commit | Line | Data |
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ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
eed6b3eb OJ |
2 | menu "Platform selection" |
3 | ||
c88cc3ee AF |
4 | config ARCH_ACTIONS |
5 | bool "Actions Semi Platforms" | |
6 | select OWL_TIMER | |
e0c27a10 | 7 | select PINCTRL |
c88cc3ee AF |
8 | help |
9 | This enables support for the Actions Semiconductor S900 SoC family. | |
10 | ||
ce3dd55b AP |
11 | config ARCH_SUNXI |
12 | bool "Allwinner sunxi 64-bit SoC Family" | |
900a9020 | 13 | select ARCH_HAS_RESET_CONTROLLER |
23485482 | 14 | select GENERIC_IRQ_CHIP |
4e346146 SH |
15 | select IRQ_DOMAIN_HIERARCHY |
16 | select IRQ_FASTEOI_HIERARCHY_HANDLERS | |
d229d205 | 17 | select PINCTRL |
900a9020 | 18 | select RESET_CONTROLLER |
cbccad66 | 19 | select SUN4I_TIMER |
ce3dd55b AP |
20 | help |
21 | This enables support for Allwinner sunxi based SoCs like the A64. | |
22 | ||
e2f0abaf AT |
23 | config ARCH_ALPINE |
24 | bool "Annapurna Labs Alpine platform" | |
5a3f75a4 | 25 | select ALPINE_MSI if PCI |
e2f0abaf AT |
26 | help |
27 | This enables support for the Annapurna Labs Alpine | |
28 | Soc family. | |
29 | ||
aea5f69f HM |
30 | config ARCH_APPLE |
31 | bool "Apple Silicon SoC family" | |
32 | select APPLE_AIC | |
33 | help | |
34 | This enables support for Apple's in-house ARM SoC family, starting | |
35 | with the Apple M1. | |
36 | ||
628d30d1 EA |
37 | config ARCH_BCM2835 |
38 | bool "Broadcom BCM2835 family" | |
bb0eb050 | 39 | select TIMER_OF |
da9a1c67 | 40 | select GPIOLIB |
7a9b6be9 | 41 | select MFD_CORE |
628d30d1 EA |
42 | select PINCTRL |
43 | select PINCTRL_BCM2835 | |
44 | select ARM_AMBA | |
781fa0a9 | 45 | select ARM_GIC |
628d30d1 | 46 | select ARM_TIMER_SP804 |
5674e314 | 47 | select BRCMSTB_L2_IRQ |
628d30d1 | 48 | help |
781fa0a9 SW |
49 | This enables support for the Broadcom BCM2837 and BCM2711 SoC. |
50 | These SoCs are used in the Raspberry Pi 3 and 4 devices. | |
628d30d1 | 51 | |
dccb22d0 RM |
52 | config ARCH_BCM4908 |
53 | bool "Broadcom BCM4908 family" | |
54 | select GPIOLIB | |
55 | help | |
56 | This enables support for the Broadcom BCM4906, BCM4908 and | |
57 | BCM49408 SoCs. These SoCs use Brahma-B53 cores and can be | |
58 | found in home routers. | |
59 | ||
36b7c583 RJ |
60 | config ARCH_BCM_IPROC |
61 | bool "Broadcom iProc SoC Family" | |
382618bb | 62 | select COMMON_CLK_IPROC |
da9a1c67 | 63 | select GPIOLIB |
382618bb | 64 | select PINCTRL |
36b7c583 RJ |
65 | help |
66 | This enables support for Broadcom iProc based SoCs | |
67 | ||
dd40fd92 JZ |
68 | config ARCH_BERLIN |
69 | bool "Marvell Berlin SoC Family" | |
70 | select DW_APB_ICTL | |
b0fc70ce | 71 | select DW_APB_TIMER_OF |
da9a1c67 | 72 | select GPIOLIB |
75d8e1ba | 73 | select PINCTRL |
dd40fd92 JZ |
74 | help |
75 | This enables support for Marvell Berlin SoC Family | |
76 | ||
ea367d38 MS |
77 | config ARCH_BITMAIN |
78 | bool "Bitmain SoC Platforms" | |
79 | help | |
80 | This enables support for the Bitmain SoC Family. | |
81 | ||
37eb56dc FF |
82 | config ARCH_BRCMSTB |
83 | bool "Broadcom Set-Top-Box SoCs" | |
809eec69 | 84 | select ARCH_HAS_RESET_CONTROLLER |
bf0349df | 85 | select BCM7038_L1_IRQ |
37eb56dc FF |
86 | select BRCMSTB_L2_IRQ |
87 | select GENERIC_IRQ_CHIP | |
724cf0ae | 88 | select PINCTRL |
37eb56dc FF |
89 | help |
90 | This enables support for Broadcom's ARMv8 Set Top Box SoCs | |
91 | ||
eed6b3eb | 92 | config ARCH_EXYNOS |
c87b3e97 | 93 | bool "ARMv8 based Samsung Exynos SoC family" |
eed6b3eb | 94 | select COMMON_CLK_SAMSUNG |
a6fe8c77 | 95 | select EXYNOS_CHIPID |
caab3df9 KK |
96 | select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS |
97 | select EXYNOS_PMU | |
eed6b3eb OJ |
98 | select HAVE_S3C_RTC if RTC_CLASS |
99 | select PINCTRL | |
100 | select PINCTRL_EXYNOS | |
5220a73a | 101 | select PM_GENERIC_DOMAINS if PM |
3b3428e3 | 102 | select SOC_SAMSUNG |
eed6b3eb | 103 | help |
c87b3e97 | 104 | This enables support for ARMv8 based Samsung Exynos SoC family. |
eed6b3eb | 105 | |
31a91c87 LP |
106 | config ARCH_SPARX5 |
107 | bool "ARMv8 based Microchip Sparx5 SoC family" | |
108 | select PINCTRL | |
109 | select DW_APB_TIMER_OF | |
110 | help | |
111 | This enables support for the Microchip Sparx5 ARMv8-based | |
112 | SoC family of TSN-capable gigabit switches. | |
113 | ||
114 | The SparX-5 Ethernet switch family provides a rich set of | |
115 | switching features such as advanced TCAM-based VLAN and QoS | |
116 | processing enabling delivery of differentiated services, and | |
117 | security through TCAM-based frame processing using versatile | |
118 | content aware processor (VCAP). | |
119 | ||
c7724572 NM |
120 | config ARCH_K3 |
121 | bool "Texas Instruments Inc. K3 multicore SoC architecture" | |
122 | select PM_GENERIC_DOMAINS if PM | |
009669e7 | 123 | select MAILBOX |
a6b112b0 | 124 | select SOC_TI |
009669e7 LV |
125 | select TI_MESSAGE_MANAGER |
126 | select TI_SCI_PROTOCOL | |
127 | select TI_SCI_INTR_IRQCHIP | |
128 | select TI_SCI_INTA_IRQCHIP | |
ec792ecf | 129 | select TI_K3_SOCINFO |
c7724572 NM |
130 | help |
131 | This enables support for Texas Instruments' K3 multicore SoC | |
132 | architecture. | |
133 | ||
53a5fde0 BS |
134 | config ARCH_LAYERSCAPE |
135 | bool "ARMv8 based Freescale Layerscape SoC family" | |
eeb3d68b | 136 | select EDAC_SUPPORT |
eed6b3eb | 137 | help |
53a5fde0 | 138 | This enables support for the Freescale Layerscape SoC family. |
eed6b3eb | 139 | |
198ed962 CM |
140 | config ARCH_LG1K |
141 | bool "LG Electronics LG1K SoC Family" | |
142 | help | |
143 | This enables support for LG Electronics LG1K SoC Family | |
144 | ||
eed6b3eb OJ |
145 | config ARCH_HISI |
146 | bool "Hisilicon SoC Family" | |
2b905d3a | 147 | select ARM_TIMER_SP804 |
f9db43bc | 148 | select HISILICON_IRQ_MBIGEN if PCI |
21adc4d7 | 149 | select PINCTRL |
eed6b3eb OJ |
150 | help |
151 | This enables support for Hisilicon ARMv8 SoC family | |
152 | ||
a6a4abf8 DA |
153 | config ARCH_KEEMBAY |
154 | bool "Keem Bay SoC" | |
155 | help | |
156 | This enables support for Intel Movidius SoC code-named Keem Bay. | |
157 | ||
eed6b3eb | 158 | config ARCH_MEDIATEK |
598f9b2e | 159 | bool "MediaTek SoC Family" |
eed6b3eb OJ |
160 | select ARM_GIC |
161 | select PINCTRL | |
c050b45d | 162 | select MTK_TIMER |
eed6b3eb | 163 | help |
598f9b2e SW |
164 | This enables support for MediaTek MT27xx, MT65xx, MT76xx |
165 | & MT81xx ARMv8 SoCs | |
eed6b3eb | 166 | |
451e9e54 AF |
167 | config ARCH_MESON |
168 | bool "Amlogic Platforms" | |
4cce442f | 169 | select COMMON_CLK |
f2c2122a | 170 | select MESON_IRQ_GPIO |
451e9e54 | 171 | help |
b3077ffc JB |
172 | This enables support for the arm64 based Amlogic SoCs |
173 | such as the s905, S905X/D, S912, A113X/D or S905X/D2 | |
451e9e54 | 174 | |
b4f596b1 GC |
175 | config ARCH_MVEBU |
176 | bool "Marvell EBU SoC Family" | |
ad87c0f6 TP |
177 | select ARMADA_AP806_SYSCON |
178 | select ARMADA_CP110_SYSCON | |
ff60d834 | 179 | select ARMADA_37XX_CLK |
d2718d13 GC |
180 | select GPIOLIB |
181 | select GPIOLIB_IRQCHIP | |
29ad6bd9 TP |
182 | select MVEBU_GICP |
183 | select MVEBU_ICU | |
b3920b2b | 184 | select MVEBU_ODMI |
04208a24 | 185 | select MVEBU_PIC |
228197c5 | 186 | select MVEBU_SEI |
d2718d13 GC |
187 | select OF_GPIO |
188 | select PINCTRL | |
189 | select PINCTRL_ARMADA_37XX | |
c4c14365 GC |
190 | select PINCTRL_ARMADA_AP806 |
191 | select PINCTRL_ARMADA_CP110 | |
b4f596b1 | 192 | help |
b3920b2b TP |
193 | This enables support for Marvell EBU familly, including: |
194 | - Armada 3700 SoC Family | |
195 | - Armada 7K SoC Family | |
196 | - Armada 8K SoC Family | |
b4f596b1 | 197 | |
930507c1 LS |
198 | config ARCH_MXC |
199 | bool "ARMv8 based NXP i.MX SoC family" | |
200 | select ARM64_ERRATUM_843419 | |
a29c7823 | 201 | select ARM64_ERRATUM_845719 if COMPAT |
67b92823 | 202 | select IMX_GPCV2 |
84a2ab25 LS |
203 | select IMX_GPCV2_PM_DOMAINS |
204 | select PM | |
205 | select PM_GENERIC_DOMAINS | |
fafaa0a2 | 206 | select SOC_BUS |
1991529f | 207 | select TIMER_IMX_SYS_CTR |
930507c1 LS |
208 | help |
209 | This enables support for the ARMv8 based SoCs in the | |
210 | NXP i.MX family. | |
211 | ||
eed6b3eb OJ |
212 | config ARCH_QCOM |
213 | bool "Qualcomm Platforms" | |
e19811a8 | 214 | select GPIOLIB |
eed6b3eb OJ |
215 | select PINCTRL |
216 | help | |
217 | This enables support for the ARMv8 based Qualcomm chipsets. | |
218 | ||
1b0d665e AF |
219 | config ARCH_REALTEK |
220 | bool "Realtek Platforms" | |
e3ca9556 | 221 | select RESET_CONTROLLER |
1b0d665e AF |
222 | help |
223 | This enables support for the ARMv8 based Realtek chipsets, | |
224 | like the RTD1295. | |
225 | ||
26a7e06d SH |
226 | config ARCH_RENESAS |
227 | bool "Renesas SoC Platforms" | |
9374eee3 | 228 | select GPIOLIB |
26a7e06d | 229 | select PINCTRL |
8d6799a9 | 230 | select SOC_BUS |
26a7e06d SH |
231 | help |
232 | This enables support for the ARMv8 based Renesas SoCs. | |
233 | ||
0964d660 GU |
234 | config ARCH_ROCKCHIP |
235 | bool "Rockchip Platforms" | |
236 | select ARCH_HAS_RESET_CONTROLLER | |
0964d660 | 237 | select PINCTRL |
0964d660 GU |
238 | select PM |
239 | select ROCKCHIP_TIMER | |
240 | help | |
241 | This enables support for the ARMv8 based Rockchip chipsets, | |
242 | like the RK3368. | |
243 | ||
3d4e0158 MM |
244 | config ARCH_S32 |
245 | bool "NXP S32 SoC Family" | |
246 | help | |
247 | This enables support for the NXP S32 family of processors. | |
248 | ||
0964d660 GU |
249 | config ARCH_SEATTLE |
250 | bool "AMD Seattle SoC Family" | |
251 | help | |
252 | This enables support for AMD Seattle SOC Family | |
253 | ||
910499e1 | 254 | config ARCH_INTEL_SOCFPGA |
4a9a1a56 KK |
255 | bool "Intel's SoCFPGA ARMv8 Families" |
256 | help | |
257 | This enables support for Intel's SoCFPGA ARMv8 families: | |
258 | Stratix 10 (ex. Altera), Agilex and eASIC N5X. | |
910499e1 | 259 | |
0964d660 GU |
260 | config ARCH_SYNQUACER |
261 | bool "Socionext SynQuacer SoC Family" | |
262 | ||
eed6b3eb OJ |
263 | config ARCH_TEGRA |
264 | bool "NVIDIA Tegra SoC Family" | |
265 | select ARCH_HAS_RESET_CONTROLLER | |
2e988a83 | 266 | select ARM_GIC_PM |
eed6b3eb | 267 | select CLKSRC_MMIO |
bb0eb050 | 268 | select TIMER_OF |
da9a1c67 | 269 | select GPIOLIB |
eed6b3eb | 270 | select PINCTRL |
98823241 JH |
271 | select PM |
272 | select PM_GENERIC_DOMAINS | |
eed6b3eb OJ |
273 | select RESET_CONTROLLER |
274 | help | |
275 | This enables support for the NVIDIA Tegra SoC family. | |
276 | ||
eed6b3eb | 277 | config ARCH_SPRD |
b5f73d47 | 278 | bool "Spreadtrum SoC platform" |
eed6b3eb OJ |
279 | help |
280 | Support for Spreadtrum ARM based SoCs | |
281 | ||
282 | config ARCH_THUNDER | |
283 | bool "Cavium Inc. Thunder SoC Family" | |
284 | help | |
285 | This enables support for Cavium's Thunder Family of SoCs. | |
286 | ||
03b6fd5d J |
287 | config ARCH_THUNDER2 |
288 | bool "Cavium ThunderX2 Server Processors" | |
289 | select GPIOLIB | |
290 | help | |
291 | This enables support for Cavium's ThunderX2 CN99XX family of | |
292 | server processors. | |
293 | ||
56aaafb6 MY |
294 | config ARCH_UNIPHIER |
295 | bool "Socionext UniPhier SoC Family" | |
75924903 | 296 | select ARCH_HAS_RESET_CONTROLLER |
56aaafb6 | 297 | select PINCTRL |
ab6ab445 | 298 | select RESET_CONTROLLER |
56aaafb6 MY |
299 | help |
300 | This enables support for Socionext UniPhier SoC family. | |
301 | ||
eed6b3eb OJ |
302 | config ARCH_VEXPRESS |
303 | bool "ARMv8 software model (Versatile Express)" | |
da9a1c67 | 304 | select GPIOLIB |
8da7cc08 SH |
305 | select PM |
306 | select PM_GENERIC_DOMAINS | |
eed6b3eb OJ |
307 | help |
308 | This enables support for the ARMv8 software model (Versatile | |
309 | Express). | |
310 | ||
0aa56c7e NI |
311 | config ARCH_VISCONTI |
312 | bool "Toshiba Visconti SoC Family" | |
313 | select PINCTRL | |
314 | select PINCTRL_VISCONTI | |
315 | help | |
316 | This enables support for Toshiba Visconti SoCs Family. | |
317 | ||
5bfb3889 | 318 | config ARCH_VULCAN |
a314520d | 319 | def_bool n |
5bfb3889 | 320 | |
eed6b3eb OJ |
321 | config ARCH_XGENE |
322 | bool "AppliedMicro X-Gene SOC Family" | |
323 | help | |
324 | This enables support for AppliedMicro X-Gene SOC Family | |
325 | ||
326 | config ARCH_ZYNQMP | |
327 | bool "Xilinx ZynqMP Family" | |
328 | help | |
329 | This enables support for Xilinx ZynqMP Family | |
330 | ||
331 | endmenu |