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Commit | Line | Data |
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ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
eed6b3eb OJ |
2 | menu "Platform selection" |
3 | ||
c88cc3ee AF |
4 | config ARCH_ACTIONS |
5 | bool "Actions Semi Platforms" | |
6 | select OWL_TIMER | |
e0c27a10 | 7 | select PINCTRL |
c88cc3ee AF |
8 | help |
9 | This enables support for the Actions Semiconductor S900 SoC family. | |
10 | ||
4b36daf9 DN |
11 | config ARCH_AGILEX |
12 | bool "Intel's Agilex SoCFPGA Family" | |
13 | help | |
14 | This enables support for Intel's Agilex SoCFPGA Family. | |
15 | ||
ce3dd55b AP |
16 | config ARCH_SUNXI |
17 | bool "Allwinner sunxi 64-bit SoC Family" | |
900a9020 | 18 | select ARCH_HAS_RESET_CONTROLLER |
23485482 | 19 | select GENERIC_IRQ_CHIP |
d229d205 | 20 | select PINCTRL |
900a9020 | 21 | select RESET_CONTROLLER |
ce3dd55b AP |
22 | help |
23 | This enables support for Allwinner sunxi based SoCs like the A64. | |
24 | ||
e2f0abaf AT |
25 | config ARCH_ALPINE |
26 | bool "Annapurna Labs Alpine platform" | |
5a3f75a4 | 27 | select ALPINE_MSI if PCI |
e2f0abaf AT |
28 | help |
29 | This enables support for the Annapurna Labs Alpine | |
30 | Soc family. | |
31 | ||
628d30d1 EA |
32 | config ARCH_BCM2835 |
33 | bool "Broadcom BCM2835 family" | |
bb0eb050 | 34 | select TIMER_OF |
da9a1c67 | 35 | select GPIOLIB |
7a9b6be9 | 36 | select MFD_CORE |
628d30d1 EA |
37 | select PINCTRL |
38 | select PINCTRL_BCM2835 | |
39 | select ARM_AMBA | |
781fa0a9 | 40 | select ARM_GIC |
628d30d1 | 41 | select ARM_TIMER_SP804 |
628d30d1 | 42 | help |
781fa0a9 SW |
43 | This enables support for the Broadcom BCM2837 and BCM2711 SoC. |
44 | These SoCs are used in the Raspberry Pi 3 and 4 devices. | |
628d30d1 | 45 | |
dccb22d0 RM |
46 | config ARCH_BCM4908 |
47 | bool "Broadcom BCM4908 family" | |
48 | select GPIOLIB | |
49 | help | |
50 | This enables support for the Broadcom BCM4906, BCM4908 and | |
51 | BCM49408 SoCs. These SoCs use Brahma-B53 cores and can be | |
52 | found in home routers. | |
53 | ||
36b7c583 RJ |
54 | config ARCH_BCM_IPROC |
55 | bool "Broadcom iProc SoC Family" | |
382618bb | 56 | select COMMON_CLK_IPROC |
da9a1c67 | 57 | select GPIOLIB |
382618bb | 58 | select PINCTRL |
36b7c583 RJ |
59 | help |
60 | This enables support for Broadcom iProc based SoCs | |
61 | ||
dd40fd92 JZ |
62 | config ARCH_BERLIN |
63 | bool "Marvell Berlin SoC Family" | |
64 | select DW_APB_ICTL | |
b0fc70ce | 65 | select DW_APB_TIMER_OF |
da9a1c67 | 66 | select GPIOLIB |
75d8e1ba | 67 | select PINCTRL |
dd40fd92 JZ |
68 | help |
69 | This enables support for Marvell Berlin SoC Family | |
70 | ||
ea367d38 MS |
71 | config ARCH_BITMAIN |
72 | bool "Bitmain SoC Platforms" | |
73 | help | |
74 | This enables support for the Bitmain SoC Family. | |
75 | ||
37eb56dc FF |
76 | config ARCH_BRCMSTB |
77 | bool "Broadcom Set-Top-Box SoCs" | |
809eec69 | 78 | select ARCH_HAS_RESET_CONTROLLER |
bf0349df | 79 | select BCM7038_L1_IRQ |
37eb56dc FF |
80 | select BRCMSTB_L2_IRQ |
81 | select GENERIC_IRQ_CHIP | |
724cf0ae | 82 | select PINCTRL |
37eb56dc FF |
83 | help |
84 | This enables support for Broadcom's ARMv8 Set Top Box SoCs | |
85 | ||
eed6b3eb | 86 | config ARCH_EXYNOS |
c87b3e97 | 87 | bool "ARMv8 based Samsung Exynos SoC family" |
eed6b3eb | 88 | select COMMON_CLK_SAMSUNG |
a6fe8c77 | 89 | select EXYNOS_CHIPID |
caab3df9 KK |
90 | select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS |
91 | select EXYNOS_PMU | |
eed6b3eb OJ |
92 | select HAVE_S3C_RTC if RTC_CLASS |
93 | select PINCTRL | |
94 | select PINCTRL_EXYNOS | |
5220a73a | 95 | select PM_GENERIC_DOMAINS if PM |
3b3428e3 | 96 | select SOC_SAMSUNG |
eed6b3eb | 97 | help |
c87b3e97 | 98 | This enables support for ARMv8 based Samsung Exynos SoC family. |
eed6b3eb | 99 | |
31a91c87 LP |
100 | config ARCH_SPARX5 |
101 | bool "ARMv8 based Microchip Sparx5 SoC family" | |
102 | select PINCTRL | |
103 | select DW_APB_TIMER_OF | |
104 | help | |
105 | This enables support for the Microchip Sparx5 ARMv8-based | |
106 | SoC family of TSN-capable gigabit switches. | |
107 | ||
108 | The SparX-5 Ethernet switch family provides a rich set of | |
109 | switching features such as advanced TCAM-based VLAN and QoS | |
110 | processing enabling delivery of differentiated services, and | |
111 | security through TCAM-based frame processing using versatile | |
112 | content aware processor (VCAP). | |
113 | ||
c7724572 NM |
114 | config ARCH_K3 |
115 | bool "Texas Instruments Inc. K3 multicore SoC architecture" | |
116 | select PM_GENERIC_DOMAINS if PM | |
009669e7 | 117 | select MAILBOX |
a6b112b0 | 118 | select SOC_TI |
009669e7 LV |
119 | select TI_MESSAGE_MANAGER |
120 | select TI_SCI_PROTOCOL | |
121 | select TI_SCI_INTR_IRQCHIP | |
122 | select TI_SCI_INTA_IRQCHIP | |
ec792ecf | 123 | select TI_K3_SOCINFO |
c7724572 NM |
124 | help |
125 | This enables support for Texas Instruments' K3 multicore SoC | |
126 | architecture. | |
127 | ||
53a5fde0 BS |
128 | config ARCH_LAYERSCAPE |
129 | bool "ARMv8 based Freescale Layerscape SoC family" | |
eeb3d68b | 130 | select EDAC_SUPPORT |
eed6b3eb | 131 | help |
53a5fde0 | 132 | This enables support for the Freescale Layerscape SoC family. |
eed6b3eb | 133 | |
198ed962 CM |
134 | config ARCH_LG1K |
135 | bool "LG Electronics LG1K SoC Family" | |
136 | help | |
137 | This enables support for LG Electronics LG1K SoC Family | |
138 | ||
eed6b3eb OJ |
139 | config ARCH_HISI |
140 | bool "Hisilicon SoC Family" | |
2b905d3a | 141 | select ARM_TIMER_SP804 |
f9db43bc | 142 | select HISILICON_IRQ_MBIGEN if PCI |
21adc4d7 | 143 | select PINCTRL |
eed6b3eb OJ |
144 | help |
145 | This enables support for Hisilicon ARMv8 SoC family | |
146 | ||
a6a4abf8 DA |
147 | config ARCH_KEEMBAY |
148 | bool "Keem Bay SoC" | |
149 | help | |
150 | This enables support for Intel Movidius SoC code-named Keem Bay. | |
151 | ||
eed6b3eb | 152 | config ARCH_MEDIATEK |
598f9b2e | 153 | bool "MediaTek SoC Family" |
eed6b3eb OJ |
154 | select ARM_GIC |
155 | select PINCTRL | |
c050b45d | 156 | select MTK_TIMER |
eed6b3eb | 157 | help |
598f9b2e SW |
158 | This enables support for MediaTek MT27xx, MT65xx, MT76xx |
159 | & MT81xx ARMv8 SoCs | |
eed6b3eb | 160 | |
451e9e54 AF |
161 | config ARCH_MESON |
162 | bool "Amlogic Platforms" | |
f2c2122a | 163 | select MESON_IRQ_GPIO |
451e9e54 | 164 | help |
b3077ffc JB |
165 | This enables support for the arm64 based Amlogic SoCs |
166 | such as the s905, S905X/D, S912, A113X/D or S905X/D2 | |
451e9e54 | 167 | |
b4f596b1 GC |
168 | config ARCH_MVEBU |
169 | bool "Marvell EBU SoC Family" | |
ad87c0f6 TP |
170 | select ARMADA_AP806_SYSCON |
171 | select ARMADA_CP110_SYSCON | |
ff60d834 | 172 | select ARMADA_37XX_CLK |
d2718d13 GC |
173 | select GPIOLIB |
174 | select GPIOLIB_IRQCHIP | |
29ad6bd9 TP |
175 | select MVEBU_GICP |
176 | select MVEBU_ICU | |
b3920b2b | 177 | select MVEBU_ODMI |
04208a24 | 178 | select MVEBU_PIC |
228197c5 | 179 | select MVEBU_SEI |
d2718d13 GC |
180 | select OF_GPIO |
181 | select PINCTRL | |
182 | select PINCTRL_ARMADA_37XX | |
c4c14365 GC |
183 | select PINCTRL_ARMADA_AP806 |
184 | select PINCTRL_ARMADA_CP110 | |
b4f596b1 | 185 | help |
b3920b2b TP |
186 | This enables support for Marvell EBU familly, including: |
187 | - Armada 3700 SoC Family | |
188 | - Armada 7K SoC Family | |
189 | - Armada 8K SoC Family | |
b4f596b1 | 190 | |
930507c1 LS |
191 | config ARCH_MXC |
192 | bool "ARMv8 based NXP i.MX SoC family" | |
193 | select ARM64_ERRATUM_843419 | |
a29c7823 | 194 | select ARM64_ERRATUM_845719 if COMPAT |
67b92823 | 195 | select IMX_GPCV2 |
84a2ab25 LS |
196 | select IMX_GPCV2_PM_DOMAINS |
197 | select PM | |
198 | select PM_GENERIC_DOMAINS | |
fafaa0a2 | 199 | select SOC_BUS |
1991529f | 200 | select TIMER_IMX_SYS_CTR |
930507c1 LS |
201 | help |
202 | This enables support for the ARMv8 based SoCs in the | |
203 | NXP i.MX family. | |
204 | ||
eed6b3eb OJ |
205 | config ARCH_QCOM |
206 | bool "Qualcomm Platforms" | |
e19811a8 | 207 | select GPIOLIB |
eed6b3eb OJ |
208 | select PINCTRL |
209 | help | |
210 | This enables support for the ARMv8 based Qualcomm chipsets. | |
211 | ||
1b0d665e AF |
212 | config ARCH_REALTEK |
213 | bool "Realtek Platforms" | |
e3ca9556 | 214 | select RESET_CONTROLLER |
1b0d665e AF |
215 | help |
216 | This enables support for the ARMv8 based Realtek chipsets, | |
217 | like the RTD1295. | |
218 | ||
26a7e06d SH |
219 | config ARCH_RENESAS |
220 | bool "Renesas SoC Platforms" | |
9374eee3 | 221 | select GPIOLIB |
26a7e06d | 222 | select PINCTRL |
8d6799a9 | 223 | select SOC_BUS |
26a7e06d SH |
224 | help |
225 | This enables support for the ARMv8 based Renesas SoCs. | |
226 | ||
0964d660 GU |
227 | config ARCH_ROCKCHIP |
228 | bool "Rockchip Platforms" | |
229 | select ARCH_HAS_RESET_CONTROLLER | |
230 | select GPIOLIB | |
231 | select PINCTRL | |
232 | select PINCTRL_ROCKCHIP | |
233 | select PM | |
234 | select ROCKCHIP_TIMER | |
235 | help | |
236 | This enables support for the ARMv8 based Rockchip chipsets, | |
237 | like the RK3368. | |
238 | ||
3d4e0158 MM |
239 | config ARCH_S32 |
240 | bool "NXP S32 SoC Family" | |
241 | help | |
242 | This enables support for the NXP S32 family of processors. | |
243 | ||
0964d660 GU |
244 | config ARCH_SEATTLE |
245 | bool "AMD Seattle SoC Family" | |
246 | help | |
247 | This enables support for AMD Seattle SOC Family | |
248 | ||
78cd6a9d DN |
249 | config ARCH_STRATIX10 |
250 | bool "Altera's Stratix 10 SoCFPGA Family" | |
251 | help | |
252 | This enables support for Altera's Stratix 10 SoCFPGA Family. | |
253 | ||
0964d660 GU |
254 | config ARCH_SYNQUACER |
255 | bool "Socionext SynQuacer SoC Family" | |
256 | ||
eed6b3eb OJ |
257 | config ARCH_TEGRA |
258 | bool "NVIDIA Tegra SoC Family" | |
259 | select ARCH_HAS_RESET_CONTROLLER | |
2e988a83 | 260 | select ARM_GIC_PM |
eed6b3eb | 261 | select CLKSRC_MMIO |
bb0eb050 | 262 | select TIMER_OF |
da9a1c67 | 263 | select GPIOLIB |
eed6b3eb | 264 | select PINCTRL |
98823241 JH |
265 | select PM |
266 | select PM_GENERIC_DOMAINS | |
eed6b3eb OJ |
267 | select RESET_CONTROLLER |
268 | help | |
269 | This enables support for the NVIDIA Tegra SoC family. | |
270 | ||
eed6b3eb | 271 | config ARCH_SPRD |
b5f73d47 | 272 | bool "Spreadtrum SoC platform" |
eed6b3eb OJ |
273 | help |
274 | Support for Spreadtrum ARM based SoCs | |
275 | ||
276 | config ARCH_THUNDER | |
277 | bool "Cavium Inc. Thunder SoC Family" | |
278 | help | |
279 | This enables support for Cavium's Thunder Family of SoCs. | |
280 | ||
03b6fd5d J |
281 | config ARCH_THUNDER2 |
282 | bool "Cavium ThunderX2 Server Processors" | |
283 | select GPIOLIB | |
284 | help | |
285 | This enables support for Cavium's ThunderX2 CN99XX family of | |
286 | server processors. | |
287 | ||
56aaafb6 MY |
288 | config ARCH_UNIPHIER |
289 | bool "Socionext UniPhier SoC Family" | |
75924903 | 290 | select ARCH_HAS_RESET_CONTROLLER |
56aaafb6 | 291 | select PINCTRL |
ab6ab445 | 292 | select RESET_CONTROLLER |
56aaafb6 MY |
293 | help |
294 | This enables support for Socionext UniPhier SoC family. | |
295 | ||
eed6b3eb OJ |
296 | config ARCH_VEXPRESS |
297 | bool "ARMv8 software model (Versatile Express)" | |
da9a1c67 | 298 | select GPIOLIB |
8da7cc08 SH |
299 | select PM |
300 | select PM_GENERIC_DOMAINS | |
eed6b3eb OJ |
301 | help |
302 | This enables support for the ARMv8 software model (Versatile | |
303 | Express). | |
304 | ||
0aa56c7e NI |
305 | config ARCH_VISCONTI |
306 | bool "Toshiba Visconti SoC Family" | |
307 | select PINCTRL | |
308 | select PINCTRL_VISCONTI | |
309 | help | |
310 | This enables support for Toshiba Visconti SoCs Family. | |
311 | ||
5bfb3889 | 312 | config ARCH_VULCAN |
a314520d | 313 | def_bool n |
5bfb3889 | 314 | |
eed6b3eb OJ |
315 | config ARCH_XGENE |
316 | bool "AppliedMicro X-Gene SOC Family" | |
317 | help | |
318 | This enables support for AppliedMicro X-Gene SOC Family | |
319 | ||
12496aea JN |
320 | config ARCH_ZX |
321 | bool "ZTE ZX SoC Family" | |
03d95c26 | 322 | select PINCTRL |
12496aea JN |
323 | help |
324 | This enables support for ZTE ZX SoC Family | |
325 | ||
eed6b3eb OJ |
326 | config ARCH_ZYNQMP |
327 | bool "Xilinx ZynqMP Family" | |
328 | help | |
329 | This enables support for Xilinx ZynqMP Family | |
330 | ||
331 | endmenu |