[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / boot / dts / altera / socfpga_stratix10.dtsi

/*
 * Copyright Altera Corporation (C) 2015. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "altr,socfpga-stratix10";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x1>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x3>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 120 8>,
			     <0 121 8>,
			     <0 122 8>,
			     <0 123 8>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
		interrupt-parent = <&intc>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	intc: intc@fffc1000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0xfffc1000 0x0 0x1000>,
		      <0x0 0xfffc2000 0x0 0x2000>,
		      <0x0 0xfffc4000 0x0 0x2000>,
		      <0x0 0xfffc6000 0x0 0x2000>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges = <0 0 0 0xffffffff>;

		clkmgr@ffd1000 {
			compatible = "altr,clk-mgr";
			reg = <0xffd10000 0x1000>;
		};

		gmac0: ethernet@ff800000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff800000 0x2000>;
			interrupts = <0 90 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC0_RESET>;
			reset-names = "stmmaceth";
			status = "disabled";
		};

		gmac1: ethernet@ff802000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff802000 0x2000>;
			interrupts = <0 91 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC1_RESET>;
			reset-names = "stmmaceth";
			status = "disabled";
		};

		gmac2: ethernet@ff804000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff804000 0x2000>;
			interrupts = <0 92 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC2_RESET>;
			reset-names = "stmmaceth";
			status = "disabled";
		};

		gpio0: gpio@ffc03200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc03200 0x100>;
			resets = <&rst GPIO0_RESET>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 110 4>;
			};
		};

		gpio1: gpio@ffc03300 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc03300 0x100>;
			resets = <&rst GPIO1_RESET>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 111 4>;
			};
		};

		i2c0: i2c@ffc02800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02800 0x100>;
			interrupts = <0 103 4>;
			resets = <&rst I2C0_RESET>;
			status = "disabled";
		};

		i2c1: i2c@ffc02900 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02900 0x100>;
			interrupts = <0 104 4>;
			resets = <&rst I2C1_RESET>;
			status = "disabled";
		};

		i2c2: i2c@ffc02a00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02a00 0x100>;
			interrupts = <0 105 4>;
			resets = <&rst I2C2_RESET>;
			status = "disabled";
		};

		i2c3: i2c@ffc02b00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02b00 0x100>;
			interrupts = <0 106 4>;
			resets = <&rst I2C3_RESET>;
			status = "disabled";
		};

		i2c4: i2c@ffc02c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02c00 0x100>;
			interrupts = <0 107 4>;
			resets = <&rst I2C4_RESET>;
			status = "disabled";
		};

		mmc: dwmmc0@ff808000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff808000 0x1000>;
			interrupts = <0 96 4>;
			fifo-depth = <0x400>;
			resets = <&rst SDMMC_RESET>;
			reset-names = "reset";
			status = "disabled";
		};

		ocram: sram@ffe00000 {
			compatible = "mmio-sram";
			reg = <0xffe00000 0x100000>;
		};

		rst: rstmgr@ffd11000 {
			#reset-cells = <1>;
			compatible = "altr,rst-mgr";
			reg = <0xffd11000 0x1000>;
			altr,modrst-offset = <0x20>;
		};

		spi0: spi@ffda4000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xffda4000 0x1000>;
			interrupts = <0 101 4>;
			num-chipselect = <4>;
			bus-num = <0>;
			status = "disabled";
		};

		spi1: spi@ffda5000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xffda5000 0x1000>;
			interrupts = <0 102 4>;
			num-chipselect = <4>;
			bus-num = <0>;
			status = "disabled";
		};

		sysmgr: sysmgr@ffd12000 {
			compatible = "altr,sys-mgr", "syscon";
			reg = <0xffd12000 0x1000>;
		};

		/* Local timer */
		timer {
			compatible = "arm,armv8-timer";
			interrupts = <1 13 0xf08>,
				     <1 14 0xf08>,
				     <1 11 0xf08>,
				     <1 10 0xf08>;
		};

		timer0: timer0@ffc03000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 113 4>;
			reg = <0xffc03000 0x100>;
		};

		timer1: timer1@ffc03100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 114 4>;
			reg = <0xffc03100 0x100>;
		};

		timer2: timer2@ffd00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 115 4>;
			reg = <0xffd00000 0x100>;
		};

		timer3: timer3@ffd00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 116 4>;
			reg = <0xffd00100 0x100>;
		};

		uart0: serial0@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x100>;
			interrupts = <0 108 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART0_RESET>;
			status = "disabled";
		};

		uart1: serial1@ffc02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02100 0x100>;
			interrupts = <0 109 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART1_RESET>;
			status = "disabled";
		};

		usbphy0: usbphy@0 {
			#phy-cells = <0>;
			compatible = "usb-nop-xceiv";
			status = "okay";
		};

		usb0: usb@ffb00000 {
			compatible = "snps,dwc2";
			reg = <0xffb00000 0x40000>;
			interrupts = <0 93 4>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB0_RESET>;
			reset-names = "dwc2";
			status = "disabled";
		};

		usb1: usb@ffb40000 {
			compatible = "snps,dwc2";
			reg = <0xffb40000 0x40000>;
			interrupts = <0 94 4>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB1_RESET>;
			reset-names = "dwc2";
			status = "disabled";
		};

		watchdog0: watchdog@ffd00200 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00200 0x100>;
			interrupts = <0 117 4>;
			resets = <&rst WATCHDOG0_RESET>;
			status = "disabled";
		};

		watchdog1: watchdog@ffd00300 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00300 0x100>;
			interrupts = <0 118 4>;
			resets = <&rst WATCHDOG1_RESET>;
			status = "disabled";
		};

		watchdog2: watchdog@ffd00400 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00400 0x100>;
			interrupts = <0 125 4>;
			resets = <&rst WATCHDOG2_RESET>;
			status = "disabled";
		};

		watchdog3: watchdog@ffd00500 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00500 0x100>;
			interrupts = <0 126 4>;
			resets = <&rst WATCHDOG3_RESET>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
78cd6a9d DN	1	/*
	2	* Copyright Altera Corporation (C) 2015. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	/dts-v1/;
e519922e	18	#include <dt-bindings/reset/altr,rst-mgr-s10.h>
5a0e622e	19	#include <dt-bindings/gpio/gpio.h>
78cd6a9d DN	20
	21	/ {
	22	compatible = "altr,socfpga-stratix10";
	23	#address-cells = <2>;
	24	#size-cells = <2>;
	25
	26	cpus {
	27	#address-cells = <1>;
	28	#size-cells = <0>;
	29
	30	cpu0: cpu@0 {
	31	compatible = "arm,cortex-a53", "arm,armv8";
	32	device_type = "cpu";
	33	enable-method = "psci";
	34	reg = <0x0>;
	35	};
	36
	37	cpu1: cpu@1 {
	38	compatible = "arm,cortex-a53", "arm,armv8";
	39	device_type = "cpu";
	40	enable-method = "psci";
	41	reg = <0x1>;
	42	};
	43
	44	cpu2: cpu@2 {
	45	compatible = "arm,cortex-a53", "arm,armv8";
	46	device_type = "cpu";
	47	enable-method = "psci";
	48	reg = <0x2>;
	49	};
	50
	51	cpu3: cpu@3 {
	52	compatible = "arm,cortex-a53", "arm,armv8";
	53	device_type = "cpu";
	54	enable-method = "psci";
	55	reg = <0x3>;
	56	};
	57	};
	58
	59	pmu {
	60	compatible = "arm,armv8-pmuv3";
	61	interrupts = <0 120 8>,
	62	<0 121 8>,
	63	<0 122 8>,
	64	<0 123 8>;
	65	interrupt-affinity = <&cpu0>,
	66	<&cpu1>,
	67	<&cpu2>,
	68	<&cpu3>;
69c4d8ed	69	interrupt-parent = <&intc>;
78cd6a9d DN	70	};
	71
	72	psci {
	73	compatible = "arm,psci-0.2";
	74	method = "smc";
	75	};
	76
	77	intc: intc@fffc1000 {
	78	compatible = "arm,gic-400", "arm,cortex-a15-gic";
	79	#interrupt-cells = <3>;
	80	interrupt-controller;
f973bfa0 DN	81	reg = <0x0 0xfffc1000 0x0 0x1000>,
	82	<0x0 0xfffc2000 0x0 0x2000>,
	83	<0x0 0xfffc4000 0x0 0x2000>,
	84	<0x0 0xfffc6000 0x0 0x2000>;
78cd6a9d DN	85	};
	86
	87	soc {
	88	#address-cells = <1>;
	89	#size-cells = <1>;
	90	compatible = "simple-bus";
	91	device_type = "soc";
	92	interrupt-parent = <&intc>;
	93	ranges = <0 0 0 0xffffffff>;
	94
	95	clkmgr@ffd1000 {
	96	compatible = "altr,clk-mgr";
	97	reg = <0xffd10000 0x1000>;
	98	};
	99
	100	gmac0: ethernet@ff800000 {
	101	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
	102	reg = <0xff800000 0x2000>;
	103	interrupts = <0 90 4>;
	104	interrupt-names = "macirq";
	105	mac-address = [00 00 00 00 00 00];
788251fa DN	106	resets = <&rst EMAC0_RESET>;
788251fa DN	107	reset-names = "stmmaceth";
78cd6a9d DN	108	status = "disabled";
	109	};
	110
	111	gmac1: ethernet@ff802000 {
	112	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
	113	reg = <0xff802000 0x2000>;
	114	interrupts = <0 91 4>;
	115	interrupt-names = "macirq";
	116	mac-address = [00 00 00 00 00 00];
788251fa DN	117	resets = <&rst EMAC1_RESET>;
788251fa DN	118	reset-names = "stmmaceth";
78cd6a9d DN	119	status = "disabled";
	120	};
	121
	122	gmac2: ethernet@ff804000 {
	123	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
	124	reg = <0xff804000 0x2000>;
	125	interrupts = <0 92 4>;
	126	interrupt-names = "macirq";
	127	mac-address = [00 00 00 00 00 00];
788251fa DN	128	resets = <&rst EMAC2_RESET>;
788251fa DN	129	reset-names = "stmmaceth";
78cd6a9d DN	130	status = "disabled";
	131	};
	132
	133	gpio0: gpio@ffc03200 {
	134	#address-cells = <1>;
	135	#size-cells = <0>;
	136	compatible = "snps,dw-apb-gpio";
	137	reg = <0xffc03200 0x100>;
788251fa	138	resets = <&rst GPIO0_RESET>;
78cd6a9d DN	139	status = "disabled";
	140
	141	porta: gpio-controller@0 {
	142	compatible = "snps,dw-apb-gpio-port";
	143	gpio-controller;
	144	#gpio-cells = <2>;
	145	snps,nr-gpios = <24>;
	146	reg = <0>;
	147	interrupt-controller;
	148	#interrupt-cells = <2>;
	149	interrupts = <0 110 4>;
	150	};
	151	};
	152
	153	gpio1: gpio@ffc03300 {
	154	#address-cells = <1>;
	155	#size-cells = <0>;
	156	compatible = "snps,dw-apb-gpio";
	157	reg = <0xffc03300 0x100>;
788251fa	158	resets = <&rst GPIO1_RESET>;
78cd6a9d DN	159	status = "disabled";
	160
	161	portb: gpio-controller@0 {
	162	compatible = "snps,dw-apb-gpio-port";
	163	gpio-controller;
	164	#gpio-cells = <2>;
	165	snps,nr-gpios = <24>;
	166	reg = <0>;
	167	interrupt-controller;
	168	#interrupt-cells = <2>;
a067fb42	169	interrupts = <0 111 4>;
78cd6a9d DN	170	};
	171	};
	172
	173	i2c0: i2c@ffc02800 {
	174	#address-cells = <1>;
	175	#size-cells = <0>;
	176	compatible = "snps,designware-i2c";
	177	reg = <0xffc02800 0x100>;
	178	interrupts = <0 103 4>;
788251fa	179	resets = <&rst I2C0_RESET>;
78cd6a9d DN	180	status = "disabled";
	181	};
	182
	183	i2c1: i2c@ffc02900 {
	184	#address-cells = <1>;
	185	#size-cells = <0>;
	186	compatible = "snps,designware-i2c";
	187	reg = <0xffc02900 0x100>;
	188	interrupts = <0 104 4>;
788251fa	189	resets = <&rst I2C1_RESET>;
78cd6a9d DN	190	status = "disabled";
	191	};
	192
	193	i2c2: i2c@ffc02a00 {
	194	#address-cells = <1>;
	195	#size-cells = <0>;
	196	compatible = "snps,designware-i2c";
	197	reg = <0xffc02a00 0x100>;
	198	interrupts = <0 105 4>;
788251fa	199	resets = <&rst I2C2_RESET>;
78cd6a9d DN	200	status = "disabled";
	201	};
	202
	203	i2c3: i2c@ffc02b00 {
	204	#address-cells = <1>;
	205	#size-cells = <0>;
	206	compatible = "snps,designware-i2c";
	207	reg = <0xffc02b00 0x100>;
	208	interrupts = <0 106 4>;
788251fa	209	resets = <&rst I2C3_RESET>;
78cd6a9d DN	210	status = "disabled";
	211	};
	212
	213	i2c4: i2c@ffc02c00 {
	214	#address-cells = <1>;
	215	#size-cells = <0>;
	216	compatible = "snps,designware-i2c";
	217	reg = <0xffc02c00 0x100>;
	218	interrupts = <0 107 4>;
788251fa	219	resets = <&rst I2C4_RESET>;
78cd6a9d DN	220	status = "disabled";
	221	};
	222
	223	mmc: dwmmc0@ff808000 {
	224	#address-cells = <1>;
	225	#size-cells = <0>;
	226	compatible = "altr,socfpga-dw-mshc";
	227	reg = <0xff808000 0x1000>;
	228	interrupts = <0 96 4>;
	229	fifo-depth = <0x400>;
788251fa DN	230	resets = <&rst SDMMC_RESET>;
788251fa DN	231	reset-names = "reset";
78cd6a9d DN	232	status = "disabled";
	233	};
	234
	235	ocram: sram@ffe00000 {
	236	compatible = "mmio-sram";
	237	reg = <0xffe00000 0x100000>;
	238	};
	239
	240	rst: rstmgr@ffd11000 {
	241	#reset-cells = <1>;
	242	compatible = "altr,rst-mgr";
	243	reg = <0xffd11000 0x1000>;
7691d626	244	altr,modrst-offset = <0x20>;
78cd6a9d DN	245	};
	246
	247	spi0: spi@ffda4000 {
	248	compatible = "snps,dw-apb-ssi";
	249	#address-cells = <1>;
	250	#size-cells = <0>;
	251	reg = <0xffda4000 0x1000>;
	252	interrupts = <0 101 4>;
	253	num-chipselect = <4>;
	254	bus-num = <0>;
	255	status = "disabled";
	256	};
	257
	258	spi1: spi@ffda5000 {
	259	compatible = "snps,dw-apb-ssi";
	260	#address-cells = <1>;
	261	#size-cells = <0>;
	262	reg = <0xffda5000 0x1000>;
	263	interrupts = <0 102 4>;
	264	num-chipselect = <4>;
	265	bus-num = <0>;
	266	status = "disabled";
	267	};
	268
	269	sysmgr: sysmgr@ffd12000 {
	270	compatible = "altr,sys-mgr", "syscon";
	271	reg = <0xffd12000 0x1000>;
	272	};
	273
	274	/* Local timer */
	275	timer {
	276	compatible = "arm,armv8-timer";
f2a89d3b MZ	277	interrupts = <1 13 0xf08>,
	278	<1 14 0xf08>,
	279	<1 11 0xf08>,
	280	<1 10 0xf08>;
78cd6a9d DN	281	};
	282
	283	timer0: timer0@ffc03000 {
	284	compatible = "snps,dw-apb-timer";
	285	interrupts = <0 113 4>;
	286	reg = <0xffc03000 0x100>;
	287	};
	288
	289	timer1: timer1@ffc03100 {
	290	compatible = "snps,dw-apb-timer";
	291	interrupts = <0 114 4>;
	292	reg = <0xffc03100 0x100>;
	293	};
	294
	295	timer2: timer2@ffd00000 {
	296	compatible = "snps,dw-apb-timer";
	297	interrupts = <0 115 4>;
	298	reg = <0xffd00000 0x100>;
	299	};
	300
	301	timer3: timer3@ffd00100 {
	302	compatible = "snps,dw-apb-timer";
	303	interrupts = <0 116 4>;
	304	reg = <0xffd00100 0x100>;
	305	};
	306
	307	uart0: serial0@ffc02000 {
	308	compatible = "snps,dw-apb-uart";
	309	reg = <0xffc02000 0x100>;
	310	interrupts = <0 108 4>;
	311	reg-shift = <2>;
	312	reg-io-width = <4>;
788251fa	313	resets = <&rst UART0_RESET>;
78cd6a9d DN	314	status = "disabled";
	315	};
	316
	317	uart1: serial1@ffc02100 {
	318	compatible = "snps,dw-apb-uart";
	319	reg = <0xffc02100 0x100>;
	320	interrupts = <0 109 4>;
	321	reg-shift = <2>;
	322	reg-io-width = <4>;
788251fa	323	resets = <&rst UART1_RESET>;
78cd6a9d DN	324	status = "disabled";
	325	};
	326
	327	usbphy0: usbphy@0 {
	328	#phy-cells = <0>;
	329	compatible = "usb-nop-xceiv";
	330	status = "okay";
	331	};
	332
	333	usb0: usb@ffb00000 {
	334	compatible = "snps,dwc2";
	335	reg = <0xffb00000 0x40000>;
	336	interrupts = <0 93 4>;
	337	phys = <&usbphy0>;
	338	phy-names = "usb2-phy";
788251fa DN	339	resets = <&rst USB0_RESET>;
788251fa DN	340	reset-names = "dwc2";
78cd6a9d DN	341	status = "disabled";
	342	};
	343
	344	usb1: usb@ffb40000 {
	345	compatible = "snps,dwc2";
	346	reg = <0xffb40000 0x40000>;
	347	interrupts = <0 94 4>;
	348	phys = <&usbphy0>;
	349	phy-names = "usb2-phy";
788251fa DN	350	resets = <&rst USB1_RESET>;
788251fa DN	351	reset-names = "dwc2";
78cd6a9d DN	352	status = "disabled";
	353	};
	354
	355	watchdog0: watchdog@ffd00200 {
	356	compatible = "snps,dw-wdt";
	357	reg = <0xffd00200 0x100>;
	358	interrupts = <0 117 4>;
788251fa	359	resets = <&rst WATCHDOG0_RESET>;
78cd6a9d DN	360	status = "disabled";
	361	};
	362
	363	watchdog1: watchdog@ffd00300 {
	364	compatible = "snps,dw-wdt";
	365	reg = <0xffd00300 0x100>;
	366	interrupts = <0 118 4>;
788251fa	367	resets = <&rst WATCHDOG1_RESET>;
78cd6a9d DN	368	status = "disabled";
	369	};
	370
	371	watchdog2: watchdog@ffd00400 {
	372	compatible = "snps,dw-wdt";
	373	reg = <0xffd00400 0x100>;
	374	interrupts = <0 125 4>;
788251fa	375	resets = <&rst WATCHDOG2_RESET>;
78cd6a9d DN	376	status = "disabled";
	377	};
	378
	379	watchdog3: watchdog@ffd00500 {
	380	compatible = "snps,dw-wdt";
	381	reg = <0xffd00500 0x100>;
	382	interrupts = <0 126 4>;
788251fa	383	resets = <&rst WATCHDOG3_RESET>;
78cd6a9d DN	384	status = "disabled";
	385	};
	386	};
	387	};