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c328666d NA |
1 | /* |
2 | * Copyright (c) 2016 BayLibre, SAS. | |
3 | * Author: Neil Armstrong <narmstrong@baylibre.com> | |
4 | * | |
5 | * Copyright (c) 2016 Endless Computers, Inc. | |
6 | * Author: Carlo Caione <carlo@endlessm.com> | |
7 | * | |
8 | * Copyright (c) 2016 Andreas Färber | |
9 | * | |
10 | * This file is dual-licensed: you can use it either under the terms | |
11 | * of the GPL or the X11 license, at your option. Note that this dual | |
12 | * licensing only applies to this file, and not this project as a | |
13 | * whole. | |
14 | * | |
15 | * a) This library is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of the | |
18 | * License, or (at your option) any later version. | |
19 | * | |
20 | * This library is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * Or, alternatively, | |
26 | * | |
27 | * b) Permission is hereby granted, free of charge, to any person | |
28 | * obtaining a copy of this software and associated documentation | |
29 | * files (the "Software"), to deal in the Software without | |
30 | * restriction, including without limitation the rights to use, | |
31 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
32 | * sell copies of the Software, and to permit persons to whom the | |
33 | * Software is furnished to do so, subject to the following | |
34 | * conditions: | |
35 | * | |
36 | * The above copyright notice and this permission notice shall be | |
37 | * included in all copies or substantial portions of the Software. | |
38 | * | |
39 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
40 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
41 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
42 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
43 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
44 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
45 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
46 | * OTHER DEALINGS IN THE SOFTWARE. | |
47 | */ | |
48 | ||
49 | #include <dt-bindings/gpio/gpio.h> | |
50 | #include <dt-bindings/interrupt-controller/irq.h> | |
51 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
52 | ||
53 | / { | |
54 | interrupt-parent = <&gic>; | |
55 | #address-cells = <2>; | |
56 | #size-cells = <2>; | |
57 | ||
58 | cpus { | |
59 | #address-cells = <0x2>; | |
60 | #size-cells = <0x0>; | |
61 | ||
62 | cpu0: cpu@0 { | |
63 | device_type = "cpu"; | |
64 | compatible = "arm,cortex-a53", "arm,armv8"; | |
65 | reg = <0x0 0x0>; | |
66 | enable-method = "psci"; | |
214ec523 | 67 | next-level-cache = <&l2>; |
c328666d NA |
68 | }; |
69 | ||
70 | cpu1: cpu@1 { | |
71 | device_type = "cpu"; | |
72 | compatible = "arm,cortex-a53", "arm,armv8"; | |
73 | reg = <0x0 0x1>; | |
74 | enable-method = "psci"; | |
214ec523 | 75 | next-level-cache = <&l2>; |
c328666d NA |
76 | }; |
77 | ||
78 | cpu2: cpu@2 { | |
79 | device_type = "cpu"; | |
80 | compatible = "arm,cortex-a53", "arm,armv8"; | |
81 | reg = <0x0 0x2>; | |
82 | enable-method = "psci"; | |
214ec523 | 83 | next-level-cache = <&l2>; |
c328666d NA |
84 | }; |
85 | ||
86 | cpu3: cpu@3 { | |
87 | device_type = "cpu"; | |
88 | compatible = "arm,cortex-a53", "arm,armv8"; | |
89 | reg = <0x0 0x3>; | |
90 | enable-method = "psci"; | |
214ec523 NA |
91 | next-level-cache = <&l2>; |
92 | }; | |
93 | ||
94 | l2: l2-cache0 { | |
95 | compatible = "cache"; | |
c328666d NA |
96 | }; |
97 | }; | |
98 | ||
99 | arm-pmu { | |
100 | compatible = "arm,cortex-a53-pmu"; | |
101 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
102 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
103 | <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, | |
104 | <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
105 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; | |
106 | }; | |
107 | ||
108 | psci { | |
109 | compatible = "arm,psci-0.2"; | |
110 | method = "smc"; | |
111 | }; | |
112 | ||
113 | timer { | |
114 | compatible = "arm,armv8-timer"; | |
115 | interrupts = <GIC_PPI 13 | |
116 | (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, | |
117 | <GIC_PPI 14 | |
118 | (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, | |
119 | <GIC_PPI 11 | |
120 | (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, | |
121 | <GIC_PPI 10 | |
122 | (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; | |
123 | }; | |
124 | ||
125 | xtal: xtal-clk { | |
126 | compatible = "fixed-clock"; | |
127 | clock-frequency = <24000000>; | |
128 | clock-output-names = "xtal"; | |
129 | #clock-cells = <0>; | |
130 | }; | |
131 | ||
132 | soc { | |
133 | compatible = "simple-bus"; | |
134 | #address-cells = <2>; | |
135 | #size-cells = <2>; | |
136 | ranges; | |
137 | ||
138 | cbus: cbus@c1100000 { | |
139 | compatible = "simple-bus"; | |
140 | reg = <0x0 0xc1100000 0x0 0x100000>; | |
141 | #address-cells = <2>; | |
142 | #size-cells = <2>; | |
143 | ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; | |
144 | ||
145 | uart_A: serial@84c0 { | |
146 | compatible = "amlogic,meson-uart"; | |
147 | reg = <0x0 0x84c0 0x0 0x14>; | |
148 | interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; | |
149 | clocks = <&xtal>; | |
150 | status = "disabled"; | |
151 | }; | |
152 | }; | |
153 | ||
154 | gic: interrupt-controller@c4301000 { | |
155 | compatible = "arm,gic-400"; | |
156 | reg = <0x0 0xc4301000 0 0x1000>, | |
157 | <0x0 0xc4302000 0 0x2000>, | |
158 | <0x0 0xc4304000 0 0x2000>, | |
159 | <0x0 0xc4306000 0 0x2000>; | |
160 | interrupt-controller; | |
161 | interrupts = <GIC_PPI 9 | |
162 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; | |
163 | #interrupt-cells = <3>; | |
164 | #address-cells = <0>; | |
165 | }; | |
166 | ||
167 | aobus: aobus@c8100000 { | |
168 | compatible = "simple-bus"; | |
169 | reg = <0x0 0xc8100000 0x0 0x100000>; | |
170 | #address-cells = <2>; | |
171 | #size-cells = <2>; | |
172 | ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; | |
173 | ||
174 | uart_AO: serial@4c0 { | |
175 | compatible = "amlogic,meson-uart"; | |
176 | reg = <0x0 0x004c0 0x0 0x14>; | |
177 | interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; | |
178 | clocks = <&xtal>; | |
179 | status = "disabled"; | |
180 | }; | |
181 | }; | |
182 | ||
183 | periphs: periphs@c8834000 { | |
184 | compatible = "simple-bus"; | |
185 | reg = <0x0 0xc8834000 0x0 0x2000>; | |
186 | #address-cells = <2>; | |
187 | #size-cells = <2>; | |
188 | ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; | |
189 | }; | |
190 | ||
191 | ||
192 | hiubus: hiubus@c883c000 { | |
193 | compatible = "simple-bus"; | |
194 | reg = <0x0 0xc883c000 0x0 0x2000>; | |
195 | #address-cells = <2>; | |
196 | #size-cells = <2>; | |
197 | ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; | |
198 | }; | |
199 | ||
200 | apb: apb@d0000000 { | |
201 | compatible = "simple-bus"; | |
202 | reg = <0x0 0xd0000000 0x0 0x200000>; | |
203 | #address-cells = <2>; | |
204 | #size-cells = <2>; | |
205 | ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; | |
206 | }; | |
207 | }; | |
208 | }; |