[mirror_ubuntu-eoan-kernel.git] / arch / arm64 / boot / dts / amlogic / meson-gxbb.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2016 Andreas Färber
 */

#include "meson-gx.dtsi"
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
#include <dt-bindings/clock/gxbb-clkc.h>
#include <dt-bindings/clock/gxbb-aoclkc.h>
#include <dt-bindings/reset/gxbb-aoclkc.h>

/ {
	compatible = "amlogic,meson-gxbb";

	soc {
		usb0_phy: phy@c0000000 {
			compatible = "amlogic,meson-gxbb-usb2-phy";
			#phy-cells = <0>;
			reg = <0x0 0xc0000000 0x0 0x20>;
			resets = <&reset RESET_USB_OTG>;
			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
			clock-names = "usb_general", "usb";
			status = "disabled";
		};

		usb1_phy: phy@c0000020 {
			compatible = "amlogic,meson-gxbb-usb2-phy";
			#phy-cells = <0>;
			reg = <0x0 0xc0000020 0x0 0x20>;
			resets = <&reset RESET_USB_OTG>;
			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
			clock-names = "usb_general", "usb";
			status = "disabled";
		};

		usb0: usb@c9000000 {
			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
			reg = <0x0 0xc9000000 0x0 0x40000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
			clock-names = "otg";
			phys = <&usb0_phy>;
			phy-names = "usb2-phy";
			dr_mode = "host";
			status = "disabled";
		};

		usb1: usb@c9100000 {
			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
			reg = <0x0 0xc9100000 0x0 0x40000>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
			clock-names = "otg";
			phys = <&usb1_phy>;
			phy-names = "usb2-phy";
			dr_mode = "host";
			status = "disabled";
		};
	};
};

&aobus {
	pinctrl_aobus: pinctrl@14 {
		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio_ao: bank@14 {
			reg = <0x0 0x00014 0x0 0x8>,
			      <0x0 0x0002c 0x0 0x4>,
			      <0x0 0x00024 0x0 0x8>;
			reg-names = "mux", "pull", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_aobus 0 0 14>;
		};

		uart_ao_a_pins: uart_ao_a {
			mux {
				groups = "uart_tx_ao_a", "uart_rx_ao_a";
				function = "uart_ao";
				bias-disable;
			};
		};

		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
			mux {
				groups = "uart_cts_ao_a",
				       "uart_rts_ao_a";
				function = "uart_ao";
				bias-disable;
			};
		};

		uart_ao_b_pins: uart_ao_b {
			mux {
				groups = "uart_tx_ao_b", "uart_rx_ao_b";
				function = "uart_ao_b";
				bias-disable;
			};
		};

		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
			mux {
				groups = "uart_cts_ao_b",
				       "uart_rts_ao_b";
				function = "uart_ao_b";
				bias-disable;
			};
		};

		remote_input_ao_pins: remote_input_ao {
			mux {
				groups = "remote_input_ao";
				function = "remote_input_ao";
				bias-disable;
			};
		};

		i2c_ao_pins: i2c_ao {
			mux {
				groups = "i2c_sck_ao",
				       "i2c_sda_ao";
				function = "i2c_ao";
				bias-disable;
			};
		};

		pwm_ao_a_3_pins: pwm_ao_a_3 {
			mux {
				groups = "pwm_ao_a_3";
				function = "pwm_ao_a_3";
				bias-disable;
			};
		};

		pwm_ao_a_6_pins: pwm_ao_a_6 {
			mux {
				groups = "pwm_ao_a_6";
				function = "pwm_ao_a_6";
				bias-disable;
			};
		};

		pwm_ao_a_12_pins: pwm_ao_a_12 {
			mux {
				groups = "pwm_ao_a_12";
				function = "pwm_ao_a_12";
				bias-disable;
			};
		};

		pwm_ao_b_pins: pwm_ao_b {
			mux {
				groups = "pwm_ao_b";
				function = "pwm_ao_b";
				bias-disable;
			};
		};

		i2s_am_clk_pins: i2s_am_clk {
			mux {
				groups = "i2s_am_clk";
				function = "i2s_out_ao";
				bias-disable;
			};
		};

		i2s_out_ao_clk_pins: i2s_out_ao_clk {
			mux {
				groups = "i2s_out_ao_clk";
				function = "i2s_out_ao";
				bias-disable;
			};
		};

		i2s_out_lr_clk_pins: i2s_out_lr_clk {
			mux {
				groups = "i2s_out_lr_clk";
				function = "i2s_out_ao";
				bias-disable;
			};
		};

		i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
			mux {
				groups = "i2s_out_ch01_ao";
				function = "i2s_out_ao";
				bias-disable;
			};
		};

		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
			mux {
				groups = "i2s_out_ch23_ao";
				function = "i2s_out_ao";
				bias-disable;
			};
		};

		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
			mux {
				groups = "i2s_out_ch45_ao";
				function = "i2s_out_ao";
				bias-disable;
			};
		};

		spdif_out_ao_6_pins: spdif_out_ao_6 {
			mux {
				groups = "spdif_out_ao_6";
				function = "spdif_out_ao";
			};
		};

		spdif_out_ao_13_pins: spdif_out_ao_13 {
			mux {
				groups = "spdif_out_ao_13";
				function = "spdif_out_ao";
				bias-disable;
			};
		};

		ao_cec_pins: ao_cec {
			mux {
				groups = "ao_cec";
				function = "cec_ao";
				bias-disable;
			};
		};

		ee_cec_pins: ee_cec {
			mux {
				groups = "ee_cec";
				function = "cec_ao";
				bias-disable;
			};
		};
	};
};

&apb {
	mali: gpu@c0000 {
		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
		reg = <0x0 0xc0000 0x0 0x40000>;
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "gp", "gpmmu", "pp", "pmu",
			"pp0", "ppmmu0", "pp1", "ppmmu1",
			"pp2", "ppmmu2";
		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
		clock-names = "bus", "core";

		/*
		 * Mali clocking is provided by two identical clock paths
		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
		 * free mux to safely change frequency while running.
		 */
		assigned-clocks = <&clkc CLKID_GP0_PLL>,
				  <&clkc CLKID_MALI_0_SEL>,
				  <&clkc CLKID_MALI_0>,
				  <&clkc CLKID_MALI>; /* Glitch free mux */
		assigned-clock-parents = <0>, /* Do Nothing */
					 <&clkc CLKID_GP0_PLL>,
					 <0>, /* Do Nothing */
					 <&clkc CLKID_MALI_0>;
		assigned-clock-rates = <744000000>,
				       <0>, /* Do Nothing */
				       <744000000>,
				       <0>; /* Do Nothing */
	};
};

&cbus {
	spifc: spi@8c80 {
		compatible = "amlogic,meson-gxbb-spifc";
		reg = <0x0 0x08c80 0x0 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clkc CLKID_SPI>;
		status = "disabled";
	};
};

&cec_AO {
	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
	clock-names = "core";
};

&clkc_AO {
	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
	clocks = <&xtal>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "mpeg-clk";
};

&efuse {
	clocks = <&clkc CLKID_EFUSE>;
};

&ethmac {
	clocks = <&clkc CLKID_ETH>,
		 <&clkc CLKID_FCLK_DIV2>,
		 <&clkc CLKID_MPLL2>;
	clock-names = "stmmaceth", "clkin0", "clkin1";
};

&gpio_intc {
	compatible = "amlogic,meson-gpio-intc",
		     "amlogic,meson-gxbb-gpio-intc";
	status = "okay";
};

&hdmi_tx {
	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
	resets = <&reset RESET_HDMITX_CAPB3>,
		 <&reset RESET_HDMI_SYSTEM_RESET>,
		 <&reset RESET_HDMI_TX>;
	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
	clocks = <&clkc CLKID_HDMI_PCLK>,
		 <&clkc CLKID_CLK81>,
		 <&clkc CLKID_GCLK_VENCI_INT0>;
	clock-names = "isfr", "iahb", "venci";
};

&sysctrl {
	clkc: clock-controller {
		compatible = "amlogic,gxbb-clkc";
		#clock-cells = <1>;
		clocks = <&xtal>;
		clock-names = "xtal";
	};
};

&hwrng {
	clocks = <&clkc CLKID_RNG0>;
	clock-names = "core";
};

&i2c_A {
	clocks = <&clkc CLKID_I2C>;
};

&i2c_AO {
	clocks = <&clkc CLKID_AO_I2C>;
};

&i2c_B {
	clocks = <&clkc CLKID_I2C>;
};

&i2c_C {
	clocks = <&clkc CLKID_I2C>;
};

&periphs {
	pinctrl_periphs: pinctrl@4b0 {
		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio: bank@4b0 {
			reg = <0x0 0x004b0 0x0 0x28>,
			      <0x0 0x004e8 0x0 0x14>,
			      <0x0 0x00520 0x0 0x14>,
			      <0x0 0x00430 0x0 0x40>;
			reg-names = "mux", "pull", "pull-enable", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_periphs 0 0 119>;
		};

		emmc_pins: emmc {
			mux {
				groups = "emmc_nand_d07",
				       "emmc_cmd",
				       "emmc_clk";
				function = "emmc";
				bias-disable;
			};
		};

		emmc_ds_pins: emmc-ds {
			mux {
				groups = "emmc_ds";
				function = "emmc";
				bias-disable;
			};
		};

		emmc_clk_gate_pins: emmc_clk_gate {
			mux {
				groups = "BOOT_8";
				function = "gpio_periphs";
				bias-pull-down;
			};
		};

		nor_pins: nor {
			mux {
				groups = "nor_d",
				       "nor_q",
				       "nor_c",
				       "nor_cs";
				function = "nor";
				bias-disable;
			};
		};

		spi_pins: spi-pins {
			mux {
				groups = "spi_miso",
					"spi_mosi",
					"spi_sclk";
				function = "spi";
				bias-disable;
			};
		};

		spi_ss0_pins: spi-ss0 {
			mux {
				groups = "spi_ss0";
				function = "spi";
				bias-disable;
			};
		};

		sdcard_pins: sdcard {
			mux {
				groups = "sdcard_d0",
				       "sdcard_d1",
				       "sdcard_d2",
				       "sdcard_d3",
				       "sdcard_cmd",
				       "sdcard_clk";
				function = "sdcard";
				bias-disable;
			};
		};

		sdcard_clk_gate_pins: sdcard_clk_gate {
			mux {
				groups = "CARD_2";
				function = "gpio_periphs";
				bias-pull-down;
			};
		};

		sdio_pins: sdio {
			mux {
				groups = "sdio_d0",
				       "sdio_d1",
				       "sdio_d2",
				       "sdio_d3",
				       "sdio_cmd",
				       "sdio_clk";
				function = "sdio";
				bias-disable;
			};
		};

		sdio_clk_gate_pins: sdio_clk_gate {
			mux {
				groups = "GPIOX_4";
				function = "gpio_periphs";
				bias-pull-down;
			};
		};

		sdio_irq_pins: sdio_irq {
			mux {
				groups = "sdio_irq";
				function = "sdio";
				bias-disable;
			};
		};

		uart_a_pins: uart_a {
			mux {
				groups = "uart_tx_a",
				       "uart_rx_a";
				function = "uart_a";
				bias-disable;
			};
		};

		uart_a_cts_rts_pins: uart_a_cts_rts {
			mux {
				groups = "uart_cts_a",
				       "uart_rts_a";
				function = "uart_a";
				bias-disable;
			};
		};

		uart_b_pins: uart_b {
			mux {
				groups = "uart_tx_b",
				       "uart_rx_b";
				function = "uart_b";
				bias-disable;
			};
		};

		uart_b_cts_rts_pins: uart_b_cts_rts {
			mux {
				groups = "uart_cts_b",
				       "uart_rts_b";
				function = "uart_b";
				bias-disable;
			};
		};

		uart_c_pins: uart_c {
			mux {
				groups = "uart_tx_c",
				       "uart_rx_c";
				function = "uart_c";
				bias-disable;
			};
		};

		uart_c_cts_rts_pins: uart_c_cts_rts {
			mux {
				groups = "uart_cts_c",
				       "uart_rts_c";
				function = "uart_c";
				bias-disable;
			};
		};

		i2c_a_pins: i2c_a {
			mux {
				groups = "i2c_sck_a",
				       "i2c_sda_a";
				function = "i2c_a";
				bias-disable;
			};
		};

		i2c_b_pins: i2c_b {
			mux {
				groups = "i2c_sck_b",
				       "i2c_sda_b";
				function = "i2c_b";
				bias-disable;
			};
		};

		i2c_c_pins: i2c_c {
			mux {
				groups = "i2c_sck_c",
				       "i2c_sda_c";
				function = "i2c_c";
				bias-disable;
			};
		};

		eth_rgmii_pins: eth-rgmii {
			mux {
				groups = "eth_mdio",
				       "eth_mdc",
				       "eth_clk_rx_clk",
				       "eth_rx_dv",
				       "eth_rxd0",
				       "eth_rxd1",
				       "eth_rxd2",
				       "eth_rxd3",
				       "eth_rgmii_tx_clk",
				       "eth_tx_en",
				       "eth_txd0",
				       "eth_txd1",
				       "eth_txd2",
				       "eth_txd3";
				function = "eth";
				bias-disable;
			};
		};

		eth_rmii_pins: eth-rmii {
			mux {
				groups = "eth_mdio",
				       "eth_mdc",
				       "eth_clk_rx_clk",
				       "eth_rx_dv",
				       "eth_rxd0",
				       "eth_rxd1",
				       "eth_tx_en",
				       "eth_txd0",
				       "eth_txd1";
				function = "eth";
				bias-disable;
			};
		};

		pwm_a_x_pins: pwm_a_x {
			mux {
				groups = "pwm_a_x";
				function = "pwm_a_x";
				bias-disable;
			};
		};

		pwm_a_y_pins: pwm_a_y {
			mux {
				groups = "pwm_a_y";
				function = "pwm_a_y";
				bias-disable;
			};
		};

		pwm_b_pins: pwm_b {
			mux {
				groups = "pwm_b";
				function = "pwm_b";
				bias-disable;
			};
		};

		pwm_d_pins: pwm_d {
			mux {
				groups = "pwm_d";
				function = "pwm_d";
				bias-disable;
			};
		};

		pwm_e_pins: pwm_e {
			mux {
				groups = "pwm_e";
				function = "pwm_e";
				bias-disable;
			};
		};

		pwm_f_x_pins: pwm_f_x {
			mux {
				groups = "pwm_f_x";
				function = "pwm_f_x";
				bias-disable;
			};
		};

		pwm_f_y_pins: pwm_f_y {
			mux {
				groups = "pwm_f_y";
				function = "pwm_f_y";
				bias-disable;
			};
		};

		hdmi_hpd_pins: hdmi_hpd {
			mux {
				groups = "hdmi_hpd";
				function = "hdmi_hpd";
				bias-disable;
			};
		};

		hdmi_i2c_pins: hdmi_i2c {
			mux {
				groups = "hdmi_sda", "hdmi_scl";
				function = "hdmi_i2c";
				bias-disable;
			};
		};

		i2sout_ch23_y_pins: i2sout_ch23_y {
			mux {
				groups = "i2sout_ch23_y";
				function = "i2s_out";
				bias-disable;
			};
		};

		i2sout_ch45_y_pins: i2sout_ch45_y {
			mux {
				groups = "i2sout_ch45_y";
				function = "i2s_out";
				bias-disable;
			};
		};

		i2sout_ch67_y_pins: i2sout_ch67_y {
			mux {
				groups = "i2sout_ch67_y";
				function = "i2s_out";
				bias-disable;
			};
		};

		spdif_out_y_pins: spdif_out_y {
			mux {
				groups = "spdif_out_y";
				function = "spdif_out";
				bias-disable;
			};
		};
	};
};

&pwrc_vpu {
	resets = <&reset RESET_VIU>,
		 <&reset RESET_VENC>,
		 <&reset RESET_VCBUS>,
		 <&reset RESET_BT656>,
		 <&reset RESET_DVIN_RESET>,
		 <&reset RESET_RDMA>,
		 <&reset RESET_VENCI>,
		 <&reset RESET_VENCP>,
		 <&reset RESET_VDAC>,
		 <&reset RESET_VDI6>,
		 <&reset RESET_VENCL>,
		 <&reset RESET_VID_LOCK>;
	clocks = <&clkc CLKID_VPU>,
	         <&clkc CLKID_VAPB>;
	clock-names = "vpu", "vapb";
	/*
	 * VPU clocking is provided by two identical clock paths
	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
	 * free mux to safely change frequency while running.
	 * Same for VAPB but with a final gate after the glitch free mux.
	 */
	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
			  <&clkc CLKID_VPU_0>,
			  <&clkc CLKID_VPU>, /* Glitch free mux */
			  <&clkc CLKID_VAPB_0_SEL>,
			  <&clkc CLKID_VAPB_0>,
			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
				 <0>, /* Do Nothing */
				 <&clkc CLKID_VPU_0>,
				 <&clkc CLKID_FCLK_DIV4>,
				 <0>, /* Do Nothing */
				 <&clkc CLKID_VAPB_0>;
	assigned-clock-rates = <0>, /* Do Nothing */
			       <666666666>,
			       <0>, /* Do Nothing */
			       <0>, /* Do Nothing */
			       <250000000>,
			       <0>; /* Do Nothing */
};

&saradc {
	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
	clocks = <&xtal>,
		 <&clkc CLKID_SAR_ADC>,
		 <&clkc CLKID_SAR_ADC_CLK>,
		 <&clkc CLKID_SAR_ADC_SEL>;
	clock-names = "clkin", "core", "adc_clk", "adc_sel";
};

&sd_emmc_a {
	clocks = <&clkc CLKID_SD_EMMC_A>,
		 <&clkc CLKID_SD_EMMC_A_CLK0>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
	resets = <&reset RESET_SD_EMMC_A>;
};

&sd_emmc_b {
	clocks = <&clkc CLKID_SD_EMMC_B>,
		 <&clkc CLKID_SD_EMMC_B_CLK0>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
	resets = <&reset RESET_SD_EMMC_B>;
};

&sd_emmc_c {
	clocks = <&clkc CLKID_SD_EMMC_C>,
		 <&clkc CLKID_SD_EMMC_C_CLK0>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
	resets = <&reset RESET_SD_EMMC_C>;
};

&spicc {
	clocks = <&clkc CLKID_SPICC>;
	clock-names = "core";
	resets = <&reset RESET_PERIPHS_SPICC>;
	num-cs = <1>;
};

&spifc {
	clocks = <&clkc CLKID_SPI>;
};

&uart_A {
	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_AO {
	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_AO_B {
	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_B {
	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_C {
	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
};

&vpu {
	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
	power-domains = <&pwrc_vpu>;
};
Commit	Line	Data
114abfe1	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4f24eda8 AF	2	/*
4f24eda8 AF	3	* Copyright (c) 2016 Andreas Färber
4f24eda8 AF	4	*/
4f24eda8 AF	5
c328666d	6	#include "meson-gx.dtsi"
f40d437f	7	#include <dt-bindings/gpio/meson-gxbb-gpio.h>
6d1a5c93	8	#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
c3929b72	9	#include <dt-bindings/clock/gxbb-clkc.h>
8d298f5b NA	10	#include <dt-bindings/clock/gxbb-aoclkc.h>
8d298f5b NA	11	#include <dt-bindings/reset/gxbb-aoclkc.h>
4f24eda8 AF	12
	13	/ {
	14	compatible = "amlogic,meson-gxbb";
4f24eda8	15
4f24eda8	16	soc {
566603e5 MB	17	usb0_phy: phy@c0000000 {
	18	compatible = "amlogic,meson-gxbb-usb2-phy";
	19	#phy-cells = <0>;
	20	reg = <0x0 0xc0000000 0x0 0x20>;
	21	resets = <&reset RESET_USB_OTG>;
	22	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
	23	clock-names = "usb_general", "usb";
	24	status = "disabled";
	25	};
	26
	27	usb1_phy: phy@c0000020 {
	28	compatible = "amlogic,meson-gxbb-usb2-phy";
	29	#phy-cells = <0>;
	30	reg = <0x0 0xc0000020 0x0 0x20>;
a5b1ef3c	31	resets = <&reset RESET_USB_OTG>;
566603e5 MB	32	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
	33	clock-names = "usb_general", "usb";
	34	status = "disabled";
	35	};
	36
c328666d NA	37	usb0: usb@c9000000 {
	38	compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
	39	reg = <0x0 0xc9000000 0x0 0x40000>;
	40	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	41	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
	42	clock-names = "otg";
	43	phys = <&usb0_phy>;
	44	phy-names = "usb2-phy";
	45	dr_mode = "host";
	46	status = "disabled";
	47	};
4f24eda8	48
c328666d NA	49	usb1: usb@c9100000 {
	50	compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
	51	reg = <0x0 0xc9100000 0x0 0x40000>;
	52	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	53	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
	54	clock-names = "otg";
	55	phys = <&usb1_phy>;
	56	phy-names = "usb2-phy";
	57	dr_mode = "host";
	58	status = "disabled";
	59	};
c328666d NA	60	};
	61	};
	62
c328666d NA	63	&aobus {
	64	pinctrl_aobus: pinctrl@14 {
	65	compatible = "amlogic,meson-gxbb-aobus-pinctrl";
	66	#address-cells = <2>;
	67	#size-cells = <2>;
	68	ranges;
8e6320dd	69
c328666d NA	70	gpio_ao: bank@14 {
	71	reg = <0x0 0x00014 0x0 0x8>,
	72	<0x0 0x0002c 0x0 0x4>,
	73	<0x0 0x00024 0x0 0x8>;
	74	reg-names = "mux", "pull", "gpio";
	75	gpio-controller;
	76	#gpio-cells = <2>;
18ae17bc	77	gpio-ranges = <&pinctrl_aobus 0 0 14>;
c328666d NA	78	};
	79
	80	uart_ao_a_pins: uart_ao_a {
	81	mux {
	82	groups = "uart_tx_ao_a", "uart_rx_ao_a";
	83	function = "uart_ao";
1c5cc1c8	84	bias-disable;
8e6320dd	85	};
c328666d	86	};
8e6320dd	87
261e1d5c MB	88	uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
	89	mux {
	90	groups = "uart_cts_ao_a",
	91	"uart_rts_ao_a";
	92	function = "uart_ao";
1c5cc1c8	93	bias-disable;
261e1d5c MB	94	};
	95	};
	96
890a96a2 MB	97	uart_ao_b_pins: uart_ao_b {
	98	mux {
	99	groups = "uart_tx_ao_b", "uart_rx_ao_b";
	100	function = "uart_ao_b";
1c5cc1c8	101	bias-disable;
890a96a2 MB	102	};
	103	};
	104
261e1d5c MB	105	uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
	106	mux {
	107	groups = "uart_cts_ao_b",
	108	"uart_rts_ao_b";
	109	function = "uart_ao_b";
1c5cc1c8	110	bias-disable;
261e1d5c MB	111	};
	112	};
	113
c328666d NA	114	remote_input_ao_pins: remote_input_ao {
	115	mux {
	116	groups = "remote_input_ao";
	117	function = "remote_input_ao";
1c5cc1c8	118	bias-disable;
8f14a893	119	};
c328666d	120	};
8f14a893	121
c328666d NA	122	i2c_ao_pins: i2c_ao {
	123	mux {
	124	groups = "i2c_sck_ao",
	125	"i2c_sda_ao";
	126	function = "i2c_ao";
1c5cc1c8	127	bias-disable;
8f14a893	128	};
c328666d	129	};
8f14a893	130
c328666d NA	131	pwm_ao_a_3_pins: pwm_ao_a_3 {
	132	mux {
	133	groups = "pwm_ao_a_3";
	134	function = "pwm_ao_a_3";
1c5cc1c8	135	bias-disable;
8f14a893	136	};
c328666d	137	};
8f14a893	138
c328666d NA	139	pwm_ao_a_6_pins: pwm_ao_a_6 {
	140	mux {
	141	groups = "pwm_ao_a_6";
	142	function = "pwm_ao_a_6";
1c5cc1c8	143	bias-disable;
8e6320dd	144	};
c328666d	145	};
f759b640	146
c328666d NA	147	pwm_ao_a_12_pins: pwm_ao_a_12 {
	148	mux {
	149	groups = "pwm_ao_a_12";
	150	function = "pwm_ao_a_12";
1c5cc1c8	151	bias-disable;
f759b640	152	};
c328666d	153	};
e9c9b651	154
c328666d NA	155	pwm_ao_b_pins: pwm_ao_b {
	156	mux {
	157	groups = "pwm_ao_b";
	158	function = "pwm_ao_b";
1c5cc1c8	159	bias-disable;
e9c9b651	160	};
c328666d	161	};
c328666d	162
552b1e56	163	i2s_am_clk_pins: i2s_am_clk {
	164	mux {
	165	groups = "i2s_am_clk";
	166	function = "i2s_out_ao";
1c5cc1c8	167	bias-disable;
552b1e56	168	};
552b1e56	169	};
c328666d	170
552b1e56	171	i2s_out_ao_clk_pins: i2s_out_ao_clk {
	172	mux {
	173	groups = "i2s_out_ao_clk";
	174	function = "i2s_out_ao";
1c5cc1c8	175	bias-disable;
552b1e56	176	};
552b1e56	177	};
c328666d	178
552b1e56	179	i2s_out_lr_clk_pins: i2s_out_lr_clk {
	180	mux {
	181	groups = "i2s_out_lr_clk";
	182	function = "i2s_out_ao";
1c5cc1c8	183	bias-disable;
552b1e56	184	};
	185	};
	186
	187	i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
	188	mux {
	189	groups = "i2s_out_ch01_ao";
	190	function = "i2s_out_ao";
1c5cc1c8	191	bias-disable;
552b1e56	192	};
	193	};
	194
	195	i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
	196	mux {
	197	groups = "i2s_out_ch23_ao";
	198	function = "i2s_out_ao";
1c5cc1c8	199	bias-disable;
552b1e56	200	};
	201	};
	202
	203	i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
	204	mux {
	205	groups = "i2s_out_ch45_ao";
	206	function = "i2s_out_ao";
1c5cc1c8	207	bias-disable;
552b1e56	208	};
552b1e56	209	};
07a4652f	210
	211	spdif_out_ao_6_pins: spdif_out_ao_6 {
	212	mux {
	213	groups = "spdif_out_ao_6";
	214	function = "spdif_out_ao";
	215	};
	216	};
	217
	218	spdif_out_ao_13_pins: spdif_out_ao_13 {
	219	mux {
	220	groups = "spdif_out_ao_13";
	221	function = "spdif_out_ao";
1c5cc1c8	222	bias-disable;
07a4652f	223	};
07a4652f	224	};
a679f5d2 NA	225
	226	ao_cec_pins: ao_cec {
	227	mux {
	228	groups = "ao_cec";
	229	function = "cec_ao";
1c5cc1c8	230	bias-disable;
a679f5d2 NA	231	};
	232	};
	233
	234	ee_cec_pins: ee_cec {
	235	mux {
	236	groups = "ee_cec";
	237	function = "cec_ao";
1c5cc1c8	238	bias-disable;
a679f5d2 NA	239	};
a679f5d2 NA	240	};
c328666d NA	241	};
	242	};
	243
8d7c7711 AF	244	&apb {
	245	mali: gpu@c0000 {
	246	compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
	247	reg = <0x0 0xc0000 0x0 0x40000>;
	248	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	249	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	250	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	251	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	252	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
	253	<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	254	<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
	255	<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
	256	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	257	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	258	interrupt-names = "gp", "gpmmu", "pp", "pmu",
	259	"pp0", "ppmmu0", "pp1", "ppmmu1",
	260	"pp2", "ppmmu2";
	261	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
	262	clock-names = "bus", "core";
	263
	264	/*
	265	* Mali clocking is provided by two identical clock paths
	266	* MALI_0 and MALI_1 muxed to a single clock by a glitch
	267	* free mux to safely change frequency while running.
	268	*/
97ac0093 NA	269	assigned-clocks = <&clkc CLKID_GP0_PLL>,
97ac0093 NA	270	<&clkc CLKID_MALI_0_SEL>,
8d7c7711 AF	271	<&clkc CLKID_MALI_0>,
8d7c7711 AF	272	<&clkc CLKID_MALI>; /* Glitch free mux */
97ac0093 NA	273	assigned-clock-parents = <0>, /* Do Nothing */
97ac0093 NA	274	<&clkc CLKID_GP0_PLL>,
8d7c7711 AF	275	<0>, /* Do Nothing */
8d7c7711 AF	276	<&clkc CLKID_MALI_0>;
97ac0093 NA	277	assigned-clock-rates = <744000000>,
	278	<0>, /* Do Nothing */
	279	<744000000>,
8d7c7711 AF	280	<0>; /* Do Nothing */
	281	};
	282	};
	283
	284	&cbus {
	285	spifc: spi@8c80 {
	286	compatible = "amlogic,meson-gxbb-spifc";
	287	reg = <0x0 0x08c80 0x0 0x80>;
	288	#address-cells = <1>;
	289	#size-cells = <0>;
	290	clocks = <&clkc CLKID_SPI>;
	291	status = "disabled";
	292	};
	293	};
	294
b16c71c9 NA	295	&cec_AO {
	296	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
	297	clock-names = "core";
	298	};
	299
7fd2c355 NA	300	&clkc_AO {
7fd2c355 NA	301	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
16361ff2 JB	302	clocks = <&xtal>, <&clkc CLKID_CLK81>;
16361ff2 JB	303	clock-names = "xtal", "mpeg-clk";
7fd2c355 NA	304	};
7fd2c355 NA	305
eed5afc6 JB	306	&efuse {
	307	clocks = <&clkc CLKID_EFUSE>;
	308	};
	309
8d7c7711 AF	310	&ethmac {
	311	clocks = <&clkc CLKID_ETH>,
	312	<&clkc CLKID_FCLK_DIV2>,
	313	<&clkc CLKID_MPLL2>;
	314	clock-names = "stmmaceth", "clkin0", "clkin1";
	315	};
	316
9dbb56ea JB	317	&gpio_intc {
	318	compatible = "amlogic,meson-gpio-intc",
	319	"amlogic,meson-gxbb-gpio-intc";
	320	status = "okay";
	321	};
	322
8d7c7711 AF	323	&hdmi_tx {
	324	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
	325	resets = <&reset RESET_HDMITX_CAPB3>,
	326	<&reset RESET_HDMI_SYSTEM_RESET>,
	327	<&reset RESET_HDMI_TX>;
	328	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
	329	clocks = <&clkc CLKID_HDMI_PCLK>,
	330	<&clkc CLKID_CLK81>,
	331	<&clkc CLKID_GCLK_VENCI_INT0>;
	332	clock-names = "isfr", "iahb", "venci";
	333	};
	334
6f95c8cd JB	335	&sysctrl {
6f95c8cd JB	336	clkc: clock-controller {
8d7c7711 AF	337	compatible = "amlogic,gxbb-clkc";
8d7c7711 AF	338	#clock-cells = <1>;
16361ff2 JB	339	clocks = <&xtal>;
16361ff2 JB	340	clock-names = "xtal";
8d7c7711 AF	341	};
	342	};
	343
	344	&hwrng {
	345	clocks = <&clkc CLKID_RNG0>;
	346	clock-names = "core";
	347	};
	348
	349	&i2c_A {
	350	clocks = <&clkc CLKID_I2C>;
	351	};
	352
	353	&i2c_AO {
	354	clocks = <&clkc CLKID_AO_I2C>;
	355	};
	356
	357	&i2c_B {
	358	clocks = <&clkc CLKID_I2C>;
	359	};
	360
	361	&i2c_C {
	362	clocks = <&clkc CLKID_I2C>;
	363	};
	364
c328666d	365	&periphs {
c328666d NA	366	pinctrl_periphs: pinctrl@4b0 {
	367	compatible = "amlogic,meson-gxbb-periphs-pinctrl";
	368	#address-cells = <2>;
	369	#size-cells = <2>;
	370	ranges;
	371
	372	gpio: bank@4b0 {
	373	reg = <0x0 0x004b0 0x0 0x28>,
	374	<0x0 0x004e8 0x0 0x14>,
9ef366a4	375	<0x0 0x00520 0x0 0x14>,
c328666d NA	376	<0x0 0x00430 0x0 0x40>;
	377	reg-names = "mux", "pull", "pull-enable", "gpio";
	378	gpio-controller;
	379	#gpio-cells = <2>;
7dbe78e5	380	gpio-ranges = <&pinctrl_periphs 0 0 119>;
c328666d	381	};
1befc626	382
c328666d NA	383	emmc_pins: emmc {
	384	mux {
	385	groups = "emmc_nand_d07",
	386	"emmc_cmd",
ab36be66 NA	387	"emmc_clk";
ab36be66 NA	388	function = "emmc";
96a13691	389	bias-disable;
ab36be66 NA	390	};
	391	};
	392
	393	emmc_ds_pins: emmc-ds {
	394	mux {
	395	groups = "emmc_ds";
c328666d	396	function = "emmc";
96a13691	397	bias-disable;
1befc626	398	};
c328666d	399	};
1befc626	400
67e7607f JB	401	emmc_clk_gate_pins: emmc_clk_gate {
	402	mux {
	403	groups = "BOOT_8";
	404	function = "gpio_periphs";
67e7607f JB	405	bias-pull-down;
	406	};
	407	};
	408
c328666d NA	409	nor_pins: nor {
	410	mux {
	411	groups = "nor_d",
	412	"nor_q",
	413	"nor_c",
	414	"nor_cs";
	415	function = "nor";
1c5cc1c8	416	bias-disable;
1befc626	417	};
c328666d	418	};
1befc626	419
68ecb5c1	420	spi_pins: spi-pins {
ec0a8260 NA	421	mux {
	422	groups = "spi_miso",
	423	"spi_mosi",
	424	"spi_sclk";
	425	function = "spi";
1c5cc1c8	426	bias-disable;
ec0a8260 NA	427	};
	428	};
	429
	430	spi_ss0_pins: spi-ss0 {
	431	mux {
	432	groups = "spi_ss0";
	433	function = "spi";
1c5cc1c8	434	bias-disable;
ec0a8260 NA	435	};
	436	};
	437
c328666d NA	438	sdcard_pins: sdcard {
	439	mux {
	440	groups = "sdcard_d0",
	441	"sdcard_d1",
	442	"sdcard_d2",
	443	"sdcard_d3",
	444	"sdcard_cmd",
	445	"sdcard_clk";
	446	function = "sdcard";
96a13691	447	bias-disable;
1befc626	448	};
4f24eda8 AF	449	};
4f24eda8 AF	450
67e7607f JB	451	sdcard_clk_gate_pins: sdcard_clk_gate {
	452	mux {
	453	groups = "CARD_2";
	454	function = "gpio_periphs";
67e7607f JB	455	bias-pull-down;
	456	};
	457	};
	458
c328666d NA	459	sdio_pins: sdio {
	460	mux {
	461	groups = "sdio_d0",
	462	"sdio_d1",
	463	"sdio_d2",
	464	"sdio_d3",
	465	"sdio_cmd",
	466	"sdio_clk";
	467	function = "sdio";
96a13691	468	bias-disable;
f40d437f	469	};
c328666d	470	};
f40d437f	471
67e7607f JB	472	sdio_clk_gate_pins: sdio_clk_gate {
	473	mux {
	474	groups = "GPIOX_4";
	475	function = "gpio_periphs";
67e7607f JB	476	bias-pull-down;
	477	};
	478	};
	479
c328666d NA	480	sdio_irq_pins: sdio_irq {
	481	mux {
	482	groups = "sdio_irq";
	483	function = "sdio";
1c5cc1c8	484	bias-disable;
f40d437f	485	};
c328666d	486	};
f40d437f	487
c328666d NA	488	uart_a_pins: uart_a {
	489	mux {
	490	groups = "uart_tx_a",
	491	"uart_rx_a";
	492	function = "uart_a";
1c5cc1c8	493	bias-disable;
4f24eda8	494	};
c328666d	495	};
c58d7785	496
261e1d5c MB	497	uart_a_cts_rts_pins: uart_a_cts_rts {
	498	mux {
	499	groups = "uart_cts_a",
	500	"uart_rts_a";
	501	function = "uart_a";
1c5cc1c8	502	bias-disable;
261e1d5c MB	503	};
	504	};
	505
c328666d NA	506	uart_b_pins: uart_b {
	507	mux {
	508	groups = "uart_tx_b",
	509	"uart_rx_b";
	510	function = "uart_b";
1c5cc1c8	511	bias-disable;
c58d7785	512	};
c328666d	513	};
8f14a893	514
261e1d5c MB	515	uart_b_cts_rts_pins: uart_b_cts_rts {
	516	mux {
	517	groups = "uart_cts_b",
	518	"uart_rts_b";
	519	function = "uart_b";
1c5cc1c8	520	bias-disable;
261e1d5c MB	521	};
	522	};
	523
c328666d NA	524	uart_c_pins: uart_c {
	525	mux {
	526	groups = "uart_tx_c",
	527	"uart_rx_c";
	528	function = "uart_c";
1c5cc1c8	529	bias-disable;
8f14a893	530	};
c328666d	531	};
1befc626	532
261e1d5c MB	533	uart_c_cts_rts_pins: uart_c_cts_rts {
	534	mux {
	535	groups = "uart_cts_c",
	536	"uart_rts_c";
	537	function = "uart_c";
1c5cc1c8	538	bias-disable;
261e1d5c MB	539	};
	540	};
	541
c328666d NA	542	i2c_a_pins: i2c_a {
	543	mux {
	544	groups = "i2c_sck_a",
	545	"i2c_sda_a";
	546	function = "i2c_a";
1c5cc1c8	547	bias-disable;
1befc626	548	};
4f24eda8 AF	549	};
4f24eda8 AF	550
c328666d NA	551	i2c_b_pins: i2c_b {
	552	mux {
	553	groups = "i2c_sck_b",
	554	"i2c_sda_b";
	555	function = "i2c_b";
1c5cc1c8	556	bias-disable;
c328666d NA	557	};
c328666d NA	558	};
f40d437f	559
c328666d NA	560	i2c_c_pins: i2c_c {
	561	mux {
	562	groups = "i2c_sck_c",
	563	"i2c_sda_c";
	564	function = "i2c_c";
1c5cc1c8	565	bias-disable;
4b7bed38	566	};
c328666d	567	};
4b7bed38	568
3be2d9cf	569	eth_rgmii_pins: eth-rgmii {
c328666d NA	570	mux {
	571	groups = "eth_mdio",
	572	"eth_mdc",
	573	"eth_clk_rx_clk",
	574	"eth_rx_dv",
	575	"eth_rxd0",
	576	"eth_rxd1",
	577	"eth_rxd2",
	578	"eth_rxd3",
	579	"eth_rgmii_tx_clk",
	580	"eth_tx_en",
	581	"eth_txd0",
	582	"eth_txd1",
	583	"eth_txd2",
	584	"eth_txd3";
	585	function = "eth";
1c5cc1c8	586	bias-disable;
f40d437f	587	};
fab6b48c CC	588	};
fab6b48c CC	589
3be2d9cf NA	590	eth_rmii_pins: eth-rmii {
	591	mux {
	592	groups = "eth_mdio",
	593	"eth_mdc",
	594	"eth_clk_rx_clk",
	595	"eth_rx_dv",
	596	"eth_rxd0",
	597	"eth_rxd1",
	598	"eth_tx_en",
	599	"eth_txd0",
	600	"eth_txd1";
	601	function = "eth";
1c5cc1c8	602	bias-disable;
3be2d9cf NA	603	};
	604	};
	605
c328666d NA	606	pwm_a_x_pins: pwm_a_x {
	607	mux {
	608	groups = "pwm_a_x";
	609	function = "pwm_a_x";
1c5cc1c8	610	bias-disable;
c328666d NA	611	};
c328666d NA	612	};
ba6a6c7f	613
c328666d NA	614	pwm_a_y_pins: pwm_a_y {
	615	mux {
	616	groups = "pwm_a_y";
	617	function = "pwm_a_y";
1c5cc1c8	618	bias-disable;
ba6a6c7f	619	};
c328666d	620	};
7b5682c6	621
c328666d NA	622	pwm_b_pins: pwm_b {
	623	mux {
	624	groups = "pwm_b";
	625	function = "pwm_b";
1c5cc1c8	626	bias-disable;
7b5682c6	627	};
fab6b48c CC	628	};
fab6b48c CC	629
c328666d NA	630	pwm_d_pins: pwm_d {
	631	mux {
	632	groups = "pwm_d";
	633	function = "pwm_d";
1c5cc1c8	634	bias-disable;
c328666d	635	};
4f24eda8	636	};
8c5509f0	637
c328666d NA	638	pwm_e_pins: pwm_e {
	639	mux {
	640	groups = "pwm_e";
	641	function = "pwm_e";
1c5cc1c8	642	bias-disable;
c328666d	643	};
566603e5 MB	644	};
566603e5 MB	645
c328666d NA	646	pwm_f_x_pins: pwm_f_x {
	647	mux {
	648	groups = "pwm_f_x";
	649	function = "pwm_f_x";
1c5cc1c8	650	bias-disable;
c328666d	651	};
566603e5 MB	652	};
566603e5 MB	653
c328666d NA	654	pwm_f_y_pins: pwm_f_y {
	655	mux {
	656	groups = "pwm_f_y";
	657	function = "pwm_f_y";
1c5cc1c8	658	bias-disable;
c328666d	659	};
8c5509f0	660	};
b949165c NA	661
	662	hdmi_hpd_pins: hdmi_hpd {
	663	mux {
	664	groups = "hdmi_hpd";
	665	function = "hdmi_hpd";
1c5cc1c8	666	bias-disable;
b949165c NA	667	};
	668	};
	669
	670	hdmi_i2c_pins: hdmi_i2c {
	671	mux {
	672	groups = "hdmi_sda", "hdmi_scl";
	673	function = "hdmi_i2c";
1c5cc1c8	674	bias-disable;
b949165c NA	675	};
b949165c NA	676	};
552b1e56	677
	678	i2sout_ch23_y_pins: i2sout_ch23_y {
	679	mux {
	680	groups = "i2sout_ch23_y";
	681	function = "i2s_out";
1c5cc1c8	682	bias-disable;
552b1e56	683	};
	684	};
	685
	686	i2sout_ch45_y_pins: i2sout_ch45_y {
	687	mux {
	688	groups = "i2sout_ch45_y";
	689	function = "i2s_out";
1c5cc1c8	690	bias-disable;
552b1e56	691	};
	692	};
	693
	694	i2sout_ch67_y_pins: i2sout_ch67_y {
	695	mux {
	696	groups = "i2sout_ch67_y";
	697	function = "i2s_out";
1c5cc1c8	698	bias-disable;
552b1e56	699	};
552b1e56	700	};
07a4652f	701
	702	spdif_out_y_pins: spdif_out_y {
	703	mux {
	704	groups = "spdif_out_y";
	705	function = "spdif_out";
1c5cc1c8	706	bias-disable;
07a4652f	707	};
07a4652f	708	};
4f24eda8 AF	709	};
4f24eda8 AF	710	};
c328666d	711
74d1c6e9 NA	712	&pwrc_vpu {
	713	resets = <&reset RESET_VIU>,
	714	<&reset RESET_VENC>,
	715	<&reset RESET_VCBUS>,
	716	<&reset RESET_BT656>,
	717	<&reset RESET_DVIN_RESET>,
	718	<&reset RESET_RDMA>,
	719	<&reset RESET_VENCI>,
	720	<&reset RESET_VENCP>,
	721	<&reset RESET_VDAC>,
	722	<&reset RESET_VDI6>,
	723	<&reset RESET_VENCL>,
	724	<&reset RESET_VID_LOCK>;
	725	clocks = <&clkc CLKID_VPU>,
	726	<&clkc CLKID_VAPB>;
	727	clock-names = "vpu", "vapb";
	728	/*
	729	* VPU clocking is provided by two identical clock paths
	730	* VPU_0 and VPU_1 muxed to a single clock by a glitch
	731	* free mux to safely change frequency while running.
	732	* Same for VAPB but with a final gate after the glitch free mux.
	733	*/
	734	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
	735	<&clkc CLKID_VPU_0>,
	736	<&clkc CLKID_VPU>, /* Glitch free mux */
	737	<&clkc CLKID_VAPB_0_SEL>,
	738	<&clkc CLKID_VAPB_0>,
	739	<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
	740	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
	741	<0>, /* Do Nothing */
	742	<&clkc CLKID_VPU_0>,
	743	<&clkc CLKID_FCLK_DIV4>,
	744	<0>, /* Do Nothing */
	745	<&clkc CLKID_VAPB_0>;
	746	assigned-clock-rates = <0>, /* Do Nothing */
	747	<666666666>,
	748	<0>, /* Do Nothing */
	749	<0>, /* Do Nothing */
	750	<250000000>,
	751	<0>; /* Do Nothing */
	752	};
	753
bd80ef5e MB	754	&saradc {
	755	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
	756	clocks = <&xtal>,
	757	<&clkc CLKID_SAR_ADC>,
bd80ef5e MB	758	<&clkc CLKID_SAR_ADC_CLK>,
bd80ef5e MB	759	<&clkc CLKID_SAR_ADC_SEL>;
e102da49	760	clock-names = "clkin", "core", "adc_clk", "adc_sel";
bd80ef5e MB	761	};
bd80ef5e MB	762
ef8d2ffe KH	763	&sd_emmc_a {
ef8d2ffe KH	764	clocks = <&clkc CLKID_SD_EMMC_A>,
50662499	765	<&clkc CLKID_SD_EMMC_A_CLK0>,
ef8d2ffe KH	766	<&clkc CLKID_FCLK_DIV2>;
ef8d2ffe KH	767	clock-names = "core", "clkin0", "clkin1";
098e5303	768	resets = <&reset RESET_SD_EMMC_A>;
ef8d2ffe KH	769	};
	770
	771	&sd_emmc_b {
	772	clocks = <&clkc CLKID_SD_EMMC_B>,
50662499	773	<&clkc CLKID_SD_EMMC_B_CLK0>,
ef8d2ffe KH	774	<&clkc CLKID_FCLK_DIV2>;
ef8d2ffe KH	775	clock-names = "core", "clkin0", "clkin1";
098e5303	776	resets = <&reset RESET_SD_EMMC_B>;
ef8d2ffe KH	777	};
	778
	779	&sd_emmc_c {
	780	clocks = <&clkc CLKID_SD_EMMC_C>,
50662499	781	<&clkc CLKID_SD_EMMC_C_CLK0>,
ef8d2ffe KH	782	<&clkc CLKID_FCLK_DIV2>;
ef8d2ffe KH	783	clock-names = "core", "clkin0", "clkin1";
098e5303	784	resets = <&reset RESET_SD_EMMC_C>;
ef8d2ffe	785	};
fafdbdf7	786
fa808631 NA	787	&spicc {
	788	clocks = <&clkc CLKID_SPICC>;
	789	clock-names = "core";
	790	resets = <&reset RESET_PERIPHS_SPICC>;
	791	num-cs = <1>;
	792	};
	793
04b36df4 NA	794	&spifc {
	795	clocks = <&clkc CLKID_SPI>;
	796	};
	797
f72d6f60 HK	798	&uart_A {
	799	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
	800	clock-names = "xtal", "pclk", "baud";
	801	};
	802
	803	&uart_AO {
9adda353	804	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
f72d6f60 HK	805	clock-names = "xtal", "pclk", "baud";
	806	};
	807
	808	&uart_AO_B {
9adda353	809	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
f72d6f60 HK	810	clock-names = "xtal", "pclk", "baud";
	811	};
	812
	813	&uart_B {
	814	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
39005e56	815	clock-names = "xtal", "pclk", "baud";
f72d6f60 HK	816	};
	817
	818	&uart_C {
	819	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
39005e56	820	clock-names = "xtal", "pclk", "baud";
f72d6f60 HK	821	};
f72d6f60 HK	822
fafdbdf7 NA	823	&vpu {
fafdbdf7 NA	824	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
74d1c6e9	825	power-domains = <&pwrc_vpu>;
fafdbdf7	826	};