[mirror_ubuntu-eoan-kernel.git] / arch / arm64 / boot / dts / amlogic / meson-gxbb.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2016 Andreas Färber
 */

#include "meson-gx.dtsi"
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
#include <dt-bindings/clock/gxbb-clkc.h>
#include <dt-bindings/clock/gxbb-aoclkc.h>
#include <dt-bindings/reset/gxbb-aoclkc.h>

/ {
	compatible = "amlogic,meson-gxbb";

	soc {
		usb0_phy: phy@c0000000 {
			compatible = "amlogic,meson-gxbb-usb2-phy";
			#phy-cells = <0>;
			reg = <0x0 0xc0000000 0x0 0x20>;
			resets = <&reset RESET_USB_OTG>;
			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
			clock-names = "usb_general", "usb";
			status = "disabled";
		};

		usb1_phy: phy@c0000020 {
			compatible = "amlogic,meson-gxbb-usb2-phy";
			#phy-cells = <0>;
			reg = <0x0 0xc0000020 0x0 0x20>;
			resets = <&reset RESET_USB_OTG>;
			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
			clock-names = "usb_general", "usb";
			status = "disabled";
		};

		usb0: usb@c9000000 {
			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
			reg = <0x0 0xc9000000 0x0 0x40000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
			clock-names = "otg";
			phys = <&usb0_phy>;
			phy-names = "usb2-phy";
			dr_mode = "host";
			status = "disabled";
		};

		usb1: usb@c9100000 {
			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
			reg = <0x0 0xc9100000 0x0 0x40000>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
			clock-names = "otg";
			phys = <&usb1_phy>;
			phy-names = "usb2-phy";
			dr_mode = "host";
			status = "disabled";
		};
	};
};

&aobus {
	pinctrl_aobus: pinctrl@14 {
		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio_ao: bank@14 {
			reg = <0x0 0x00014 0x0 0x8>,
			      <0x0 0x0002c 0x0 0x4>,
			      <0x0 0x00024 0x0 0x8>;
			reg-names = "mux", "pull", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_aobus 0 0 14>;
		};

		uart_ao_a_pins: uart_ao_a {
			mux {
				groups = "uart_tx_ao_a", "uart_rx_ao_a";
				function = "uart_ao";
				bias-disable;
			};
		};

		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
			mux {
				groups = "uart_cts_ao_a",
				       "uart_rts_ao_a";
				function = "uart_ao";
				bias-disable;
			};
		};

		uart_ao_b_pins: uart_ao_b {
			mux {
				groups = "uart_tx_ao_b", "uart_rx_ao_b";
				function = "uart_ao_b";
				bias-disable;
			};
		};

		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
			mux {
				groups = "uart_cts_ao_b",
				       "uart_rts_ao_b";
				function = "uart_ao_b";
				bias-disable;
			};
		};

		remote_input_ao_pins: remote_input_ao {
			mux {
				groups = "remote_input_ao";
				function = "remote_input_ao";
				bias-disable;
			};
		};

		i2c_ao_pins: i2c_ao {
			mux {
				groups = "i2c_sck_ao",
				       "i2c_sda_ao";
				function = "i2c_ao";
				bias-disable;
			};
		};

		pwm_ao_a_3_pins: pwm_ao_a_3 {
			mux {
				groups = "pwm_ao_a_3";
				function = "pwm_ao_a_3";
				bias-disable;
			};
		};

		pwm_ao_a_6_pins: pwm_ao_a_6 {
			mux {
				groups = "pwm_ao_a_6";
				function = "pwm_ao_a_6";
				bias-disable;
			};
		};

		pwm_ao_a_12_pins: pwm_ao_a_12 {
			mux {
				groups = "pwm_ao_a_12";
				function = "pwm_ao_a_12";
				bias-disable;
			};
		};

		pwm_ao_b_pins: pwm_ao_b {
			mux {
				groups = "pwm_ao_b";
				function = "pwm_ao_b";
				bias-disable;
			};
		};

		i2s_am_clk_pins: i2s_am_clk {
			mux {
				groups = "i2s_am_clk";
				function = "i2s_out_ao";
				bias-disable;
			};
		};

		i2s_out_ao_clk_pins: i2s_out_ao_clk {
			mux {
				groups = "i2s_out_ao_clk";
				function = "i2s_out_ao";
				bias-disable;
			};
		};

		i2s_out_lr_clk_pins: i2s_out_lr_clk {
			mux {
				groups = "i2s_out_lr_clk";
				function = "i2s_out_ao";
				bias-disable;
			};
		};

		i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
			mux {
				groups = "i2s_out_ch01_ao";
				function = "i2s_out_ao";
				bias-disable;
			};
		};

		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
			mux {
				groups = "i2s_out_ch23_ao";
				function = "i2s_out_ao";
				bias-disable;
			};
		};

		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
			mux {
				groups = "i2s_out_ch45_ao";
				function = "i2s_out_ao";
				bias-disable;
			};
		};

		spdif_out_ao_6_pins: spdif_out_ao_6 {
			mux {
				groups = "spdif_out_ao_6";
				function = "spdif_out_ao";
			};
		};

		spdif_out_ao_13_pins: spdif_out_ao_13 {
			mux {
				groups = "spdif_out_ao_13";
				function = "spdif_out_ao";
				bias-disable;
			};
		};

		ao_cec_pins: ao_cec {
			mux {
				groups = "ao_cec";
				function = "cec_ao";
				bias-disable;
			};
		};

		ee_cec_pins: ee_cec {
			mux {
				groups = "ee_cec";
				function = "cec_ao";
				bias-disable;
			};
		};
	};
};

&apb {
	mali: gpu@c0000 {
		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
		reg = <0x0 0xc0000 0x0 0x40000>;
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "gp", "gpmmu", "pp", "pmu",
			"pp0", "ppmmu0", "pp1", "ppmmu1",
			"pp2", "ppmmu2";
		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
		clock-names = "bus", "core";

		/*
		 * Mali clocking is provided by two identical clock paths
		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
		 * free mux to safely change frequency while running.
		 */
		assigned-clocks = <&clkc CLKID_GP0_PLL>,
				  <&clkc CLKID_MALI_0_SEL>,
				  <&clkc CLKID_MALI_0>,
				  <&clkc CLKID_MALI>; /* Glitch free mux */
		assigned-clock-parents = <0>, /* Do Nothing */
					 <&clkc CLKID_GP0_PLL>,
					 <0>, /* Do Nothing */
					 <&clkc CLKID_MALI_0>;
		assigned-clock-rates = <744000000>,
				       <0>, /* Do Nothing */
				       <744000000>,
				       <0>; /* Do Nothing */
	};
};

&cbus {
	spifc: spi@8c80 {
		compatible = "amlogic,meson-gxbb-spifc";
		reg = <0x0 0x08c80 0x0 0x80>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clkc CLKID_SPI>;
		status = "disabled";
	};
};

&cec_AO {
	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
	clock-names = "core";
};

&clkc_AO {
	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
	clocks = <&xtal>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "mpeg-clk";
};

&efuse {
	clocks = <&clkc CLKID_EFUSE>;
};

&ethmac {
	clocks = <&clkc CLKID_ETH>,
		 <&clkc CLKID_FCLK_DIV2>,
		 <&clkc CLKID_MPLL2>;
	clock-names = "stmmaceth", "clkin0", "clkin1";
};

&gpio_intc {
	compatible = "amlogic,meson-gpio-intc",
		     "amlogic,meson-gxbb-gpio-intc";
	status = "okay";
};

&hdmi_tx {
	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
	resets = <&reset RESET_HDMITX_CAPB3>,
		 <&reset RESET_HDMI_SYSTEM_RESET>,
		 <&reset RESET_HDMI_TX>;
	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
	clocks = <&clkc CLKID_HDMI_PCLK>,
		 <&clkc CLKID_CLK81>,
		 <&clkc CLKID_GCLK_VENCI_INT0>;
	clock-names = "isfr", "iahb", "venci";
};

&sysctrl {
	clkc: clock-controller {
		compatible = "amlogic,gxbb-clkc";
		#clock-cells = <1>;
		clocks = <&xtal>;
		clock-names = "xtal";
	};
};

&hwrng {
	clocks = <&clkc CLKID_RNG0>;
	clock-names = "core";
};

&i2c_A {
	clocks = <&clkc CLKID_I2C>;
};

&i2c_AO {
	clocks = <&clkc CLKID_AO_I2C>;
};

&i2c_B {
	clocks = <&clkc CLKID_I2C>;
};

&i2c_C {
	clocks = <&clkc CLKID_I2C>;
};

&periphs {
	pinctrl_periphs: pinctrl@4b0 {
		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio: bank@4b0 {
			reg = <0x0 0x004b0 0x0 0x28>,
			      <0x0 0x004e8 0x0 0x14>,
			      <0x0 0x00520 0x0 0x14>,
			      <0x0 0x00430 0x0 0x40>;
			reg-names = "mux", "pull", "pull-enable", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_periphs 0 0 119>;
		};

		emmc_pins: emmc {
			mux-0 {
				groups = "emmc_nand_d07",
				       "emmc_cmd";
				function = "emmc";
				bias-pull-up;
			};

			mux-1 {
				groups = "emmc_clk";
				function = "emmc";
				bias-disable;
			};
		};

		emmc_ds_pins: emmc-ds {
			mux {
				groups = "emmc_ds";
				function = "emmc";
				bias-pull-down;
			};
		};

		emmc_clk_gate_pins: emmc_clk_gate {
			mux {
				groups = "BOOT_8";
				function = "gpio_periphs";
				bias-pull-down;
			};
		};

		nor_pins: nor {
			mux {
				groups = "nor_d",
				       "nor_q",
				       "nor_c",
				       "nor_cs";
				function = "nor";
				bias-disable;
			};
		};

		spi_pins: spi-pins {
			mux {
				groups = "spi_miso",
					"spi_mosi",
					"spi_sclk";
				function = "spi";
				bias-disable;
			};
		};

		spi_ss0_pins: spi-ss0 {
			mux {
				groups = "spi_ss0";
				function = "spi";
				bias-disable;
			};
		};

		sdcard_pins: sdcard {
			mux-0 {
				groups = "sdcard_d0",
				       "sdcard_d1",
				       "sdcard_d2",
				       "sdcard_d3",
				       "sdcard_cmd";
				function = "sdcard";
				bias-pull-up;
			};

			mux-1 {
				groups = "sdcard_clk";
				function = "sdcard";
				bias-disable;
			};
		};

		sdcard_clk_gate_pins: sdcard_clk_gate {
			mux {
				groups = "CARD_2";
				function = "gpio_periphs";
				bias-pull-down;
			};
		};

		sdio_pins: sdio {
			mux-0 {
				groups = "sdio_d0",
				       "sdio_d1",
				       "sdio_d2",
				       "sdio_d3",
				       "sdio_cmd";
				function = "sdio";
				bias-pull-up;
			};

			mux-1 {
				groups = "sdio_clk";
				function = "sdio";
				bias-disable;
			};
		};

		sdio_clk_gate_pins: sdio_clk_gate {
			mux {
				groups = "GPIOX_4";
				function = "gpio_periphs";
				bias-pull-down;
			};
		};

		sdio_irq_pins: sdio_irq {
			mux {
				groups = "sdio_irq";
				function = "sdio";
				bias-disable;
			};
		};

		uart_a_pins: uart_a {
			mux {
				groups = "uart_tx_a",
				       "uart_rx_a";
				function = "uart_a";
				bias-disable;
			};
		};

		uart_a_cts_rts_pins: uart_a_cts_rts {
			mux {
				groups = "uart_cts_a",
				       "uart_rts_a";
				function = "uart_a";
				bias-disable;
			};
		};

		uart_b_pins: uart_b {
			mux {
				groups = "uart_tx_b",
				       "uart_rx_b";
				function = "uart_b";
				bias-disable;
			};
		};

		uart_b_cts_rts_pins: uart_b_cts_rts {
			mux {
				groups = "uart_cts_b",
				       "uart_rts_b";
				function = "uart_b";
				bias-disable;
			};
		};

		uart_c_pins: uart_c {
			mux {
				groups = "uart_tx_c",
				       "uart_rx_c";
				function = "uart_c";
				bias-disable;
			};
		};

		uart_c_cts_rts_pins: uart_c_cts_rts {
			mux {
				groups = "uart_cts_c",
				       "uart_rts_c";
				function = "uart_c";
				bias-disable;
			};
		};

		i2c_a_pins: i2c_a {
			mux {
				groups = "i2c_sck_a",
				       "i2c_sda_a";
				function = "i2c_a";
				bias-disable;
			};
		};

		i2c_b_pins: i2c_b {
			mux {
				groups = "i2c_sck_b",
				       "i2c_sda_b";
				function = "i2c_b";
				bias-disable;
			};
		};

		i2c_c_pins: i2c_c {
			mux {
				groups = "i2c_sck_c",
				       "i2c_sda_c";
				function = "i2c_c";
				bias-disable;
			};
		};

		eth_rgmii_pins: eth-rgmii {
			mux {
				groups = "eth_mdio",
				       "eth_mdc",
				       "eth_clk_rx_clk",
				       "eth_rx_dv",
				       "eth_rxd0",
				       "eth_rxd1",
				       "eth_rxd2",
				       "eth_rxd3",
				       "eth_rgmii_tx_clk",
				       "eth_tx_en",
				       "eth_txd0",
				       "eth_txd1",
				       "eth_txd2",
				       "eth_txd3";
				function = "eth";
				bias-disable;
			};
		};

		eth_rmii_pins: eth-rmii {
			mux {
				groups = "eth_mdio",
				       "eth_mdc",
				       "eth_clk_rx_clk",
				       "eth_rx_dv",
				       "eth_rxd0",
				       "eth_rxd1",
				       "eth_tx_en",
				       "eth_txd0",
				       "eth_txd1";
				function = "eth";
				bias-disable;
			};
		};

		pwm_a_x_pins: pwm_a_x {
			mux {
				groups = "pwm_a_x";
				function = "pwm_a_x";
				bias-disable;
			};
		};

		pwm_a_y_pins: pwm_a_y {
			mux {
				groups = "pwm_a_y";
				function = "pwm_a_y";
				bias-disable;
			};
		};

		pwm_b_pins: pwm_b {
			mux {
				groups = "pwm_b";
				function = "pwm_b";
				bias-disable;
			};
		};

		pwm_d_pins: pwm_d {
			mux {
				groups = "pwm_d";
				function = "pwm_d";
				bias-disable;
			};
		};

		pwm_e_pins: pwm_e {
			mux {
				groups = "pwm_e";
				function = "pwm_e";
				bias-disable;
			};
		};

		pwm_f_x_pins: pwm_f_x {
			mux {
				groups = "pwm_f_x";
				function = "pwm_f_x";
				bias-disable;
			};
		};

		pwm_f_y_pins: pwm_f_y {
			mux {
				groups = "pwm_f_y";
				function = "pwm_f_y";
				bias-disable;
			};
		};

		hdmi_hpd_pins: hdmi_hpd {
			mux {
				groups = "hdmi_hpd";
				function = "hdmi_hpd";
				bias-disable;
			};
		};

		hdmi_i2c_pins: hdmi_i2c {
			mux {
				groups = "hdmi_sda", "hdmi_scl";
				function = "hdmi_i2c";
				bias-disable;
			};
		};

		i2sout_ch23_y_pins: i2sout_ch23_y {
			mux {
				groups = "i2sout_ch23_y";
				function = "i2s_out";
				bias-disable;
			};
		};

		i2sout_ch45_y_pins: i2sout_ch45_y {
			mux {
				groups = "i2sout_ch45_y";
				function = "i2s_out";
				bias-disable;
			};
		};

		i2sout_ch67_y_pins: i2sout_ch67_y {
			mux {
				groups = "i2sout_ch67_y";
				function = "i2s_out";
				bias-disable;
			};
		};

		spdif_out_y_pins: spdif_out_y {
			mux {
				groups = "spdif_out_y";
				function = "spdif_out";
				bias-disable;
			};
		};
	};
};

&pwrc_vpu {
	resets = <&reset RESET_VIU>,
		 <&reset RESET_VENC>,
		 <&reset RESET_VCBUS>,
		 <&reset RESET_BT656>,
		 <&reset RESET_DVIN_RESET>,
		 <&reset RESET_RDMA>,
		 <&reset RESET_VENCI>,
		 <&reset RESET_VENCP>,
		 <&reset RESET_VDAC>,
		 <&reset RESET_VDI6>,
		 <&reset RESET_VENCL>,
		 <&reset RESET_VID_LOCK>;
	clocks = <&clkc CLKID_VPU>,
	         <&clkc CLKID_VAPB>;
	clock-names = "vpu", "vapb";
	/*
	 * VPU clocking is provided by two identical clock paths
	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
	 * free mux to safely change frequency while running.
	 * Same for VAPB but with a final gate after the glitch free mux.
	 */
	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
			  <&clkc CLKID_VPU_0>,
			  <&clkc CLKID_VPU>, /* Glitch free mux */
			  <&clkc CLKID_VAPB_0_SEL>,
			  <&clkc CLKID_VAPB_0>,
			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
				 <0>, /* Do Nothing */
				 <&clkc CLKID_VPU_0>,
				 <&clkc CLKID_FCLK_DIV4>,
				 <0>, /* Do Nothing */
				 <&clkc CLKID_VAPB_0>;
	assigned-clock-rates = <0>, /* Do Nothing */
			       <666666666>,
			       <0>, /* Do Nothing */
			       <0>, /* Do Nothing */
			       <250000000>,
			       <0>; /* Do Nothing */
};

&saradc {
	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
	clocks = <&xtal>,
		 <&clkc CLKID_SAR_ADC>,
		 <&clkc CLKID_SAR_ADC_CLK>,
		 <&clkc CLKID_SAR_ADC_SEL>;
	clock-names = "clkin", "core", "adc_clk", "adc_sel";
};

&sd_emmc_a {
	clocks = <&clkc CLKID_SD_EMMC_A>,
		 <&clkc CLKID_SD_EMMC_A_CLK0>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
	resets = <&reset RESET_SD_EMMC_A>;
};

&sd_emmc_b {
	clocks = <&clkc CLKID_SD_EMMC_B>,
		 <&clkc CLKID_SD_EMMC_B_CLK0>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
	resets = <&reset RESET_SD_EMMC_B>;
};

&sd_emmc_c {
	clocks = <&clkc CLKID_SD_EMMC_C>,
		 <&clkc CLKID_SD_EMMC_C_CLK0>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
	resets = <&reset RESET_SD_EMMC_C>;
};

&simplefb_hdmi {
	clocks = <&clkc CLKID_HDMI_PCLK>,
		 <&clkc CLKID_CLK81>,
		 <&clkc CLKID_GCLK_VENCI_INT0>;
};

&spicc {
	clocks = <&clkc CLKID_SPICC>;
	clock-names = "core";
	resets = <&reset RESET_PERIPHS_SPICC>;
	num-cs = <1>;
};

&spifc {
	clocks = <&clkc CLKID_SPI>;
};

&uart_A {
	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_AO {
	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_AO_B {
	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_B {
	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_C {
	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
	clock-names = "xtal", "pclk", "baud";
};

&vpu {
	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
	power-domains = <&pwrc_vpu>;
};
Commit	Line	Data
114abfe1	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4f24eda8 AF	2	/*
4f24eda8 AF	3	* Copyright (c) 2016 Andreas Färber
4f24eda8 AF	4	*/
4f24eda8 AF	5
c328666d	6	#include "meson-gx.dtsi"
f40d437f	7	#include <dt-bindings/gpio/meson-gxbb-gpio.h>
6d1a5c93	8	#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
c3929b72	9	#include <dt-bindings/clock/gxbb-clkc.h>
8d298f5b NA	10	#include <dt-bindings/clock/gxbb-aoclkc.h>
8d298f5b NA	11	#include <dt-bindings/reset/gxbb-aoclkc.h>
4f24eda8 AF	12
	13	/ {
	14	compatible = "amlogic,meson-gxbb";
4f24eda8	15
4f24eda8	16	soc {
566603e5 MB	17	usb0_phy: phy@c0000000 {
	18	compatible = "amlogic,meson-gxbb-usb2-phy";
	19	#phy-cells = <0>;
	20	reg = <0x0 0xc0000000 0x0 0x20>;
	21	resets = <&reset RESET_USB_OTG>;
	22	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
	23	clock-names = "usb_general", "usb";
	24	status = "disabled";
	25	};
	26
	27	usb1_phy: phy@c0000020 {
	28	compatible = "amlogic,meson-gxbb-usb2-phy";
	29	#phy-cells = <0>;
	30	reg = <0x0 0xc0000020 0x0 0x20>;
a5b1ef3c	31	resets = <&reset RESET_USB_OTG>;
566603e5 MB	32	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
	33	clock-names = "usb_general", "usb";
	34	status = "disabled";
	35	};
	36
c328666d NA	37	usb0: usb@c9000000 {
	38	compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
	39	reg = <0x0 0xc9000000 0x0 0x40000>;
	40	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	41	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
	42	clock-names = "otg";
	43	phys = <&usb0_phy>;
	44	phy-names = "usb2-phy";
	45	dr_mode = "host";
	46	status = "disabled";
	47	};
4f24eda8	48
c328666d NA	49	usb1: usb@c9100000 {
	50	compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
	51	reg = <0x0 0xc9100000 0x0 0x40000>;
	52	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	53	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
	54	clock-names = "otg";
	55	phys = <&usb1_phy>;
	56	phy-names = "usb2-phy";
	57	dr_mode = "host";
	58	status = "disabled";
	59	};
c328666d NA	60	};
	61	};
	62
c328666d NA	63	&aobus {
	64	pinctrl_aobus: pinctrl@14 {
	65	compatible = "amlogic,meson-gxbb-aobus-pinctrl";
	66	#address-cells = <2>;
	67	#size-cells = <2>;
	68	ranges;
8e6320dd	69
c328666d NA	70	gpio_ao: bank@14 {
	71	reg = <0x0 0x00014 0x0 0x8>,
	72	<0x0 0x0002c 0x0 0x4>,
	73	<0x0 0x00024 0x0 0x8>;
	74	reg-names = "mux", "pull", "gpio";
	75	gpio-controller;
	76	#gpio-cells = <2>;
18ae17bc	77	gpio-ranges = <&pinctrl_aobus 0 0 14>;
c328666d NA	78	};
	79
	80	uart_ao_a_pins: uart_ao_a {
	81	mux {
	82	groups = "uart_tx_ao_a", "uart_rx_ao_a";
	83	function = "uart_ao";
1c5cc1c8	84	bias-disable;
8e6320dd	85	};
c328666d	86	};
8e6320dd	87
261e1d5c MB	88	uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
	89	mux {
	90	groups = "uart_cts_ao_a",
	91	"uart_rts_ao_a";
	92	function = "uart_ao";
1c5cc1c8	93	bias-disable;
261e1d5c MB	94	};
	95	};
	96
890a96a2 MB	97	uart_ao_b_pins: uart_ao_b {
	98	mux {
	99	groups = "uart_tx_ao_b", "uart_rx_ao_b";
	100	function = "uart_ao_b";
1c5cc1c8	101	bias-disable;
890a96a2 MB	102	};
	103	};
	104
261e1d5c MB	105	uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
	106	mux {
	107	groups = "uart_cts_ao_b",
	108	"uart_rts_ao_b";
	109	function = "uart_ao_b";
1c5cc1c8	110	bias-disable;
261e1d5c MB	111	};
	112	};
	113
c328666d NA	114	remote_input_ao_pins: remote_input_ao {
	115	mux {
	116	groups = "remote_input_ao";
	117	function = "remote_input_ao";
1c5cc1c8	118	bias-disable;
8f14a893	119	};
c328666d	120	};
8f14a893	121
c328666d NA	122	i2c_ao_pins: i2c_ao {
	123	mux {
	124	groups = "i2c_sck_ao",
	125	"i2c_sda_ao";
	126	function = "i2c_ao";
1c5cc1c8	127	bias-disable;
8f14a893	128	};
c328666d	129	};
8f14a893	130
c328666d NA	131	pwm_ao_a_3_pins: pwm_ao_a_3 {
	132	mux {
	133	groups = "pwm_ao_a_3";
	134	function = "pwm_ao_a_3";
1c5cc1c8	135	bias-disable;
8f14a893	136	};
c328666d	137	};
8f14a893	138
c328666d NA	139	pwm_ao_a_6_pins: pwm_ao_a_6 {
	140	mux {
	141	groups = "pwm_ao_a_6";
	142	function = "pwm_ao_a_6";
1c5cc1c8	143	bias-disable;
8e6320dd	144	};
c328666d	145	};
f759b640	146
c328666d NA	147	pwm_ao_a_12_pins: pwm_ao_a_12 {
	148	mux {
	149	groups = "pwm_ao_a_12";
	150	function = "pwm_ao_a_12";
1c5cc1c8	151	bias-disable;
f759b640	152	};
c328666d	153	};
e9c9b651	154
c328666d NA	155	pwm_ao_b_pins: pwm_ao_b {
	156	mux {
	157	groups = "pwm_ao_b";
	158	function = "pwm_ao_b";
1c5cc1c8	159	bias-disable;
e9c9b651	160	};
c328666d	161	};
c328666d	162
552b1e56	163	i2s_am_clk_pins: i2s_am_clk {
	164	mux {
	165	groups = "i2s_am_clk";
	166	function = "i2s_out_ao";
1c5cc1c8	167	bias-disable;
552b1e56	168	};
552b1e56	169	};
c328666d	170
552b1e56	171	i2s_out_ao_clk_pins: i2s_out_ao_clk {
	172	mux {
	173	groups = "i2s_out_ao_clk";
	174	function = "i2s_out_ao";
1c5cc1c8	175	bias-disable;
552b1e56	176	};
552b1e56	177	};
c328666d	178
552b1e56	179	i2s_out_lr_clk_pins: i2s_out_lr_clk {
	180	mux {
	181	groups = "i2s_out_lr_clk";
	182	function = "i2s_out_ao";
1c5cc1c8	183	bias-disable;
552b1e56	184	};
	185	};
	186
	187	i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
	188	mux {
	189	groups = "i2s_out_ch01_ao";
	190	function = "i2s_out_ao";
1c5cc1c8	191	bias-disable;
552b1e56	192	};
	193	};
	194
	195	i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
	196	mux {
	197	groups = "i2s_out_ch23_ao";
	198	function = "i2s_out_ao";
1c5cc1c8	199	bias-disable;
552b1e56	200	};
	201	};
	202
	203	i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
	204	mux {
	205	groups = "i2s_out_ch45_ao";
	206	function = "i2s_out_ao";
1c5cc1c8	207	bias-disable;
552b1e56	208	};
552b1e56	209	};
07a4652f	210
	211	spdif_out_ao_6_pins: spdif_out_ao_6 {
	212	mux {
	213	groups = "spdif_out_ao_6";
	214	function = "spdif_out_ao";
	215	};
	216	};
	217
	218	spdif_out_ao_13_pins: spdif_out_ao_13 {
	219	mux {
	220	groups = "spdif_out_ao_13";
	221	function = "spdif_out_ao";
1c5cc1c8	222	bias-disable;
07a4652f	223	};
07a4652f	224	};
a679f5d2 NA	225
	226	ao_cec_pins: ao_cec {
	227	mux {
	228	groups = "ao_cec";
	229	function = "cec_ao";
1c5cc1c8	230	bias-disable;
a679f5d2 NA	231	};
	232	};
	233
	234	ee_cec_pins: ee_cec {
	235	mux {
	236	groups = "ee_cec";
	237	function = "cec_ao";
1c5cc1c8	238	bias-disable;
a679f5d2 NA	239	};
a679f5d2 NA	240	};
c328666d NA	241	};
	242	};
	243
8d7c7711 AF	244	&apb {
	245	mali: gpu@c0000 {
	246	compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
	247	reg = <0x0 0xc0000 0x0 0x40000>;
	248	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	249	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	250	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	251	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	252	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
	253	<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	254	<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
	255	<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
	256	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	257	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	258	interrupt-names = "gp", "gpmmu", "pp", "pmu",
	259	"pp0", "ppmmu0", "pp1", "ppmmu1",
	260	"pp2", "ppmmu2";
	261	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
	262	clock-names = "bus", "core";
	263
	264	/*
	265	* Mali clocking is provided by two identical clock paths
	266	* MALI_0 and MALI_1 muxed to a single clock by a glitch
	267	* free mux to safely change frequency while running.
	268	*/
97ac0093 NA	269	assigned-clocks = <&clkc CLKID_GP0_PLL>,
97ac0093 NA	270	<&clkc CLKID_MALI_0_SEL>,
8d7c7711 AF	271	<&clkc CLKID_MALI_0>,
8d7c7711 AF	272	<&clkc CLKID_MALI>; /* Glitch free mux */
97ac0093 NA	273	assigned-clock-parents = <0>, /* Do Nothing */
97ac0093 NA	274	<&clkc CLKID_GP0_PLL>,
8d7c7711 AF	275	<0>, /* Do Nothing */
8d7c7711 AF	276	<&clkc CLKID_MALI_0>;
97ac0093 NA	277	assigned-clock-rates = <744000000>,
	278	<0>, /* Do Nothing */
	279	<744000000>,
8d7c7711 AF	280	<0>; /* Do Nothing */
	281	};
	282	};
	283
	284	&cbus {
	285	spifc: spi@8c80 {
	286	compatible = "amlogic,meson-gxbb-spifc";
	287	reg = <0x0 0x08c80 0x0 0x80>;
	288	#address-cells = <1>;
	289	#size-cells = <0>;
	290	clocks = <&clkc CLKID_SPI>;
	291	status = "disabled";
	292	};
	293	};
	294
b16c71c9 NA	295	&cec_AO {
	296	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
	297	clock-names = "core";
	298	};
	299
7fd2c355 NA	300	&clkc_AO {
7fd2c355 NA	301	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
16361ff2 JB	302	clocks = <&xtal>, <&clkc CLKID_CLK81>;
16361ff2 JB	303	clock-names = "xtal", "mpeg-clk";
7fd2c355 NA	304	};
7fd2c355 NA	305
eed5afc6 JB	306	&efuse {
	307	clocks = <&clkc CLKID_EFUSE>;
	308	};
	309
8d7c7711 AF	310	&ethmac {
	311	clocks = <&clkc CLKID_ETH>,
	312	<&clkc CLKID_FCLK_DIV2>,
	313	<&clkc CLKID_MPLL2>;
	314	clock-names = "stmmaceth", "clkin0", "clkin1";
	315	};
	316
9dbb56ea JB	317	&gpio_intc {
	318	compatible = "amlogic,meson-gpio-intc",
	319	"amlogic,meson-gxbb-gpio-intc";
	320	status = "okay";
	321	};
	322
8d7c7711 AF	323	&hdmi_tx {
	324	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
	325	resets = <&reset RESET_HDMITX_CAPB3>,
	326	<&reset RESET_HDMI_SYSTEM_RESET>,
	327	<&reset RESET_HDMI_TX>;
	328	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
	329	clocks = <&clkc CLKID_HDMI_PCLK>,
	330	<&clkc CLKID_CLK81>,
	331	<&clkc CLKID_GCLK_VENCI_INT0>;
	332	clock-names = "isfr", "iahb", "venci";
	333	};
	334
6f95c8cd JB	335	&sysctrl {
6f95c8cd JB	336	clkc: clock-controller {
8d7c7711 AF	337	compatible = "amlogic,gxbb-clkc";
8d7c7711 AF	338	#clock-cells = <1>;
16361ff2 JB	339	clocks = <&xtal>;
16361ff2 JB	340	clock-names = "xtal";
8d7c7711 AF	341	};
	342	};
	343
	344	&hwrng {
	345	clocks = <&clkc CLKID_RNG0>;
	346	clock-names = "core";
	347	};
	348
	349	&i2c_A {
	350	clocks = <&clkc CLKID_I2C>;
	351	};
	352
	353	&i2c_AO {
	354	clocks = <&clkc CLKID_AO_I2C>;
	355	};
	356
	357	&i2c_B {
	358	clocks = <&clkc CLKID_I2C>;
	359	};
	360
	361	&i2c_C {
	362	clocks = <&clkc CLKID_I2C>;
	363	};
	364
c328666d	365	&periphs {
c328666d NA	366	pinctrl_periphs: pinctrl@4b0 {
	367	compatible = "amlogic,meson-gxbb-periphs-pinctrl";
	368	#address-cells = <2>;
	369	#size-cells = <2>;
	370	ranges;
	371
	372	gpio: bank@4b0 {
	373	reg = <0x0 0x004b0 0x0 0x28>,
	374	<0x0 0x004e8 0x0 0x14>,
9ef366a4	375	<0x0 0x00520 0x0 0x14>,
c328666d NA	376	<0x0 0x00430 0x0 0x40>;
	377	reg-names = "mux", "pull", "pull-enable", "gpio";
	378	gpio-controller;
	379	#gpio-cells = <2>;
7dbe78e5	380	gpio-ranges = <&pinctrl_periphs 0 0 119>;
c328666d	381	};
1befc626	382
c328666d	383	emmc_pins: emmc {
b43033b1	384	mux-0 {
c328666d	385	groups = "emmc_nand_d07",
b43033b1 JB	386	"emmc_cmd";
	387	function = "emmc";
	388	bias-pull-up;
	389	};
	390
	391	mux-1 {
	392	groups = "emmc_clk";
ab36be66	393	function = "emmc";
96a13691	394	bias-disable;
ab36be66 NA	395	};
	396	};
	397
	398	emmc_ds_pins: emmc-ds {
	399	mux {
	400	groups = "emmc_ds";
c328666d	401	function = "emmc";
b43033b1	402	bias-pull-down;
1befc626	403	};
c328666d	404	};
1befc626	405
67e7607f JB	406	emmc_clk_gate_pins: emmc_clk_gate {
	407	mux {
	408	groups = "BOOT_8";
	409	function = "gpio_periphs";
67e7607f JB	410	bias-pull-down;
	411	};
	412	};
	413
c328666d NA	414	nor_pins: nor {
	415	mux {
	416	groups = "nor_d",
	417	"nor_q",
	418	"nor_c",
	419	"nor_cs";
	420	function = "nor";
1c5cc1c8	421	bias-disable;
1befc626	422	};
c328666d	423	};
1befc626	424
68ecb5c1	425	spi_pins: spi-pins {
ec0a8260 NA	426	mux {
	427	groups = "spi_miso",
	428	"spi_mosi",
	429	"spi_sclk";
	430	function = "spi";
1c5cc1c8	431	bias-disable;
ec0a8260 NA	432	};
	433	};
	434
	435	spi_ss0_pins: spi-ss0 {
	436	mux {
	437	groups = "spi_ss0";
	438	function = "spi";
1c5cc1c8	439	bias-disable;
ec0a8260 NA	440	};
	441	};
	442
c328666d	443	sdcard_pins: sdcard {
b43033b1	444	mux-0 {
c328666d NA	445	groups = "sdcard_d0",
	446	"sdcard_d1",
	447	"sdcard_d2",
	448	"sdcard_d3",
b43033b1 JB	449	"sdcard_cmd";
	450	function = "sdcard";
	451	bias-pull-up;
	452	};
	453
	454	mux-1 {
	455	groups = "sdcard_clk";
c328666d	456	function = "sdcard";
96a13691	457	bias-disable;
1befc626	458	};
4f24eda8 AF	459	};
4f24eda8 AF	460
67e7607f JB	461	sdcard_clk_gate_pins: sdcard_clk_gate {
	462	mux {
	463	groups = "CARD_2";
	464	function = "gpio_periphs";
67e7607f JB	465	bias-pull-down;
	466	};
	467	};
	468
c328666d	469	sdio_pins: sdio {
b43033b1	470	mux-0 {
c328666d NA	471	groups = "sdio_d0",
	472	"sdio_d1",
	473	"sdio_d2",
	474	"sdio_d3",
b43033b1 JB	475	"sdio_cmd";
	476	function = "sdio";
	477	bias-pull-up;
	478	};
	479
	480	mux-1 {
	481	groups = "sdio_clk";
c328666d	482	function = "sdio";
96a13691	483	bias-disable;
f40d437f	484	};
c328666d	485	};
f40d437f	486
67e7607f JB	487	sdio_clk_gate_pins: sdio_clk_gate {
	488	mux {
	489	groups = "GPIOX_4";
	490	function = "gpio_periphs";
67e7607f JB	491	bias-pull-down;
	492	};
	493	};
	494
c328666d NA	495	sdio_irq_pins: sdio_irq {
	496	mux {
	497	groups = "sdio_irq";
	498	function = "sdio";
1c5cc1c8	499	bias-disable;
f40d437f	500	};
c328666d	501	};
f40d437f	502
c328666d NA	503	uart_a_pins: uart_a {
	504	mux {
	505	groups = "uart_tx_a",
	506	"uart_rx_a";
	507	function = "uart_a";
1c5cc1c8	508	bias-disable;
4f24eda8	509	};
c328666d	510	};
c58d7785	511
261e1d5c MB	512	uart_a_cts_rts_pins: uart_a_cts_rts {
	513	mux {
	514	groups = "uart_cts_a",
	515	"uart_rts_a";
	516	function = "uart_a";
1c5cc1c8	517	bias-disable;
261e1d5c MB	518	};
	519	};
	520
c328666d NA	521	uart_b_pins: uart_b {
	522	mux {
	523	groups = "uart_tx_b",
	524	"uart_rx_b";
	525	function = "uart_b";
1c5cc1c8	526	bias-disable;
c58d7785	527	};
c328666d	528	};
8f14a893	529
261e1d5c MB	530	uart_b_cts_rts_pins: uart_b_cts_rts {
	531	mux {
	532	groups = "uart_cts_b",
	533	"uart_rts_b";
	534	function = "uart_b";
1c5cc1c8	535	bias-disable;
261e1d5c MB	536	};
	537	};
	538
c328666d NA	539	uart_c_pins: uart_c {
	540	mux {
	541	groups = "uart_tx_c",
	542	"uart_rx_c";
	543	function = "uart_c";
1c5cc1c8	544	bias-disable;
8f14a893	545	};
c328666d	546	};
1befc626	547
261e1d5c MB	548	uart_c_cts_rts_pins: uart_c_cts_rts {
	549	mux {
	550	groups = "uart_cts_c",
	551	"uart_rts_c";
	552	function = "uart_c";
1c5cc1c8	553	bias-disable;
261e1d5c MB	554	};
	555	};
	556
c328666d NA	557	i2c_a_pins: i2c_a {
	558	mux {
	559	groups = "i2c_sck_a",
	560	"i2c_sda_a";
	561	function = "i2c_a";
1c5cc1c8	562	bias-disable;
1befc626	563	};
4f24eda8 AF	564	};
4f24eda8 AF	565
c328666d NA	566	i2c_b_pins: i2c_b {
	567	mux {
	568	groups = "i2c_sck_b",
	569	"i2c_sda_b";
	570	function = "i2c_b";
1c5cc1c8	571	bias-disable;
c328666d NA	572	};
c328666d NA	573	};
f40d437f	574
c328666d NA	575	i2c_c_pins: i2c_c {
	576	mux {
	577	groups = "i2c_sck_c",
	578	"i2c_sda_c";
	579	function = "i2c_c";
1c5cc1c8	580	bias-disable;
4b7bed38	581	};
c328666d	582	};
4b7bed38	583
3be2d9cf	584	eth_rgmii_pins: eth-rgmii {
c328666d NA	585	mux {
	586	groups = "eth_mdio",
	587	"eth_mdc",
	588	"eth_clk_rx_clk",
	589	"eth_rx_dv",
	590	"eth_rxd0",
	591	"eth_rxd1",
	592	"eth_rxd2",
	593	"eth_rxd3",
	594	"eth_rgmii_tx_clk",
	595	"eth_tx_en",
	596	"eth_txd0",
	597	"eth_txd1",
	598	"eth_txd2",
	599	"eth_txd3";
	600	function = "eth";
1c5cc1c8	601	bias-disable;
f40d437f	602	};
fab6b48c CC	603	};
fab6b48c CC	604
3be2d9cf NA	605	eth_rmii_pins: eth-rmii {
	606	mux {
	607	groups = "eth_mdio",
	608	"eth_mdc",
	609	"eth_clk_rx_clk",
	610	"eth_rx_dv",
	611	"eth_rxd0",
	612	"eth_rxd1",
	613	"eth_tx_en",
	614	"eth_txd0",
	615	"eth_txd1";
	616	function = "eth";
1c5cc1c8	617	bias-disable;
3be2d9cf NA	618	};
	619	};
	620
c328666d NA	621	pwm_a_x_pins: pwm_a_x {
	622	mux {
	623	groups = "pwm_a_x";
	624	function = "pwm_a_x";
1c5cc1c8	625	bias-disable;
c328666d NA	626	};
c328666d NA	627	};
ba6a6c7f	628
c328666d NA	629	pwm_a_y_pins: pwm_a_y {
	630	mux {
	631	groups = "pwm_a_y";
	632	function = "pwm_a_y";
1c5cc1c8	633	bias-disable;
ba6a6c7f	634	};
c328666d	635	};
7b5682c6	636
c328666d NA	637	pwm_b_pins: pwm_b {
	638	mux {
	639	groups = "pwm_b";
	640	function = "pwm_b";
1c5cc1c8	641	bias-disable;
7b5682c6	642	};
fab6b48c CC	643	};
fab6b48c CC	644
c328666d NA	645	pwm_d_pins: pwm_d {
	646	mux {
	647	groups = "pwm_d";
	648	function = "pwm_d";
1c5cc1c8	649	bias-disable;
c328666d	650	};
4f24eda8	651	};
8c5509f0	652
c328666d NA	653	pwm_e_pins: pwm_e {
	654	mux {
	655	groups = "pwm_e";
	656	function = "pwm_e";
1c5cc1c8	657	bias-disable;
c328666d	658	};
566603e5 MB	659	};
566603e5 MB	660
c328666d NA	661	pwm_f_x_pins: pwm_f_x {
	662	mux {
	663	groups = "pwm_f_x";
	664	function = "pwm_f_x";
1c5cc1c8	665	bias-disable;
c328666d	666	};
566603e5 MB	667	};
566603e5 MB	668
c328666d NA	669	pwm_f_y_pins: pwm_f_y {
	670	mux {
	671	groups = "pwm_f_y";
	672	function = "pwm_f_y";
1c5cc1c8	673	bias-disable;
c328666d	674	};
8c5509f0	675	};
b949165c NA	676
	677	hdmi_hpd_pins: hdmi_hpd {
	678	mux {
	679	groups = "hdmi_hpd";
	680	function = "hdmi_hpd";
1c5cc1c8	681	bias-disable;
b949165c NA	682	};
	683	};
	684
	685	hdmi_i2c_pins: hdmi_i2c {
	686	mux {
	687	groups = "hdmi_sda", "hdmi_scl";
	688	function = "hdmi_i2c";
1c5cc1c8	689	bias-disable;
b949165c NA	690	};
b949165c NA	691	};
552b1e56	692
	693	i2sout_ch23_y_pins: i2sout_ch23_y {
	694	mux {
	695	groups = "i2sout_ch23_y";
	696	function = "i2s_out";
1c5cc1c8	697	bias-disable;
552b1e56	698	};
	699	};
	700
	701	i2sout_ch45_y_pins: i2sout_ch45_y {
	702	mux {
	703	groups = "i2sout_ch45_y";
	704	function = "i2s_out";
1c5cc1c8	705	bias-disable;
552b1e56	706	};
	707	};
	708
	709	i2sout_ch67_y_pins: i2sout_ch67_y {
	710	mux {
	711	groups = "i2sout_ch67_y";
	712	function = "i2s_out";
1c5cc1c8	713	bias-disable;
552b1e56	714	};
552b1e56	715	};
07a4652f	716
	717	spdif_out_y_pins: spdif_out_y {
	718	mux {
	719	groups = "spdif_out_y";
	720	function = "spdif_out";
1c5cc1c8	721	bias-disable;
07a4652f	722	};
07a4652f	723	};
4f24eda8 AF	724	};
4f24eda8 AF	725	};
c328666d	726
74d1c6e9 NA	727	&pwrc_vpu {
	728	resets = <&reset RESET_VIU>,
	729	<&reset RESET_VENC>,
	730	<&reset RESET_VCBUS>,
	731	<&reset RESET_BT656>,
	732	<&reset RESET_DVIN_RESET>,
	733	<&reset RESET_RDMA>,
	734	<&reset RESET_VENCI>,
	735	<&reset RESET_VENCP>,
	736	<&reset RESET_VDAC>,
	737	<&reset RESET_VDI6>,
	738	<&reset RESET_VENCL>,
	739	<&reset RESET_VID_LOCK>;
	740	clocks = <&clkc CLKID_VPU>,
	741	<&clkc CLKID_VAPB>;
	742	clock-names = "vpu", "vapb";
	743	/*
	744	* VPU clocking is provided by two identical clock paths
	745	* VPU_0 and VPU_1 muxed to a single clock by a glitch
	746	* free mux to safely change frequency while running.
	747	* Same for VAPB but with a final gate after the glitch free mux.
	748	*/
	749	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
	750	<&clkc CLKID_VPU_0>,
	751	<&clkc CLKID_VPU>, /* Glitch free mux */
	752	<&clkc CLKID_VAPB_0_SEL>,
	753	<&clkc CLKID_VAPB_0>,
	754	<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
	755	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
	756	<0>, /* Do Nothing */
	757	<&clkc CLKID_VPU_0>,
	758	<&clkc CLKID_FCLK_DIV4>,
	759	<0>, /* Do Nothing */
	760	<&clkc CLKID_VAPB_0>;
	761	assigned-clock-rates = <0>, /* Do Nothing */
	762	<666666666>,
	763	<0>, /* Do Nothing */
	764	<0>, /* Do Nothing */
	765	<250000000>,
	766	<0>; /* Do Nothing */
	767	};
	768
bd80ef5e MB	769	&saradc {
	770	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
	771	clocks = <&xtal>,
	772	<&clkc CLKID_SAR_ADC>,
bd80ef5e MB	773	<&clkc CLKID_SAR_ADC_CLK>,
bd80ef5e MB	774	<&clkc CLKID_SAR_ADC_SEL>;
e102da49	775	clock-names = "clkin", "core", "adc_clk", "adc_sel";
bd80ef5e MB	776	};
bd80ef5e MB	777
ef8d2ffe KH	778	&sd_emmc_a {
ef8d2ffe KH	779	clocks = <&clkc CLKID_SD_EMMC_A>,
50662499	780	<&clkc CLKID_SD_EMMC_A_CLK0>,
ef8d2ffe KH	781	<&clkc CLKID_FCLK_DIV2>;
ef8d2ffe KH	782	clock-names = "core", "clkin0", "clkin1";
098e5303	783	resets = <&reset RESET_SD_EMMC_A>;
ef8d2ffe KH	784	};
	785
	786	&sd_emmc_b {
	787	clocks = <&clkc CLKID_SD_EMMC_B>,
50662499	788	<&clkc CLKID_SD_EMMC_B_CLK0>,
ef8d2ffe KH	789	<&clkc CLKID_FCLK_DIV2>;
ef8d2ffe KH	790	clock-names = "core", "clkin0", "clkin1";
098e5303	791	resets = <&reset RESET_SD_EMMC_B>;
ef8d2ffe KH	792	};
	793
	794	&sd_emmc_c {
	795	clocks = <&clkc CLKID_SD_EMMC_C>,
50662499	796	<&clkc CLKID_SD_EMMC_C_CLK0>,
ef8d2ffe KH	797	<&clkc CLKID_FCLK_DIV2>;
ef8d2ffe KH	798	clock-names = "core", "clkin0", "clkin1";
098e5303	799	resets = <&reset RESET_SD_EMMC_C>;
ef8d2ffe	800	};
fafdbdf7	801
03b37035 MJ	802	&simplefb_hdmi {
	803	clocks = <&clkc CLKID_HDMI_PCLK>,
	804	<&clkc CLKID_CLK81>,
	805	<&clkc CLKID_GCLK_VENCI_INT0>;
	806	};
	807
fa808631 NA	808	&spicc {
	809	clocks = <&clkc CLKID_SPICC>;
	810	clock-names = "core";
	811	resets = <&reset RESET_PERIPHS_SPICC>;
	812	num-cs = <1>;
	813	};
	814
04b36df4 NA	815	&spifc {
	816	clocks = <&clkc CLKID_SPI>;
	817	};
	818
f72d6f60 HK	819	&uart_A {
	820	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
	821	clock-names = "xtal", "pclk", "baud";
	822	};
	823
	824	&uart_AO {
9adda353	825	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
f72d6f60 HK	826	clock-names = "xtal", "pclk", "baud";
	827	};
	828
	829	&uart_AO_B {
9adda353	830	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
f72d6f60 HK	831	clock-names = "xtal", "pclk", "baud";
	832	};
	833
	834	&uart_B {
	835	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
39005e56	836	clock-names = "xtal", "pclk", "baud";
f72d6f60 HK	837	};
	838
	839	&uart_C {
	840	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
39005e56	841	clock-names = "xtal", "pclk", "baud";
f72d6f60 HK	842	};
f72d6f60 HK	843
fafdbdf7 NA	844	&vpu {
fafdbdf7 NA	845	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
74d1c6e9	846	power-domains = <&pwrc_vpu>;
fafdbdf7	847	};