[mirror_ubuntu-bionic-kernel.git] / arch / arm64 / boot / dts / arm / juno-base.dtsi

	/*
	 *  Devices shared by all Juno boards
	 */

	memtimer: timer@2a810000 {
		compatible = "arm,armv7-timer-mem";
		reg = <0x0 0x2a810000 0x0 0x10000>;
		clock-frequency = <50000000>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";
		frame@2a830000 {
			frame-number = <1>;
			interrupts = <0 60 4>;
			reg = <0x0 0x2a830000 0x0 0x10000>;
		};
	};

	mailbox: mhu@2b1f0000 {
		compatible = "arm,mhu", "arm,primecell";
		reg = <0x0 0x2b1f0000 0x0 0x1000>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "mhu_lpri_rx",
				  "mhu_hpri_rx";
		#mbox-cells = <1>;
		clocks = <&soc_refclk100mhz>;
		clock-names = "apb_pclk";
	};

	gic: interrupt-controller@2c010000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		reg = <0x0 0x2c010000 0 0x1000>,
		      <0x0 0x2c02f000 0 0x2000>,
		      <0x0 0x2c04f000 0 0x2000>,
		      <0x0 0x2c06f000 0 0x2000>;
		#address-cells = <2>;
		#interrupt-cells = <3>;
		#size-cells = <2>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
		ranges = <0 0 0 0x2c1c0000 0 0x40000>;
		v2m_0: v2m@0 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0 0 0 0x1000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
	};

	sram: sram@2e000000 {
		compatible = "arm,juno-sram-ns", "mmio-sram";
		reg = <0x0 0x2e000000 0x0 0x8000>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x0 0x2e000000 0x8000>;

		cpu_scp_lpri: scp-shmem@0 {
			compatible = "arm,juno-scp-shmem";
			reg = <0x0 0x200>;
		};

		cpu_scp_hpri: scp-shmem@200 {
			compatible = "arm,juno-scp-shmem";
			reg = <0x200 0x200>;
		};
	};

	pcie_ctlr: pcie-controller@40000000 {
		compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
		device_type = "pci";
		reg = <0 0x40000000 0 0x10000000>;	/* ECAM config space */
		bus-range = <0 255>;
		linux,pci-domain = <0>;
		#address-cells = <3>;
		#size-cells = <2>;
		dma-coherent;
		ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
			 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
			 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
				<0 0 0 2 &gic 0 0 0 137 4>,
				<0 0 0 3 &gic 0 0 0 138 4>,
				<0 0 0 4 &gic 0 0 0 139 4>;
		msi-parent = <&v2m_0>;
		status = "disabled";
	};

	scpi {
		compatible = "arm,scpi";
		mboxes = <&mailbox 1>;
		shmem = <&cpu_scp_hpri>;

		clocks {
			compatible = "arm,scpi-clocks";

			scpi_dvfs: scpi_clocks@0 {
				compatible = "arm,scpi-dvfs-clocks";
				#clock-cells = <1>;
				clock-indices = <0>, <1>, <2>;
				clock-output-names = "atlclk", "aplclk","gpuclk";
			};
			scpi_clk: scpi_clocks@3 {
				compatible = "arm,scpi-variable-clocks";
				#clock-cells = <1>;
				clock-indices = <3>;
				clock-output-names = "pxlclk";
			};
		};

		scpi_sensors0: sensors {
			compatible = "arm,scpi-sensors";
			#thermal-sensor-cells = <1>;
		};
	};

	/include/ "juno-clocks.dtsi"

	dma@7ff00000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0x7ff00000 0 0x1000>;
		#dma-cells = <1>;
		#dma-channels = <8>;
		#dma-requests = <32>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_faxiclk>;
		clock-names = "apb_pclk";
	};

	hdlcd@7ff50000 {
		compatible = "arm,hdlcd";
		reg = <0 0x7ff50000 0 0x1000>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpi_clk 3>;
		clock-names = "pxlclk";

		port {
			hdlcd1_output: endpoint@0 {
				remote-endpoint = <&tda998x_1_input>;
			};
		};
	};

	hdlcd@7ff60000 {
		compatible = "arm,hdlcd";
		reg = <0 0x7ff60000 0 0x1000>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpi_clk 3>;
		clock-names = "pxlclk";

		port {
			hdlcd0_output: endpoint@0 {
				remote-endpoint = <&tda998x_0_input>;
			};
		};
	};

	soc_uart0: uart@7ff80000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x0 0x7ff80000 0x0 0x1000>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
		clock-names = "uartclk", "apb_pclk";
	};

	i2c@7ffa0000 {
		compatible = "snps,designware-i2c";
		reg = <0x0 0x7ffa0000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <400000>;
		i2c-sda-hold-time-ns = <500>;
		clocks = <&soc_smc50mhz>;

		hdmi-transmitter@70 {
			compatible = "nxp,tda998x";
			reg = <0x70>;
			port {
				tda998x_0_input: endpoint@0 {
					remote-endpoint = <&hdlcd0_output>;
				};
			};
		};

		hdmi-transmitter@71 {
			compatible = "nxp,tda998x";
			reg = <0x71>;
			port {
				tda998x_1_input: endpoint@0 {
					remote-endpoint = <&hdlcd1_output>;
				};
			};
		};
	};

	ohci@7ffb0000 {
		compatible = "generic-ohci";
		reg = <0x0 0x7ffb0000 0x0 0x10000>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_usb48mhz>;
	};

	ehci@7ffc0000 {
		compatible = "generic-ehci";
		reg = <0x0 0x7ffc0000 0x0 0x10000>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_usb48mhz>;
	};

	memory-controller@7ffd0000 {
		compatible = "arm,pl354", "arm,primecell";
		reg = <0 0x7ffd0000 0 0x1000>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
	};

	memory@80000000 {
		device_type = "memory";
		/* last 16MB of the first memory area is reserved for secure world use by firmware */
		reg = <0x00000000 0x80000000 0x0 0x7f000000>,
		      <0x00000008 0x80000000 0x1 0x80000000>;
	};

	smb {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0 0x08000000 0x04000000>,
			 <1 0 0 0x14000000 0x04000000>,
			 <2 0 0 0x18000000 0x04000000>,
			 <3 0 0 0x1c000000 0x04000000>,
			 <4 0 0 0x0c000000 0x04000000>,
			 <5 0 0 0x10000000 0x04000000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 15>;
		interrupt-map = <0 0  0 &gic 0 0 0  68 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  1 &gic 0 0 0  69 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  2 &gic 0 0 0  70 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;

		/include/ "juno-motherboard.dtsi"
	};
Commit	Line	Data
e8020874 LD	1	/*
	2	* Devices shared by all Juno boards
	3	*/
	4
79502355 LD	5	memtimer: timer@2a810000 {
	6	compatible = "arm,armv7-timer-mem";
	7	reg = <0x0 0x2a810000 0x0 0x10000>;
	8	clock-frequency = <50000000>;
	9	#address-cells = <2>;
	10	#size-cells = <2>;
	11	ranges;
	12	status = "disabled";
	13	frame@2a830000 {
	14	frame-number = <1>;
	15	interrupts = <0 60 4>;
	16	reg = <0x0 0x2a830000 0x0 0x10000>;
	17	};
	18	};
	19
ff9a6262 SH	20	mailbox: mhu@2b1f0000 {
	21	compatible = "arm,mhu", "arm,primecell";
	22	reg = <0x0 0x2b1f0000 0x0 0x1000>;
	23	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	24	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	25	interrupt-names = "mhu_lpri_rx",
	26	"mhu_hpri_rx";
	27	#mbox-cells = <1>;
	28	clocks = <&soc_refclk100mhz>;
	29	clock-names = "apb_pclk";
	30	};
	31
e8020874 LD	32	gic: interrupt-controller@2c010000 {
	33	compatible = "arm,gic-400", "arm,cortex-a15-gic";
	34	reg = <0x0 0x2c010000 0 0x1000>,
	35	<0x0 0x2c02f000 0 0x2000>,
	36	<0x0 0x2c04f000 0 0x2000>,
	37	<0x0 0x2c06f000 0 0x2000>;
9e6f374f	38	#address-cells = <2>;
e8020874	39	#interrupt-cells = <3>;
9e6f374f	40	#size-cells = <2>;
e8020874 LD	41	interrupt-controller;
e8020874 LD	42	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_HIGH)>;
9e6f374f LD	43	ranges = <0 0 0 0x2c1c0000 0 0x40000>;
	44	v2m_0: v2m@0 {
	45	compatible = "arm,gic-v2m-frame";
	46	msi-controller;
	47	reg = <0 0 0 0x1000>;
	48	};
e8020874 LD	49	};
	50
	51	timer {
	52	compatible = "arm,armv8-timer";
	53	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	54	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	55	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>,
	56	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) \| IRQ_TYPE_LEVEL_LOW)>;
	57	};
	58
ff9a6262 SH	59	sram: sram@2e000000 {
	60	compatible = "arm,juno-sram-ns", "mmio-sram";
	61	reg = <0x0 0x2e000000 0x0 0x8000>;
	62
	63	#address-cells = <1>;
	64	#size-cells = <1>;
	65	ranges = <0 0x0 0x2e000000 0x8000>;
	66
	67	cpu_scp_lpri: scp-shmem@0 {
	68	compatible = "arm,juno-scp-shmem";
	69	reg = <0x0 0x200>;
	70	};
	71
	72	cpu_scp_hpri: scp-shmem@200 {
	73	compatible = "arm,juno-scp-shmem";
	74	reg = <0x200 0x200>;
	75	};
	76	};
	77
36582c60 SH	78	pcie_ctlr: pcie-controller@40000000 {
	79	compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
	80	device_type = "pci";
	81	reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
	82	bus-range = <0 255>;
	83	linux,pci-domain = <0>;
	84	#address-cells = <3>;
	85	#size-cells = <2>;
	86	dma-coherent;
	87	ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
	88	<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
	89	<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
	90	#interrupt-cells = <1>;
	91	interrupt-map-mask = <0 0 0 7>;
	92	interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
	93	<0 0 0 2 &gic 0 0 0 137 4>,
	94	<0 0 0 3 &gic 0 0 0 138 4>,
	95	<0 0 0 4 &gic 0 0 0 139 4>;
	96	msi-parent = <&v2m_0>;
	97	status = "disabled";
	98	};
	99
ff9a6262 SH	100	scpi {
	101	compatible = "arm,scpi";
	102	mboxes = <&mailbox 1>;
	103	shmem = <&cpu_scp_hpri>;
	104
	105	clocks {
	106	compatible = "arm,scpi-clocks";
	107
	108	scpi_dvfs: scpi_clocks@0 {
	109	compatible = "arm,scpi-dvfs-clocks";
	110	#clock-cells = <1>;
	111	clock-indices = <0>, <1>, <2>;
	112	clock-output-names = "atlclk", "aplclk","gpuclk";
	113	};
	114	scpi_clk: scpi_clocks@3 {
	115	compatible = "arm,scpi-variable-clocks";
	116	#clock-cells = <1>;
9fd9288e LD	117	clock-indices = <3>;
9fd9288e LD	118	clock-output-names = "pxlclk";
ff9a6262 SH	119	};
ff9a6262 SH	120	};
dfacaf0e PA	121
	122	scpi_sensors0: sensors {
	123	compatible = "arm,scpi-sensors";
	124	#thermal-sensor-cells = <1>;
	125	};
ff9a6262 SH	126	};
ff9a6262 SH	127
e8020874 LD	128	/include/ "juno-clocks.dtsi"
	129
	130	dma@7ff00000 {
	131	compatible = "arm,pl330", "arm,primecell";
	132	reg = <0x0 0x7ff00000 0 0x1000>;
	133	#dma-cells = <1>;
	134	#dma-channels = <8>;
	135	#dma-requests = <32>;
	136	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
	137	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	138	<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
	139	<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
	140	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	141	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	142	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	143	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	144	clocks = <&soc_faxiclk>;
	145	clock-names = "apb_pclk";
	146	};
	147
9fd9288e LD	148	hdlcd@7ff50000 {
	149	compatible = "arm,hdlcd";
	150	reg = <0 0x7ff50000 0 0x1000>;
	151	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	152	clocks = <&scpi_clk 3>;
	153	clock-names = "pxlclk";
	154
	155	port {
	156	hdlcd1_output: endpoint@0 {
	157	remote-endpoint = <&tda998x_1_input>;
	158	};
	159	};
	160	};
	161
	162	hdlcd@7ff60000 {
	163	compatible = "arm,hdlcd";
	164	reg = <0 0x7ff60000 0 0x1000>;
	165	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	166	clocks = <&scpi_clk 3>;
	167	clock-names = "pxlclk";
	168
	169	port {
	170	hdlcd0_output: endpoint@0 {
	171	remote-endpoint = <&tda998x_0_input>;
	172	};
	173	};
	174	};
	175
e8020874 LD	176	soc_uart0: uart@7ff80000 {
	177	compatible = "arm,pl011", "arm,primecell";
	178	reg = <0x0 0x7ff80000 0x0 0x1000>;
	179	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	180	clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
	181	clock-names = "uartclk", "apb_pclk";
	182	};
	183
	184	i2c@7ffa0000 {
	185	compatible = "snps,designware-i2c";
	186	reg = <0x0 0x7ffa0000 0x0 0x1000>;
	187	#address-cells = <1>;
	188	#size-cells = <0>;
	189	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	190	clock-frequency = <400000>;
	191	i2c-sda-hold-time-ns = <500>;
	192	clocks = <&soc_smc50mhz>;
	193
9fd9288e	194	hdmi-transmitter@70 {
e8020874 LD	195	compatible = "nxp,tda998x";
e8020874 LD	196	reg = <0x70>;
9fd9288e LD	197	port {
	198	tda998x_0_input: endpoint@0 {
	199	remote-endpoint = <&hdlcd0_output>;
	200	};
	201	};
e8020874 LD	202	};
e8020874 LD	203
9fd9288e	204	hdmi-transmitter@71 {
e8020874 LD	205	compatible = "nxp,tda998x";
e8020874 LD	206	reg = <0x71>;
9fd9288e LD	207	port {
	208	tda998x_1_input: endpoint@0 {
	209	remote-endpoint = <&hdlcd1_output>;
	210	};
	211	};
e8020874 LD	212	};
	213	};
	214
	215	ohci@7ffb0000 {
	216	compatible = "generic-ohci";
	217	reg = <0x0 0x7ffb0000 0x0 0x10000>;
	218	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	219	clocks = <&soc_usb48mhz>;
	220	};
	221
	222	ehci@7ffc0000 {
	223	compatible = "generic-ehci";
	224	reg = <0x0 0x7ffc0000 0x0 0x10000>;
	225	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	226	clocks = <&soc_usb48mhz>;
	227	};
	228
	229	memory-controller@7ffd0000 {
	230	compatible = "arm,pl354", "arm,primecell";
	231	reg = <0 0x7ffd0000 0 0x1000>;
	232	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
	233	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	234	clocks = <&soc_smc50mhz>;
	235	clock-names = "apb_pclk";
	236	};
	237
	238	memory@80000000 {
	239	device_type = "memory";
	240	/* last 16MB of the first memory area is reserved for secure world use by firmware */
	241	reg = <0x00000000 0x80000000 0x0 0x7f000000>,
	242	<0x00000008 0x80000000 0x1 0x80000000>;
	243	};
	244
	245	smb {
	246	compatible = "simple-bus";
	247	#address-cells = <2>;
	248	#size-cells = <1>;
	249	ranges = <0 0 0 0x08000000 0x04000000>,
	250	<1 0 0 0x14000000 0x04000000>,
	251	<2 0 0 0x18000000 0x04000000>,
	252	<3 0 0 0x1c000000 0x04000000>,
	253	<4 0 0 0x0c000000 0x04000000>,
	254	<5 0 0 0x10000000 0x04000000>;
	255
	256	#interrupt-cells = <1>;
	257	interrupt-map-mask = <0 0 15>;
9e6f374f LD	258	interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
	259	<0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
	260	<0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
	261	<0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
	262	<0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
	263	<0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
	264	<0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
	265	<0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
	266	<0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
	267	<0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
	268	<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
	269	<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
	270	<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
e8020874 LD	271
	272	/include/ "juno-motherboard.dtsi"
	273	};